High-Voltage Energy Storage: The Key to Efficient Holdup Jean Picard

Ab s t r a c t This topic provides a tutorial on how to design a high-voltage-energy storage (HVES) system to minimize the storage capacitor bank size. The first part of the topic demonstrates the basics of energy and the benefits/limitations of HVES; it also provides volumetric analysis graphs illustrating volume reduction and energy density. The second part provides an overview of the critical aspects of an HVES design. It compares the possible topologies and control techniques, identifies the pitfalls and design challenges of the recharge and holdup modes, and discusses the impact of design decisions on power losses. Design guidelines applicable to a preselected power topology and control strategy are also provided, including a design example for a 48-V application.

I. Fu n d a m e n ta l s o f Hi g h -Vo lta g e holdup event such as a momentary input-power En e r g y St o r a g e interruption. Fig. 2 shows typical Vbus levels with A. Basic Principles and without an energy-storage system. For example, in telecommunications applications, the Many high-reliability systems have a require­ ® ® ment for modules to ride through short input- PICMG AdvancedTCA specification requires power interruptions. Some systems require a continuous operation in the presence of a 5-ms, graceful shutdown mechanism while others need a 0-V input-voltage transient (the total duration is local bank of energy to supply power during 9.2 ms when rise and fall times are included). The occasional and brief high-load-current demand. 5 ms is the time in which a fuse can blow when There are also other applications that require there is a short circuit on a module or a short- short-term backup power when the main power circuited module is plugged into the system. Many fails—for example, a security system that needs to other similar examples can be enumerated, both record information for a limited time following a for DC and AC bus voltages.

power interruption. 5 Topic Vbus t Input-power interruptions can come from a holdup

short-circuited module or from the switchover Vholdup from a primary to a redundant bus when a power- Without Energy bus failure occurs. Fig. 1 shows a basic energy- 0V Storage storage system that could maintain V during a bus Fig. 2. Bus voltage during holdup event.

Bus #1 Hotswap Regulated Input DC (Optional) DC/DC Rectifiers Vbus Voltage Voltage + Converter to Load EMI Filter Bus #n

Energy-Storage System

Capacitor Bank

Fig. 1. Bulk-capacitors solution for energy storage.

5-1 One way to ride through the fault is to use Rectifiers + Regulated storage capacitors. The Input DC/DC Hot Swap Voltage energy available is Voltage Converter (Optional) to Load defined as + EMI Filter

HVES System 1 2 2 EC=−×()VV1 2 , (1) 2 High Step-Down Voltage where E is the energy Regulation at in joules (J), C is the Vholdup capacitance in farads (F), V1 is the starting Capacitor capacitor voltage before HVES Bank Recharge at V discharge, and V2 is the 1 final capacitor voltage after discharge. The greater the voltage decrease, the smaller is Fig. 3. HVES Solution. the capacitance required to hold up the circuit. 2.5 In a bulk-capacitors solution (Fig. 1),

energy is stored in capacitors on the power ) Panasonic EEFK

2 2 bus. This requires a large capacitance value NCC KZE

kJ/m

because the allowed voltage decrease is ( usually a small percentage of the bus 1.5 voltage. An alternative solution, high-voltage- Density 1 energy storage (HVES) stores the energy on

a capacitor at a higher voltage and then Energy 0.5 transfers that energy to the power bus during Topic 5 Topic the dropout (see Fig. 3). This allows a smaller 0 capacitor to be used because a large 100 80 63 50 35 25 16 10 percentage of the energy stored is used for Cap Voltage Rating (V) holdup. HVES is a particularly good choice Fig. 4. PCB energy density with V2 = 39 V and HVES when the bus voltage has a wide range of solution with V1 = 88% of capacitor rating. variation (for example, a 48-V bus with 72 V maximum), already requiring high-voltage bulk If, for example, 2 J are required over a 10-ms capacitors; or the minimum normal bus voltage is time period, V2 is 39 V, and V1 is only 44 volts, not much higher than the minimum needed by the then 9639 µF is required. If V1 is increased to loads to stay in operation (for example, 44 V 88 V and the power-conversion efficiency is 91%, versus 39 V). the required capacitance decreases to less than 706 µF, which means a reduction factor of close to B. Volumetric Design Examples 14. In both cases, some derating must be applied In Fig. 3 and Equation (1), the capacitor bank to the required capacitance. This includes the has initially been recharged and its voltage is V1. initial tolerance, the temperature variation, and the V2 represents the capacitor bank’s minimum lifetime variation. voltage required to maintain Vholdup, which is the Figs. 4 and 5 illustrate how increasing the regulated bus voltage during a holdup event. storage voltage reduces the PCB area, assuming

5-2 30.5 Square Inches 24.8 Square Inches 4.86 Square Inches

HVES TopView

1.8 Inches

6.1 Inches 5.5 Inches 2.7 Inches

HVES Bottom View 5 Inches 4.5 Inches a. Bulk-capacitors solution b. Bulk-capacitors solution c. HVES solution with with V=1244 V, V=39 V, a with V=1244 V, V=39 V, a V=1288 V=39 V, a 200-W 200-W load, and 330-µF/100-V 200-W load, and smaller load, and 330-µF/100-V capacitors. 330-µF/80-V capacitors. capacitors.

Fig. 5. PCB area with HVES solution versus bulk-capacitors solution.

that the capacitor’s height is no more than 21 mm Fig. 6 illustrates the energy density achievable and the capacitor’s final voltage (V2) is 39 V. with a bulk-capacitors solution that uses the same Capacitor types considered are the Panasonic final voltage and capacitor types. The starting surface-mount EEFK and the Nippon Chemi-Con capacitor voltage has been set to 44 V, and the (NCC) leaded through-hole KZE. The storage capacitor voltage rating varies depending on the voltage has been arbitrarily set to 88% of the maximum expected bus voltage during system maximum capacitor voltage rating, the capacitance operation. derating factor has been set to 74%, and the conversion efficiency has been set to 91%.

0.35 5 Topic

0.3 Panasonic EEFK

) 2 NCC KZE 0.25

kJ/m

( 0.2

Density 0.15

0.1

Energy 0.05

0 100 80 63 Cap Voltage Rating (V) Fig. 6. PCB energy density with V2 = 39 V and bulk- capacitors solution.

5-3 2.5 0.08

Panasonic EEFK 0.07 Panasonic EEFK

)

)

2 2 NCC KZE 2 0.06 NCC KZE

kJ/m

kJ/m

( 1.5 ( 0.05 0.04

Density

Density 1 0.03

0.02

Energy 0.5 Energy 0.01

0 0 100 80 63 50 35 25 50 35 25 16 10 Cap Voltage Rating (V) Cap Voltage Rating (V)

Fig. 7. PCB energy density for 12-V system and Fig. 8. PCB energy density with V1 = 11 V, HVES solution with V1 = 90% of capacitor rating V2 = 10 V, and bulk-capacitors solution. and 70% conversion efficiency.

Analysis results for a 12-V system having a impact on the system. It is also highly preferable conversion efficiency of 70% are shown in Figs. 7 to make use of a single inductor for all modes of and 8. It is clear that storing energy at 50 V is operation for a compact system solution. EMI enough to provide a high size-reduction ratio. requirements, thermal aspects, and total cost must also be considered. II. Cr i t i c a l As p e c t s o f HVES Im p l e m e n tat i o n B. Optimum Power-Bridge Configuration and A. General System Requirements Control Strategy for Bidirectional Converter Basically, an HVES system must be able to: A simplified system diagram is shown in Fig. 9, which presents the HVES like a virtual • use the bus voltage to charge and maintain the capacitor. While the key to minimizing the size of storage capacitors to a nominal voltage, the HVES unit is high-voltage storage, conversion • use the energy available in the storage capacitors efficiency also has some impact. to quickly maintain and regulate the internal input bus voltage during a short input-power

Topic 5 Topic interruption, • automatically dis­ Rectifiers + DC/DC Regulated charge the storage Input Hot Swap Converter Voltage Voltage (Optional) + ca­pacitors on unit to Load + HF Input re­moval for safety, and EMI Filter Filter • minimize the size of Simple 2-Wire Connection HVES System the storage capacitor bank. High Holdup Voltage Regulation Secondary needs include inrush-current control during initial Storage Capacitor recharge, short-circuit Recharge Bank pro­tection during Capacitor Bleed- recharge and very low Down power consumption when the capacitors Control become com­pletely charged for minimum Fig. 9. Simpified HVES functional diagram.

5-4 The storage capacitor Rectifiers DC/DC bank is connected only to + Converter Input Hot Swap + the HVES power-bridge Voltage (Optional) HF Input + circuit. It is also normally Filter physically located very close EMI Filter to this circuit, with Simple 2-Wire Connection enclosure(s) or other types HVES System of barriers that bar user High access to satisfy safety Holdup Q Voltage Regulation D concerns. These conditions remove any need for an isolation transformer during Capacitor Bank energy transfer. Recharge QC The power bridge configurations considered are (1) the boost/buck, (2) the flyback/buck, and (3) the multimode buck/boost. Control Bridge Configuration 1: Boost/Buck This power-bridge Fig. 10. Bridge configuration 1: Boost in recharge, buck in holdup. config­uration is simple, requiring only two MOSFETs and a diode with control or load short-circuit protection. A hot- one high-side gate driver (see Fig. 10). It uses a swap device operates its MOSFET in linear mode boost topology operating in peak-current control during inrush, during which it must keep the to recharge the capacitors (see Fig. 11). The current MOSFET within its safe operating area (SOA) in sensing is simply done with a low-side resistor. worst-case temperature conditions. Because of The boost topology does not provide any inrush additional energy storage in the HVES capacitors, limiting or any protection against a short-circuit in the SOA limitations result in a largely oversized the storage capacitor bank. This requires additional hot-swap MOSFET, a very long recharge time, or circuitry, for example a hot-swap device located even both. For these reasons, the boost/buck 5 Topic upstream. Note that a hot-swap device in the main solution is not the preferred one. power path introduces power loss during normal Note that a hot-swap device could instead be operation, so that using it makes more sense if the inserted directly within the HVES charge/ system already needs it for bus-capacitor inrush discharge path and out of the main load power

Vstorage Vstorage +Vbus +Vbus Low- Low- Low- Low- Capacitor Capacitor R ESR QD ESR RLOAD ESR QD ESR LOAD Bank Bank CLOAD Cap. Cap. CLOAD Cap. Cap.

–Vbus –Vbus

QC QC

a. QC is on and QD is off. b. QC and QD are off. Fig. 11. Current flow in boost recharge mode.

5-5 path. The limitations, Rectifiers DC/DC however, would remain + Converter Regulated Input Hot Swap similar; and additional + Voltage Voltage (Optional) HF Input to Load complexity would be + Filter introduced, including a EMI Filter Simple 2-Wire current-sensing element Connection HVES System and a power parallel High diode. Holdup QA QD Voltage During holdup, a Regulation boost/buck solution uses a nonsynchronous buck Capacitor topology similar to that Bank used in a flyback/buck Recharge QC

topology discussed next. DC Bridge Configuration 2: Flyback/Buck This configuration uses a flyback (also known as buck-boost) Control topology with peak- current-mode control to Fig. 12. Bridge configuration 2: flyback/buck. recharge the capacitors. Many current-sensing strategies are possible. During holdup, a buck topology with voltage- Fig. 12 shows a low-side resistor acting as a mode control is used. Voltage-mode control does current sensor similar to the boost/buck topology. not use current sensing and therefore does not One advantage of the flyback topology over the need slope compensation, which would be required boost is that it provides complete inrush-current for current-mode control at higher duty cycles. control while the storage capacitors are being This is particularly important in the actual recharged from 0 V (Fig. 13). This control also application, where the storage-capacitor voltage provides protection against capacitor short-circuits. drops down to Vbus during holdup, resulting in the

Topic 5 Topic The QA MOSFET is operated only in switch mode, duty cycle approaching 100%. resulting in a smaller MOSFET than would be required for a circuit that linearly limits inrush.

Vstorage Vstorage +Vbus +Vbus Low- Low- Low- Low- Capacitor Capacitor R ESR QA QD ESR R ESR QA QD ESR LOAD Bank LOAD Bank CLOAD Cap. Cap. CLOAD Cap. Cap. L –Vbus –Vbus VQC_drain

QC QC DB DB

Vsense

R sense

a. QA and QC are on and QD is off. b. QA, QC, and QD are off. Fig. 13. Current flow in flyback recharge mode.

5-6 Vstorage Vstorage +Vbus +Vbus Low- Low- Low- Low- Capacitor ESR Q Q Capacitor RLOAD ESR QA QD ESR RLOAD A D ESR Bank Cap. Bank CLOAD Cap. Cap. CLOAD Cap. L L –Vbus –Vbus

QC QC D DC C

a. QD is on and QA and QC are off. b. QA, QC, and QD are off. Fig. 14. Current flow in buck holdup mode.

Note that in Fig. 14, the ultrafast diode, DC, Bridge Configuration 3: Multimode Buck/Boost shunts the holdup current around Rsense so that the The third power-bridge configuration is by far recharge current can be optimized without the most complex. It uses a flyback topology to penalizing the buck efficiency. Also note that recharge the capacitor, but during holdup it the Rsense value is normally high enough to ensure transitions from a buck to a flyback topology and that DC is the preferred path over QC’s body diode to a boost topology as the storage voltage goes during holdup, providing a much lower and more down (see Figs. 15 and 16). predictable reverse-recovery loss. With this configuration during holdup mode, The main drawback in using a buck topology the converter can be run as a buck when Vstorage is is that if operation needs to be maintained when greater than Vbus (bus voltage) and as a boost the storage voltage is becoming equal to the bus when Vstorage is less than Vbus. It is also run as a voltage, operation at virtual 100% duty cycle is flyback when Vstorage is close to Vbus. needed, which adds some complexity to the control Analyses indicate that in many cases there is circuitry and the high-side gate driver of QD little benefit in trying to use this multimode MOSFET. configuration in holdup, as it results in an oversized

DC/DC Hot Swap Converter Input (Optional) + Voltage + HF Input 5 Topic EMI Filter Filter Simple 2-Wire Connection HVES System

High Q Holdup Q Voltage A Regulation D

Capacitor Bank QB Recharge QC

Control

Fig. 15. Bridge configuration 3: Multimode buck/boost.

5-7 Vstorage Vstorage +Vbus +Vbus

RLOAD QA QD RLOAD QA QD

–Vbus –Vbus

QB QC QB QC

a. Buck (Vstorage > Vbus ).

Vstorage Vstorage +Vbus +Vbus

RLOAD QA QD RLOAD QA QD

–Vbus –Vbus

QB QC QB QC

b. Flyback (Vstorage ≈ Vbus ).

Vstorage Vstorage +Vbus +Vbus

RLOAD QA QD RLOAD QA QD

–Vbus –Vbus Topic 5 Topic

QB QC QB QC

c. Boost (Vstorage < Vbus ). Fig. 16. Current flow in holdup with bridge configuration 3.

and much more complex power circuitry. Four complexity, and/or costs. For all these reasons, power MOSFETs with gate drivers are needed, switching and gate losses become higher in holdup which is two more than configuration 1 and one with bridge configuration 3. more than configuration 2. There are additional Also, the rms ripple current circulating in the concerns with potential body-diode reverse- output capacitor is much higher with a boost recovery problems in each operating mode, for converter than with a buck converter. See Figs. 17 example, when MOSFET QB is turned on while and 18. Consequently, a bus capacitor’s equivalent there is already a current circulating in QA’s body series resistance (ESR) may become an issue diode. Trade-off solutions exist but add losses, mainly because of bus voltage ripple during

5-8 )

A holdup, particularly if an electrolytic capacitor is ( 2 used. Of secondary importance is the impact on 1 efficiency during holdup.

Current The required inductance value is higher for a 0 –1 buck topology while the required current capability acitor

is higher with a boost topology. Cap –2 0 123456 78910 An inductor designed for both modes would Time (µs) therefore be larger than one optimized for either Fig. 17. Output-capacitor current with buck mode by itself. Similar considerations apply to the topology, 250-W load, 80-V input, and 40-V output. MOSFETs, for example QD, for which the voltage

)

A rating is dictated by the buck topology while the ( 10 conduction loss, being proportional to RDS(on), is 5 at its worst in the boost topology. The consequence Current 0 is either lower system efficiency, larger component –5 size, higher cost, or a combination of these. acitor

Also, the energy in a capacitor is proportional Cap –10 2 0 123456 78910 to V , which reduces the benefits of boosting at Time (µs) low voltage. For example, the energy left in a Fig. 18. Output-capacitor current with boost capacitor between 40 V and 20 V is quite low topology and same buck inductance value, 250-W (<18%) versus that left between 90 V and 40 V. load, 20-V input, and 40-V output. Finally, the control strategy is much more complex when this multimode configuration is Power-Bridge Trade-offs Summary used during holdup. For example, a right-half- A comparison of the three power-bridge plane zero will be present during operation in configurations is shown in Table 1. Note that all of boost and buck/boost modes, and slope compen­ these configurations use N-channel MOSFETs, sation is required for each mode when the source which provide better performance and efficiency voltage is going down. at lower cost than PMOS devices. Storing energy Ta b l e 1. HVES Co n fi g u r at i o n s Co m pa r i s o n Configurations, HVES Topologies, and Control Mode Benefits Drawbacks Cost Size

1 Recharge: Boost, Recharge • Low HVES parts count • Needs upstream hot swap in Low Low 5 Topic peak-current-mode main path to handle inrush control • Oversized hot-swap MOSFET • Long recharge time Holdup: Buck, Holdup • Low power-bridge • 100% duty cycle may be needed voltage-mode control complexity • No current sensing • Simple control strategy

2 Recharge: Flyback, Recharge • Inrush control • High-side gate driver for QA Low Low peak-current-mode • short-circuit protection control

Holdup: buck, Holdup • Low power bridge • Less efficient with QA MOSFET voltage-mode control complexity • 100% duty-cycle may be needed • No current sensing • Simple control strategy

3 Recharge: Flyback, Recharge • Inrush control • High-side gate driver for QA Medium Medium peak current mode • Short-circuit protection control Holdup: Buck, Holdup • Operates even if • High complexity flyback and boost, Vstorage < Vbus • Larger inductor current-mode control • Bus capacitors ripple current • Four large power MOSFETs and drivers

5-9 at high voltage is the main factor that reduces the Based on the current path shown in Fig. 13b, the size of HVES systems, while conversion efficiency change in current during OFF time can be also has some impact, but to a lesser degree. expressed as Since bridge configuration 2 (flyback/buck) (VVstoraged++BdVtDO)× FF appears to be the best choice, it will be the focus of ∆I = , (3) F L the rest of this topic. This topology provides a good trade-off between addressing the basic where VdB and VdD correspond respectively to system needs (HVES functionality with small diode DB and QD’s body diode (supposing QD is size) and keeping the complexity and costs to an maintained off), and tOFF is the OFF time. Note acceptable level. that VdB and VdD go down as the junction During recharge mode, peak-current mode temperature of DB and QD increases. While Vstorage provides good current control and adjustability of is close to 0 V, volt-second imbalance will occur if the total recharge time. tOFF is not long enough. This imbalance will cause Using the voltage-mode buck topology during the inductor current to rise very high even though holdup mode results in straightforward control, there is still peak-current detection. good transient response, low output-ripple current, A second issue during recharge is the risk and small size. Also, no synchronous rectification of not reaching the peak-current threshold during is used and the QC/QA packages can be small. the ON time while V is close to 0 V. Based During recharge mode, the converter operates storage on Fig. 13a, when QC is turned on, the drain in discontinuous mode most of the time, with the voltage is exception of the initial recharge from 0 V. In order VIQC __drain =+QC ×(RRsenseonQC ). (4) to achieve quasi-zero current consumption under such conditions, QD’s body diode is used. This is explained in more detail in the next section. Before using Equation (4), the following equation must be satisfied or some of the inductor current C. Recharge Mode will flow through QD’s body diode and the current- Charging the Bank on Power Up: Bus Protection sensing circuit will detect only part of the inductor and Recharge Time current. The HVES capacitor bank can be very large, VVQC _ drain <+storage VdD (5) which poses several challenges during the recharge cycle. It is important to minimize the impact of the Also, given that the voltage across the sense Topic 5 Topic HVES on the system, particularly at the start of resistor is recharge when the capacitor voltage is near 0 VDC, VRQC _ drain × sense which can result in very high input current. Short- V = , sense RR+ (6) circuit protection is also needed, and the total senseonQ_ C recharge time must be considered. the selection of R and R must ensure that One issue is related to the inductor’s volt- sense on_QC the V threshold can always be reached while second balance when the voltage across the storage sense V ≈ 0 V. Otherwise, Q will stay on even at capacitors is close to 0 V for a long time. In peak- storage A very high current. current-mode control, the use of leading-edge A third issue is that the total recharge time blanking and/or filtering on current sensing must be low enough to support application introduces a minimum time (t ) during which LEB_filt performance requirements. In some applications, the power switch is on. This means that during the however, a recharge time of many seconds may be ON time, neglecting the voltage drop in the series acceptable to minimize the impact of the HVES elements, the minimum increase of inductor capacitor recharge on the input bus. current is Vt× IN LEBf_ ilt (2) ∆IR = . L

5-10 Charge Maintenance and Recharge: Low Noise D. Holdup Mode and Minimal Loss Speed, Accuracy, and Load Protection When the HVES capacitors are in a fully The transient response at the beginning of a recharged state, the HVES power consumption on holdup event is critical. This includes the detection the bus must be less than the leakage loss of an of the bus-voltage drop and the transition from equivalent bulk-capacitors solution. To achieve recharge mode to holdup mode. low current consumption during charge mainten­ Many issues related to holdup mode need to be ance, synchronous rectifiers should not be used. considered during the HVES design. This allows the converter to operate in discontinu­ • The holdup error-amplifier reaction time is ous conduction, resulting in maximum efficiency. important since the holdup-voltage regulation There are many techniques that can be used in loop is open prior to the holdup event. Depending order to minimize power consumption of a power on the dynamics of the compensation design for supply at light load. One popular technique is the holdup error amplifier, the transient response pulse-frequency modulation (PFM), which of the system may be unacceptable. Note that an activates the power bridge only when the advantage of voltage-mode control versus capacitor’s voltage is below a predefined threshold. current-mode control is that the error amplifier’s As a result, the total consumption becomes output directly defines the operating dutycycle, proportional to the storage capacitor’s leakage which could result in enhanced transient current and the idle consumption of the control response. circuitry, including the voltage-feedback • It is important to consider the bus-capacitance network(s). Note that using this hysteretic-control ESR and the effect on the bus voltage when the technique means that an output-voltage ripple system voltage drops out. The bus capacitance is regulated at a very low frequency. The leakage is expected to be lower as a benefit of using characteristic of the capacitors (including HVES. The bus capacitors’ ESR introduces a temperature effects), in addition to the negative voltage step during the transition to allowed voltage-ripple amplitude, has a strong holdup mode. Also, some capacitor types exhibit impact on this modulation frequency. See Fig. 45 strong ESR variation over temperature. in Section III.B. • Some applications require high regulation and The HVES system must be designed so that detection accuracy during a holdup event. there are minimal conducted and radiated Vholdup, the regulated voltage during holdup, emissions, particularly when the capacitors are in must be higher than V but lower than

load_min 5 Topic a fully recharged state. The use of PFM with a low Vbus_min (see Fig. 19). The closer Vbus_min and recharge current may help to achieve that goal. Vload_min are, the more precise the detection and Stability regulation need to be. The HVES capacitance required can change considerably Vbus_max depending on specific system Normal requirements. Energy storage at Bus- tholdup Voltage high voltage normally requires Vbus_min Variations the use of electrolytic capacitors Vholdup for which the ESR varies Vload_min considerably, particularly over Load Does Not temperature. These variables Operate need to be considered during the 0V Below Vload_min design to result in a stable control loop. Fig. 19. Critical voltage levels for holdup circuit.

5-11 • To be able to handle a series of short dropout As mentioned before, the conversion efficiency events, the HVES system needs to draw from during holdup has some impact on the size of the the capacitors only the energy required by the HVES unit. The losses can be categorized as load for the dropout event and must automati- follows: cally detect the return of the input bus. • Conduction losses in MOSFETs, diodes, PCB • The holdup mechanism must provide load traces, and capacitors’ ESR protection and preferably maintain the internal • MOSFET switching and gate losses bus voltage within maximum limits (Vbus_max) • Reverse-recovery losses during some types of failures. A dedicated • Inductor losses—winding losses and core overvoltage-detection feedback network might losses be required to provide protection against loss of feedback in the main HVES voltage loop. Figs. 20 and 21 show an example of the • Finally, the possibility of a complete short- efficiency and major losses for an HVES system

circuit on the internal bus needs to be configured as in Fig. 12. In this example, only QD is switched while Q and Q are maintained off, considered—for example, a capacitor or C A using D and Q ’s body diode. semiconductor failure in the input stage of a C A load unit. One mitigating factor is that the amount of energy available is limited to the ) 20 100

W amount of HVES capacity. ( 40.5-V/250-W output,300 kHz, 47 µH

es

ss Efficiency and Energy 15 Conduction Losses 95 )

Lo The following component (% TotalEfficiency

ode

i

selection has been assumed for the 10 90 ency

ci

efficiency and dissipation graphs d D

ffi

E

an Gate andSwitching Losses of this topic: Vishay SUD15N15-95 5 85 for QD, Fairchild FDD2512 for QC, NXP PHT4NQ10T for QA, ReverseRecoveryLosses

MOSFET 0 80 Vishay ES3C for DC, Renco 40 45 50 55 60 65 70 75 80 85 90

RL-1256-1-47 for inductor L, and V(storage V) Panasonic EEVFK2A331M for Fig. 20. Total MOSFET and power-diode losses with overall Topic 5 Topic the HVES capacitors (unless efficiency versus storage capacitor’s voltage for HVES buck at otherwise noted). high temperature (TJ ≈ 100°C).

6 40.5-V/250-Woutput,300 kHz, 47 µH 5

)

W ( 4 InductorCopperLoss(105°C)

s

os 3 r L HVES Capacitor

we 2 Loss (Cold: ~30°C)

Po 1 HVES CapacitorLoss(Hot):~75°C

0 40 45 50 55 60 65 70 75 80 85 90 95 100 Vstorage (V) Fig. 21. Capacitor losses (at high and low temperature) and inductor losses versus storage voltage.

5-12 Note that the dissipation in the HVES capa­citors E. Safety and Bank Discharge increases at cold temperature because of the increase People whose safety needs must be considered in ESR. Dissipation also increases as the voltage are the users of the equipment and service goes down, since the duty cycle then goes up. personnel [1]. Lower efficiency results in the need for higher Users must be protected against inadvertent storage capacitance, although the change in volume contact with hazardous voltages. In an HVES may vary on a case-by-case basis. system, this is achieved with physical spacing and In the example in Section I.B where the grounded enclosures that isolate the user from the Panasonic EEFK 100-V capacitor series is used charged capacitor bank. and V1 equals 88 V, if the average efficiency goes Service personnel, who normally have access down to 80%, the minimum required storage to all parts of a system, must also be protected capacitance becomes approximately 803 µF, which from inadvertent contact with a hazardous surface is a 14% increase. After a capacitance derating and from unknowingly bridging a tool between factor of 74% is applied for worst-case variations, parts with high energy levels while servicing the capacitor bank’s PCB area increases by close another part. The main concern with an HVES to 30% because a fourth 330-μF capacitor becomes system is that the storage capacitor’s voltage and necessary. energy must be reduced to a safe level in a reasonable time after the unit has been unplugged. EMI and Self-Compatibility This requires a mechanism that automatically Holdup is the highest-power mode and discharges these storage capacitors upon unit therefore a potential source of EMI; but because removal. holdup events are infrequent and short in duration, the EMI conducted and radiated to the outside F. State-Machine Considerations world during such events may not be an issue. Fig. 22 shows an example of a simplified However, requirements for self-compatibility HVES state machine and timing diagram using a between the elements of a system using HVES PFM recharge mode. In this state machine, must still be met, and this is applicable to any “V = Low” stands for “low storage voltage” and operating mode, including a holdup event. st

Vbus = High and Vst = High Topic 5 Topic V=Low Power-Up Recharge bus Initialization Sleep Holdup Mode Mode V=bus High and V=bus Low Vst = Low V=High and bus Recharge V = High V=bus Low st Active Mode V=bus High and Vst = Low

V=bus High

Recharge Recharge Maintain Holdup Maintain Vstorage

Sleep Holdup Vbus Input Bus Interruption Bus Return Fig. 22. Simplified HVES state machine.

5-13 indicates when the capacitor’s voltage is below a G. Thermal Aspects threshold. “Vbus = Low” means that the input When the thermal performance of an HVES power goes down, and “Vbus = High” means there system is analyzed, the following aspects need to is no input-power interruption or the system be considered. returns to the beginning state. • The recharge mode uses the PFM technique, The following describes a typical operating which implies sleep intervals. The duration of sequence based on this state machine. initial recharge varies with the storage • After input-power-bus power up, the HVES capacitance and the nominal recharge voltage. capacitors are recharged (Recharge Active HVES MOSFETs are operated in switch mode Mode) and maintained at an elevated voltage. only; there is no linear inrush limiting. Once the capacitors are fully charged (Vst = • The holdup mode duration is limited, so dynamic High), the PFM technique is used. thermal behavior needs to be considered. This • With the PFM technique, the HVES system concerns the MOSFETs, the diodes, and the operates in Recharge Active Mode only PCB when used as a heatsink. Allowed dynamic when the capacitors’ voltage is below a stresses can be significantly higher than static threshold (Vst = Low). Otherwise, it operates stresses, depending on component types, in Recharge Sleep Mode for minimum packages, and power-pulse duration. See Fig. 23 power consumption. See Fig. 45. for an example. • The input-power bus is momentarily interrupted. • The mechanism that automatically discharges The bus voltage goes below the holdup trigger the storage capacitors upon unit removal needs threshold (Vbus = Low). The HVES operates in to be able to dissipate all of the stored energy as holdup mode and maintains the bus voltage at heat without exceeding critical temperatures. the holdup regulation voltage, discharging the • There are three basic methods to move heat storage capacitors partly or completely. away from the source: conduction, convection, • At the end of input-power-bus interruption (Vbus and radiation. = High), the HVES returns to recharge mode. • With the use of small component packages, Other aspects not shown in Fig. 22 also need conduction is particularly important because it to be considered, for example the automatic spreads out the heat to the surface area needed discharge of storage capacitors upon unit removal, to dissipate the heat by means of convection and whatever the current operating mode. radiation. PCB copper planes are commonly

Topic 5 Topic used for that purpose.

Graph data courtesy of Vishay Intertechnology. 2

1 Duty Cycle=0.5

ransient

T 0.2 0.1

Impedance,

Effective 0.1 0.02 0.05

Junction-to-Case

Thermal Single Pulse

Normalized 0.01 0.1ms1ms 10 ms 100 ms 110 Square-Wave PulseDuration (s) Fig. 23. Example of MOSFET effective transient thermal impedance (with Vishay SUD15N15-95).

5-14 PowerPAD™ + PCB (Heat spread and Rdie Rdieattach RPCB Junction transmission to air) Tj

J Cdie Cdieattach CPPAD + Solder

Conduction through bond wires, mold compound, T and lead frame not shown in this model a a. Circuit model.

Lead Frame (Copper Alloy) IC (Silicon)

Die Attach Mold Compound (Epoxy) ( ) Epoxy Lead Frame Die Pad— Exposed at Base of the Package b. Package components. Fig. 24. Example of simplified thermal model for integrated circuit with PowerPAD™.

The wattage that can be safely dissipated A. Power-Stage Considerations within the part depends on how well heat is Although the HVES system has two main removed from the package. Fig. 24 shows an operating modes, the holdup mode needs to be example of a simplified thermal model where heat considered first during the selection or design of is transferred to the air from the die mainly through power components. The recharge mode, which is a Topic 5 Topic the die attach material, the PowerPAD™ [2], and low-power mode, needs to be flexible enough to the PCB. Each capacitor in fact represents an accommodate itself to these selections. element’s thermal capacitance determined by its Inductor Design or Selection specific heat and mass. The design or selection of the inductor should III. Bi d i r e c t i o n a l Co n v e r t e r be made based on the following criteria. HVES Sy s t e m De s i g n Inductance Value—For a buck topology, the The following design guidelines are based on inductor is directly in series with the output load. bridge configuration 2 shown in Fig. 12, which Consequently, it carries the load current added to uses a nonisolated flyback topology in recharge the ripple current circulating into the output capacitors. Typically, a buck inductor is designed and a voltage-mode buck topology (QC and QA being maintained off) in holdup mode. The PFM to have a ripple factor of around 20% when technique with constant OFF time is also used operated with continuous current at full load (the during recharge. Note that during holdup operation, ripple factor being the ratio of the peak-to-peak the voltage source becomes the storage capacitor ripple current to the average maximum current bank while the load is on the bus side of the power value). bridge.

5-15 In an HVES application, the capacitor bank inductance value changes according to what level constitutes the input of the buck power supply, and of Vstorage the 20% rule is applied (see Fig. 26). its voltage goes down as the capacitors’ energy is Also, the required inductance value will decrease delivered. This means that the ripple factor also as the switching frequency increases. goes down, as shown in Figs. 25 and 26. The inductance value has a strong impact on The peak maximum inductor current and the transient response. A low inductance value results peak-to-peak ripple inductor current can be in a higher di/dt with theoretically faster speed. estimated respectively as However, with a higher inductance, the buck power supply stays in continuous mode at a lower Po 1 ILp_(k max) =+ (7a) load level. This in turn improves the transient V 2 bus response to a strong load step simply because, in (×VV++VD))(1− × bus fA fC , discontinuous mode, the error-amplifier output Lf× s goes down with the load current and would take longer to rise to the level needed for the load step. and Selecting a higher inductance value also ()VV++VD×(1− ) reduces the ripple current, which then reduces the I = bus fA fC , (7b) rip _ pkpk Lf× output voltage ripple which depends on the ESR s of the output-bus capacitors. and where Po is the load power; Vbus is the buck output; VfA and VfC are the forward voltage drop of, 10 100 respectively, QA’s body diode and 40.5-Voutput,300 kHz, 47 µH

QC’s parallel diode series elements; D ) 90

A 8

) is the duty cycle; fs is the switching ( MaxCPeak urrent at 250-WLoad

(% frequency; and L is the inductance. nt 80

le re 6

ur The duty cycle can be predicted as MaxCPeak urrent at 200-W Load 70 yc

-C

r C

VV++V 4 ty D = bus fA fC , Duty Cycle 60

(8) Du VVstorage +−fC VQD Peak-to-Peak

Inducto 2 Ripple Current 50 where V is the input of the buck storage 0 40

Topic 5 Topic and VQD is QD’s RDS(on) voltage drop. 40 45 50 55 60 65 70 75 80 85 90 95 100 Note that the impact of the series loss Vstorage (V) elements is to increase the duty cycle. Fig. 25. Buck inductor current and duty cycle versus V Note also that, as shown in the storage. previous equation and Figs. 25 and 26, the ripple current isn’t a function 25 ) 40.5-Voutput,300 kHz, 47 µH

of load in a continuous-mode buck. (% The inductor is calculated as 20 Ripple Factor at

actor

DV×( −−VV− V ) F 200-W Load L = storage bus fA QD , (9) 15

fIsr× ip _ pkpk ipple 10

r R where Irip_pkpk is the peak-to-peak inductor current as already defined. 5 Ripple Factor at

Inducto 250-W Load Note that since the storage capacitors’ 0 voltage is not constant, the calculated 40 45 50 55 60 65 70 75 80 85 90

Vstorage (V)

Fig. 26. Buck inductor ripple factor versus Vstorage.

5-16 Graph data courtesy of Renco Electronics. www.Rencousa.com Low enough DC and AC winding 1 0.910  resistance for good efficiency—DC resis­ tance is dictated by wire size and the

 0.748  number of winding turns. AC resistance, () which is related to skin effect but is largely 0.588  due to proximity effect [3], is also ance 0.5 influenced by wire type (single-strand or 0.430  Litz) and the number of winding layers. Resist AC resistance can be estimated, but a measurement with adequate instrumenta­ ­ 0.049  at 10 kHz tion (i.e., with the inductor’s magnetic 0 0 300 600 900 1200 core not installed to exclude core loss) is Frequency (kHz) necessary for better accuracy. See Fig. 27. Fig. 27. Inductor AC resistance versus frequency (with The simplified equation for total winding Renco RL-1256-1-47). loss is 22 PRWD=+()CD××IRCA()CAI C (10) The unshielded open-core inductor using ferrite provides a good cost and size alternative, with although it has its limitations. Due to its inherent 22 2 open flux path, it couples noise to circuits nearby IIAC =−RMSDI C , (11) and radiates EMI to the outside world. It is worth where RDC is the DC resistance of the inductor; noting that the very close proximity of a metallic RAC is its resistance measured at the switching surface having magnetic properties can change the frequency; and IDC and IAC are, respectively, the inductance by an amount that is difficult to predict. DC and AC current circulating through the For example, steel material, because of its high- inductor. absorption-loss properties, can reduce the RAC is in the form inductance value [4]. In addition, currents induced in a surface having conduction properties can RRAC =+DC ×(1)KPSE , (12) introduce additional power losses. where KPSE is the resistance-increase factor related For example, with the Coilcraft DO-5040H to the proximity and skin effects. Analysis can inductor, the core loss per unit of core volume can

demonstrate that for a buck operating in CCM, the be calculated as 5 Topic DC losses in the inductor dominate in most PK=×fBXY× , (13) applications, even when single-strand wire is used. loss 3 The AC losses become more important with high where P is in mW/cm , Kloss is 0.041, f is the ripple current where higher harmonics are no frequency in kHz, B is the peak value of flux longer negligible or at high switching frequencies. density in kilogauss, x = 1.63, and y = 2.51. Core Shape and Material—This has a direct B can be calculated in gauss as impact on core loss and inductor-radiated DV××()−−VV− V 105 storage bus fA QD (14) emissions. Gapped ferrite cores provide lower B = , 2fNst××urns Acore core loss at high frequency and have large flux swings, but they have a sharp saturation where all voltages are in volts, Nturns is the number characteristic and low-saturation flux density. A of turns, Acore is the inductor’s core cross-section 2 torroidal core with distributed gap material, for in cm , and fs is in kHz. The parameter values example powdered iron or Permalloy powder, mentioned are normally not available in data provides a softer saturation characteristic and catalogs and need to be provided by the inductor lower radiated EMI (torroid shape) but has much manufacturer. Other manu­facturers instead provide more core loss at high frequency. a simple equation calculating the core loss*, starting from the frequency and the ripple current. *See Equation (43) on page 5-29. 5-17 Graph data courtesy of Coilcraft. 20 60

)

% Typical Isat Derating

( 10 50

(µH) 0 40

Current

25°C

–10 at 30

Rated

ance in –20 20

–30 Induct 10 25°C

Change –40 0 –40 –20 020406080 100 120 140 0510 15 20 25 30 35 Ambient Temperature (°C) Current (A) a. Saturation current versus temperature. b. Inductance versus current.

Fig. 28. Inductor saturation characteristic (with Coilcraft DO-5040H-473 inductor).

High DC Saturation Current—The peak current at low, the QC and QA packages can be small and full load should be considered. The worst case is at low-cost, for example D-PAK or even SOT-223 minimum switching frequency and maximum and SOIC. Since a holdup event is a relatively Vstorage where the ripple current is maximum (see short event, physically smaller diodes can be Figs. 25 and 26), and at high temperature where used. typical inductors show a decrease in saturation The selection of QD is critical to holdup current level (see Fig. 28). There should also be performance and efficiency. While Vstorage varies some margin for overloads of short duration as from its initial to its final value, QD should provide well as for inductors’ manufacturing tolerance a good balance between conduction loss, which is variations. proportional to RDS(on); reverse-recovery loss; and gate-drive and switching losses. Also, a low Q of Small Physical Size—Since the inductor dissipates rr the body diode of Q and low drain-to-source high power only during a short holdup event, its D capacitance will provide a more efficient and physical size and PCB footprint depends mainly faster recharge mode. on its peak saturation current and to a much lesser Fig. 29 shows an example in which 40.5 V is

Topic 5 Topic extent on its winding resistance. regulated with a 250-W load, with the Vishay Selecting Switches and Diodes SUD15N15-95 MOSFET. Not surprisingly, the The selection of power semiconductors is a trade-off between size, efficiency, and 8 cost. As shown in Fig. 12, during holdup 40.5-V/250-WOutput, 300 kHz, 47 µH, 7 Gate Turn Off=0.47A,GateTurnOn=0.27 A mode only Q is activated and the release of D ) 6

W

the inductor energy to the bus is done ( Gate and

s 5 through diodes. Using an ultrafast diode in Switching Loss

sse 4 parallel with QC and a sense resistor o 3 Conduction Loss constitutes a good trade-off, providing D acceptable conduction loss with low reverse- QL 2 recovery loss and no QC-gate switching loss 1 ReverseRecovery Loss in holdup mode. For higher efficiency, a 0 Schottky diode can be used in parallel with 40 45 50 55 60 65 70 75 80 85 90 Vstorage (V) QA, particularly at lower bus voltages. Because the average and peak currents Fig. 29. QD’s power losses versus Vstorage at Tj = 110°C involved during recharge mode are very using Vishay SUD15N15-95 MOSFET and ES3C diode.

5-18 conduction loss is dominant at low Vstorage while the gate-drive, switching, and reverse- recovery losses become more important at a high voltage. The switching frequency used, Vgs fs = 300 kHz, has a strong impact on the results as reflected in several equations below. Vgs_th The loss types for QD during holdup are conduction, switching, reverse recovery, and gate drive. QD’s conduction loss can be Qgs2 Qgd calculated as Qg_tot 2 PRQD __cond =×on QD IQD _ RMS , (15) Fig. 30. General plot of a gate-charge waveform. where

2  2  Graph data courtesy of Vishay Intertechnology.  Po  Irip _ pkpk IDQD _ RMS = ×   +  (15a) 20 V 12  bus   I=D 6.5 A

15 and ) QagDtV S =45V

V

( ()VVbus ++fA VDfC ×()1− 10 QagDtV S = 120 V I = . (16) GS rip _ pkpk × V Lfs 5 QagDtV S =75V QD’s switching loss can be calculated as shown below in Equation (17) where QgdD and Qgs2D are the gate-drain and gate-source 0 charges as shown in Fig. 30; IG_off and IG_on 010203040 are the average gate-drive currents during Qg (nC) Q turnoff and turn-on, respectively; and D Fig.31. Gate-charge waveform for Vishay SUD15N15-95. CdsD is the drain-to-source parasitic capacitance with V equal to V .

ds_QD storage 5 Topic Note that QgdD and Qgs2D vary depending on derived from Vbus with linear regulation, Vbus Vstorage (shown in Fig. 31) and the load current. should be used in the equation instead of Vg. For the selected configuration, only QD is It is worth noting that activated. This limits the gate switching losses, fs 2 which can be calculated as PQOSS_ D =+××()CVdsDstorage QVgdD × storage . (19) 2  1  Pfgdrvs=+×× VQggTD QVgdD × storage , (18) The first element is part of P since it is  2  QD_SW dissipated in QD (at turn-on), while the second where QgTD is QD’s total gate charge as shown in element is part of Pgdrv because it is dissipated in Fig. 30 (Qg_tot), and Vg is the supply voltage the gate driver. needed by the gate driver. However, if Vg is If, at the time QD is turned on there is a forward current through the diode placed in parallel with

   fVss× torage   ILp_mk ax ILp_mk in   PQD _SW =+××  ()QggdD + QCgs2Dd + sD × Vstorage , (17) 2  I I   Go_ ff Go_ n   

5-19 IfC

IL_pk(min) trr ta tb di/dt VfC Vstorage

Low QA QD Capacitor RLOAD ESR IRM(REC) CLOAD Bank L Cap Vstorage

QC EQRR DQC

VQD IL_pk(min) IfC

Vstorage

IQD

t1 t2 t3 t4 t5 a. Timing waveforms. b. Current paths.

Fig. 32. Example of reverse-recovery effect with fast QD turn-on.

QC (DQC), there will be a reverse-recovery effect During holdup there is also conduction loss for as shown in Fig. 32. This effect could occur, for DQC which can be calculated as example, when the power circuit is operated with Po a continuous current. The following simplified PDQCc_ ond =−××VDfC ()1 . (22) V equation provides an estimate of the extra loss bus

related to the reverse-recovery effect: The only type of loss for QA’s body diode is Pf≈×VQ× , (20) conduction, which can be calculated as rr _ totsstorage rrC Po where QrrC is the reverse-recovery charge of DQC. PQA _ cond =×VfA . (23) Vbus Note that Prr_tot is distributed between the diode Topic 5 Topic and QD. This power distribution can be influenced Unless negative bias is used to keep the MOSFETs by many factors including diode characteristics, turned off, it is better to select MOSFETs that have speed of MOSFET turn-on, and circuit parasitics. a relatively high Vgs threshold (for example, 2 to In most cases, the reverse-recovery losses are 4 V at 25°C), particularly for QC and QD, which higher in the MOSFET (a ratio of 2 is common) are part of a half-bridge circuit. Note that Vgs_th than in the diode when an ultrafast diode is used. typically goes down as the temperature increases. QrrC can be estimated as Fig. 33 shows plots of typical losses using I − fC PHT4NQ10T and Vishay SUD15N15-95 td× id/ t QI= ××teT , (21) MOSFETs and ES3C diode. rrC fC T Selecting Capacitors where IfC is DQC’s current prior to QD turn-on, tT The primary concerns when selecting is the diode transit time (estimated using QrrC’s equation and diode reverse-recovery data with test capacitors are size, voltage ripple, power conditions), and di/dt is the slew rate of the current dissipation, leakage current, circuit noise, and the as shown in Fig. 32. To mitigate reverse-recovery impact on the control loops. Although there is a wide variety of capacitors on the market, very few losses, DQC should be selected for ultrafast reverse- recovery performance. can provide high capacitance per volume and

5-20 Graph data courtesy of TDK Corporation of America. 20 20 18 40.5-V/250-Woutput,300 kHz, 47 µH 10

) 16 0

W ( 14 –10 Capacitor: C3225X7R2A105M QTD otal Loss ) –20

%

( ses 12 (excluding gate-drive loss) –30 os 10

C/C –40 r L 8 QTA otal Loss –50 we 6 –60 Po 4 DTQC otal Loss –70 2 Gate-Drive Loss –80 0 020406080 100 120 40 45 50 55 60 65 70 75 80 85 90 95 100 Bias Voltage (V) Vstorage (V) Fig. 34. Example of capacitance change versus Fig. 33. Power losses with PHT4NQ10T (QA), voltage for a 100-V-rated TDK X7R ceramic SUD15N15-95 (QD) and ES3C. capacitor. Graph data courtesy of Panasonic. operate at 50 V or higher. This leaves the aluminium 10 electrolytic capacitor as the first choice for energy storage, based on volume and cost. On the bus side, depending on the operating voltage, additional selection includes tantalum, polymer aluminium, and OS-CON capacitors, for example. Ceramic 1 – 55°C

low-impedance capacitors are also required, on – 40°C

) both the bus and the storage-bank sides, for the ( –25°C

high-frequency switching current and noise ESR filtering. Note that ceramic capacitors are strongly –10°C 0.1 dependent on DC bias voltage, with capacitance 20°C going down substantially at higher voltage. See Fig. 34. 105°C Capacitors for Energy Storage—Since the current is pulsating similarly to QD during holdup, the 0.01 ESR is of prime importance. Electrolytic capacitors 100 1k 10 k 100 k 1M 10 M Topic 5 Topic typically exhibit a very strong ESR variation, Frequency (Hz) initially and over temperature (with the maximum a. ESR variation. ESR value at low temperature), as shown in Fig. 35. This variation has a direct impact on the 100 capacitors’ power loss which can be calculated as 80

(µA) ESR cs_ t 2 Pcaps_ t =×IQD _ RMS , (24) 60 n cs_ t Current 40 where ESRc_st is the ESR per capacitor, nc_st is the number of storage capacitors in parallel, and all Leakage 20 ESRs are assumed to be equal. The temperature 0 dependency of capacitor power loss is shown in 020406080 100 120 Fig. 21. Temperature (°C) b. Leakage current.

Fig. 35. Typical ESR and leakage current at 100 V over temperature for Panasonic EEVFK2A331M, 330-µF/100-V electrolytic capacitor.

5-21 The presence of a strong equivalent series operates in holdup mode. They minimize inductance (ESL) in series with these capacitors switching-noise voltage and help regulate voltage can introduce undesirable resonance during during load transients. Variations in peak output recharge mode. Surface-mount or radial capacitors voltage can be estimated [6] with mounted vertically (with no right-angle mount) VZpk var_ bus ≈×out _ pk Istep , (25) are recommended for storage, and they should be installed on the same PCB as the power bridge. where Zout_pk is the peak output impedance (Zout) The leakage current of storage capacitors is of the HVES buck power supply including bus also important as it influences the sleep-mode capacitance, and Istep is the load-step current. The duration when the power bridge is off in recharge initial spike is handled by capacitors and their mode. The lower the leakage current, the lower the parasitics. The overshoot duration during a load average current con­sumption of the HVES system drop may be longer than expected since no while in sleep mode. The leakage normally synchronous rectifier is used. increases with temper­ ature (see Fig. 35).

Capacitors on Internal Third-Order EMI Filter Bus—On the bus side, the capacitors are typically part of an Rd DC/DC existing EMI filter as CHF Load Ceramic Converter shown in Fig. 36. Cb Input Hot Swap Cb represents the internal- Voltage (Optional) bus main capacitor(s). The DC/DC converter provides a constant power load and represents HVES System a negative incre­mental

impedance to the EMI Virtual Capacitor filter [5] and the HVES system. The EMI filter a. With third-order differential-mode EMI filter.

Topic 5 Topic typically requires a damping resistance, Rd, as in Fig. 36 to avoid Fourth-Order EMI Filter introducing insta­bility into the system DC/DC converter(s). R includes d Rd DC/DC CHF Load the capacitor’s ESR. Ceramic Converter Input Hot Swap C and C play the C b HF Voltage (Optional) b role of output capacitors when the HVES system

HVES System

Virtual Capacitor b. With fourth-order differential-mode EMI filter. Fig. 36. HVES systems with EMI filters.

5-22 Zout As shown in Fig. 37, the output impedance, Zout, of a power supply can be determined over a frequency range by + Rd driving the supply output with a current DC/DC CHF Load V i Converter o o source, io, then measuring the output C – Hot Swap b voltage vo. (Optional) Cb and CHF also help maintain the bus voltage during the transition from recharge to holdup mode. The capacitors’ HVES System series impedances (ESR, ESL) affect performance during that time. If, for example, C is electrolytic, the worst- Virtual Capacitor b case maximum ESR is at cold temperature Fig. 37. In holdup mode, the load is powered by the HVES as shown in Fig. 38. If the buck error systems and the bus capacitance (parasitics not shown) is amplifier is in open loop during recharge part of the system’s output impedance. mode, significant additional bus-voltage drop may be introduced at the beginning Graph data provided by Nippon Chemi-Con. of the holdup mode. 10 The bus ripple voltage (see Fig. 39) caused by the HVES system switching during holdup can be conservatively ESR at –40°C 1 estimated as



() ESR at –25°C Irip _ pkpk ESR at –10°C Vrip _ bus ≈+IRrip _ pkpk × d . (26) ESR 8fCsb× 0.1 ESR at +20°C The Cb ESL-related spike is not ESR at +105°C shown in the equation because with the 0.01 addition of ceramic capacitors, which can 0.1 110 100 1000 also reduce Vrip_bus, the ESL is not Frequency (kHz) contributing significantly to the noise.

Fig. 38. Typical variation of ESR over frequency and For more accurate simulations, 5 Topic temperature for Nippon Chemi-Con EKZE101E__101MJ16S, parasitic impedances of capacitor and 100-µF/100-V electrolytic capacitor. PCB traces should be modeled. See the capacitor model in Fig. 40.

0.5

) 40.5-V output, 300 kHz, 47 µH

k L1 0.4 10.4 nH

pk-p

V ( 100Fµ ,0.25- ESR e 0.3

ag R1 R2

lt 496 m 111 m Vo 0.2 47 µF,0.1-E SR

le C1 C2 pp 100Fµ ,0.1-E SR 0.1 7.7 µF 322.3 µF

Ri

0 40 45 50 55 60 65 70 75 80 85 90 95 100 Fig. 40. PSpice® model for Panasonic Vstorage (V) EEVFK2A331M electrolytic capacitor Fig. 39. Output-bus ripple voltage versus Vstorage with various at 100 kHz and 20°C. ESRs and capacitances.

5-23 The dissipation in the bus capacitors and • Adequate power-dissipation capability of gate damping resistor related to HVES operation can be drivers. estimated with the equation • Adequate dead time between QD and QC if used 2 in the same operating mode. Irip _ pkpk Pcap _ bus = × R d . (27) 12 B. Control-Circuit Design Considerations Capacitor ESR also has a strong influence on the Recharge-Mode Control-Loop Design buck-voltage control loop, introducing a zero at Considerations the frequency 1/(2�RdCb) and providing damping The recharge-control circuit operates in a against the negative impedance of the constant constant-off-time using peak-current-mode control power load. (CMC) with a hysteretic error amplifier. See Figs. 42 and 43. Typical voltage-loop compensation is Gate Drivers normally highly dependent on output capacitance When gate-drive circuits are defined, the and parasitics. One benefit of hysteretic control is following needs should be considered: that no compensation is required. Another is that • Optimal gate-drive voltage amplitude for full there is no stability concern with a right-half-plane enhancement of MOSFETs and minimal gate- zero and a double pole at half the switching drive losses. frequency. Peak CMC inherently provides current • Very low pull-down impedance for low turnoff switching loss and minimal risk of parasitic turn-on.

• Slower QD and QC turn-on to get the Ld following: Cdg • Lower IRM and voltage transients and stress related to reverse Lg Rg recovery (higher PQD_SW but lower Gate Driver Cds Prr_tot) • Lower risk of parasitic turn-on of Cgs the “other” MOSFET of the half

bridge through its Cdg (see Fig. 41). Ls

Topic 5 Topic • Limited dV/dt applied to the “other” MOSFET of the half bridge, a. Simplified view. reducing the risk of destructive turn-on [7, 8] of a parasitic bipolar junction transistor (BJT) if the body diode is conducting (see Fig. 41). Ld

• Immunity of high-side QA and QD gate Cdg drivers to common-mode noise. Lg Cdb • Stable floating supply voltage for QA Rg Parasitic Gate BJT and QD under all conditions, for Driver example by using a bootstrap technique. Rb

This can be done by monitoring the Cgs floating supply voltage and forcing a refresh of the bootstrap capacitor. The Ls technique is particularly useful for the buck operation which requires the duty b. With parasitic BJT. cycle to virtually reach 100%. Fig. 41. MOSFET with parasitic components.

5-24 Hysteretic Amplifier REF +

– VStorage ENABLE

To QC and S Q QA Gate VNEG Current Drive Comparator QC Gate R Drive Vlpk_th + QC Leading- – RSEN_C Edge Blanking

VNEG_P

VNEG

Fig. 42. Peak-current mode during recharge.

limiting. Note that turnoff time delays Vgs_QA (tdel_OFF) and leading-edge blanking result Vgs_QC Inductor Current in a higher peak current (Ipk) than the Ipk programmed threshold (Ipk_th), as shown in Ipk_th Fig. 43. With the constant-OFF-time m2 m1 technique, any current disturbance dies out in one cycle and the current loop is 0A inherently stable. When the capacitors are tdel_OFF DxT fully recharged, the converter operates in s toff_CONT the discontinuous-conduction mode (DCM). Ts In continuous-conduction mode (CCM), Fig. 43. Discontinuous peak-current operation in for example at the beginning of recharge, recharge mode. Topic 5 Topic Ipk_th and toff_CONT always define Ipk_min as shown in Fig. 44. toff_ CONT The PFM technique provides high I efficiency as shown in Fig. 45. The duration pk_th of the sleep interval depends mainly on Ipk_m in I leakage currents. tdel_OFF Hysteretic control means that an t output-voltage ripple is regulated. This is off_ CONT acceptable since only a capacitor bank is at Fig. 44. Peak-current mode with current perturbation. the output. The amount of ripple should be high enough to prevent any erratic behavior related to the capacitors’ ESR. Icaps Sleep Interval

Vcaps VST_th

Fig. 45. PFM operation in recharge mode.

5-25 The total recharge time can be estimated with the equation –1 B1 E Cf_ inal  trech _ tot ≈ (28) i i EL Feed Kff = KxST D K =D  ILpk _ th ×  Forward di × ++ttoffC__ONTdel OFF ,,  Vbus  + – where + 1 d + 1 K1 = K2 =Vi KLC_ZLOAD 1 2  KST xVi  ECCf_ inal = storages× V torageF (29) 2 C o – is the final storage energy, VstorageF is the final  V , and the minimum energy transferred per + storage KEACL V cycle is (Compensation REF 1 and Feedback) EL= × I2 . (30) Lpkt_ h a. Buck voltage-mode-control model in CCM. 2

The leakage currents and the conversion efficiency Vc + PWM are neglected but should be in the equation if Feedforward Compensation Error significant. Ipk_th is used instead of Ipk since tdel_ Oscillator Amplifier V=ramp Output Ramp OFF is hard to predict. In reality, EL is higher, KxST Vi which reduces the recharge time. Also, at the beginning of the recharge, the converter operates Vc

in CCM so that the recharge is faster. It operates in DxTs DCM as soon as Ts

LI× pk < t . PWM Dual-Edge offC_ ONT (31) Modulation Vstorage b. Oscillator ramp and PWM signals. Holdup-Mode Control-Loop Design Fig. 46. Small-signal control model in CCM. Considerations The buck power supply is a pulse-width- cancels Kdi), and block K1 (which cancels K2),

Topic 5 Topic modulation (PWM) fixed-frequency, voltage- ensures that the loop gain stays independent of the mode-control type. A small-signal representation input voltage. This is particularly important since of the control model in CCM is shown in Fig. 46. the storage capacitors’ voltage changes consider­ In this model, Vi and D are the buck input DC ably during a holdup event. voltage and the steady-state duty cycle; ni, d, no, In order to compensate for the double poles and n1 are small-signal variations; and KLC_ZLOAD inherent in voltage-mode control, a type III compen­ represents the output LC filter with load imped­ sation network (Fig. 47), which provides two ance. B1 represents the impact of the duty-cycle zeros, is required. The double-pole frequency is variation, d, on the input voltage, vi, of the buck 1 power supply. Note that B1 is greatly influenced fdp = . (32) 2π×LC by the input-network impedance, which in this b case, includes the storage-bank capacitance. It is also important to pay attention to the zero The output voltage of a voltage-mode-control introduced by the ESR of the bus capacitor (mostly buck is Vo = D × Vi and its small-signal variation is Rd as shown in Fig. 37). Its frequency is proportional to (d × Vi) + (D x ni). Blocks K2 and 1 Kdi show this relationship and how the small- fZc_ ap = . (33) signal behaviour is affected by Vi and ni. The 2π×RCdb× feed-forward effect shown with block Kff (which

5-26 +Vbus The critical load power below which the converter

VREF1 operates in DCM is 2 VVbus ×()storage − Vbus P = . (39) RH crit + Vc 2××LVstorages×f VLD_FB – IV. De s i g n Ex a m p l e : –48-V HVES

RL Ap p l i c at i o n f o r ATCA Us i n g t h e TPS2355 COMP VNEG A. Basic Design Overview Fig. 47. With type III compensation. To illustrate the design of an HVES system (see Fig. 48), a –48-V bus application has been If the effect of V and V is neglected, the overall fA fC selected. The design requirements are (see open-loop gain is shown by Equation (34) below, Fig. 19): where K is the feedforward factor defining the ST • Power output = 250 W maximum constant- ramp amplitude from V , and K (s) is the storage EACL power load compensator gain. The output impedance is • t = 9.3 ms 1 holdup Zsout ()= , • Vbus_min = 44 V, Vbus_max = 72 V KsEACL () 11 ++ (35) • Vload_min = 38 V KL××sZ ()sL×s ST load • Vholdup = 40.5 V ± 1.5 V • Storage voltage = 87.8 V ± 4% where Zload(s) is the total impedance seen by the inductance, mainly the bus capacitance in parallel • Bus capacitance (C7) = 100 μF with 0.1 to with the load, and s = jw, which is based on the 0.25-Ω ESR (including R20) Laplace Transform function. • fs = 300 kHz ±15%

The previous equations (in Section III.B) are If a 25% ripple factor (Krip) at 87.8 V is applicable to CCM. If DCM is used and the effect assumed, the inductance calculation becomes of VfA and VfC is neglected, the duty-cycle 47.%88×()78..VV−−40 51.3V equations then become as follows. L = (40) • MOSFET conduction: 300kHzA×1.543 Topic 5 Topic 2××LP ×f ≈ 47µH D = load s , MOSFET _ DM (36) where the peak-to-peak ripple is defined as ()VVstorage − bus × Vstorage Po IKrip _ pkpk = rip × (41) where Pload is the load power. Vbus • Diode conduction: (See Equation (37) below.) 250 W ==25%× 1.543A • Off period: 40.5V DD3__DM =−1 MOSFET DM − DDIODE _ DM (38)

(34) KsLC ()××KK12()− KBdi × 1()s KsLC () GsVOLE()= KsACL ()× = KEAACL ()s × 1− KK11××ff Bs() KST

2 8××LPload ×fs −+DDMOSFET __DM MOSFET DM + V2 (37) D = bus DIODED_ M 2

5-27

+ µ

+ µ µ

+ µ

 + µ   µ

+ µ k  µ µ µ k  Topic 5 Topic µ k  k  k   k  k  k  k  k  k  k  k  k  k   k  k 

Fig. 48. Example of HVES system for a –48-V/250-W bus application.

5-28 Graph data courtesy of Renco Electronics. www.Rencousa.com Graph data courtesy of BI Technologies. 60 50 45 50 25°C 70°C 40

)

) 35

µH

µH

( ( 40 5% Drop 30 at 7.5 A 125°C 5% Drop 100°C

ance ance 30 at 125°C 25 at 10.8 A at 25°C 20 20

Induct Induct 15 10 10 At 125°C, derate Isatby 30% 5 0 0 0.0 7.2 7.5 7.8 8.1 8.4 8.7 9.3 10.2 10.8 11.1 7 7.5 8 8.5 9 9.5 Current (A) DC Current (A) a. Renco RL-1256-1-47 b. BI Technologies HM00-A7802LFTR Fig. 49. Inductor saturation characteristics.

For 250 W, the Renco RL-1256-1-47 is selected to Note that if a standard 200-W ATCA is needed, provide a margin against saturation at high the small surface-mount Coilcraft DO-5040H-473 temperature and high Vstorage. is a possibility, depending on the maximum temp­ 250 W 1 era­ture (see Figs. 25, 26, and 28) and the storage I ≈+ voltage. However, for a 250-W output, the power Lp_(k max_1) 40.5V 2 (42) losses are as shown in Figs. 20, 21, 29, and 33. ()40..51VV+ 61×()− 45.%4 × = 71. 3A Equation (43) shows the typical core loss for the 47µHk× 255 Hz Renco RL-1256-1-47 from 100 kHz to 500 kHz. If the maximum gate charge, a high temperature,­ 80 V, and 0.47-A and 0.27-A gate-drive currents The BI Technologies HM00-A7802LFTR is are assumed, Equations (44) through (46) apply. another alternative. See Fig. 49.

16. 3 26. 2 (43) Pfcore = 0..1436××()sr()0 1262456× I ip _ pkpk = 26mW at 3000 kHz, Topic 5 Topic

where Pcore is in mW, fs is in kHz, and Irip _ pkpk is in A.

300kHzV×80  6.895A 54. 5A    PQD _SW ≈+××  (()87. 55nC + nC  + 45pF×80VW = 5.794 (44) 2  04. 7 A 02. 7 A   

 1  (45) Pkgdrv =+300 Hz×× 40..52Vn5 Cn××8758CV00 = .,409 W  2 

Q − gs2D tITE__SC3 × Gon Pfrr __tots= ××VIstoragefCT××teES3C (46) 5nC − ≈ 300kHzzV××80 54..53An××99 se 39..90ns × 27A = 26..4 W

5-29 B. Simulation Results 1 Following is a summary of the buck feedback fZ _(cap 250mEΩ SR) = (49) 20πµ××.25Ω 100 F loop design. Graphs of predicted performance (operation in CCM) are shown in Figs. 50–52. = 63. 6kHz The double-pole nominal frequency of the LC The compensation poles and zeros are as filter is follows: 1 fdp _ nom = 1 2π LC× (47) fz ==758Hz (50a) b 21π×RC91× 1 1 ==23..2kHz CC11+ 16 24πµ7 HF×100µ f = = 76.55kHz (50b) p 21π×RC91××11C 6 The bus capacitor’s zero frequency changes with its series resistor: 1 fzi = = 958Hz (51a) 1 25π×()RR+ 18 ×C21 fZ _(cap 100mEΩ SR) = (48) 2π××RCdb 1 1 f ==31.974kHz (51b) = pi 21π×RC82× 1 20πµ××.1Ω 100 F =15.91kHz

50 40 30

) 20

dB

(

in 5 0.25- ESR

Ga 0 0.1- ESR –10

–20 250-W Constant-Power Load

Topic 5 Topic –30 1001k 10 k 100 k Frequency(Hz) a. Power stage and PWM gain.

80 70 60 Error-Amplifier Limit ) 50

dB

( 40 30

ude 20 it Compensation Gain

pl 10 0 Am –10 –20 –30 –40 1 10 100 1k 10 k1100 k 1M 0M Frequency(Hz) b. Compensation-amplifier gain. Fig. 50. Bode plots of system frequency response.

5-30 40 30 20

) 0.25- ESR 10

dB

(

in 0 0.4- ESR

Ga –10 0.1- ESR –20

–30 250-W Constant-Power Load –40 100 1k 10 k1100 k M Frequency(Hz) a. System loop gain.

225

180 ) 0.4- ESR

ees 135

degr 90

e (

as 45 0.1- ESR 0.25- ESR

Ph 0 250-W Constant-Power Load –45 1001k 10 k 100 k1M Frequency(Hz) b. System loop phase margin. Fig. 51. Typical system open-loop gain and phase shows effects of capacitor’s high ESR of up to 0.4 W. Topic 5 Topic 40 30 Open-Loop Zout

) 20

dB

( 10

e 0 –10 –20

Amplitud –30 Closed-Loop Zout –40 –50 250-W Constant-Power Load –60 1001k 10 k 100 k1M Frequency(Hz)

Fig. 52. Typical output impedance with 0.1-Ω Cb ESR and 250-W constant-power load.

5-31 Simulations have been performed on a large- C. Test Results signal average model operating in both CCM and The HVES system discussed has been built DCM. An examples of HVES-system behavior and tested. Fig. 54 shows the transient response during holdup is shown in Fig. 53. during a holdup event. The response matches well with the predictions in Fig. 53. The duty-cycle preset provides a quick response at the beginning of holdup. See Appendix A for more details.

4.0V TPS2355 COMP Output

2.0V

0V

10 A Load Current (2.28 ms, 5.98 A) 5A Inductor Average (4.31 ms, 674.1 mA) Current 0A

46.88 V BusVoltage (3.04 ms, 41.2 V) 43.75 V (616 µs, 40.7 V) (4.92 ms, 40.4 V) (6.53 ms, 39.7 V) 40.63 V (410 µs, 39.9 V) 38.00 V 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 Time (ms) Fig. 53. HVES-system simulation results: buck response with load pulsed between 241 and 27.5 W.

Buck Inductor Current (10 A/div) 4 Topic 5 Topic

Load Current (4 A/div)

3 Vbus (40-V Offset) (2 V/div) 1

TPS2355 COMP Output (2 V/div)

2

Time (2 ms/div) Fig. 54. Transient response of HVES system during holdup. Test used the TI TPS2355, and power load pulsed between 241 and 27.5 W.

5-32 Fig. 55 shows the recharge cycle of the storage- V. Co n c l u s i o n capacitor bank when starting from 0 V. Adaptive The design of an HVES system is complex and soft start is used for adequate inrush current control requires a broad knowledge of power supplies. and the capacitor’s short-circuit protection. As This topic has presented the basics. More details shown in the expanded-time insets, when Vstorage are provided in Appendix A. is very low, the peak-current threshold (Ipk_th) is substantially reduced and the off time (toff_CONT) has increased.

Vstorage (20 V/div)

4

Time (5 µs/div)

4

1

Time (5 µs/div)

4 Flyback Inductor Current (500 mA/div) Topic 5 Topic Time (200 ms/div) Fig. 55. HVES system capacitor recharge cycle with adaptive soft start. Test used the TPS2355 with VIN = 44 V.

5-33 VI. Re f e r e n c e s [8] Jonathan Dodge, Power MOSFET Tutorial, Microsemi, APT-0403 Rev B [1] Bob Mammano and Lal Bahra, “Safety Considerations in Power Supply Design,” TI [9] Vrej Barkhordarian, Power MOSFET Basics, Literature No. SLUP227 IR, AN-1084. [2] “PowerPAD Thermally Enhanced Package,” [10] Kent Walters, Rectifier Reverse Switching TI Literature No. SLMA002A Performance, Microsemi, MicroNote Series 302. [3] Lloyd H. Dixon, JR., “Eddy Current Losses in Transformer Windings and Circuit Wiring,” TI [11] Ray Ridley, “Proximity Loss in Magnetics Literature No. SLUP197 Windings,” Switching Power, Vol. 4, No. 4. [4] Henry W. Ott, Noise Reduction Techniques in [12] Y. Khersonsky, M. Robinson, and D. Gutierrez, Electronic Systems, 2nd ed., John Wiley & The HEXFRED Ultrafast Diode in Power Sons Inc. Switching Circuits, IR AN-989. [5] R.D. Middlebrook, Input Filter Considerations [13] Brian Lynch and Kurt Hesse, “Under the Hood in Design and Application of Switching of Low-Voltage DC/DC Converters,” TI Regulators, IEEE, Oct. 1976. Literature No. SLUP206 [6] John Betten and Robert Kollman, Easy [14] Randy Brandt, “A Generalized Large/Small Calculation Yields Load Transient Response, Signal Average PWM Converter Model,” TI, PCIM, February 2005. Boeing, SAE Technical Paper Series, 1999-01-2597. [7] Thomas Wu and Huu Tran, Dynamic Stresses Can Cause Power MOSFET Failures, IR, [15] Lloyd Dixon, “Magnetic Core Characteristics,” PCIM, April 2000. TI Literature No. SLUP124 Topic 5 Topic

5-34 Ap p e n d i x A. Du t y -Cy c l e Pr e s e t Fu n c t i o n

I. Description of the Problem holdup is critical. One characteristic of a buck During recharge mode, the holdup error topology operating with voltage-mode control and amplifier system loop is not closed, which means feedforward is that the output of the voltage-loop the normal speed of its reaction to a holdup event error amplifier directly defines the operating duty will be inadequate. Fig. 56 shows what happens in cycle. This can be used to achieve immediate such circumstances—the bus voltage goes down to response to a holdup event by presetting the error- 27 V before slowly rising up to 40.5 V. amplifier output while in the recharge mode. Fig. 57 shows a possible implementation of this II. The Duty-Cycle Preset Solution function. The transient response at the beginning of

TPS2355 COMP Output (1 V/div)

3 V=2 58.8 V

V=31.8 V Vbus (40-V Offset) (10 V/div) 1

V=1 27.0 V Buck Inductor Current (10 A/div)

4 Time (1 ms/div)

Fig. 56. Reaction of HVES system if there is no duty-cycle preset function. 5 Topic Test used the TI TPS2355 with R13 uninstalled, Vstorage = 60 V, and power load pulsed between 241 and 27.5 W.

+Vbus Vinp_pos

RH + Vc –

RL

VNEG Error Amplifier Preset Circuit RFB S1 S2 VREF1 5k Rint Fig. 57. Duty-cycle preset circuit.

5-35 During recharge mode, switches S1 and S2 are is the ramp offset. If Vstorage has decreased and is closed, so that the amplifier behaves like an inverter still at 55 V when the next holdup happens, with a gain defined by R and R . During that int FB 42VV+16. time, the compensation capacitors are precharged D ≈ = 78.%84 . (54) for a fast holdup response. This DC feedback is 55VV+ 03. disconnected as soon as the holdup mode begins. The ramp peak-to-peak voltage is 5 V × 55/88 = The equation defining the offset injected by 3.125 V, and Vc_req = (78.84% × 3.125 V) + 0.5 V = the duty-cycle preset circuit (see Fig. 57) is 2.964 V. Equation (52) below. In the duty-cycle equation, Vbus_preset represents The preset voltage provided by the error the target bus voltage for which the error amplifier amplifier is defined independently from the storage gets preset during recharge mode. Vbus_preset does voltage, but it follows the state of the bus voltage. not have to be exactly equal to Vbus, and it may be For example, if V _preset = 40.5 V, R = 5 kΩ, bus int slightly higher. This helps to mitigate the first Vbus RH = 237 kΩ, RL = 25.24 kΩ, VREF1 = 5 V, RFB = undershoot (at the beginning of holdup), which is 4.53 kΩ and Vinp_pos = 3.9 V, then Vc = 2.904 V. influenced by circuit parameters that can vary with If Vbus_preset = 42 V and RFB = 4.12 kΩ, device manufacturing tolerances, temperature, and then V = 2.968 V. c age. However, the Vbus_preset voltage selection On the other hand, because of the feedforward, represents a trade-off because a higher voltage can the required voltage at Vc is constant whatever increase the first overshoot. In the duty-cycle Vstorage may be. This is useful when multiple calculation, 42 V was selected, although a different successive holdup events occur, in which case the value could be used. storage voltage does not have time to reach its Equation (55) below defines RFB. Note that final recharge value before the next holdup event. RFB corresponds to R13 in the schematic of Fig. For example, if Vstorage nominal is 88 V, 48.

VVbus _ presetf++AfV C D = (53) III. Test Results VVstoragef+−CQV D A comparison between Figs. 55 and 56 shows 42VV+16. the effect of using the duty-cycle preset function. ≈ = 49.337%. 88VV+ 03. Figs. 58 and 59 show the performance of the duty- cycle preset function with different R13 (RFB) The ramp peak-to-peak voltage is 5 V, and Vc_req values. Topic 5 Topic = (49.37% × 5 V) + 0.5 V = 2.968 V, where 0.5 V

  1111 Vbus _ preset VREF1  VRcF=+Bi××V np _ pos  ++ −−. (52)   RRHLRRint FB  RH Rint 

VVcr__eq − inp pos RFB = (55)  111  Vbus _ preset VREF1 Vinp _ pos × ++  − −  RRHLRint  RH Rint

5-36 4 Buck Inductor Current (10 A/div)

Load Current (4 A/div)

3 V (40-V Offset) (2 V/div) V=1 41.04 V bus V=2 40.64 V 1 V=400 mV

TPS2355 COMP Output (2 V/div)

2

Time (1 ms/div) a. Power load pulsed between 161 and 27.5 W.

4 Buck Inductor Current (10 A/div)

Load Current (4 A/div)

3 V=2 40.6 V Vbus (40-V Offset) (2 V/div) V=1 41.2 V 1 5 Topic V=600 mV

TPS2355 COMP Output (2 V/div)

2

Time (2 ms/div) b. Power load pulsed between 81 and 27.5 W. Fig. 58. Reaction of HVES system with duty-cycle preset function when test used the TI TPS2355 with R13 = 4.12 kΩ.

5-37 4 Buck Inductor Current (10 A/div)

Vbus (40-V Offset) (2 V/div)

V=2 39.2 V 1 V=1.152 V V=1 40.71 V

Time (1 ms/div) a. Power load pulsed between 241 and 27.5 W.

4 Buck Inductor Current (10 A/div)

TPS2355 COMP Output (1 V/div) Topic 5 Topic

Vbus (40-V Offset) (2 V/div) 2 1

Time (1 ms/div) b. Power load pulsed between 161 and 27.5 W.

Fig. 59. Reaction of HVES system with duty-cycle preset function when test used the TI TPS2355 with R13 = 4.5 kΩ.

5-38