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A Study of Multiprocessor Systems Using the Picoblaze 8-Bit Microcontroller Implemented on Field Programmable Gate Arrays Venkata Mandala

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A Study of Multiprocessor Systems Using the Picoblaze 8-Bit Microcontroller Implemented on Field Programmable Gate Arrays Venkata Mandala University of Texas at Tyler Scholar Works at UT Tyler Electrical Engineering Theses Electrical Engineering Fall 8-2011 A Study of Multiprocessor Systems using the Picoblaze 8-bit Microcontroller Implemented on Field Programmable Gate Arrays Venkata Mandala Follow this and additional works at: https://scholarworks.uttyler.edu/ee_grad Part of the Electrical and Computer Engineering Commons Recommended Citation Mandala, Venkata, "A Study of Multiprocessor Systems using the Picoblaze 8-bit Microcontroller Implemented on Field Programmable Gate Arrays" (2011). Electrical Engineering Theses. Paper 21. http://hdl.handle.net/10950/59 This Thesis is brought to you for free and open access by the Electrical Engineering at Scholar Works at UT Tyler. It has been accepted for inclusion in Electrical Engineering Theses by an authorized administrator of Scholar Works at UT Tyler. For more information, please contact [email protected]. A STUDY OF MULTIPROCESSOR SYSTEMS USING THE PICOBLAZE 8-BIT MICROCONTROLLER IMPLEMENTED ON FIELD PROGRAMMABLE GATE ARRAYS by VENKATA CHANDRA SEKHAR MANDALA A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering David H. K. Hoe, Ph.D., Committee Chair College of Engineering and Computer Science The University of Texas at Tyler August 2011 Acknowledgements First of all, I am thankful to my father Mandala Maheswara Rao and mother Suguna Kumari and sister Geetha Devi for making my dream come true. I would like to thank Dr. David Hoe, my thesis advisor, for his support in my research in different areas of Electrical Engineering. I would also thank him for his encouragement, patience and supervision from the preliminary stages to the concluding level in my thesis. Without his guidance and persistent help this thesis would not have been possible. I would like to thank my committee members, Dr. Hector A. Ochoa and Dr. Mukul V. Shirvaikar for taking the time to review my work. I am thankful to Dr. Mukul Shirvaikar for supporting and guiding me throughout my Master’s degree. I would like to thank the entire Electrical Engineering department and the University of Texas at Tyler for supporting me throughout my Master’s degree. Also, I would like to thank Chris Martinez, an undergraduate student in Electrical Engineering, for helping me in my thesis. Finally, I would like to thank all those who supported me in any respect during the completion of the thesis. Table of Contents List of Figures .................................................................................................................... iv List of Tables ..................................................................................................................... vi Abstract ............................................................................................................................. vii Chapter One: Introduction .................................................................................................. 1 1.1 Soft Processor Cores on FPGA ............................................................................ 1 1.2 Research Objectives ............................................................................................. 2 1.3 Research Method .................................................................................................. 3 1.4 Thesis Outline ....................................................................................................... 3 Chapter Two: Background .................................................................................................. 4 2.1 Trend Towards Multicore Processors ................................................................... 4 2.1.1 Power Wall Problem ..................................................................................... 4 2.2 Multicore Processor .............................................................................................. 7 2.2.1 Array of Processors ....................................................................................... 8 2.2.2 Array of Functional Units ............................................................................. 9 2.3 Reconfigurable Computing ................................................................................ 11 2.3.1 Advantages of Reconfigurable Computing ................................................ 11 2.3.2 FPGAs......................................................................................................... 11 2.3.2.1 Microcontroller within an FPGA ......................................................... 11 2.3.3 Array of Soft Processors ............................................................................. 12 2.3.4 PicoBlaze Microcontroller .......................................................................... 13 2.4 Interprocessor Communication .......................................................................... 15 2.5 Summary ............................................................................................................. 16 Chapter Three: FIFO Style Interprocessor Communication ............................................. 17 3.1 FIFO Style Communication ............................................................................... 17 3.1.1 FIFO ............................................................................................................ 17 3.1.2 PicoBlazes with a FIFO Buffer ................................................................... 19 3.1.3 Experimental Verification of the FIFO with Two PicoBlazes ................... 20 i 3.2 Array of PicoBlazes ............................................................................................ 20 3.2.1 The Wrapper ............................................................................................... 20 3.2.2 Need for an Array of PicoBlaze Units ........................................................ 24 3.2.3 Details of the Array .................................................................................... 25 3.2.4 Routing/Logic Cell Resources Comparison ............................................... 26 3.3 Experiment with Array of PicoBlazes ................................................................ 26 3.3.1 Counting Numbers Experiment .................................................................. 27 3.3.2 Status Signals and Read/Write Strobe Conditions Setup ........................... 27 3.3.3 Validation and Results ................................................................................ 28 3.4 Application (A 4-tap FIR Filter) ......................................................................... 29 3.4.1 Algorithm and Simulation of FIR ............................................................... 29 3.4.2 Array Structural Flow For FIR ................................................................... 29 3.4.3 Validation and Results ................................................................................ 31 3.5 Summary ............................................................................................................. 33 Chapter Four: Shared Memory Inter-Processor Communication ..................................... 34 4.1 Shared Memory .................................................................................................. 34 4.1.1 Shared Memory Mode of Communication ................................................. 34 4.1.2 Sharing BlockRAM Between Two PicoBlazes .......................................... 35 4.1.3 Shared Memory for Communication Between PicoBlaze Processors ........ 36 4.2 Need for an Arbiter ............................................................................................. 36 4.2.1 Arbitration ................................................................................................... 37 4.3 Round-Robin Arbiter .......................................................................................... 37 4.3.1 Implementation of a Round-Robin Bus Arbiter ......................................... 38 4.3.2 Round-Robin Arbiter with Four Processors ............................................... 39 4.4 PicoBlazes Using Round-Robin Arbiter ............................................................ 40 4.4.1 Four PicoBlazes Using Round-Robin Arbiter ............................................ 40 4.4.2 Implementation Description of Shared Memory with Round-robin Arbiter ............................................................................................................................. 40 4.4.3 Observations ............................................................................................... 42 4.5 Summary ............................................................................................................. 43 Chapter Five: Conclusions and Future Work ................................................................... 44 ii 5.1 Conclusion .......................................................................................................... 44 5.2 Future Work ........................................................................................................ 44 References ......................................................................................................................... 46 Appendix A: Assembly Code for Button Press Experiment ............................................. 50 A.1 PicoBlaze 1 to FIFO Assembly Code for Button Press Experiment ................. 50 A.2 FIFO to PicoBlaze 2
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