Awards ................................................................................................................................................................ The 2014 MICRO Test of Time Award Winners: From 1978 to 1992 ONUR MUTLU Carnegie Mellon University RICH BELGARD ......As you may know, the Interna- tions. The two-level control store is tes code-generation choices for correctly tional Symposium on Microarchitecture essentially two carefully codesigned pro- and efficiently optimizing instruction (MICRO)—the flagship microarchitecture grammable logic arrays (PLAs) that schedules of loops for various architec- conference, and a premier computer together comprise more compact stor- tures, including very long instruction word architecture conference for nearly five age for microinstructions than a single (VLIW) and superscalar. The paper covers decades—selected 10 papers as recipi- monolithic control store. It was born architectures incorporating a varying set ents of the first set of MICRO Test of from the necessity to “maximize the of features for loop schedule optimiza- Time (ToT) Awards in December 2014. contribution of every transistor spent” tion, using the notions of software pipelin- We announced the winning papers and (to quote Tredennick’s retrospective) in ing and modulo scheduling. The work is described the selection process in the the design of the Motorola MC68000 based on the authors’ extensive (about a March/April 2015 issue of IEEE Micro.1 processor. The paper also described in decade long) experience in hardware/soft- The authors of these 10 distinguished detail the microprogrammed control logic ware codesign for realizing Cydrome’s papers were invited to write short retro- implementation of a single-chip micro- Cydra 5 processor. Yet, the paper’s loop spectives to reflect on their work, which architecture, based on the MC68000 code scheduling strategies apply far was done at least 20 years ago. This experience. In his retrospective, Treden- beyond the extensive architectural sup- issue features retrospectives written by nick describes his experience at Motor- port provided by the Cydra 5 for loop the original coauthors of two of the ola that led to this paper and discusses scheduling purposes, as Schlansker’s ret- award-winning papers. We briefly intro- his subsequent experiences in industry, rospective beautifully describes. duce these papers and retrospectives, which were partially shaped by his and we hope that you will enjoy reading involvement with the MC68000. He also s we conclude, we would like to them as much as we have. muses about the connection between A take the opportunity to pay tribute The first retrospective is for the old- design and design automation proc- to the extremely valuable impact that est paper that won the 2014 MICRO ToT esses, which makes the retrospective a Bob Rau has had in our field, especially in Award. “Microprogrammed Implemen- fun historical perspective and a delightful the development of compiler technology tation of a Single Chip Microprocessor” read for the IEEE Micro audience. and VLIW processors, as well as hard- by Skip Stritter and Nick Tredennick was The second retrospective is for one of ware/software cooperation in instruc- published in MICRO 1978.2 It introduced the youngest papers that won the 2014 tion-level parallelism. It has been 13 the idea of a two-level control store (text- MICRO ToT Award. “Code Generation years since Bob died, but his impact is book material in computer architecture Schema for Modulo Scheduled Loops,” wonderfully felt in the compiler technol- today) with the goal of minimizing the authored by Bob Ramakrishna Rau, ogy commonly in use today, along with chip real estate dedicated to the control Michael S. Schlansker, and P.P. Tirumalai, the many clearly articulated technical logic used in microprogrammed pro- was published in MICRO 1992.3 The articles he contributed to academic litera- cessor designs, and in particular the paper provides a “recipe book” (to quote ture. His works are taught in many mod- memory used to store the microinstruc- Schlansker) that discusses and enumera- ern compiler and computer architecture ....................................................... 60 Published by the IEEE Computer Society 0272-1732/16/$33.00 c 2016 IEEE classes today. Bob was one of the most the scaling of the underlying circuit and 3. B. Ramakrishna Rau, Michael S. prominent contributors to MICRO for device technologies. MICRO Schlansker, and P.P. Tirumalai, “Code decades, and our selection of the 1992 Generation Schema for Modulo Sched- article, for which he was the primary ............................................................ uled Loops,” Proc. 25th Ann. Int’l Symp. driver (according to Schlansker’s retro- References Microarchitecture, 1992, pp. 158–169. spective), as part of the first set of 1. O. Mutlu and R. Belgard, “Introducing the MICRO Test of Time Awards: MICRO ToT Awards points to the techni- Onur Mutlu is the Strecker Early Career Concept, Process, 2014 Winners, and cal excellence and value of insight he Professor at Carnegie Mellon Univer- the Future,” IEEE Micro, vol. 35, no. upheld as a leading member of our com- sity. Contact him at [email protected]. munity. We hope these two key values 2, 2015, pp. 85–87. continue to thrive as microarchitecture/ 2. S. Stritter and N. Tredennick, Rich Belgard is an independent consul- architecture and hardware/software “Microprogrammed Implementation tant for computer manufacturers, soft- codesign become even more important of a Single Chip Microprocessor,” ware companies, and investor groups with fundamental challenges threatening Proc. 11th Ann. Workshop Microprog- and an expert and consultant to law firms. the large improvements obtained from ramming, 1978, pp. 8–16. Contact him at [email protected]. .............................................................................................................................................................................................. Evolution of Microprocessor Logic Design NICK TREDENNICK Jonetix ......In the summer of 1977, I was wanted me to work on the design of the The microprocessor’s entire design had teaching as an assistant professor at the on-chip cache, but that he first needed to fit on a single power-, pin-, and transis- University of Texas in Austin when Tom me to begin work on the microproces- tor-constrained, size-limited silicon chip. Gunter walked into my office and intro- sor’s logic design “until we find a compe- All of the microprocessor’s comput- duced himself. He asked if I’d like to work tent logic designer.” Of course, that ing resources (data registers, address for Motorola on a microprocessor design never happened, and I spent my time registers, program counter, and arith- project. My areas of expertise were com- doing the logic design for what became metic units), interrupt logic, interface puters and logic design, and I had a little the MC68000. logic (pin and external bus control), and experience with microprocessor applica- I began looking for books and articles control logic had to fit inside the transis- tions, but no experience with microproc- on microprocessor logic design. I was tor, area, and power budget. Since we essor design or semiconductor design. unable to find documentation for any began by doubling or more than doubling Nevertheless, there was mutual interest microprocessor logic design methods. the width of the data and address regis- and I took a job with Motorola beginning That seemed odd, given that the Design ters and the arithmetic units, as well as in September 1977. The project was a Automation Conference was already 14 substantially increasing the number of next-generation microprocessor design years old in 1977. Just what processes data and address registers compared to called MACS (Motorola Advanced Com- were all those software engineers auto- an 8-bit accumulator-based design, we puter System). Motorola’s previous mating? Well, OK, I’d have to make up quickly ate into the transistor-budget microprocessor designs had been 8-bit the design process as I went along. increases provided by our move to the accumulator-based designs suitable for At the time, the biggest differences next most advanced semiconductor embedded applications; MACS was to be between computer design and micro- process. The consequence of these a 16-/32-bit design more suitable for com- processor design were in the constraints decisions was that, in the implementa- puter applications. Tom said he eventually placed on the microprocessor’s designer. tion of the control logic, we had to ............................................................. JANUARY/FEBRUARY 2016 61 .............................................................................................................................................................................................. AWARDS maximize the contribution of every tran- sequences. One instruction decoder First, I decided to make a list of the prob- sistor spent. pointed to the operand address calcula- lematic design decisions that I had made In 1977, moving to the next semicon- tion sequence and a second pointed to during the project, so that I could avoid ductor process meant designers had the required operation sequence. The those errors in the next design. Second, somewhat more than twice the number of address calculation sequence computed because available design tools did not transistors enabled by the previous-genera- the operand address and sent a request support