WCAE 2003

Proceedings of the Workshop on Computer Architecture Education

in conjunction with

The 30th International Symposium on Computer Architecture

DQG

2003 Federated Computing Research Conference

Town and Country Resort and Convention Center b

San Diego, California

June 8, 2003

 Workshop on Computer Architecture Education Sunday, June 8, 2003

Session 1. Welcome and Keynote 8:45–10:00 8:45 Welcome Edward F. Gehringer, workshop organizer 8:50 Keynote address, “Teaching and teaching computer Architecture: Two very different topics (Some opinions about each),” Yale Patt, teacher, University of Texas at Austin 1 Break 10:00–10:30 Session 2. Teaching with New Architectures 10:30–11:20 10:30 “Intel Itanium floating-point architecture,” Marius Cornea, John Harrison, and Ping Tak Peter Tang, Intel Corp...... 5 10:50 “DOP — A CPU core for teaching basics of computer architecture,” Miloš BeþváĜ, Alois Pluháþek and JiĜí DanƟþek, Czech Technical University in Prague ...... 14 11:05 Discussion Break 11:20–11:30 Session 3. Class Projects 11:30–12:30 11:30 “Superscalar out-of-order demystified in four instructions,” James C. Hoe, Carnegie Mellon University ...... 22 11:50 “Bridging the gap between undergraduate and graduate experience in computer systems studies,” Lori Carter and Scott Rae, Point Loma Nazarene University ...... 28 12:05 “Integration of computer security laboratories into computer architecture courses to enhance undergraduate curriculum,” Jayantha Herath and Ajantha Herath, St. Cloud State U. and U. of Dubuque ...... 36 12:20 Discussion Lunch 12:30–2:00 Session 4. Teaching Techniques 2:00–3:30 2:00 “Combining learning strategies in a first course in computer architecture,” Patricia Teller, Manuel Nieto, and Steve Roach, U. of Texas at El Paso ...... 41 2:25 “Building resources for teaching computer architecture through electronic peer review,” Edward F. Gehringer, North Carolina State University ...... 49 2:40 “Laboratory options for the computer science major," Christopher Vickery and Tamara Blain, Queens College of CUNY ...... 57 2:55 “Activating computer architecture with Classroom Presenter,” Beth Simon, U. of San Diego; and Richard Anderson and Steven Wolfman, U. of Washington ...... 64 3:15 Discussion Break 3:30–4:00 Session 5. Simulation Environments 4:00–5:40 4:00 “The Liberty simulation environment as a pedagogical tool,” Jason Blome, Manish Vachhajarani, Neil Vachhajarani, and David I. August, Princeton University ...... 72 4:25 “Multimedia components for the visualization of dynamic behavior in computer architectures,” Peter Marwedel and Brigit Sirocic, U. of Dortmund ...... 79 4:40 “Didactic architectures and simulator for network processor learning,” Henrique Cota de Freitas and Carlos Augusto P. S. Martins, Pontifical Catholic U. of Minas Gerais ...... 86 5:00 “On the introduction of reconfigurable hardware into computer architecture education,” Ross Brennan and Michael Manzke, Trinity College, Dublin ...... 96 5:15 “Use of HDLs in teaching of computer hardware courses,” Zvonko Vranesic and Stephen Brown, U. of Toronto ...... 103 5:30 Discussion

Teaching and Teaching Computer Architecture: Two Very different topics (Some Opinions about each)

Yale N. Patt teacher, The University of Texas at Austin

Abstract Distance Learning produces better education, not cheaper education

This year’s Computer Architecture Education work- We pay teachers enough that those who would opt shop is remarkable in its recognition that to teach com- for this career don’t opt for medical school instead puter architecture well, one has to pay attention to two things (a) teaching and (b) computer architecture. Hav- We teach high school English teachers enough En- ing been doing both for a good number of years, I har- glish that students at the University can write two bor a fair number of opinions on what one should do consecutive coherent sentences and what one should not do with respect to each. This We get past this insane preoccupation with political talk will get into some of those opinions. With respect correctness, so we can get on with the business of to teaching, I will discuss some of my Ten Command- teaching and learning ments of Good Teaching, what I think of distance learn- We stop canonizing the use of high tech education. ing, political correctness, emphasis on memorization, the Bad pedagogy is NOT good pedagogy if draped in inability of American students to write English, the value technology of having students study in groups, and what I feel is of- ten the sad misuse of technology. Most importantly, I We stop rewarding memorization ability, so maybe will discuss my motivated bottom up approach to learn- students will learn to think,...and perhaps under- ing. With respect to teaching computer architecture, I stand believe the single most important point to get across is that computer architecture, if it is a science at all, is a Figure 1. Visions (Re: Education) science of tradeoffs. The student is best served if he/she thoroughly understands the fundamental principles so as to be able to make the appropriate tradeoffs in reaching a particular design objective. I also plan to discuss the The remaining figures deal with the two parts of my use (and too often, misuse) of measurements, simulation, talk, a focus on teaching, and a focus on teaching com- and real ISAs as opposed to concocted ISAs. puter architecture.

1 Introduction I have been asked to provide copies of the transparen- 2 Focus on Teaching cies I will use in my Keynote Address. I have added Teaching involves at least three things: how to teach some annotated text to hopefully provide some context. (Section 2.1), what to teach (Section 2.2), and what aids Knowing from past experience that the dynamic to use in the process (Section 2.3). schedule of my talks usually bears only casual resem- blance to the static schedule that I prepared ahead of time, I provide these copies somewhat timidly. Figure 1 is from a talk I gave last fall at the annual 2.1 My Ten Commandments of Good Teaching Visions Lecture of the Computer Sciences Department Someone suggested I come up with a set of command- at The University of Texas at Austin. The subject was ments for good teaching. For historical reasons, they Education. I was asked to give my dream for an ideal thought ten would be a good number. So, I set out to future with respect to education. do it, and came up with nine. Ergo, note the tenth one. On sober reflection, that one in itself is a tenth command-

1 ment. So, the list on Figure 2 really does contain ten, not nine as some have commented.

Know the material

Want to teach

Genuinely respect your students and show it

Set the bar high; students will measure up

Emphasize understanding; de-emphasize memo- rization

Take responsibility for what is covered

Don’t even try to cover the material

Encourage interruptions; don’t be afraid to digress

Don’t forget those three little words

Reserved for future use

Figure 2. My Ten Commandments of Good Teaching Figure 4. My motivated bottom-up ap- proach 2.2 Emphasis on the Fundamentals My emphasis on teaching the fundamentals has been ”Aha!” happens. How well someone can do that depends part of me forever. No doubt my PhD students get tired on how well that person has mastered the fundamentals. of hearing about it. For example, I believe that an ap- My views crystallized particularly strongly with the propriate PhD qualifier is not a written test on some ad- development of our ”new” introduction to computing, vanced course in the graduate curriculum, but rather an which we first developed at Michigan in the mid-90s[1] oral exam on the fundamental concepts found in relevant and later turned into a textbook, published by McGraw- senior level undergraduate courses. Hill[2]. My view of what is important is expressed in My view is simple: research, development, prob- Figure 3. More specific detail of the motivated bottom- lem solving are all about breaking problems down into up approach is shown in Figure 4. small pieces and working with the small pieces until the 2.3 High Tech in the Classroom

Top-down design, Bottom-up learning for under- There seems to be a preoccupation with using tech- standing nology in the classroom. Certainly, there is much that can be done with technology to improve learning. I am Abstraction is vital, but... concerned that in our leap to technologize everything, we Not bottom-up, but ”motivated” bottom-up are developing some very bad pedagogy under the um-

Engineering is about DESIGN, first understand the brella of ”using technology.” Figure 5 shows some com- components mon uses. Figure 6 lists some serious concerns. From Concrete to Abstract (Dijkstra notwithstand- 3 Focus on Teaching Computer Architec- ing) ture Cut through protective layers We are lucky. We get to teach computer architecture. Memorizing is not understanding Some will tell you that computer architecture is dead,

Students do better working in groups that the microprocessor is to computing like a brick is to buildings. Wrong. Computer architecture is the in- Figure 3. Some thoughts on what is impor- terface between what technology can provide and what tant the marketplace demands. Technology continues to pro- vide more and more. We are told that within a very few

2

Email

The transformation hierarchy

Web site

Three parts of a Microarchitecture

Power Point

The DSI

Document Reader

IPC vs. cycle time

Animations

Partitioning Plato, vintage 2003

Clever attendance mechanism Figure 7. Some fundamentals of computer

Other bookkeeping architecture

Text+Voice (WOW Factor, see Shriver’s CDROM)[3]

Figure 5. Some uses of high tech Problems

Algorithms

Baseline Power Point Programs

Cost ISA

Extemporaneous Effect Microarchitecture

Visual/voice disconnect Circuits

Attendance vs. Participation Devices

Figure 6. Some caveats associated with us- Figure 8. Levels of Transformation ing high tech

years, each chip will contain more than a billion transis- Instruction Perfect I−Cache tors. And the marketplace continues to demand more. In Supply No Packet Breaks fact, the higher and high performance chip becomes an 100% Br. Pred. important enabler. As we develop more, the marketplace dreams of more things it needs. Contrary to being dead, computer architecture is in Perfect Data Flow a constant state of high volatility. The state-of-the-art Data Path Irregular Parallelism examples we studied yesterday are boring today. Enough Functional Units Computer architecture will always be alive and Perfect Intraconnect healthy as long as people continue to dream up new needs for our future products. The design points may change. Not just higher performance, but higher reliabil- Data Supply Data when needed ity, availability, cheaper cost, and more power-sensitive designs, for example. Within that framework, what do we teach. In my view, we focus on three things: the fundamental princi- Figure 9. The Microarchitecture ples (which do not change, or change very, very slowly), the tradeoffs that always result, and the concrete imple- mentation of those principles. Figure 7 identifies a number of the fundamentals, Fig- Focus on Measurements ure 8 (levels of transformation) and Figure 9 (three parts Use of Simulation

of a microarchitecture) elaborate on two of them. Fig- Real ISA vs. Concocted ISA ure 10 lists some concerns. Figure 10. Some concerns

3 the new data path

internal fault tolerance

asynch and synch co-existing

different cycle times for different functions

SSMT (aka helper threads)

Block-structured ISA

uarch support for CAD

greater use of microcode

greater impact of the compiler

compiler/uarch communication

Figure 11. The Microprocessor ten years from now (perhaps)

Finally, because a course in Computer Architecture is not only about what is, but also about preparing the stu- dent for what will be, it should also give our best current guess into the future (see Figure 11).

References [1] Y. N. Patt. The First Computing Course for CS, CE, and EE Majors at Michigan. In The Interface, pages 1–3, November 1998. [2] Y. N. Patt and S. J. Patel. Introduction to Computing Sys- tems: From Bits and Gates to C and Beyond.McGraw- Hill, 2001. [3] B. D. Shriver and B. Smith. The Anatomy of a High Per- formance Microprocessor: A Systems Perspective. IEEE Computer Society Press, 1998.

4 Intel® Itanium® Floating-Point Architecture Marius Cornea, John Harrison, and Ping Tak Peter Tang Intel Corporation Abstract Itanium 2 processor, increased the performance level of the Itanium processor by a factor of 1.5 to 2 in several cases. The Intel® Itanium® architecture is increasingly becoming one of the major processor architectures Itanium processors target the most demanding present in the market today. Launched in 2001, the Intel enterprise and high-performance computing Itanium processor was followed in 2002 by the Itanium applications, addressing the growing needs for data 2 processor, with increased integer and floating-point communications, storage, analysis and security, while performance. Measured by the SPEC CINT2000 also providing performance, scalability and reliability benchmarks, the Itanium 2 processor still trails by about advantages at significantly lower costs than before. 25% the Intel P4 processor in integer performance, Common desktop applications have no immediate need albeit P4 runs at more than three times Itanium’s clock for the computing power or addressing capabilities of a frequency. However, its floating-point performance 64-bit processor, but an increasing number of mid- clearly leads in the SPEC CFP2000 charts, and its range and high-end applications already do, or will rating is about 25% higher than that of the P4 soon, require such capabilities. These are mainly processor. While the general features of the Itanium programs that demand a lot of memory space and/or architecture such as large register sets, predication, perform a large amount of computation. Examples speculation, and support for explicit parallelism [1] include applications accessing large databases or have been presented in several papers, books, and delivering Internet content, programs that use 64-bit mainstream college textbooks [2], its floating-point long integers, and data-intensive applications solving architecture has been less publicized. Two books, [3] scientific and engineering problems. Itanium processor and [4], cover well this area. The present paper focuses features that benefit the latter category will be the focus on the floating-point architecture of the Itanium of the present paper. processor family, and points out a few remarkable features suitable to be the focus of a lecture, lab session, Scientific and engineering applications that can take or project in a computer architecture class. advantage of the increased floating-point performance of Itanium processors include among others quantum chromodynamics (QCD), quantum mechanics, Introduction molecular simulation, cell research, or new drug discovery applications, computer-aided design tools, The performance of today’s processors continues to and solvers for large equation systems used in a variety increase. But the physical limits for the manufacturing of scientific and technical problems. Digital content technology will eventually be reached, rendering creation applications that require high bandwidth, large Moore’s Law inapplicable. Substantial further advances memory, and powerful floating-point performance are can be attained only by allowing a processor to operate also going to benefit from running on Itanium on more bits at a time, and to execute more instructions processors. Such applications can run very slowly on in parallel. This was the motivation that led to the workstations based on 32-bit processors because of the design of the Itanium processor family. Based on the smaller data item size, and also because of the EPIC (Explicitly Parallel Instruction Computing) continuous data traffic between storage disks and the design philosophy [5], the Itanium architecture was co- memory system. Reduced swapping between memory developed by Intel Corporation and Hewlett-Packard and disk on Itanium-based systems are likely to Company, combining the best in the RISC and VLIW increase performance of some applications by up to two architectures, while also adding several features orders of magnitude. originating from recent research studies in processor architecture. The result is a processor architecture that can handle a large amount of work based on its ability Itanium Floating-Point Architecture to feed instructions quickly to several execution units. The Itanium floating-point architecture has been To date, two implementations of the Itanium designed to combine high performance and good architecture have been introduced by Intel Corporation. accuracy. A large floating-point register set of 128 The Itanium processor provided hardware man- registers is provided, and almost all operations can read ufacturers and software writers with a first development their arguments from, and write their results to, vehicle. The second implementation, represented by the

5 arbitrary registers. Together with register rotation for affect the exponent range, as the exponent uses a 15-bit software-pipelined loops, this large number of registers field until the number is actually written back to allows the encoding of common algorithms without memory. Although the greater exponent range is running short of registers or needing to move data normally advantageous, it can lead to subtle variations between them in elaborate ways. Registers can store in underflow and overflow behavior depending on floating-point numbers in a variety of formats, and the exactly when a result is written to memory (which may rounding of results is determined by a flexible be compiler-dependent and hard to predict). combination of several selectable defaults and In order to maintain the useful extra exponent range but additional instruction completers. allow the user complete control over rounding, the The basic arithmetic operation, the floating-point Itanium architecture allows for both conventional single multiply-add (fused multiply-add), allows higher and double precision formats and formats with the same accuracy and performance in many common precision but a 15-bit exponent field. In addition, a still algorithms. Several additional features are also present wider exponent field of 17 bits is provided in each case, to support common programming idioms. The fused a very useful feature for intermediate calculations with multiply-add operation combines two basic floating- double-extended precision numbers. This means that point operations in one, with only one rounding error. there are actually eight floating-point formats directly Besides the increased accuracy, this can effectively supported by the Itanium architecture, shown in Table double the execution rate of certain floating-point 3-1. calculations, as the fused multiply-add operation forms an efficient computation core that maps perfectly to Table 3.1. Floating-Point Formats Available in the several common algorithms used for technical and Itanium Architecture scientific purposes. The fused multiply-add operation Format Precision Exponent Exponent creates the possibility of implementing new algorithms, Bits Range such as software-based division and square root Single 24 8 operations. As execution units are pipelined, a division –126 to or square root operation does not block the floating- 127 point unit for the entire duration of the computation, Double 53 11 –1022 to and several other operations can be initiated or carried 1023 out in parallel. Double 64 15 –16382 to extended The large number of floating-point registers available, 16383 of which some are static and some are rotating, allows IA-32 24 15 –16382 to for efficient implementation of complicated floating- stack 16383 point calculations. An illustration of software and single hardware interaction in the Itanium architecture, this is IA-32 53 15 –16382 to achieved on one side by avoiding frequent accesses to stack 16383 memory, and on the other through software pipelining double of loops containing floating-point computations. For Register 24 17 example, the throughput for division operations can be –65534 to single as high as one result for every 3.5 clock cycles on the 65535 Itanium and Itanium 2 processors. Register 53 17 –65534 to double 65535 Floating-Point Formats Register 64 17 –65534 to 65535 The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [6] mandates precisely defined floating- point formats referred to as single precision and double Register and Memory Encodings precision. As well as these IEEE-mandated formats, Intel architectures have traditionally supported a The Itanium architecture specifies 128 floating-point double-extended precision type, with 64 bits of registers f0, f1, ..., f127. Register f0 is hardwired to precision and a 15-bit exponent field. In current IA-32 +0.0 and f1 to +1.0, and both are read-only, but all implementations, results computed in the floating-point other registers are available for reading and writing. register stack may be rounded to 24, 53 or 64 bits of Each register is 82 bits long, with a 64-bit significand precision. Although the first two precisions coincide (using an explicit integer bit), a 17-bit exponent field with the IEEE single and double precision, the and a 1-bit sign. The exponent bias has the value 65535, precision control setting in IA-32 processors does not or 0xFFFF (hexadecimal).

6 Certain values, such as NaNs, are neither negative nor computations that encounter failed speculative loads, positive. Special encodings, such as zeros, infinities, has an encoding as an otherwise unused positive pseudo-zeros, pseudo-denormals, NaNs, pseudo-NaNs, floating-point number: positive sign, biased exponent of pseudo-infinities, or NaTVal are all possible. Some of 0x1FFFE and significand of 0 (a pseudo-zero). Second, these special categories are explained below. encodings with a positive sign and a biased exponent of 0x1003E (corresponding to the unbiased decimal value The minimum (biased) exponent value of 0 is reserved of 64) are used also for canonical integers, and for for double-extended real denormalized numbers 1 (denormals), and for pseudo-denormals. The maximum SIMD floating-point numbers (pairs of 32-bit single precision numbers). These are stored in the significand (biased) exponent value of 131071, or 0x1FFFF, is reserved for special numbers such as infinities and portion of a floating-point register. NaNs. The register encoding used differs from the encoding used when floating-point values are stored in memory. Other exponent values, between 0 and 0x1FFFE in biased form, are used for finite numbers. The value in a Single precision and double precision floating-point floating-point register with sign s, biased exponent e numbers are stored in the memory format specified by the IEEE Standard, with exponent biases of 127 (0x7F) and significand m0m1m2…m63 is determined by the following formula for biased 17-bit exponents between and 1023 (0x3FF) respectively, and no explicit integer 1 and 0x1FFFE: bit. Double-extended and register format numbers are stored in a more direct mapping of the register contents s e–65535 (–1) ˜ 2 ˜ m0.m1m2…m63 (the exponent bias for double-extended values is and the following for biased exponents that are zero: 0x3FFF). s –16382 For example, the value of a single precision floating- (–1) ˜ 2 ˜ m .m m m 0 1 2… 63 point number with sign s, biased exponent e and The register encoding is redundant: the same real value significand m0m1m2…m23 stored in memory is can sometimes be represented in several different ways. determined by the following formula for biased 8-bit This is a consequence of the presence of an explicit exponents between 0x1 and 0xFE: integer bit, and is true of all floating-point formats that s e–127 support it. For example, one can have positive pseudo- (–1) ˜ 2 ˜ m0.m1m2…m23 zeros with significand equal to zero but exponent from and the following for biased exponents that are zero: 0x000001 to 0x1FFFD rather than zero. Most of these s –126 alternative representations of the same number are (–1) ˜ 2 ˜ 0.m1m2…m23 equally acceptable as inputs to floating-point For double precision values, the exponent bias to operations, the only exceptions being the unsupported subtract from the exponent e is 1023, and denormals numbers with exponent 0x1FFFF and integer bit 0 have an exponent of –1022. For double-extended (pseudo-infinities and pseudo-NaNs). In particular, the precision values, the exponent bias is 16383, and user can freely operate on arguments of mixed format denormals have an exponent of –16382. without any time-consuming format conversions. This is often useful, especially when: Status Fields and Exceptions Using double-extended intermediate precision x Given the number of floating-point formats available in calculations to compute a double precision function. the Itanium architecture, it is important to have a The double precision input argument can be freely flexible means of specifying the desired floating-point combined with double-extended intermediate results. format for a particular result to be rounded into, as well x Computing functions involving constants with few as the direction of rounding (e.g. rounding to nearest or significant digits. Whatever the precision of the truncation). Moreover, in accordance with the IEEE computation, the short constants can be stored in single Standard, floating-point operations on the Itanium precision. architecture not only produce results, but may optionally trigger exceptions or record exceptional However, results of floating-point operations, and conditions by setting sticky status flags. It would be floating-point values loaded from memory, are always impractical to encode all this information into the mapped to fixed canonical representatives in the register. 1 Note that the subsets of positive and negative register SIMD is an acronym for Single Instruction and format numbers are almost symmetrical, with only two Multiple Data, a form of parallel computing in exceptions. First, NaTVal, the special Not a Thing which one operation is performed in parallel on Value quantity used to track floating-point multiple sets of operands.

7 format of each instruction, so some global status and The pc and wre fields together determine the floating- control word is necessary for specifying options as well point format into which the result will normally be as recording exception flags. On the other hand, having rounded. The rounding control rc determines the IEEE only a single record would be inconvenient where there rounding mode. are several parallel threads of control, or where Although the status fields determine the default exceptions in some intermediate instructions need to be rounding behavior of operations, it is often possible to ignored. Therefore, the Itanium architecture features override them by explicit completers. This applies, for four different status fields which can be specified by example, to many of the instructions to be discussed completers in most floating-point instructions. An below. If an instruction has an explicit .s or .d instruction with a given status field completer is then completer, then the destination format is single or controlled by, and records certain information in, that double precision respectively, except if the wre flag is status field. set, in which case register single or register double is A 64-bit Floating-Point Status Register (FPSR) used. controls floating-point operations and records Software conventions for the FPSR determine many of exceptions that occur. The FPSR contains 6 trap dis- the appropriate applications for particular status fields. able bits that control which floating-point exception Typically, s0 is the main user status field used for most conditions actually result in a trapped exception (where floating-point calculations. Status field s1, with wre control passes to the OS and possibly to a user handler), enabled and all exceptions disabled, is used for and which are merely recorded in sticky status flags. intermediate calculations in many standard numerical These bits control the five IEEE Standard exceptions: software kernels such as those for division, square root, invalid operation (vd), division by zero (zd), overflow and transcendental functions. Status fields s2 and s3 are (od), underflow (ud) and inexact result (id), as well as also commonly used for speculation. The default setting the additional denormal/unnormal operand exception of the FPSR is such that all status fields use the 64-bit (dd), which occurs if an input to a floating-point precision, the round-to-nearest rounding mode, and instruction is an unnormalized number. In addition to have floating-point exceptions and the flush-to-zero this field, the FPSR contains four 13-bit status fields, mode disabled. Only status field s1 uses the widest- denoted in the assembly language syntax by s0, s1, s2 range exponent. and s3. Each status field can be divided into two parts: flags The Floating-Point Multiply-Add and controls. The six flags are bits that record the occurrence of each of the 6 exceptions mentioned In most existing computer architectures, there are above, when exceptions are masked, or, for the separate instructions for floating-point multiplication overflow, underflow or inexact result exceptions, also and floating-point addition. In the Itanium architecture, when they are enabled (unmasked). These flags are these are subsumed by a more general instruction, the sticky, meaning that later operations that do not cause floating-point multiply-add or fused multiply- exceptions will not set flags back to 0, so the accumulate, which takes three arguments, multiplies occurrence of an exception anywhere in a computation two of them and adds in the third. The basic assembly sequence will be apparent at the end of that sequence. syntax is: Of the control part, one bit (td) allows all exceptions to (qp) fma.pc.sf f = f , f , f be disabled irrespective of the individual trap disable 1 3 4 2 bits from the FPSR (often useful in intermediate which sets f1 = f3 ˜ f4 + f2. Note that no intermediate calculations). The remaining 6 bits control the rounding rounding is performed on the result of the mode, precision and exponent width, and the flushing to multiplication, and the result is written to f1 as if it were zero of tiny2 results. first computed exactly and then rounded, in a natural extension of the way conventional arithmetic operations are specified to behave in the IEEE Standard. The rounding of the result and the triggering of exceptions

2 is controlled by the status field specified by the sf The IEEE Standard allows for two methods of completer and possibly by the FPSR trap disable bits, determining whether a result is tiny. Intel except that the rounding precision from sf may be architecture processors choose to define a result overridden by an optional precision control completer as being tiny if the exact value rounded to the pc. destination precision while assuming an unbounded exponent is less than the smallest Since the floating-point registers f0 and f1 are normal value that can be represented in the hardwired to the values +0.0 and +1.0 respectively, given floating-point format. addition and multiplication can easily be implemented

8 as special cases of the fma: x + y = x˜1 + y and x ˜ y = Now consider the case when the result of an fma x˜y + 0. In fact, the floating-point addition and instruction without rounding is exactly zero. Normally, multiplication assembly instructions the sign of x ˜ y + z is determined by multiplying the signs of x and y to give a sign for the intermediate (qp) fadd.pc.sf f = f , f 1 3 2 result, then using the rules of the IEEE Standard, (qp) fmpy.pc.sf f1 = f3, f4 treating w + z as if it were an ordinary sum. However, are simply pseudo-operations that expand into this is not appropriate for considering the ordinary product a special case of the fma. For example, (+1.0) (qp) fma.pc.sf f = f , f1, f ˜ 1 3 2 (– 0.0) + (+0.0) would give +0.0, whereas the IEEE- (qp) fma.pc.sf f1 = f3, f4, f0 specified product is (–0.0). This difficulty is respectively. In order to change signs, there are two circumvented as follows: if the third argument to the variants of the fma: the fms (floating-point multiply- fma is actually register zero (f0), then the sign of zero is subtract) and fnma (floating-point negative multiply- determined by the IEEE rules for products. Otherwise, add). The instructions the sign of zero results is decided as specified above for fma, even if the third argument to fma is not the special (qp) fms.pc.sf f = f , f , f 1 3 4 2 register zero f0 but nevertheless contains the value zero. (qp) fnma.pc.sf f1 = f3, f4, f2 This applies equally to the variants fms and fnma. compute f1 = f3 ˜ f4 – f2 and f1 = –f3 ˜ f4 + f2 respectively. A floating-point multiply-add is a very valuable Floating-point subtraction architectural feature, for reasons of both speed and

(qp) fsub.pc.sf f1 = f3, f2 accuracy. In typical implementations, the final addition can be combined into the floating-point multiplication is likewise a pseudo-operation for operation without significantly increasing its latency.

(qp) fms.pc.sf f1 = f3, f1, f2 Thus, a single fma is faster than a multiplication and an addition executed successively. Since additions and An even more degenerate instance of fma, called fnorm multiplications are heavily interleaved in many (floating-point normalize) can be used to round a result important floating-point kernels (the evaluation of into a given floating-point format. This can be used as a inner, or dot, products of vectors or the evaluation of ‘lowering’ operation to convert a value to a smaller polynomials for example), the use of an fma can lead to floating-point format, but the most common use is just significant performance improvements. For example the to ensure that the number is normalized. (This is often useful, because processing unnormalized values is vector dot product x ˜ y: N-1 slower in most cases than performing an fnorm p = ¦i=0 xi ˜ yi followed by the intended operation.) This rounding to a can be evaluated by a succession of fma operations of canonical value is accomplished by the standard fma the form behavior, and so fnorm.pc.sf f1 = f3 is simply a pseudo- operation for fma.pc.sf f1 = f3,f1,f0. p = p + xi ˜ yi It was stated above that the fma behaves in accordance requiring only n floating-point operations, whereas with with the IEEE Standard. Strictly speaking, that standard a separate multiplication and addition it would require does not cover the fma instruction, but all the 2n operations, with a longer overall latency. stipulations are extended to it in a natural way. Apart from its speed advantage, the fact that no However, there is some subtlety over the signs of zero intermediate rounding is performed on the product also results. tends to reduce overall rounding errors. In common If the result of an fma without the final rounding would cases this difference may be relatively unimportant, but be nonzero, then should it round to zero, the sign of the in special situations, the lack of an intermediate final zero will reflect the sign of the exact result. This rounding makes possible a number of techniques that of course is the ‘correct’ decision, but is a non-trivial are difficult or costly on a traditional architecture. The extrapolation of the IEEE Standard. Here, the sign rules floating-point division and square root implementations for multiplications and divisions are obvious (the provide ample illustration of this fact, but here are three exclusive or of the input signs). And for addition and other characteristic examples. subtraction, when the rounded result is nonzero, the exact result must be too (in a fixed floating-point Exact Arithmetic format), so only the special case of exactly zero results needs to be dealt with. In certain applications it is important to perform arithmetic to very high precisions, perhaps hundreds of bits. A natural way of manipulating very precise

9 numbers is as floating-point expansions; that is, sums of a – b ˜ q by an fnma instruction will give an exact standard floating-point numbers of decreasing answer provided q is accurate enough.3 magnitude. In order to perform efficient computations on such expansions, the basic building blocks are Accurate Range Reduction operations that compute exact arithmetic operations on individual pairs of floating-point numbers. For A similar situation arises when one has an integer example, it is known (Moller [7], and Dekker [8]) that approximation to the exact quotient. Many algorithms if |x| t |y| the exact sum x + y can be obtained as a 2- for mathematical functions, in particular trigonometric piece expansion Hi + Lo by the following sequence of functions such as sin, begin with an initial range floating-point adds: reduction phase, subtracting an integer multiple of a Hi = x + y constant such as S / 2. With the fma this can be done in a single instruction x – N ˜ P yielding an accurate result. tmp = x – Hi Without the fma however, the rounding error in the Lo = tmp + y multiplication could severely distort the result, so it This is straightforward to implement on traditional might be necessary to represent P as the sum of two architectures, though features of the Itanium numbers with fewer significant bits. (Each of these architecture make it significantly more efficient. numbers can be multiplied by N without error, and after However, on traditional architectures there is no several operations the main result can be obtained.) The similarly easy way of obtaining the exact product of fma is also useful for obtaining the appropriate N rap- floating-point numbers as an expansion; this requires idly in the first place. Typically, one wants to perform fairly complicated and inefficient methods based on some operation such as splitting the numbers into high and low parts by y = Q ˜ x masking and performing numerous sub-computations. N = rint (y) However, with the fms instruction, this computation is simple and efficient: r = x – N ˜ P Hi = x ˜ y where rint (y) denotes the rounding of y to an integer, and Q | 1 / P. Rather than using the special fcvt Lo = x ˜ y - Hi instructions to convert y to an integer, the integer This sequence always results in Hi + Lo = x ˜ y exactly conversion can be performed by adding and subtracting with Lo a rounding error in Hi | x ˜ y. a large constant like S = 2p–1 + 2p–2 where p is the floating-point precision, for example p = 53 for double Accurate Remainders precision. (Adding such a constant fixes the most significant bit of the sum and hence performs integer p–2 p–2 It is often the case that given a floating-point number q rounding of y, provided |y| d 2 ; the use of 2 makes approximately equal to the quotient a / b of two the technique work for both positive and negative y.) floating-point numbers, one wants to know the Using the fma the multiplication by Q and the addition remainder r = a – b ˜ q. This arises whenever evaluation of S can be combined, and hence the reduced argument of a quotient to higher precision is needed, for example, can be obtained by just three fma operations: in floating-point expansions. Provided the y = S + Q ˜ x approximation q is good enough, it can be shown that r N = y – S is always representable exactly as a floating-point r = x – N P number. However, that does not mean it is always ˜ straightforward to obtain it on traditional architectures. This approach has the additional advantage of avoiding In fact, if a – b ˜ q is computed by a multiplication and a some rare problems with the intermediate rounding of subsequent subtraction, the rounding error in the the product Q ˜ x. multiplication may be comparable in size to r itself, rendering the result essentially meaningless. Thus, Comparison and Classification complicated masking and multiple computations are necessary. But in the Itanium architecture, evaluating Floating-point comparisons are similar to the integer comparisons. The basic instruction is

3 It suffices for q to be accurate to one unit in the last place (ulp).

10 (qp) fcmp.fcrel.fctype p1, p2 = f2, f3 instruction frsqrta, which given a floating-point number Here the fcrel completer, which is compulsory, a, normally returns an approximation to 1 / —a good to determines the relation that is tested for. The about 8 bits. mnemonics differ slightly from those used in the integer (qp) frsqrta.sf f1, p2 = f3 comparison: eq for f2 = f3, lt for f2 < f3, le for f2 d f3, gt In special cases such as b = 0 for frcpa or a = 0 for for f2 > f3, ge for f2 t f3,and unord for f2 ? f3. There is no frsqrta, these instructions actually return the full IEEE- signed/unsigned distinction but there is a new correct result for the relevant operation (the full possibility, shown in the last case (f2 ? f3): two values quotient in the case of frcpa), and indicate this by may be unordered, since a NaN (Not a Number) clearing the output predicate register p2. Usually, compares false with any floating-point value, even with however, the initial approximations need to be refined itself. Mnemonics are also provided for the to perfectly rounded quotients or square roots by complements of all these conditions, although in the software, and this is indicated by setting the predicate actual instruction encoding these simply swap the register p2. Consequently, one can simply predicate the predicate registers and/or the input floating-point software responsible for refining the initial approx- registers. imation by this predicate register. Thanks to the The fctype field has two possible values, none (i.e. the presence of the fma instruction, quite short straight-line field is omitted in the assembly syntax), and unc. If sequences of code suffice to do this correction. There omitted, the result of the comparison and its are several reasons for relegating division and square complement are written to the designated predicate root to software. registers in the usual way. If the completer unc is used, however, then the behavior is the same if the qualifying x By implementing division and square root in predicate qp of the instruction is true, but both the software, they immediately inherit the high degree of predicate registers p and p are cleared if qp is false. pipelining in the basic fma operations. Even though 1 2 these operations take several clock cycles, new ones It is often desirable to classify a floating-point number, can be started while others are in progress. Hence, for example to abort a calculation if an input is infinite many division or square root operations can proceed in or NaN. A comprehensive instruction for classifying the parallel, leading to much higher throughput than is the floating-point value in a register is fclass: case with typical hardware implementations. (qp) fclass.fcrel.fctype p , p = f , fclass 1 2 2 x Greater flexibility is afforded because alternative The result of classifying the contents of f2 is written to algorithms can be substituted where it is advantageous. the predicate registers p1 and p2, controlled by the It is often the case that in a particular context a faster optional fctype in the same way as for comparisons (i.e. algorithm suffices, for example because the ambient its values can be none or unc). The fcrel field may be m IEEE rounding mode is known at compile time, or even (f2 is a member of the class specified by fclass) or nm because only a moderately accurate result is required (f2 is not a member of the class specified by fclass). The (this might arise in some graphics applications). actual classification is encoded as a 9-bit field whose bits are interpreted to determine whether the floating- x In typical applications, division is not an extremely point value is: positive or negative; zero, unnormalized, frequent operation, and so it may be that the die area on normalized or infinity; NaN or NaTVal. the chip would be better devoted to something else. Intel Corporation distributes a number of recommended Division and Square Root algorithms for various precisions and performance constraints, so the user will not ordinarily have to be There are no instructions specified in the Itanium concerned with the details of how to implement these architecture (except in IA-32 compatibility mode) for operations. As an example, consider the single performing floating-point division or square root precision division algorithm, optimized for throughput operations. Instead, the only instruction specifically (it has the smallest possible number of floating-point intended to support division is the floating-point instructions, resulting in the minimum latency per result reciprocal approximation instruction, frcpa, which in software-pipelined loops): The algorithm calculates q given floating-point numbers a and b, normally returns = a/b in single precision, where a and b are single an approximation to 1 / b good to about 8 bits. The precision numbers, rn is the IEEE round to nearest syntax of this instruction is as follows: mode, and rnd is any IEEE rounding mode. All other

(qp) frcpa.sf f1, p2 = f2, f3 symbols used are 82-bit, register format numbers. The precision used for each step is shown below. Similarly, the only instruction to support square root is the floating-point reciprocal square root approximation

11 -8.886 (1) y0 = 1 / b˜ (1+H0), |H0|<2 table lookup floating-point add/subtract, multiply, or fused multiply- add operation has a latency of 4 clock cycles, and a (2) d = (1 - b ˜ y0)rn 82-bit register format precision throughput of 0.5 clock cycles (meaning that two (3) e = (d + d d) 82-bit register format precision ˜ rn results can be generated every clock cycle, for example (4) y1 = (y0 + e ˜ y0) rn 82-bit register format precision in a software-pipelined loop). (5) q1 = (a ˜ y1) rn 17-bit exponent, 24-bit mantissa

(6) r = (a - b ˜ q1) rn 82-bit register format precision Additional Features (7) q = (q + r y ) single precision (IEEE) 1 ˜ 1 rnd The Itanium architecture includes a number of other The assembly language implementation follows [9], useful floating-point instructions that have not been assuming the input values are in floating-point registers mentioned, which are covered in detail in [4]. They f6 and f7, and the result in f8: include: frcpa.s0 f8,p6=f6,f7;; // Step (1) y0=1/b in f8 x transferring values between floating-point and integer (p6) fnma.s1 f9=f7,f8,f1;; // Step (2) d = 1-b*y0 in f9 registers by means of the getf and setf instructions (p6) fma.s1 f9=f9,f9,f9;; // Step (3) e = d+d*d in f9 x floating-point merging, useful in order to combine (p6) fma.s1 f8=f9,f8,f8;; // Step (4) y1 = y0+e*y0 in f8 fields of multiple floating-point numbers to give a new (p6) fma.s.s1 f9=f6,f8,f0;; // Step (5) q1 = a*y1 in f9 number using the fmerge instruction (p6) fnma.s1 f6=f7,f9,f6;; // Step (6) r = a-b*q1 in f6 x floating-point to integer and integer to floating-point (p6) fma.s.s0 f8=f6,f8,f9;; // Step (7) q = q1+r*y1 in f8 conversion using the fcvt instructions Support for software pipelining on Itanium processors x integer multiplication and division - the Itanium allows for this algorithm to be scheduled without any architecture does not specify a full-length integer additional code, so that one result is generated every 3.5 multiplication or division instruction; instead, such clock cycles (since there are 7 floating-point operations are intended to be implemented using the instructions to schedule on 2 floating-point units on floating-point unit, by first transferring the arguments to Itanium and Itanium 2 processors). This is a lot more floating-point registers, performing the multiplication efficient than on most present-day processor or division there, and transferring the result back architectures. x floating-point maximum and minimum, using the Table 3.2 shows the Itanium 2 processor cycle times for fmax and fmin instructions the division root algorithms of various precisions (a similar table is available for square root [9]). For Conclusion algorithms optimized for latency, the operation latency is given, in number of clock cycles. For operations The Itanium floating-point architecture was designed so optimized for throughput, the number of clock cycles that its high performance, accuracy, and flexibility required to generate one result is given. characteristics make it ideal for technical computing. Table 3.2. Latency and Throughput for Floating-Point Floating-point enhancements include a high precision Division on the Itanium 2 Processor and wide range basic floating-point data type, the fused floating-point multiply-add operation, software division and square root operations, and a large number of Division Single Double Double- floating-point registers. Floating-point code can also Precision Precision Extended draw on other generic Itanium architecture features Precision such as predication, register rotation, high memory Optimized 24 28 32 bandwidth, and speculation. Latency All floating-point data types are mapped internally to an 82-bit format, with 64 bits of accuracy and a 17-bit Optimized 3.5 5 7 exponent. This affords calculations that are more Throughput accurate, and do not underflow or overflow as often as on other processors. The great flexibility in using and The square root algorithms rely on loading constants, combining various floating-point formats and and the time taken to load these constants is not computation models makes it easy to implement included in the overall latencies. If the function is complex numerical algorithms more efficiently than inlined by an optimizing compiler, these loads should before. be issued early as part of normal operation reordering. For comparison, note that on the Itanium 2 processor, a

12 The fused multiply-add operation combines two basic [8] T. J. Dekker, “A Floating-Point Technique for floating-point operations in one, with only one rounding Extending the Available Precision”, Numerical error. Besides the increased accuracy, this can Mathematics journal, Vol. 18, 1971, pages 224-242 effectively double the execution rate of certain floating- [9] “Divide, Square Root, and Remainder Algorithms point calculations, as the fused multiply-add operation for the Itanium Architecture”, Intel Corporation, Nov. forms an efficient computation core that maps perfectly 2000, to several common algorithms used for technical and http://www.intel.com/software/products/opensource/libr scientific purposes. aries/numnote2.htm, The large number of floating-point registers available, http://developer.intel.com/software/products/opensourc of which some are static and some are rotating, allows e/libraries/numdown2.htm for efficient implementation of complicated floating- point calculations. An illustration of software and hardware interaction in the Itanium architecture, this is achieved on one side by avoiding frequent accesses to memory, and on the other through software pipelining of loops containing floating-point computations. The highest SPEC CFP2000 score for a single processor system, of 1431, belongs currently to an Itanium 2 system running at 1GHz - the Hewlett- Packard HP Server RX2600. The best performing P4 system, running at 3.06 GHz, has a score of 1092. The SPEC CINT2000 scores are in reverse order though – 810 and 1099 respectively. This gap will likely decrease and the advantage is expected to be on the Itanium processor family side as its core frequencies will get higher - today’s Itanium processors run at relatively low frequencies, and as the compiler technology on which Itanium processors depend so much continues to evolve. References [1] Intel(R) Itanium(TM) Architecture Software Developer's Manual, Revision 2.0, Vol 1-4, Intel Corporation, December 2001 [2] John Hennessy, David Patterson, “Computer Architecture - A Quantitative Approach”, Morgan Kauffman Publishers, Inc., third edition, 2002 [3] Peter Markstein, ‘‘IA-64 and Elementary Functions: Speed and Precision”, Hewlett-Packard/Prentice-Hall 2000 [4] Marius Cornea, John Harrison, Ping Tak Peter Tang, “Scientific Computing on Itanium-based Systems”, Intel Press 2002 [5] John Crawford, Jerry Huck, “Motivations and Design Approach for the IA-64 64-Bit Instruction Set Architecture”, Oct. 1997, San Jose, http://www.intel.com/pressroom/archive/speeches/mpf1 097c.htm [6] ANSI/IEEE Standard 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, IEEE, New York, 1985 [7] O. Moller, “Quasi double-precision in floating-point addition”, BIT journal, Vol. 5, 1965, pages 37-50

13 DOP – A CPU CORE FOR TEACHING BASICS OF COMPUTER ARCHITECTURE

Milos Becvar, Alois Pluhacek and Jiri Danecek

Department of Computer Science and Engineering Faculty of Electrical Engineering Czech Technical University in Prague,

Abstract: A simple 16-bit processor core called DOP and its teaching environment is presented. The DOP processor illustrates the basic principles of computer organization and is therefore used in the introductory hardware course. Its major features are simplicity, availability of an FPGA implementation and a C compiler. This paper presents the description of the core, HW and SW tools and teaching methodology.

computing performance. The DOP processor core was 1. INTRODUCTION developed at our department together with various SW and HW visualization tools (Danecek et al., 1994a). An introductory computer hardware course should teach students to the fundamental principles of computer The goal of this paper is to describe this processor core internal functionality. Students, who are familiar with and its learning environment for teaching basics of programming in high-level languages, are required to computer organization. The paper is organized as understand the interaction between a processor, a follows - section 2 outlines the introductory course and memory and I/O devices, an internal organization of characterizes the students, section 3 describes the DOP processor, computer arithmetic and basics of digital processor core, section 4 describes the SW and HW design. Our experience has shown that it is not an easy tools supporting this processor and finally section 5 task for most of them. The functionality of the processor outlines the use of the DOP in our introductory course. executing instructions seems to be something almost mythical and totally unrelated to intuitive execution of 2. COURSE REQUIREMENTS a program in high-level language. The introductory computer organization is a one- It is obvious that we have to provide some practical semester course, which is mandatory for all experience helping to understand these abstract undergraduate students of 3rd year of computer science principles. One common way is to let students to create and engineering. Almost 200 students take this course a program in high-level language, which simulates a every year. The course covers the basic principles of simple processor. However, this approach is not good computer functionality, the data representation, for illustrating the relation between high-level computer arithmetic and the controller design. languages, compilers, program in assembly language Furthermore it introduces basics of practical digital and actual “binary” program executed by processor. design. Another approach uses visualization simulators and HW emulators (Bruschi, 1999; Yurcik et al, 2001; Brorson, Students have relatively strong background in high-level 2002; Ellard et. al, 2002). languages and assembly language of x86 and are mostly SW-oriented. The majority of students thoughts that the We present a simple 16-bit processor core called DOP only computer is an Intel x86 PC. The minority of that is currently used in our introductory computer students has experience in implementing simple digital organization course. The processor is simple, yet fully circuits and wants to choose HW specialization in operational, and could be used in the embedded graduate study. applications, which do not require an excessive

14 x86 assembly language Machine-Oriented programming Languages (x86 ASM) 3. DOP ARCHITECTURE OVERVIEW

introduction to computer organization, Computer and Logic components of digital computer, Logic Systems The abbreviation “DOP” means “Danecek’s Original Design (DOP) computer arithmetic, controller design Processor” according to one of its proponents. The

ISA design, RISC, pipelining, introduction to Computer Architecture DOP processor has not been primarily designed to be an ILP processors, memory hierarchy, (DLX, MIPS) introduction to parallel computers educational platform. Its ISA was designed as a result of experience with writing HLL compilers for Peripheral Devices Computer Networks 8-bit and 16-bit microcontrollers like 8051, 68HC11,

Undergraduate Courses PIC16C5x, SAB80C166. These simple processors were Graduate Courses designed for assembly language programming and ILP processors, multithreading, Advanced Computer quantitative analysis of peripheral subsystem Architecture (MIPS) architectures of parallel computers writing efficient compilers for them is difficult and sometimes even impossible (Danecek et al., 1994b). Fig.1. Computer architecture course flow at CTU The DOP was intended to be a simple 16-bit processor core suitable for embedded systems and implementation Figure 1 shows the place of “Computer and Logic in FPGA (Danecek et al, 1994a). The main feature of Design” course in the overall Computer Architecture the processor is the simple compilation of high-level flow at Czech Technical University. It also outlines the languages. From the nature of applications comes the main topics covered at each level and a reference requirement to optimize the program size over the speed platform. of execution.

The main goal of “Computer and Logic Design” course It is not surprising that the result of this development is is to explain the components of digital computer and an accumulator-oriented processor with variable length functionality of sequential processor built from a simple instruction encoding. Its main characteristics are datapath and controller. The reference processor should outlined in Table 1. The processor contains only few illustrate these principles. The processor internal programmer-visible registers. Local variables, organization should be reasonably simple to be temporaries and parameters are allocated on the stack in understood without deep knowledge in the digital the main memory. This arrangement is valuable for design (note that “Logic Systems” course is illustrating relation between HLL programs and actual unfortunately scheduled in parallel). “binary” program executed by the processor.

The next undergraduate course traditionally called The DOP processor is connected to the byte-organized “Computer Architecture” revisits the processor main memory and peripheral subsystem by 16-bit architecture and introduces the concept of pipelining Address Bus and 8-bit Data Bus. (Multibyte data are and basics of techniques used in modern ILP processors stored using Little Endian format) The main memory is as well as other concepts found in modern computers. common for the data and instructions. Some topics are covered in separated courses Main RESET Main “Peripheral Devices” and “Computer Networks”. DOP CPU MAINMemory Memory Undergraduate courses together cover all topics in the CLK MEMORY popular reference book “Computer Organization and AB(15:0) CLK MRD, MWR 16 Design – HW/SW Interface” (Patterson and Hennessy, GEN. & INT INTA WAIT 2 1998). Some topics from the area of peripheral POR DB(7:0) subsystem and computer networks are covered in more 8

CLK INTERRUPT detail than in this book. The main graduate course I/O I/O CONTROLLER DEVICE #1 DEVICE #N “Advanced Computer Architectures” is obligatory only RESET (OPTIONAL) for students of HW specialization. This course is based IRQ#1 on the book (Patterson and Hennessy, 2002). IRQ#n Interrupt requests

With this course flow in mind, we can describe the Fig.2. DOP system level overview organization of the DOP, which is used to illustrate the basic principles of computer organization and design. Peripheral devices for DOP could be memory mapped The relation between the DOP and more advanced and processor supports single external maskable courses is discussed in the section 5.4. interrupt signal. The interrupt subsystem could be further expanded by an external interrupt controller. Interrupt subsystem was added to illustrate the interrupt service cycle at the HW level. Figure 2 shows the

15 interconnection between DOP processor, memory and added or subtracted (if the shorter operand is an 8-bit peripherals. Some parts of this system exists as an short integer, it is sign-extended). In the same time, the FPGA implementation, others are only modeled in SW sign of the second ALU operand is stored in the special or exist only in the specification (peripheral devices). Auxiliary Flag (AF) (see also AUXF signal on the fig. For further discussion of HW and SW tools please refer 6). The addition or subtraction is finished by applying to section 4. instruction AAF to the remaining words of the longer operand (instruction adds extended sign XAF of shorter Table 1 DOP Characteristics operand stored in the AF and carry flag CF from the previous operation.) DOP ALU width 16 bit Internal bus width 16 bit There are also two special instruction prefixes Address bus width 16 bit modifying the behavior of the following ALU Data bus width 8 bit instruction. First prefix is an UCF (use carry flag) this Encoding of signed 2’s complement prefix enforces the use of the CF in the following ALU numbers Data types supported Word (16 bit), unsigned byte (8 instruction. For example the prefix UCF followed by an by ISA bit), signed short (8 bit) ADD instruction is equivalent to the ADDC instruction Multibyte data storage Little Endian (add with carry) whereas the UCF followed by the SUB format behaves like the SUBB (subtract with borrow). Second I/O subsystem Memory Mapped prefix is the SWW (suppress write to W) that allows Programmer visible PC, SP, W, S, D synthesizing the comparison and test instruction. The 16-bit registers SWW followed by the SUB behaves like the CMP (only Programmer visible 8- L (loop counter), F (Flags) flags are set, W is not modified) and the SWW followed bit registers by an AND is similar to the TEST instruction. External interrupts 1 (maskable), 16 interrupts with external 8-bit Instructions without interrupt controller OPERATION CODE Immediate

8-bit 8-bit Instructions with short or byte OPERATION CODE 8-bit IMMEDIATE 3.1 DOP Instruction Set Architecture immediate 8-bit 16-bit Instructions with word immediate, OPERATION CODE 16-bit IMMEDIATE The DOP ISA is an example of an accumulator-oriented jump and call instr. instruction set with several enhancements. First operand of ALU instruction is always an Fig.3. DOP instruction formats accumulator – register W. Second operand can be register or memory location (typically on the stack The DOP is oriented to the high instruction encoding where local variables and temporaries are located). density and uses three formats of instruction. Most of The instruction set also includes a dedicated instruction instructions occupy only a single byte (1st format); LLA, which computes the address of local variable on other formats are used for instructions with 8-bit or the stack. Figure 4 shows the example of computation 16-bit immediate. The DOP encoding density is with local variables. superior over comparable processors. It has been reported that programs compiled for DOP occupy less DOP instruction set supports three data types – 16-bit than 60 % of memory space than for 8051. This feature word, 8-bit unsigned byte and 8-bit signed short integer. can be very valuable for embedded systems (Danecek Bytes and short integers are internally extended to word et. al, 1994c) length and all operations are performed with these 16- bit operands. This is another solution than in x86 ISA, which provides separated instructions for 8-bit LLA S, 0x04 ; S <= SP – 0x04 (address of a) operands. Moreover, all data manipulation instructions LLA W, 0x07 ; W<=SP – 0x07 (address of b) support all three data types. This regularity simplifies LLA D, 0x03 ; W<=SP – 0x03 (address of c) the task of code generation and is also a good LD W, [W] ; W<=Mem[W] educational example. ADD [S+] ; W<= W + Mem[S], S++ ST [D] ; Mem[D]<=W DOP ISA also includes several provisions for efficient support of operands longer than 16-bit word and Fig. 4 Example of c:=a+b in DOP assembly language addition and subtraction of operands of different sizes (a,b and c are local variables allocated on stack) (see Fig.5). Firstly, lower words of the two operands are

16 A3 A2 A1 A0 ± B0 Auxiliary Flag used for addition or subtraction of operands longer than 16-bit word. All Flags are set after each ALU operation. A3 A2 A1 A0 3.3 DOP Registers B0 Beside mandatory 16-bit PC (program counter) register XAF the DOP contains only a few programmer-visible AF AF registers - SP (stack pointer), W (accumulator), which is a part of the ALU, S (source register) and D (destination register). Both S and D register could be CF AAF CF ADDS/SUBS used as general-purpose data storage during expression evaluation or address computation. All registers could be connected via 16-bit internal bus to ALU or to 16-bit Fig.5 Example of addition/subtraction of short integer external address bus and serve as an address for the (8-bit signed) to doubleword (32-bit signed) main memory. The SP, S and D register support autoincrement and autodecrement addressing modes for 3.2 DOP Arithmetic and Logic Unit accessing arrays and longer operands. Therefore these registers are implemented as bi-directional counters. The DOP Arithmetic and Logic Unit is based on the 16- bit W register which serves as an accumulator. This The DOP also includes the 8-bit L register, which is organization is very simple yet efficient for this class of used as loop counter for an easy compilation of short processor. The second operand for ALU could be an for loops. The L register could be accessed separately internal register or an operand read from memory (to or together with the FLAGS register as a 16-bit PSW temporary register). The second operand is connected (program status word). by the internal 16-bit bus to the second ALU input. BUS(15:0)

"0" PSW CF ALU and FLAGS L U OP(3) OP(3:0) 0 1 BLF W register register register AUXF R(15) W0 AB(15:0) S(15:0) R(15:0) BUS(15:0) ADDRESS CY ECW DATA DB(7:0) cy(16) CIN CIS CI0 16 I/O UCF OVERF cy(15) + SUM(15:0) ZERO CLK PC SP S D T SIGN SUM(15) register register register register register

RESET ENW ECW W EC WEN SWW

W(15:0) BUS(15:0)

OEW Fig. 7. DOP datapath

Fig.6. DOP ALU organization The whole datapath is outlined in figure 7. Note that U and T registers are not visible to the programmer and The ALU internally contains the Block of Logic could be used as a temporary storage for the complex Functions (BLF) and 16-bit binary adder. This instructions. These registers were added only for organization implements all basic binary arithmetic and educational purposes (original DOP ISA could be fully logical operations (addition, subtraction, logical and, or, implemented without these registers). xor, negation and shifts). The logical operations are implemented in BLF, while the second input of adder is 3.4 DOP Controller connected to zero. More complex operations such as multiplication or division could be synthesized by SW The DOP processor was originally implemented with routine (library of these routines is available). optimized hardwired controller. However, this The blocks labeled CIS (carry in selection) and WEN controller is not very suitable for practical experiments (write enable) implement the prefixing instructions UCF of our students. Consequently, a very simple horizontal and SWW. microprogrammed controller was designed. The DOP controller currently needs the 58-bit wide The ALU also contains Flags – Carry Flag, 2’s microinstruction for all control signals (actual width is complement Overflow Flag, Zero Flag, Sign Flag and 64-bit including several spare control signals). Each

17 microinstruction corresponds to a single clock cycle. Table 2 DOP SW simulators and models An Address of the next microinstruction is specified as a field in the current microinstruction. Three the lowest Type of Modeling Purpose significant bits of this address could be modified by the simulator Language Instruction C++ Assembly program debugging, condition multiplexer. This organization allows Cycle Accurate compiler debugging branching to the 8 destination addresses in a single Functional Pascal Microprogram development, microinstruction depending on the status of various Clock Cycle observation of the int. function internal and external signals. The DOP controller uses Accurate of the processor the condition multiplexer for gradual instruction VHDL RTL VHDL Design verification, detailed model view of signal flow decoding (decoding takes 2-3 clock cycles per VHDL post VHDL Timing verification, detailed instruction). The condition multiplexer is also employed P&R model + SDF view of real delays on FPGA for the testing of flags and external signal WAIT (from main memory or I/O) and INT (from interrupt controller). The instruction-cycle accurate simulator can be used for debugging of DOP assembly program and the compiler development. The functional clock-cycle accurate Control Memory 512 x 64 bits simulator is used for development of DOP microprogram (firmware) for each instruction. The SC(4:0) MA(8:0) third type of model is synthesizable RTL VHDL model

Condition selection including memory and an interrupt controller. This model could be used to confirm results of functional clock-cycle accurate simulation. It allows more detailed ANM(8:3)=MA(8:3) Control Signals view of the CPU behavior in time (namely signal ACM(8:0) Address of the next sequences). The most accurate model is the post-place microinstruction Register of microinstruction MA(2:0) and route generated VHDL Vital model with SDF file. address ANM(2:0) It shows the real delays of signals on FPGA. IR(7:0), OVF, SF,ZF, CF, IF, LZERO, WAIT, INT

Condition multiplexer CLK, RESET 4.2 HW emulator board Fig.8. DOP microprogrammed controller A FPGA based emulator board was designed for the The complete implementation of the DOP instruction DOP processor. The board contains the control memory set needs less than 270 microinstructions in the control 8 k x 64 bits made from 8 SRAM chips. The size of memory. This controller is definitely not the fastest control memory is significantly higher than necessary possible microprogrammed one for this processor. for the DOP. It allows reusing the emulator board for However, its major advantage is the simplicity and different processors. The rest of the DOP is regularity. implemented in the Main FPGA (XC4013E-PQ160). The board also includes the additional 8k x 8bit SRAM 4. DOP HW AND SW TOOLS circuit as the main memory for the program and data and some interface circuitry with the host system 4.1 DOP simulators and models (implemented in separate Interface and Control FPGA). SW on the host computer controls all functionality of Four SW models of the DOP currently available are the emulator board. characterized in Table 2. Each of them allows the analyzing of the processor behavior on the different Having configured the Main FPGA, the control level of abstraction for various purposes. The first two memory could be downloaded with the microprogram. simulators are executable on almost any personal The SW on the host computer generates clock signal for computer, whereas the VHDL models require complex CPU. The status of each register could be read out from and relatively expensive VHDL simulator. Therefore the DOP processor after each clock cycle. Besides this only a limited number of students could use the VHDL debugging mode, the DOP processor is able to execute models simultaneously. Recently, the major FPGA the sequence of instructions independently and later vendors offers relatively cheap versions of VHDL generates an interrupt to the host system. simulators but it is still unlikely that every student can buy one and run it at home on his computer.

18 MAIN CONTROL 5.2 DOP classroom seminars MEMORY MEMORY 8k x 8bit 8k x 64bit SRAM SRAM During the first four seminars the internal organization RD/WR MAddr Microinstr. AB(15:0) of the DOP processor is explained to students. This is ISA INTERFACE DOP AND HOST BUS DB(7:0) DATAPATH done with aim to maximally involve students in CONTROL SYSTEM XC4013E-3PQ160 FPGA Clock and control (PC) (MAIN FPGA) explaining the DOP schematic diagrams. These XC4003-6PC84 MRD, MWR seminars have a strong link to lectures and goal is to illustrate the topics of lectures on practical examples. Fig. 9. DOP HW emulator board block diagram For example: during the DOP ALU description, arithmetic is exercised and other possible organizations Moreover, the HW emulator board offers the possibility are discussed. Similar approach is used for explaining of experiments that are not possible with the SW the DOP controller and basic cycle. simulators. For example, it is possible to extend the basic DOP processor by additional functional units such 5.3 DOP laboratory seminar as multiplier or divider and control them by currently unused signals in the control memory. After explaining the DOP schematics, the SIMDOP – functional clock cycle accurate simulator is introduced 5. USE OF DOP IN COMPUTER AND LOGIC during laboratory seminar. Students are let to write a DESIGN COURSE short program in DOP assembly language, translate instructions into hexadecimal form and execute them 5.1 Overview of seminars step-by-step on the simulator. Students are also shown that the same program is executed in the VHDL The “Computer and Logic Design” course is in the simulator and most importantly on the HW emulator typical format of CTU. It takes one semester (14 board. The majority of students does not understand the weeks). Every week is a single 90-minutes lecture and VHDL simulator and the HW emulator board but they 90-minutes seminar. Seminars are held in classrooms or appreciate that the processor “really exists”. in laboratories. The table 4 describes the current schedule of these course seminars. Most of the seminars are held in classroom and there are only two laboratory seminars. This is not optimal, but it is the result of limited availability of laboratories, which are used by parallel Logic Design course. It can be also seen that DOP currently occupies approximately half of the semester.

Table 4 Example of Computer and Logic Design seminar schedule

Seminar Scope 1 Introduction to DOP processor, Fig. 10. SIMDOP – functional cycle accurate simulator Instruction Set Architecture and Data Types 2 Principles of synchronous design, 5.4 DOP homework assignment Datapath of DOP - design of registers, ALU and interface circuitry, arithmetic The main educational method based on the DOP is the 3 DOP controller implementation, homework, which is solved by every student principles of horizontal microprogram., independently. Each student has to write a discussion of possible enhancements microprogram implementing some complex instruction, 4 DOP basic cycle, DOP firmware, which can possibly extend the DOP instruction set. homework assignment Currently, we have collection of around 50 complex 5 Exercise with DOP cycle accurate instructions usable as homework. Most instructions are (laboratory) simulator 6 Evaluation of homework on VHDL extending DOP arithmetic capabilities (e.g. (optional) simulator and HW emulator multiplication and division, operations on long operands). Typical complexity of homework is between 10 and 20 microinstructions. One of the requirements is

19 preserving functionality of the original instructions. how the processor works. Microprogrammed controller Two registers U and T were added to the DOP for offers the possibility to easy modify the processor making the implementation of these complex functionality, which is advantage over the hardwired instructions easier. controller.

The microprograms are developed using functional Student reports shows very frequently that they were cycle accurate simulator (SIMDOP), which is available afraid from the complexity of the homework but finally to all students (see figure 10). For easier writing of found it simple and interesting. They claim that horizontal microinstructions symbolic language - homework helps them to finally understand how the microassembler and its compiler were developed. processor works. It also seems that classroom seminars Microassebler represents each microinstruction as a set are not very efficient way to explain the DOP and of active signals and uses labels to represent addresses students forgot most of it before they start to solve the in Control Memory (see Control Memory section on homework assignment. figure 10). Compiler is responsible for allocation of microinstruction in the Control Memory and translates It is also interesting to note the most frequent mistakes the microprogram to the binary format. It also does students make in homework. Typically they use some some correctness checks on the microprogram – for dedicated register as PC or SP for intermediate storage example it checks the control of tri-state buffers to in instruction and do not understand that it is not avoid the most frequent mistakes coming from the possible. Second most frequent mistake is made in collision on the internal bus. reports where students are not able to write a reasonable description of instruction for a programmer. Description This compiler simplifies the student task but can also usually contains a lot of implementation details but lead to misunderstanding of the real content of Control important requirements for the programmer are omitted Memory (binary format of microinstructions is created (state of input registers, modified registers, and flags). as a side effect of compilation, this format can be used with VHDL models). 5.6 Relation of the DOP to more advanced courses Besides the implementation of the instruction, student has to write a report, which can become a part of DOP’s It has been shown that the DOP reasonably describes documentation for a programmer. Students have to the basic principles of computer organization, which are describe the number of clock cycles and typical use of explained in the “Computer and Logic Design” course. the added instruction. It introduces some old concepts (accumulator-oriented Homework are reviewed at the end of semester by the ISA, microprogramming), which are not currently used teaching assistants and become part of students in the mainstream general-purpose computers evaluation. On the other hand similar processors are still used in the area of embedded systems. It seems more 5.4 Optional seminar appropriate to show these principles on this type of architecture than building some artificial combination of At the end of semester one optional laboratory seminar RISC ISA and non-pipelined datapath with is offered. There is usually no time to present this for microprogrammed controller. every student. Volunteers are typically students more interested in HW. During this seminar, homework are After introducing the quantitative approach and ILP in evaluated on the VHDL models and downloaded to the the following “Computer Architecture” course, students HW emulator. can see that the main idea behind the DOP (orientation to simple HLL compilation and high instruction 5.5 Experience with the DOP encoding density) has lead to simple processor but with poor performance. More advanced concepts such as Before the DOP processor was chosen a simple CPU pipelining and superscalar execution are explained on based on AMD 2900 CPU slices had been used for the the RISC processors. This is perhaps not a direct way same purpose. It means that this approach of teaching to the contemporary computer architecture but it this course has a relatively long tradition. explains the evolution of processor architectures and Student reports shows that t he main pedagogical tool is ISA and relation between them. the homework. It has to be stressed that nowadays the main goal of the homework is not to teach microprogramming but make the students understand

20 6. CONCLUSIONS AND FUTURE WORK Danecek, J., Drápal, F., Pluhácek, A., Salcic, Z., Servít, M. (1994a): DOP – A Simple Processor for Custom The DOP core presents an example of a simple Computing Machines. In: Journal of processor that could be used to illustrate the basics of Microcomputer Applications , vol. 17, pp. 239-253, computer organization and digital design. Academic Press Limited In comparison with commercial products, it has simple and orthogonal architecture. The DOP is currently used Danecek, J., Drápal, F., Pluhácek, A., Servít, M. in introductory computer organization course seminars. (1994b) The Architecture of General-Purpose Students participate on the design of the DOP datapath Processor Cell. In: Proc. of 4th International and controller and finally write a microprogram for Workshop on Field-Programmable Logic and DOP, implementing some complex instruction. Students Applications, FPL94, pp. 321-325, Prague use the cycle accurate simulator for homework assignment and could later evaluate the results on more Danecek, J., Drápal, F., Pluhácek, A., Salcic Z.,Servít, accurate VHDL model or HW emulator board. The M. (1994c) Methodologies for Computer Aided feedback from our students is mostly positive. They Hardware/Software Co-Design Using Field claim that homework assignment finally helped them to Programmable Gate Arrays. In: Research Report. understand the processor functionality. More Department of Computers, CTU Prague experienced students appreciated introduction to FPGA and VHDL style of circuit description. Drápal, F., Danecek, J., Pluhácek, A., Servít, M. (1995), Implementation of a General-Purpose Processor In the future we want to increase the number of Macro, In: Proc. Design Methodologies for laboratory seminars which are more efficient than Microelectronics, pp. 89 –97, Smolenice, Slovakia explaining the DOP processor in the classroom. We prepare new laboratory seminar for experimenting with Ellard, D., Holland, D., Murphy, N., Seltzer M. (2002) C compiler and DOP instruction-cycle accurate On the Design of a New CPU Architecture for simulator. The HW emulator board can be also used Pedagogical Purposes In: Proc. of the Workshop of more efficiently. New experiments with this emulator Computer Architecture Education, Anchorage, would allow extending the DOP by additional units USA such as multiplier and controlling it by spare bits in the microinstruction. However, this requires significant Patterson, D., Hennessy, J. (1998), rearrangement of the seminars and other courses. Computer Organization and Design: The Hardware/Software Interface, 2nd edition, Morgan At the same time the DOP is used also in more Kaufmann Publishers , San Francisco, USA advanced digital design courses for experiments with FPGAs and as a simple target for developing compiler Patterson, D., Hennessy, J. (2002), from subset of C in the introductory to compilers Computer Architecture A Quantitative Approach, , course. Currently, we plan to make the DOP 3rd edition, Morgan Kaufmann Publishers, documentation and tools available via Internet and San Francisco, USA JAVA version of SIMDOP is prepared. Yurcik, W., Wolffe, G., Holliday, M. (2001). A Survey of Simulators Used in Computer REFERENCES Organization/Architecture Courses, In: Proc. of the 2001 Summer Computer Simulation Conference Brorson, M. (2002). MipsIT – a Simulator and (SCS 2001), Orlando, USA Development Environment using Animation for Computer Architecture Education, In: Proc. of Workshop of Computer Architecture Education, Anchorage, USA

Bruschi, S. M. (1999). Simulation as a Tool for Computer Architecture Teaching, In: Proc. of SCS Summer Simulation Conference, pp. 81-86., Orlando, USA

21 Superscalar Out-of-Order Demystified in Four Instructions

James C. Hoe Computer Architecture Laboratory Carnegie Mellon University Pittsburgh, PA 15213 [email protected]

complexity of the subject, the material is often presented Abstract—This paper describes a processor design at a fairly high level; rarely are students required to project intended to illustrate the detail inner workings work out a coherent, complete datapath in a hands-on of modern superscalar out-of-order processors. In the fashion. It is our contention that most students are only project, the students implement a cycle-accurate RTL- able to walk away with a “warm-and-fuzzy”  level model of an out-of-order core including rename, understanding of how an out-of-order core really issue, execute, completion and retirement operates. In other words, many students may  stages based on the MIPS R10000. The processor comprehend the basic principle of microdataflow core only supports four instruction types. First, the instruction scheduling, but very few students would be basic integer subtract instruction is included to exercise able to accurately describe the intricacies in the the mechanisms related to register-renamed out-of- instruction issue and data forwarding logic that permit order execution. Second, two types of branch two instructions with read-after-write dependency to instructions, resolving correctly and incorrectly execute in back-to-back cycles.1 respectively, exercise speculative execution and branch rewind capabilities. Lastly, an exception-triggering In this paper, I described a project designed to impart instruction tests the support for precise exceptions. The students with precise and accurate understanding of project is designed to be completed in six weeks by a modern superscalar out-of-order processor design. In team of two to three students with solid background and this project, the students implement a cycle-accurate strong interest in computer architecture and digital RTL-level model of an out-of-order core, i.e., rename, design. This project has been used twice in an issue, execute, completion and retirement stages. To advanced graduate computer architecture course (CMU stay within a reasonable workload, students only need to 18-744 Hardware Systems Engineering) and has support the execution of four simple instruction types. received favorable feedback from students and industry First, the integer subtract instruction is sufficient to recruiters. The project handout and required Verilog exercise all of the mechanisms involved in register- source files can be downloaded from renamed out-of-order execution. Second, two types of http://www.ece.cmu.edu/~jhoe/superscalar. branch instructions, resolving correctly and incorrectly respectively, exercise speculative execution and branch I. INTRODUCTION rewind capabilities. Lastly, an exception-triggering Implementing an n-stage in-order pipelined processor instruction tests the support for precise exceptions. The is the staple design project in undergraduate RTL model produced by the student must be both introductory computer architecture courses. Such a simulatable and synthesizable. The students’ final RTL hands-on project is very instructive in that the students implementations are evaluated both in terms of IPC walk away with an in-depth understanding of not just the performance and hardware cost. abstract principle of pipelining but also the exact mechanisms that make a real instruction pipeline work 1 Data dependence between a pair of dependent single- well (e.g., stalling, squashing and forwarding). Modern cycle ALU instructions is resolved in the same cycle when the superscalar out-of-order microarchitecture, on the other producer instruction is selected for issue. This way, the hand, is a central topic in most graduate-level computer dependent instruction itself is eligible for scheduling in the architecture courses. Unfortunately, due to the next cycle while the producer instruction is still being executed.

22 fetch 4xinst decode core

fetch map table (16R4W) map table …,sub;sub;sub;… 4xinst decode map table map table

(16R4W)

16-entry 16-entry int. Q FP. Q 16-entry 16-entry 8x4 entries isource (R.S.) (R.S.) Active List 8x4 entries int. Q FP. Q (ROB) 64-entry 64-entry Int GPR FPR Active List (R.S.) (R.S.) 7R3W 5R3W

ALU1 ALU2 LD/ST FPU1 FPU2 (ROB) 64-entry 64-entry Int GPR FPR 7R3W 5R3W in-order checker ALU1 ALU2 LD/ST FPU1 FPU2

Fig. 1. MIPS R10000 Block Diagram Fig. 2. The Simulation Environment

The project can be completed in six weeks by a team The scope of the project only covers the mechanisms of two to three graduate (or advanced undergraduate) for renaming, microdataflow scheduling, data students who have solid background and strong interest forwarding, branch rewind and exception recovery. in computer architecture and digital design. This project Datapath elements relevant to this project are has been used twice in an advanced graduate computer highlighted in gray in Figure 1. Memory and floating- architecture course (CMU 18-744 Hardware Systems point portions of the datapath are left out in the current Engineering, Spring 2002 and Spring 2003). CMU 18- version of the project. For the purpose of testing and 744 is a depth course in our ECE department’s graduate simulation, a synthetic randomized instruction source computer architecture curriculum. This course has as that mimics the instruction fetch stage provides test prerequisite our first-year graduate computer stimulus to the out-of-order core. architecture course (CMU 18-741 Advanced Computer The synthetic instruction source emits a randomized Architecture). The project is liked by the students who instruction stream composed of 4 instruction types in the have taken the class and has gotten positive comments MIPS ISA [3]. The out-of-order core only needs to from industry recruiters who talked to the students. support the execution of the integer subtract instruction (SUB rd, rs, rt). A sequence of SUB instructions with Paper Outline: Following this introduction, the randomized source and destination registers is sufficient remainder of the paper is organized as follows. Section to exercise the hardware related to register renaming, II gives an overview of the project specification. Section microdataflow scheduling, and data forwarding. III and IV provide details in the project setup and The synthetic instruction source also emits ADD, execution, respectively. Section V explains the project’s BNE and BEQ instructions. The semantics of these stated objectives and acceptance criteria. Section VI instructions, however, have been redefined for the suggests ways to extend or expand the project in the purpose of exercising the mechanisms for precise future. Section VII concludes with a few remarks exception and branch rewind. regarding our experience in running this project. • The execution of an ADD should always lead to an exception. The ADD instruction itself cannot II. PROJECT OVERVIEW be finished. The state of the out-of-order core The project calls for the Verilog RTL implementation should rewind to just before the ADD instruction of a superscalar speculative out-of-order core based on prior to continuing with the corrected instruction the MIPS R10000 microarchitecture. Figure 1 gives a fetch stream. high-level sketch of MIPS R10000’s out-of-order core. • The execution of a BEQ should always confirm The details of the microarchitecture are described its corresponding branch prediction, requiring no extensively in [5]. The MIPS R10000 microarchitecture change to the incoming instruction stream. is selected for the project because similar • The execution of a BNE should always reverse microarchitectural arrangementsmost notably the use its corresponding branch prediction. The state of of a common physical register pool to serve as both the out-of-order core should rewind to just after rename registers and architectural registersare the BNE prior to continuing with the corrected employed by most of the recent superscalar out-of-order instruction fetch stream. processors.

23 64 inst0 clk inst1 accept inst2 accept inst3 restart 16 valid 1111 1100 1111 0000 1111 restartOn ISOURCE id0 id1 reset inst’s XXXX id2 clk id3 4 Fig. 4. Stalling Fetch by Deasserting accept valid[3:0]

Fig. 3. The isource Module Interface clk

accept The frequency of these special instructions can be adjusted as necessary. The out-of-order core inst’s X,X,X,X S,S,S,Be S,Be,Bn,S S,A,S,Bn S,S,S,Be S,S,A,S implementation is not allowed to take advantage of the X,X,X,X n n n n n n n n n n n n n n n n n n n n special semantics of the ADD, BEQ and BNE sn’s 0 1 2 3 4 5 6 7 8 9 10 11 12 11 13 14 15 16 17 18 instructions except when the instructions are being restart executed. In other words, until ADD, BEQ and BNE X n X n reach the execution unit, they must be treated normally restartOn 11 6 as if they were expected to complete; similarly, the speculatively fetched wrong-path instructions following Fig. 5. Restarting Fetch by Asserting restart an ADD or BNE must also be treated normally (although they must be later discarded) until the rewind, the correct instruction stream is resumed by exceptional condition is determined in the execution asserting the restart input port for 1 clock edge. (See unit. example waveform in Figure 5.) The new instruction stream begins immediately on the following cycle. III. PROJECT SETUP Instruction fetch is restarted in the same way following a The students are provided with two behavior-level precise exception caused by an ADD instruction. The Verilog modules that constitute the testbench isource module generates a sequencing ID for each environment for developing their core (Figure 2). The instruction in the stream. The sequence ID of the first is a synthetic instruction source, and the second is a exceptional instruction must accompany the assertion of checker module. the restart signal to properly resolve the situation when nested branch mispredictions are resolved out of A. Instruction Source Module program order. The isource module mimics a 4-wide instruction fetch buffer. The interface to the isource module is B. Checker Module depicted in Figure 3. On each cycle, the isource The checker module maintains a shadow copy of the module presents a sequence of 0 to 4 randomly architecture register file. The checker module passively generated instruction words on its four inst ports. The monitors the activities on all input and output ports of corresponding bits in the 4-bit valid mask indicate the the isource module. The checker module computes the validity of individual instruction words. If less than four correct in-order-state of the register file according to the instructions are valid, the valid instructions are always observed instruction stream. The checker module clustered together toward inst0. The output of the inst executes the instructions in order. Instruction processing and valid ports do not change until the accept input is skipped following an ADD or BNE instruction until port is asserted on a clock edge. (See example waveform the restart signal is asserted for the correct exceptional in Figure 4). In other words, the instruction fetch stream instruction. The checker module provides a reference can be stalled by deasserting accept. The instructions state to verify the execution of the out-of-order core. that follow a BNE instruction are, by our redefinition, The checker module also collects and displays basic wrong-path instructions and hence must be discarded performance and instruction stream statistics (e.g., IPC, after the BNE instruction is later executed. After branch instruction mix, and the number of exceptions) during

24 simulation. from behavioral Verilog down to synthesizable RTL code. After each refinement step, the students can IV. PROJECT EXECUTION immediately simulate against the testbench environment Four major milestones demarcate the different phases to ensure the correctness of the most recent changes. of the project. These milestones both help pace the Although the core must be implemented using the students’ effort and also steer the students’ attention. synthesizable subset of Verilog, students are encouraged to incorporate behavioral-level Verilog code for • Phase 1: Develop a one-instruction-wide out-of- monitoring and debugging purposes. These out-of-band order core for just the SUB instruction. The core behavioral debugging code can dynamically examine the only needs to handle one instruction per cycle in processor state cycle-by-cycle and compute elaborate each of the decode, dispatch, execute and runtime invariant conditions. In our experience, writeback stages. The emphasis in this step is to carefully designed runtime invariants are very powerful develop the register renaming and dataflow debugging aids. These invariants help flag an erroneous algorithms. This step is allotted 2.5 weeks, operation in a timely manner such that they allow much which includes allowance for getting up to speed better localization of the origin of that error. on the MIPS R10000 microarchitecture. • Phase 2: Extend the one-instruction-wide core to V. PROJECT OBJECTIVES support branch instructions (BNE and BEQ) and branch rewinds. A. General Implementation Guidelines • Phase 3: Extend the one-instruction-wide core to It is suggested that the students base their core on the also support precise exceptions. Step 2 and 3 are MIPS R10000. As a general guideline, their RTL together allotted 2 weeks. models should capture all details explicitly mentioned in • Phase 4: Extend the fully-capable core from one- [5]. Nevertheless, the students also need to improvise in wide to superscalar operations in all stages. This several places where design decisions are not spelled out step is allotted 1.5 weeks. explicitly. In addition to the general guideline above, the following set of specific criteria must be met by the An appropriately restricted isource module is provided students’ RTL models. for in each phase to facilitate testing of the restricted core in the first three phases. 1) The execution of the out-of-order core must The project can run alongside of a normal lecture correspond to the reference behavior of the sequence. However, a part of each lecture should be checker. reserved to discuss and clarify project related issues. As 2) In the out-of-order core, pending instructions necessary, a number of the lectures can also be devoted must issue as soon and as fast as possible after to covering the more subtle details of the MIPS R10000 (true) data dependence and structural hazards design. Another option is to have the students take turn have been cleared. presenting different aspects of the MIPS R10000 core, 3) Back-to-back dependent instructions must be as described in [5]. capable of issuing on consecutive cycles (in the The RTL models produced for the project must not absence of structural hazards). only simulate correctly but also be synthesizable. 4) Branch rewind must be fast, i.e., taking O(1) Synthesizabilty is a project acceptance criterion to time, independent of the number of instructions ensure the students do not include unrealistic hardware to rewind.2 A branch rewind must start and structures in their processor models. The students can complete as soon as possible, without waiting only implement the core using the synthesizable subset for older instructions to retire. of Verilog Hardware Description Language [2]. In this 5) Exception rewind can be slow, i.e., taking O(n) regard, students with RTL design experience have a time where n is the number of instructions to significant advantage. Therefore, it is important each rewind. team includes at least one member who is familiar with 6) The core cannot make use of the special the RTL design flow. semantics of ADD and BNE instructions until Students are encouraged to follow a top-down design they are in the functional unit. flow where they begin with a very high-level, possibly behavioral, model for the major datapath structures. Next, they can refine the datapath structures piecewise 2 This criterion forces the student to implement a “branch rewind stack”.

25 Other aspects of this design project are essentially left to VI. PROJECT EXTENSIONS the students’ whim. The project as described is designed to be completed B. Evaluations by groups of two to three students in a half semester (~six weeks). The duration and scope of the project can The quality of the resulting RTL model is judged on be extended by including other aspects of modern high- correctness, IPC performance and hardware cost. For performance processors, such as branch prediction, the early milestones, the acceptance criterion is simply aggressive load/store ordering and cache hierarchy. for the out-of-order core to simulate correctly against the Here, we briefly suggest some specific ideas. test environment (isource and checker) for an agreed upon number of instructions. During simulation, the 1. Instead of MIPS R10000, one could also checker keeps count and reports the progress. After a retarget the project to be based on Alpha sufficient number of instructions has elapsed, instruction 21264 with clustered datapath. This fetch from isource is stopped, and the out-of-order core microarchitecture is as described in detail in is switched into the “drain” mode. The students can [3]. next verify that the out-of-order core’s committed 2. One could augment a baseline implementation register file state agrees with the reference register file of MIPS R10000 with support for state in the checker. Simultaneous Multithreading (SMT) [1]. The In Phase 4, the out-of-order core must also achieve a project would serve to clarify the minimum IPC performance. The IPC lower bound helps implementation consequences of SMT support. diagnose performance bugs. For example, we had seen 3. The project currently does not handle loads a case where one team did not handle back-to-back and stores. The memory subsystem in modern execution of dependent instruction. The consequence of superscalar processors can easily be made into this oversight is obvious in their abysmal IPC relative to a similar but stand-alone project. the other teams. During Phase 4, the different teams in 4. Similarly the project can also be extended to the class are routinely informed of each other’s latest examine instruction fetch and prediction issues IPC achievements. This effectively turned the last phase in modern superscalar processors (e.g. wide of the project into a competition. The students were fetch using a trace cache). self-driven to fine-tune things like the issue priority logic and the branch rewind process to stay ahead of the The key is to carefully confine the scope of the rest of the class. project so the students are exposed to all of the Although the RTL models produced by the students important details but without unnecessary tedium. are synthesizable, we do not use the synthesis outcome to evaluate hardware cost. Synthesized storage VII. CONCLUSION structures (RAM, CAM, and FIFO) are much less The intent of this project is for students to gain an in- efficient that the custom blocks instantiated in real depth understanding of modern superscalar processor implementations. As a compromise, we microarchitecture through hands-on practice. In compute an estimate manually using empirical values. addition, the project also gives the students a chance to We assume each bit of storage (a bit cell) costs 1 unit experience issues in project teaming and participate in a and the integer ALU costs 50,000 units. To compute the full engineering cycle of specification, implementation, final cost of a storage structure, the raw bit-cell cost validation and analysis. We believe this course is must be further multiplied by the number of normal read invaluable training for students who are headed for or write ports and by two times the number of either industry or graduate research. associative lookup ports. (For logical structures that This project is challenging and time-consuming. require different types of references in its different Although the students often gripe about its load and columns, the students would have to break the logical difficulty, in our experience, the students really did structure into its physical components to get an accurate enjoy spending the time to work out the details, estimate.) This very coarse grain model does not especially for the moments when a fuzzy concept in their account for random logic, registers or routing head suddenly becomes crystal clear in their congestions. Nevertheless, it does force the students to implementation. be aware of the tremendous cost and tradeoffs of adding additional ports and associative lookup.

26 REFERENCES [1] S. J. Eggers, J. S. Emer, H. M. Leby, J. L. Lo, R. L. Stamm and D. M. Tullsen, “Simultaneous multithreading: a platform for next-generation processors,” IEEE Micro, vol 17 no 5, pp 12-19, Sep/Oct 1997. [2] HDL Compiler for Verilog Reference Manual, Synopsys, Inc., 2000. [3] G. Kane and J. Heinrich, MIPS RISC Architecture, New Jersy:Prentice Hall, 1991. [4] R. E. Kessler, “The Alpha 21264 microprocessor,” IEEE Micro, vol 16, no. 2, pp 24-36, Mar/Apr 1999. [5] K. C. Yeager, “The MIPS R10000 superscalar microprocessor,” IEEE Micro, vol. 16, pp. 28-41, Apr 1996.

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34



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35 Integration of Computer Security Laboratories into Computer Architecture Courses to Enhance Undergraduate Education

Jayantha Herath, Susantha Herath, Ajantha Herath* St. Cloud State University, St. Cloud, MN 56301 *University of Dubuque, Dubuque, IA 52807 [email protected]

Abstract one or more persons during a one-year period aggregating at least $5000.00 in value”. The Professor Most computer science and engineering programs hadtofindanattorneytorepresenthimself.Many have two or more required computer architecture attorneys asked him to pay $150,000 and another asked courses but lack suitable interfacing laboratory for $60,000 upfront and $450 per hour to represent him experience for other upper-level classes. Information in this case. assurance and network security tracks have been developed over the recent years without providing The case above illustrates the complexity of conflicting necessary and sufficient background knowledge in technical and legal issues. Interestingly, most lawyers logic, storages and processor architecture. and judges do not understand the technologies involved Integration of real-world applications is always a and need help from technical expert witnesses to find better approach to not only to excite the passive out what happened in the computer using the forensic student body but also to explore the computer evidence available in the storage. And often the architecture subject area. At the intermediate level, technical experts do not know much about the legal architecture knowledge can be extended to provide issues involved. Finding the hidden evidence in storage information and network security experiences to systems and presenting it in an acceptable form to the students. Such extensions to the course will provide court is a hard problem for a computer architect to proper interfacing to networking, operating systems, solve. For this reason, it is important to provide basic databases and other senior level security related computer forensic techniques in a computer courses. This paper describes possible integration of architecture setting, to provide a way to recover security and privacy concepts into computer information in storage systems that ensures its integrity. architecture course sequence with hands-on classroom activities, laboratories and web-based In general, knowledge gained in computer architecture assignments. courses serves as the gateway for upper level undergraduate computer science courses. The main objective of this study is to develop computer 1. Introduction architecture course modules with computer security One day a tenured Professor of Medicine received an e- applications for undergraduate students. One of the mail from a close friend via Yahoo e-mail, with an challenges facing us in the classroom is finding attachment file. He opened this e-mail with other experiments to engage the interests of students while messages, and continued to work as usual. The improving the quality of computer architecture courses attachment contained a worm that causes automatic [1]. The goal has been and continues to be helping them transmission of more e-mail messages. A few days become good computer scientists in a relatively short later his computer was confiscated, his supervisors period of time with a solid grounding in both theoretical accused him of creating and transmitting a virus from understanding and practical skills so that they can enter his computer, and the FBI was called in. His entire the profession and make valuable contributions to the address list had received e-mails with a worm, society. The proposed active learning modules aim to automatically. One and half years later he found provide students with an exciting learning environment himself indicted by a grand jury for violating Federal and the necessary tools and training to become law 18 USC 1030 a 5 (a). The grand Jury charged that proficient in the computer architecture subject matter this Professor “knowingly caused the transmission of a with applications in security and privacy. The following program, information, code or command, and as a sections outline the details of course plan, examples, result of such conduct, did intentionally cause damage assessment plan, future work and summary. without authorization to a protected computer, which is used in interstate and foreign commerce and communication, and, by such conduct, caused loss to 2. Detailed Course Plan

36 To help master computer architectures, our curriculum This approach provides interfacing for cs-1 and cs-2 provides three semester courses. The first course in this courses taken in the previous semesters. Increasing the sequence covers the fundamentals of digital logic performance of the processor by reducing program circuit design [2]. This foundation course helps the execution time is considered at the gate, register and students develop component integration skills from functional levels of the processor design [3] [4]. At the gate-level to register-transfer-level, when designing a end of the semester, students in this course design a circuit to perform a particular task. The laboratories for pipeline processor using VHDL as their final project. this course consist of hardware and VHDL software simulations of combinational and sequential digital It is observed that learning processor architecture alone logic circuits. The intermediate level course introduces is insufficient at this level. Students should start to both complex instruction set and reduced instruction set understand the importance of storage systems and processor architectures. The laboratories for this course applying classroom knowledge to solve real-life consist of hardware and software simulations of basic problems. A course sequence with extensions to programming constructs in CISC and RISC security applications would help students develop such architectures. The third course focuses on advanced skills using several different architectures before their concepts in special purpose architectures to provide graduation. The following examples constitute a way to both depth and breadth to the subject matter. One could, integrate real-life problem solving to this level of conceivably, introduce security protocols for storage students. Example 1 illustrates a closed laboratory and system-on-a-chip related laboratories at this level. designed to help students understand the changes in the content of the memory. The open laboratory followed Integrating Computer Architecture with Security by this lab, a packet-sniffing example, would provide The focus of the intermediate-level course so far has necessary interfacing with a network security course been on implementing techniques of basic programming module. Example 3 shows an application of the constructs such as I/O, arithmetic expressions, memory knowledge acquired in logic-design class to provide operations, register operations, if-else and switch interfacing with database security course module. It conditional operations, for-while iterative computation describes a simple logic extension used to break into controls, simple functions and recursive functions in database systems. Example 4 describes the application several different instruction set processor architectures. of the clock values in a legal issue. This could provide interface to secure operating system course module.

TUTOR 1.32> MS 2000 'ABCDEFGHIJKLMNOPWRSTUVWXYZ'

TUTOR 1.32> MS 2020 'abcdefghijklmnopwrstuvwxyz'

TUTOR 1.32> MS 2040 '0123456789'

MEMORY DISPLAY

TUTOR 1.32> MD 2000 256 002000 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 ABCDEFGHIJKLMNOP 002010 57 52 53 54 55 56 57 58 59 5A FF FF FF FF FF FF WRSTUVWXYZ...... 002020 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 abcdefghijklmnop 002030 77 72 73 74 75 76 77 78 79 7A FF FF FF FF FF FF wrstuvwxyz...... 002040 30 31 32 33 34 35 36 37 38 39 FF FF FF FF FF FF 0123456789...... 002090 12 EB 00 13 12 EB 00 0E 12 FC 00 20 12 EA 00 02 .k...k...|. .j.. 0020A0 12 EA 00 12 12 EA 00 03 12 EA 00 02 12 FC 00 21 .j...j...j...|.! .... 0020F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ......

Figure 1. Setting and Displaying the Content of Storage

Example-1 memory is set by using MS and the content of the To understand how the processor operates, students memory is displayed using MD. In addition, students need to recognize the contents of registers and memory, also perform translations of arithmetic expressions, data learn the limitations of instruction sets and how the transfers, if-else-for-while control and recursive basic programming constructs are implemented in functions as in-class activity. They perform traces of processor architecture. Figure 1 depicts the first registers and memory as an in-class activity using classroom activity used to help students understand the Motorola 68000 instruction set architecture. addresses and content of the memory. In this example,

37 Example -2 email accounts using a packet analyzer. Also, they were The objective of this experiment is to apply the instructed about the legal issues involved in packet knowledge acquired in interpreting content of memory capturing. After doing this experiment, one student displays in the previous experiment into network observed that rediff login is not secure. However, he security applications. Network traffic is easy to capture noted that hotmail.com is not only using secure login, and analyze using the tools available in the web. but also encrypts the traffic. Hence, students could not Network protocol analyzers, such as Ethereal Packet identify their user-Id, password or message in that Sniffer, can be used to accumulate both incoming and communication. Moreover, they found that encryption outgoing network data [11] [12]. Most packet analyzers will significantly increase network traffic by observing assemble all the packets in a TCP conversation and the amount of data captured. This experiment would be represent the data using tcpdump format. Students were a good interfacing for a Network-security class. Figure asked to capture the user-id and password of their own 2 shows the memory display of the captured data.

00000000 50 4f 53 54 20 2f 63 67 69 2d 62 69 6e 2f 6c 6f POST /cg i-bin/lo 00000010 67 69 6e 2e 63 67 69 20 48 54 54 50 2f 31 2e 31 gin.cgi HTTP/1.1 00000020 0d 0a 41 63 63 65 70 74 3a 20 61 70 70 6c 69 63 ..Accept : applic 00000030 61 74 69 6f 6e 2f 76 6e 64 2e 6d 73 2d 65 78 63 ation/vn d.ms-exc 00000040 65 6c 2c 20 61 70 70 6c 69 63 61 74 69 6f 6e 2f el, appl ication/ 00000050 6d 73 77 6f 72 64 2c 20 61 70 70 6c 69 63 61 74 msword, applicat

Figure 2(a) Packet Sniffer Output - www.rediff.com

00000000 16 03 00 04 79 02 00 00 46 03 00 2f ed 29 44 2a ....y... F../.)D* 00000020 7a b2 b5 95 40 08 c3 74 ae 70 98 20 49 08 00 00 [email protected] .p. I... 00000030 82 32 61 be ad eb b1 27 ee 5e 93 e6 b3 1e ac 79 .2a....' .^.....y 00000040 7e 80 31 0b d2 2e b9 70 3b e5 55 b3 00 03 00 0b ~.1....p ;.U..... 00000050 00 03 5a 00 03 57 00 03 54 30 82 03 50 30 82 02 ..Z..W.. T0..P0.. 00000060 bd a0 03 02 01 02 02 10 3c f4 4e cc 7b c3 e6 34 ...... <.N.{..4 00000070 b0 3f 2d 8e b8 78 41 27 30 0d 06 09 2a 86 48 86 .?-..xA' 0...*.H. 00000080 f7 0d 01 01 05 05 00 30 5f 31 0b 30 09 06 03 55 ...... 0 _1.0...U

Figure 2 (b) Packet Sniffer Output - www.hotmail.com

Example -3 without analyzing its content. The defense team In general, database systems track their own users accurately analyzed the data column that represented before allowing the access. Access to database systems clock values to illustrate the time line of events. The is controlled using a user-id and a password for defendant was found not guilty [10]. legitimate users. However, some databases can be attacked without a valid user-id and password. Such Other Architecture-Security Applications attacks can be performed by applying the knowledge of In addition to the network-database-security Boolean logic expressions learned in an introductory experiments described above, it is possible to search, digital-logic design class. In one such successful develop and integrate introductory experiments for database intrusions, the attacker entered the system by intrusion detection, forensic analysis of storages, converting user-id and password expressions combined sanitizing storages, web security and network security. with one AND operation into two arbitrary expressions Providing hardware and software support, and combined with an AND operation followed by an OR specifying protocols to make the processor and storage operation with an expression that always evaluated to a secure can also be considered at any stage of the course True value [8][9]. sequence. The most time-consuming task in solving security issues, similar to the one described in the Example -4 introductory part of this paper, will be the postmortem Often legal experts have difficulties interpreting the analysis. There is a need to perform forensic analysis of forensic data available in the memories. Utah vs. Payne the data in the storage to determine the source of e-mail presents an interesting application of clock values. In transmissions and decode other communications. A this case, the prosecution presented data to the courts computer architecture course with security and privacy

38 related applications, such as the ones described above, applications in a relatively passive classroom and protocols to provide security and privacy to storage environment. One of the reasons for diminished student will enhance students' higher level skills: teamwork, interest of learning the subject is poor interfacing with analysis, synthesis and active participation in the other courses in the curriculum. In general, learning classroom. These course modules will help students takes place if the student can both integrate what he is learn architectural concepts in an active learning learning in the classroom into real-life applications and environment, thus providing students an opportunity to understand how the subject pertains to learning other function well in an increasingly competitive society in subjects in the degree program. To promote this in the which security is highest priority. classroom and to overcome the above-mentioned deficiencies, an intermediate computer architecture Difficulties course can be developed with hands-on classroom Incorporating security and privacy related issues in activities and laboratories involving architecture and many subject areas into the architecture course may security. Computer security issues are important for overload the students and faculty. Selecting a series of businesses, industries and government. There is a need projects that increase enthusiasm among a diverse body for increased computer architecture education with of students will not be an easy task. To overcome this security and privacy emphasis through undergraduate difficulty, we plan to work with information security level computer science curricula. This need can be met faculty to develop suitable laboratory experiments. through several stages. Computer architecture laboratories should have application interfaces to other Course Assessment courses in the curriculum such as operating systems, Once developed, the course material can be evaluated network, databse security. And further training of by soliciting criticism from faculty and students. students can be accomplished by developing Student learning can be evaluated in many different mathematics, operating systems, networking and ways. Background knowledge can be performed in the database courses with an emphasis on security. form of a simple questionnaire/worksheet that the Regular regional symposiums are very helpful to share students fill out prior to completing the lab assignments. the laboratory and curriculum development efforts with Students will be asked to explain the concepts they other colleges and universities. The availability of learned. Recording experiences from laboratory properly designed and developed course materials, with assignments is an essential part of student work. Group- a series of hands-on laboratories as well as classroom work evaluations will also be used to assess the course. activities, will reduce both instructors’ preparation time The faculty and teaching assistants regularly observe and multiple copying stages, and increased students’ the team work. There are opportunities to test course ability to absorb the subject matter. Developing a series materials within a large university system that could of system-on-chip experiments and/or security possibly extend use to other faculty and students. protocols for storages would be useful for the laboratories in the third course of the sequence. These Information Security Symposium objectives can be accomplished through the optimal use Two computer security symposiums were organized at of available resources. Through such platforms, the end of the Spring 2003 semester to stimulate our students will learn to appreciate instruction set students, computer science, information systems and architecture. engineering faculty in five neighboring states as well as businesses and industry. Invited speakers from West Acknowledgments Point Military Academy, Carnegie Melon University, University of Idaho, the University of Minnesota, the Our computer architecture project has been supported University of Iowa, the University of Wisconsin and the by the MnSCU Center for Teaching and Learning University of North Dakota delivered lectures based on through the Bush/MnSCU Learning by Doing Program. their work. The symposium was well attended by Many students helped to make our extensions to the students, faculty and industry representatives. These courses successful. We would like to specially thank to symposiums helped our efforts to develop a curriculum Professor Larry Grover, Dr. Splittgerber, Erik Cramer, emphasizing secure storages, forensics, network- Mark Ebersole, WeiShin, Mohammad Khan, Amit database security that presents an integrated view of Parnerkar for helping us throughout the years to hardware, software and security issues to the accumulate experimental data. undergraduate students [6][7]. 3. Summary and Future Work 4. References Traditionally, computer architecture courses are 1. Gehringer, E.F. A Web-Based Computer presented to a less-than-enthusiastic student body and Architecture Course Database, often delivered without indicating real world

39 http://www.csc.ncsu.edu/eos/users/e/efg/archdb/FI 6. Symposium on Information Assurance and Security E/2000CACDPaper.pdf -2003 2. Computer Architecture I http://web.stcloudstate.edu/sherath/SIAS2003 http://web.stcloudstate.edu/jherath/CompArch-1 7. Information and Network Security Workshop-2003 3. Hennessy, J. L., Patterson, D. A. Computer http://web.stcloudstate.edu/sherath/INSW2003 Organization and Design: Hardware/Software 8. Pfleeger, Security in Computing, Interface, Second Edition, 1997 http://www.prenhall.com http://www.mkp.com 9. http://www.cs.uwec.edu/~wagnerpj/security/ 4. Computer Architecture II 10. http://www.simson.net/2002-11-Forensics.ppt http://web.stcloudstate.edu/jherath/CompArch-2 11. http://winpcap.mirror.ethereal.com/install/default.ht 5. Hardware/Software Interfacing for High m Performance Symposium -02 12. http://www.ethereal.com/distribution/win32/ http://web.stcloudstate.edu/jherath/Conference.htm

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48 Building Resources for Teaching Computer Architecture Through Electronic Peer Review

Edward F. Gehringer Depts. of ECE and Computer Science North Carolina State University [email protected]

1. Abstract has been used in a wide variety of disciplines, among them accounting [8], engineering [7, 10], mathematics Electronic peer review is a concept that allows students [3], and mathematics education [6]. to get much more feedback on their work than they However, electronic peer review experiments have normally do in a classroom setting. Students submit been much rarer. Although the Daedalus Integrated assignments to the system, which presents them to other Writing Environment [1] is widely used for peer assess- students for review. Reviewer and author then com- ment of student writing, only a few computer-mediated municate over a shared Web page, and the author has a peer-review experiments have taken place in other chance to submit revised versions in response to re- fields. An early project in computer-science and nursing viewer comments. At the end of the period, the review- education was MUCH (Many Using and Creating Hy- er gives the author a grade. Each author gets reviews permedia) [9, 11]. The earliest reported software pro- from several reviewers, whose grades are averaged. At gram to support peer evaluation was evidently created the end of the review period, there is a final round when at the University of Portsmouth [12]. The software students grade each other’s reviews. Their grade is provided organizational and record-keeping functions, determined by the quality of both their submitted work randomly allocating students to peer assessors, allowing and their reviewing. peer assessors and instructors to enter grades, integra- ting peer- and staff-assessed grades, and generating This paper reports on our use of peer review in two feedback for students. One of the early Web-based computer architecture courses, a microarchitecture peer-review experiments was described by Downing course and a parallel-architecture course. Students in and Brown [2]. Their psychology students collaborated these courses engaged in a variety of peer-reviewed to create hypertexts which were published in draft on tasks: Writing survey papers on an aspect of computer the World Wide Web and peer reviewed via e-mail. architecture, making up homework problems over the Our project was one of the first to use the Web for both material covered in class, creating machine-scorable submission and review of student work. questions on topics covered during the semester, anima- ting and improving graphics in the lecture presenta- tions, and annotating the lecture notes by inserting hyperlinks to other Web documents. Students generally 3. Peer Review on the Web found these exercises beneficial to their learning exper- ience, and they have provided resources that can be There is much to recommend a Web-based approach to used to improve the course. In fact, with such a system, peer review. Unlike software that is written for a large classes are actually a blessing, since they produce specific academic field (e.g., English composition), a better and more copious educational materials to be Web-based application can accept submissions in used in subsequent semesters. practically any format, including diagrams, still pictures, interactive demonstrations, music, or video clips. Of course, the student has to understand how to 2. Peer Review in the Classroom produce such a submission, but for each field, that expertise tends to “come with the territory.” Peer review is a concept that has served the academic Secondly, the Web is a familiar interface. Most community well for several generations. Thus, it is not students use the Web in their day-to-day studies, so surprising that it has found its way into the classroom. they can pick up a Web-based application for peer Dozens of studies report on different aspects of peer review with minimal effort. In addition, many if not review, peer assessment, and peer grading in an most students are already familiar with tools for academic setting. A comprehensive survey can be producing Web pages; for example, almost all found in Topp 98. Experiments with peer assessment wordprocessors can save files in HTML format. of writing go back more than 25 years [4]. Peer review

49 Thirdly, Web creation skills are of increasing importance in business as well as academia. In producing work for Web-based peer review, students not only learn about the subject of their submission, but also gain valu- able experience with software they will use in their later studies and on the job.

Fourthly, a Web interface enables the peer-review program to be used in distance education, which is an important and rapidly growing segment of the education market. On- campus students can review distance- education students, and vice versa, bringing the two groups closer togeth- er in their educational experience. With Web-based submission, there is no extra overhead for the instructor or TAs in handling distance-education Figure 1. PG’s welcome page students.

Finally, Web-based peer review facili- tates the production of Web-based resources. The best peer-reviewed work can be turned into materials to help future classes learn. For example, students can create machine-scorable questions for each lecture, with differ- ent sets of students choosing different lectures. The best questions on each lecture can be incorporated into daily quizzes delivered via a Web-based testing system such as LON-CAPA [15], Mallard [16], or WebAssign [17].

Or, students can write research papers on various topics assigned by the instructor (e.g., the branch-prediction strategy of a particular processor arch- itecture). The best paper on each topic canthenbepresentedtothenext semester’s students as background reading on that topic. The writers can Figure 2. PG’s login page be asked to include liberal doses of hyperlinks in their papers, so that later students can read Reviewers can be assigned pseudo-randomly by PG, or not only their work, but also the analyses of experts. by the instructor, using a spreadsheet. The number of reviewers is arbitrary, but usually three or four students are assigned to review each submission. Reviewers and 4.ThePGSystem authors communicate double-blindly via a shared Web page. At the end of the review process, the reviewer PG (Figure 1) is a Web-based application for peer assigns a grade to each author whose work (s)he has review and grading. It is written in Java and is servlet reviewed. A student’s grade is the average of the based. Students submit their work over the Web. grades given by the reviewers, plus an incentive

50 described below to encourage careful reviews.

A student entering the PG system(Figure2)hasachoice of whether to submit a new page or review pages submitted by others. If more than one Web page is to be submitted, they may be sub- mitted sequentially, each with a different filename, or sub- mitted in a single Zip or tar file, which PG will unpack into its components. Entire directory hierarchies may be submitted in this manner. Since the files themselves are copied, all work to be reviewed will have a URL beginning with the pathname of the PG system, not the submitter. This ensures that the reviewers will not be able to guess their authors’ Figure 3. Page with links to submissions to be reviewed identities by dissecting the URL. The ability to submit directory hierarchies allows large projects to be submitted as easily as small ones.

Reviewers communicate with their authors via a shared Web page. There is one such page for each author (Figure 3); the author can view the reviewers’ comments and vice versa. The instructor can configure the system either to allow (Figure 4) or not to allow reviewers to see the other reviewers’ comments and assigned grades. There are reasons in support of both strategies. Allowing reviewers to see each other’s feedback provokes better dialogue over the quality of a submission, but the first reviewer’s comments may unfairly influence subsequent reviewers’ assessments.

Grading is based on a rubric consisting of several questions that the reviewer must answer with a numeric score. The questions may be assigned different weights, if desired. The grade that a particular reviewer gives a student is calculated by summing the product of each score with the corresponding question weight. A rubric-oriented approach is used to insure that all students are graded on the same criteria, and to reduce the chance that a Figure 4. Review page reviewer will give an unrealistically high

51 grade due to ignoring some of the criteria that the submission is supposed to meet. In addition to giving numeric scores, the reviewer has ample opportunity to give feedback to the student on how to improve. This can be seen in Figure 5.

5. The Submit- Review-Publish Cycle

Our experience with PG has ledustoafour-tosix-phase cycle, capable of producing high-quality peer-reviewed work suitable for Web publi- cation. 1. The signup phase (optional): If not all studentsaretodothe same assignment, the students are given a list of potential topics (relating to research, or to a partic- ular lecture, etc.) and sign up for one of them. To assure that all topics are chosen, only a limited number of students is allowedtosignupfor any particular topic. 2. The submit phase. Students prepare their workandsubmitittoPG. 3. The initial feedback phase. Students are given a certain period of time— Figure 5. Grading rubric usually 3 to 7 days—to make initial comments on grade. This grade is one component of the author’s all the work This phase was instituted after final grade for the assignment. students complained that their reviewers often did not comment on their work until it was too late to revise it. Reviewers may assign a grade during this 5. The review of review phase. After the review period period, but they are not required to do so. is over, each student is presented with a set of reviews to assess. The students grade each review 4. The grading phase. During the next period—again based on whether it was a careful and helpful review usually 3 to 7 days—students can revise their work of the submission. The grades the students receive in response to reviewers’ comments, and reviewers on their reviewing is then factored into their grade can comment on the revisions. At the end of this for the assignment (usually 25% of their grade is give-and-take, reviewers are required to assign a based on their reviewing). This phase was instituted

52 after it was discovered that many students were hyperlinks to other Web pages that define the term or doing cursory reviews. As will be seen in Section 7, describe the topic I am covering. Typically the students this is a sufficient incentive to be careful in insert several dozen hyperlinks in each 75-minute lec- reviewing. ture. The best annotation of each lecture (the one with the highest grade) is then made available to students in 6. The Web publishing phase (optional). PG creates a the next semester. In this way, students in one semester Web page with links to the best student assignment produce a resource that helps students in subsequent in each category. As described below, this can serve as a useful study tool for future generations of semesters to fill in gaps in their understanding of the students. material. An excellent way to improve students’ understanding of the material is to have them make up questions over 6. How Peer Review Has Been Used what they have studied. I have assigned two different kinds of peer-reviewed questions. The first is madeup in Computer-Architecture Classes homework problems. Students are asked to make up a problem similar to those on the problem sets I assign There are opportunities to use peer review in almost for homework (typically these are problems from the any course. One of the best opportunities is in evalu- textbook or similar problems). The students then peer- ating student writing. Prospective employers and thesis review each other’s problems. Students learn by check- advisors widely believe that technical students need ing each other’s work, and the problems they make up frequent opportunities to hone their writing skills. But are often good enough to be used for subsequent home- students need ample feedback in order to improve. Peer works and exams in the course. For example, in the last review can give more copious feedback than instructor three times I’ve taught my parallel architecture course, or teaching-assistant review, for the simple reason that I’ve used 27 problems that were made up by students in each student has only a few submissions to review, previous semesters. Given the fact that most instructors rather than several dozen. Moreover, students will be say [14] it is either important or very important to in- writing for an audience of their peers later in their ca- crease their supply of questions beyond what they now reers, so it is important for them to learn how to do this. have, the usefulness of this approach cannot be denied.

In computer-architecture courses, I have assigned Students’ comprehension of lectures can be improved if students to write reviews of papers from the technical they are asked a set of questions about the lecture after literature. I always assign two or three related papers viewing it. In recent years it has become possible to so that the students cannot simply summarize a paper, pose questions and score student answers via a Web but must instead integrate material learned from assessment and testing system like LON-CAPA [15], different sources. For example, in my microarchitect- Mallard [16], or WebAssign [17]. It would be a major ure course (using the Hennessy-Patterson text time commitment for the instructor personally to write a Computer Architecture: A Quantitative Approach), I set of questions on each lecture, but peer review makes assigned these papers on power-aware architectures: it possible for the students to write the questions them- selves. Moreover, these questions come already “pre- “Energy-effective issue logic,” Daniele tested” by a small set of students—the peer evaluators. Folegnani and Antonio Gonzalez, 28th Beginning in Fall 2002, I had students write a set of International Symposium on Computer machine-scorable questions over the material in a Architecture, July 2001, pp. 230-239. specific lecture. This produced a “bank” of questions “Drowsy caches: simple techniques for that can be used to create daily quizzes for students in reducing leakage power,” Krisztian Flautner, later semesters. Ultimately, they could become a Nam Sung Kim, Steve Martin, David Blaauw, resource for a Web-enhanced version of the textbook and Trevor Mudge 29th International we are using. Symposium on Computer Architecture,May Computer architecture is a rather visual subject—one’s 2002, pp. 148-157. comprehension is often improved by seeing a picture, I also have students do annotations of my lecture or a graphical simulation, of a topic or an algorithm. notes, which are on line as PowerPoint or Word files Cache coherence and instruction-level parallelism are [13]. Each student signs up to annotate one of the examples of such topics. Since some students are gifted lectures during the semester. Depending on how many in visual arts, I have allowed students to choose an students there are in the course, two to four annotations animation as one of their peer-reviewed assignments. of each lecture are produced. This consists of inserting The best of their animations can then be incorporated into future lectures.

53 Peer review can be used for research papers. Though I have not yet assigned this in a computer-architecture course, in my opera- ting-systems course, I had each student select a research topic from a set that included topics like “Scheduling in Windows NT,” “Dead- lock handling in Unix or a particular flavor of Unix,” and “Virtual memory in Linux.” Figure 6. Peer-reviewed assignments in parallel-architecture class Similar topics in arch- itecture would be the cache-coherence algorithm, branch predictor, or instruc- tion-retirement ap- proach used by a particular architecture.

Assuming that students have the requisite computer skills, elec- tronic peer review is as widely applicable as peer review in general. The author has prev- iously reported on its use in computer science [18] and ethics in com- puting [19] courses.

Through peer review, each class can stand on the shoulders of prev- ious classes, learning the material with better resources, and produ- cing ever-better tools to teach future classes. In Figure 7. Peer-reviewed assignments in microarchitecture class some cases, instead of seeing large classes as a burden, an instructor may come to prefer them because they can create more formidable Web-based resources, 7. Choosing Assignment Types and do so without burdening the instructor and with additional grading responsibility. This is an example of During the semester, I assign several peer-reviewed “education engineering” [20]—developing methodol- assignments, and several types of peer-reviewed work. ogies and tools to create educational materials more I give the students a choice of which order to do the quickly and in greater volume, and disseminate them assignments, subject to the constraint that there is a without loss of quality to the increasing numbers of limit to the number of students doing each type of students seeking a technologically up-to-date education. assignment for each deadline. This strategy is

54 motivated by a desire to students doing all kinds of reviewers. Currently, there is no guarantee that a assignment soon after each lecture, so that, e.g., while reviewer won’t complete reviewing in Round 2 Lecture 10 is fresh in their minds, some students will be before an author resubmits. The scheme will be making up problems, some will be annotating, and changed in Spring 2003 to have extra deadline, so some will be creating animations. This insures that I that there is a review period followed by a get problems, animations, etc. over a wide range of resubmission period, followed by a second review lectures, rather than having all submissions concen- period. This should take care of the problem. trated on the lectures that were covered near the time an assignment was announced. • A number of students objected to reviewers who gave low grades but few if any suggestions on how Figures 6 and 7 show the assignments I recently gave in to improve. Now students are told, during the my masters-level parallel-architecture class (CSC/ECE review-of-review period, to downgrade reviewers 506) and my combined senior/masters-level who deduct points without explaining why. microarchitecture class (ECE 463/521). Note that, in general, students thought that reviews of reviews were effective (3.9 on a scale of 5) in motiva- 8. Student reaction ting careful reviews. This suggests that giving students some guidance in how to evaluate reviews can motivate Students in both architecture classes were surveyed at students to review according to guidelines that they are the beginning of January 2003. In CSC/ECE 506, 16 of given. 36 students responded, a rate of 44.4%. In ECE 463/521, 71 of 96 students responded, a rate of 74.0%. The classes did not vary much in their reaction. 9. Conclusion The comments provided by students indicate fairly Electronic peer review has proved to be an effective strong support for the concept of peer review, but they technique for teaching computer architecture. It allows take issue with three aspects of the way it was the students to get experience writing for their peers, implemented for these two courses. and it facilitates the production of educational resources • They thought they were hurt by the fact thbat a few that can be used by future classes, such as annotated students did not do their reviews. In fact, the lecture notes, homework and test questions, and daily version of PG used at the time did not deduct machine-scorable quizzes. However, effective points for students who failed to do their reviews. implementation of peer review is tricky. Reviewers During Fall 2002, PG was modified to do this must be given good guidance in how to review and checking, and it will be in the system in coming sufficient motivation to do a good job. Authors must be semesters. This should lead to more reliable given enough time to revise their work pursuant to reviewing and therefore address this criticism. reviews, and reviewers must be given enough time to complete their final pass. Our experience with PG has • While generally supporting the idea of multiple given us many ideas on how to improve the process and review deadlines, they sometimes submitted an outcomes of peer review. update that was never re-reviewed by their

Table 1. Student Evaluation of PG CSC/ECE ECE 506 463/521 1 Peer review is helpful to the learning process. 3.63 3.41 2 I was satisfied with the reviews of my work. 3.53 3.47 3 The feedback I obtained from the reviews helped me to improve my work. 3.60 3.49 4 Two review deadlines were imposed, one for the first review and another for the final grade. Did this provide an adequate opportunity for you as an author to respond to the comments of your reviewers? 3.60 3.83 5 The knowledge that my reviews would be reviewed motivated me to do a careful job of reviewing. 3.93 3.92

55 [10] Rafiq, Y., & Fullerton, H., "Peer assessment of group projects in civil engineering," Assessment and 10. References Evaluation in Higher Education 21, 1996, pp. 69-81.

[1] The Deadalus Group, Daedalus Integrated Writing [11] Rushton, C., Ramsey, P., and Rada, R., "Peer assessment Environment, in a collaborative hypermedia environment: A case- http://www.daedalus.com/info/overtext.html study," Journal of Computer-Based Instruction 20, 1993, pp. 75-80. [2] Downing, T. and Brown, I., "Learning by cooperative publishing on the World-Wide Web," Active Learning 7, [12] University of Portsmouth, "Transferable peer 1997, pp. 14-16. assessment," in National Council for Educational Technology [ed.], Using information technology for [3] Earl, S. E., "Staff and peer assessment: Measuring an assessment, recording and reporting: Case study individual’s contribution to group performance," Assessment and Evaluation in Higher Education 11, [13] http://courses.ncsu.edu/ece521/common/lectures/notes.ht 1986, pp. 60-69. ml

[4] Ford, B. W., The effects of peer editing/grading on the [14] Gehringer, E., “Reuse of homework and test questions: grammar-usage and theme-composition ability of college When, why, and how to maintain security?” submitted to freshmen. Dissertation Abstracts International, 33, 6687. ASEE 2003 Annual Conference, Educ. Res. & Methods Division. [5] Gehringer, Edward F., “Strategies and mechanisms for electronic peer review,” Proc. Frontiers in Education [15] The Learning Online Network with CAPA, 2000, Kansas City, October 18–21, 2000 (to appear). http://www.lon-capa.org.

[6] Lopez-Real, Francis and Chan, Yin-Ping Rita, "Peer [16] Mallard: Asynchronous Learning on the Web, assessment of a group project in a primary mathematics http://www.ews.uiuc.edu/Mallard/. education course," Assessment and Evaluation in Higher Education 24:1, March 1999, pp. 67-79. [17] WebAssign, http://webassign.net.

[7] MacAlpine, J. M. K., "Improving and encouraging peer [18] Gehringer, E., “Peer review and peer grading in assessment of student presentations, Assessment and computer-science courses,” SIGCSE 2001: Thirty- Evaluation in Higher Education 24:1, March 1999, pp. Second Technical Symposium on Computer Science 15-25. Education,” Charlotte, Feb. 21–25, 2001, pp. 139–143.

[8] Persons, Obeua S., “Factors influencing students’ peer [19] Gehringer, E., “Building an Ethics in Computing evaluations in cooperative learning,” Journal of Business Website using peer review,” 2001 ASEE Annual for Education, Mar.–Apr. 1998. Conference and Exposition, Session 1461.

[9] Rada, R., Acquah, S., Baker, B., and Ramsey, P., [20] Gehringer, E., "A Web-Based Computer Architecture "Collaborative learning and the MUCH System," Course Database," 1999 ASEE Annual Conference and Computers and Education 20, 1993, pp. 225-233. Exposition, Session 3232.

56 Laboratory Options for the Computer Science Major Christopher Vickery Tamara Blain Queens College of CUNY Computer Science and Computer Engineering programs typically converge on the Dynamic-Static Interface (DSI) from opposite directions. Computer Science (CS) introduces students to system architecture and organization so they can have a better appreciation for the mechanisms that make their software work, whereas Computer Engineer- ing (CE) introduces students to software design so they can have a better appreciation for the software that will be using the hardware systems they design. Mindful of this distinction between CS and CE, we chronicle the efforts of our CS department to capitalize on current trends in the design and implementation of digital systems to extend our students’ expertise in this area. We summarize the current curriculum in our department, present a survey of the language options we have explored for evolving our curriculum, and conclude with a brief description of the labora- tory environment we have adopted, which is centered on the Handel-C hardware implementation language.

1 Introduction 2 Context: A CS Department Computer Science and Computer Engineering curricula Our undergraduate curriculum prepares students in the have traditionally brought significantly different per- broad areas of i)software design and implementation, ii) spectives to bear on what to cover and how to teach formal methods, iii) hardware design, and iv) applica- computer architecture, the point where the two disci- tions, in roughly that order of emphasis. Our offerings plines meet. Broadly speaking, the CS students bring in the “hardware design” area include a course in as- good software skills to their architecture courses, sembly language and basic logic design, and a second whereas the CE students bring stronger circuit design course that covers additional logic design and an intro- skills to theirs. The distinction carries over to the de- duction to computer architecture. We have used a sign of digital systems in industry, where a software number of textbooks for these courses over the years, team and a separate engineering team typically work in never finding ones that both students and faculty found parallel during the development of a new product completely suitable. The current text for both courses (codesign), with software/hardware integration occur- is by Murdocca and Heuring [22]. ring late in the development cycle. Our curriculum also includes a “Hardware Laboratory” But the inexorable advance of circuit complexity has course, which has not been offered in recent years. caused the traditional engineer/programmer dichotomy This course was developed in the days of SSI and MSI to start to break down. We are not talking here about integrated circuits and dropped by the wayside as simu- shifting the dynamic-static interface [23, 25] for a par- lators have allowed us to develop a similar degree of ticular system design, nor about the dual roles individu- mastery to the old lab course without requiring the stu- als might play in a design effort. Rather, we are dents to spend time in the lab itself. Thus, the closest responding to changes in the way digital systems are our students have come to a hardware laboratory ex- developed due to changes in the functionality of pro- perience for the past several years has been through grammable logic devices (FPGAs in particular) and the simulation assignments in the two courses mentioned software tools used to develop systems using them. above. The student edition of CircuitMaker [2] has Ours is a Computer Science department in a liberal arts served our purposes in this regard, although the free college. There is no engineering department on cam- version must be installed only on the students’ personal pus. Although the university encourages cooperation computers, not in college laboratory facilities. among its member colleges, the fact remains that the Four years ago, we received NSF funding [16] to revise closest CE courses available to our students are a 90- our curriculum to use HDLs to give our students a more minute subway ride away from us. In this context of realistic view of circuit design technologies. Our stated CS isolated from CE, this paper reports on the options goals were, “to give all of our students some knowledge we have considered as we adjust our curriculum to pro- of the methods that are used in designing modern digi- vide our undergraduate students with a better under- tal circuits [and] to provide those students who are in- standing of the principles and practices of terested with hands-on experience in designing and implementing digital architectures. using digital logic as a method of teaching them about computer architecture.”

57 At the time we prepared our grant proposal, VHDL On the other hand, implementing actual circuits can be seemed to be the natural vehicle for introducing CS much more motivating than just running “yet another students to logic design, leveraging their existing soft- program.” ware skills to introduce them to hardware design tech- We have not had good luck with most of the student- niques. There were several textbooks based on VHDL oriented simulators for logic design that are available at available, it was an IEEE Standard, and seemed gener- low or no cost. Many had problems with reliable ally well suited to our needs. Although Verilog also schematic entry, and many have had unnecessarily poor become an IEEE Standard in 1995, at the time of our user interfaces. The student edition of the CircuitMaker grant proposal, VHDL seemed like the most straight- schematic entry and simulation software from Altium forward way to go. Since then, there has been a good cited above has been the best we have found so far [2]. deal of foment in the CAD world, propelled by the need Compared to a textbook-only presentation, it’s far supe- for tools to adapt to the ever-increasing complexity of rior. But it limits the size of the designs students can digital devices. What follows is a survey of the evolv- implement, cannot be installed in departmental labs for ing software development options we have seen. free, and it doesn’t provide a tie-in to actual hardware implementation. 3 Laboratory Options Another option for those graduates who become inter- A first question CS departments have to answer in ested in chip design is to send them to commercially planning instruction in digital design is whether to fo- available short courses that teach digital IC or systems cus on simulation only, or to have the students target design, ECAD, or hardware/software codesign. But the actual hardware devices. A second question is whether danger in these courses is that there is “insufficient time to use commercial development tools or instructional to address any topic in the depth required by students to software. Once those questions are resolved, the issues gain proper insight into the subject area”. Thus these of software and (if hardware devices are targeted) pro- courses may not adequately provide them with the skill totyping platforms need to be addressed. set necessary for designing and implementing complex distributed embedded systems and Systems on Chip 3.1.1 Simulation or Hardware? (SOCs) [12]. And, of course, this option begs the ques- Simulation is a critical step in developing new hardware tion of what to do in the context of a university curricu- designs, but in an instructional environment, simulation lum. can arguably be the end step in a student’s lab experi- The gamut of options available for implementing cir- ence. cuits in hardware is extremely broad, ranging from in- There are several arguments for using only simulation expensive breadboards with SSI and MSI ICs for introducing CS students to the design of digital sys- connected by jumper wires to industrial-grade prototyp- tems: ing systems used in the development of commercial ASIC designs at costs that are prohibitively high for x Cost. Except for the computers to run the simula- virtually all instructional purposes. FPGA-based de- tions, a relatively abundant commodity, simulation velopment systems strike a middle ground between avoids the overhead and costs of purchasing and these two extremes, and are particularly well suited to maintaining prototyping equipment and instrumen- instructional laboratories. The boards are self- tation for a laboratory. contained units requiring no assembly on the part of the student, although expansion headers are normally avail- Ease of debugging. In addition to avoiding the x able for customized projects. Student designs are pre- issues associated with bad connections and failed pared and simulated on PCs, and downloaded to the components, simulation provides a software view of prototyping board through a serial or parallel cable. the system under development which is not only The use of reprogrammable FPGAs as the implementa- more familiar to CS students, but also more flexible tion target gives students a development cycle familiar than hardware in terms of allowing students to visu- to them familiar from the software development world: alize and locate problems in their designs. edit, compile, debug. x Simplicity. Development tools for hardware im- Major FPGA vendors, notably Altera and Xilinx, pro- plementations need to provide a richer feature set vide inexpensive or free student versions of their com- than instructional simulations. The result can be mercial tools for FPGA development suitable for use that students need to spend more effort learning to with a variety of prototyping boards from companies use the tool than studying the simulations. such as Xess and Digilent. An inexpensive package available from Altera’s University Program, for exam- ple, includes a prototyping board with a 20,000 gate

58 FPGA, several LEDs, displays, and switches mounted signs. It is relatively weaker in lower level designs but on the board, and I/O connectors for a mouse and VGA superior in higher level and system level designs, which display. This kit comes packaged with a good tutorial results in slower simulations. Its wealth of constructs, volume [17] featuring a number of interesting projects attributes, and types make VHDL a good language for students can do. The kit includes a student edition of design and verification [7]. It is strongly typed and Altera’s MAX+Plus development software, which in- there are many ways to model the same circuit, features cludes schematic, waveform, and HDL text editors for which make it more robust and powerful than Verilog design entry. It should be noted, however, that this kit but also more complex. This complexity means it is uses a relatively small FPGA by today’s standards, (not more difficult to understand and use. large enough to implement a full CPU) and that the Verilog has adopted many of VHDL’s features, thus MAX+Plus software does not provide the same func- Verilog is moving towards increasing complexity as tionality as Altera’s Quartus toolchain. Systems of this well [7]. Verilog is used for high-speed gate-level and type are more appropriate for introductory logic design register-level circuit descriptions, fast IC modeling and laboratories rather than CS Computer Architecture RTL simulation, easy synthesis, and test applications courses, where students need to explore architectural [9]. Gate simulations in Verilog are 10x to 100x faster design parameters. than the same simulations in VHDL, which means Hardware Description Languages (HDLs), most com- shorter time to verify designs [8]. Compared to VHDL, monly VHDL and/or Verilog, are the most commonly Verilog data types are simple, easy to use and geared used means for entering designs for platforms like those towards modeling hardware structure as opposed to discussed so far. But today’s FPGA devices can have abstract modeling. Because it is simpler, Verilog is millions of gates instead of tens of thousands, providing easier to learn. On a Verilog vs. VHDL debate forum, architecture students with hardware targets rich enough an engineer who knows both languages cites: “If you to support investigations into topics as advanced as were just taught Verilog syntax, you're in trouble. If pipelining, cache design, and multiprocessor communi- you were taught syntax with guidelines, and warned cation, not just basic logic design. Furthermore HDL about legal Verilog constructs that should never be programming is evolving to deal with the complexity of used, you can gain expertise in half the time it takes to these newer devices. We review some of these lan- become proficient in VHDL [8].” Because of its back- guages below. An appealing alternative to working ground as an interpretive language, there are no librar- with an HDL or one of its derivatives, at least for CS ies in Verilog whereas VHDL stores compiled entities, students who are approaching the DSI from the soft- architectures, packages, and configurations. Verilog ware side, is to use a language based on a traditional was originally developed with gate-level modeling in High Level Programming Language (HLL). After our mind, and so has very good constructs for modeling at survey HDLs and their derivatives, we will turn our this level and for modeling cell primitives of ASIC and attention to Handel-C, a hardware implementation lan- FPGA libraries. For this reason, students may find Ver- guage based on C that we are adopting for use by our ilog more digestible than VHDL at first. Because it is CS majors. geared towards lower level modeling, it is faster in simulations and effective synthesis. It lacks, however, 4 HDLs and Their Derivatives constructs needed for system level specifications. Ver- ilog’s simple, intuitive and effective way of describing 4.1.1 Verilog and VHDL digital circuits for modeling, simulation, and analysis purposes make it very popular in the industry. Hardware design is dominated by the use of Verilog and VHDL. They are most powerful as gate-level im- 4.1.2 ESL Design plementation languages [1][3]. VHDL allows a multi- tude of language or user-defined data types, which may There is a movement towards system level modeling, mean confusing conversion functions needed to convert also called electronic system level (ESL) design. This objects from one type to the other. All of the logical is the design of an electronic product at the conceptual operators, NAND, NOR, XOR, etc, are included in level, including hardware/software codesign; design VHDL but separate constructs, typically defined using partitioning, and specification writing [20]. It demands the VITAL language, must be used to define cell primi- being able to describe requirements and functions inde- tives of ASIC and FPGA libraries. VHDL offers a pendently of implementation, and being able to talk great deal of flexibility in terms of its abundance of about interfaces and protocols without describing the permissible coding styles. It allows for concurrent syn- actual hardware [19]. Verilog is neither object-oriented chronization schemes, such as semaphores. VHDL is nor strongly typed, which makes it cumbersome for better suited than Verilog to handle very complex de- system level design. Also, the previously attractive flexibility of its syntax can lead to difficult to detect

59 errors. Neither Verilog nor VHDL provides the syntax part of SystemVerilog, Superlog will remain a superset or semantics to describe a product at the system level of SystemVerilog. With its new additions, SystemVer- [20]. The trend of RTL engineers moving up in ab- ilog may remove some of the impetus for C-language straction and systems engineer moving down, as well as design, at least for RTL chip designers. The question of the fact that both Verilog and VHDL have shortcom- whether or not vendors will create tools to support Sys- ings in the requirements of ESL design, has necessi- temVerilog remains to be seen. [15] tated the need for either a new language, or the extension of an existing language to bridge the gap be- 4.1.4 HLL Pros and Cons tween specification and implementation. The new topic of debate is the question of which language is right for Teaching system level design in a High Level Language ESL design [20]. (HLL) is well suited to students with limited electronics or CAD backgrounds and are unfamiliar with hardware 4.1.3 Extended HDLs concepts such as signals, voltages, and details of the clock. By starting with either Handel-C or SystemC, Superlog is an extension of Verilog that includes fea- hardware/software codesign becomes more accessible tures that allow a more abstract description of an elec- to students whose initial programming experience will tronic system [20]. While most of the semantic most likely be C, C++, or Java rather than assembly elements added were borrowed from VHDL, it retains language [12]. It exposes the students to concurrency, most of the features of Verilog, including support for parallelism, software-to-hardware mapping, pipelining, hierarchy, events, timing, concurrency, and multi- and computer architectures as well programming prin- valued logic [6]. Superlog’s major technical advan- ciples [11]. In Handel-C, for example, each assignment tages over VHDL are a clean and powerful interface to statement takes one clock cycle and each expression C that allows hardware/software codesign, and C-based evaluation takes no clock cycles, which makes it easy to constructs for system design and decomposition [1]. It reason about the number of clock cycles required to borrows useful features from C and Java, including execute the code. This relationship encourages efficient support for dynamic processes, recursion, arrays, and compact code form a hardware perspective [11]. pointers. It also includes support for communicating processes with interfaces, protocol definition, state ma- However, there is a risk in HLL-based design for the chines, and queuing. It has been estimated that Super- student who already has a software mindset. Specify- log needs one half to one third the number of lines of ing hardware using an HDL is not programming, but code to describe a function as Verilog at the same ab- rather the building of hardware and arrays of gates. straction level, and Superlog can go much higher in Applying general purpose programming tactics to an abstraction [6]. HDL too often makes too many gates and highly ineffi- cient chip and logic layouts [21]. System Verilog. A radically revised version of Verilog was presented at the 2001 International HDL Confer- There are other shortcomings to the HLL approach. ence [15]. These changes represent a move towards an One is that it is hard to integrate outside IP with any even higher level of abstraction for the language and an hardware designed this way. This is due to the fact that extension to its capability to verify large designs. Sys- close examination of compiler-generated circuits re- temVerilog is a blend of Verilog, C/C++, and Superlog veals little of their purpose or about how they were that allows module connections at a high level of ab- generated. Therefore, the “hooks” into the circuitry are straction [15]. Verilog currently allows the connection not readily apparent. The obfuscated nature of the of one module to another only through module ports, compiler generated circuits also makes it nearly impos- which can be tedious. SystemVerilog introduces inter- sible to hand optimize any of these circuits. These faces which makes it possible to begin a design without problems stem from the fact that the original HLL on first establishing all the module connections. C- which these new languages are based either cannot ex- language constructs, such as globals, are another addi- press parallelism, or their concepts of memory, meth- tion. In Verilog, only modules and primitive names can ods, and objects map poorly onto real hardware. Thus be global. SystemVerilog allows global variables and the new languages are forced to include tools that in- functions. SystemVerilog borrows abstract data types clude the necessary attributes, but at the expense of from C, such as ‘bit’, ‘char’, ‘int’, and ‘logic’, which generating clean hardware. But as one industry expert provide more versatility then the existing ‘reg’ and ‘net’ points out, “elegance of implementation has never tri- types and allows C/C++ code to be included directly in umphed over timesaving hacks. Mnemonics overtook Verilog models and verification routines. Also in- opcodes, compilers overtook assembly, and HDLs over- cluded is an assertion construct, similar to VHDL’s, took schematics. Each time, the old guard maligned the intended to do away with proprietary assertion lan- inefficiency of the automated tools vs. the craftsman- guages. Because there’s much in Superlog that is not

60 ship of their methods; but each time automation carried support the development of models of embedded soft- the day [26].” ware [10]. Many ASIC or FPGA based products include a mixture The major drawback of SystemC is the need to convert of algorithmic processing most readily expressed in an a C/C++ based description to Verilog or VHDL in order HLL and other sets of operations most efficiently im- to synthesize it [20]. The problem is that there is not plemented directly in gates. FPGAs accommodate yet a working behavioral synthesis tool available for these designs by providing CPU cores that can be commercial use that can accept C++ as it’s input lan- drawn from a library and implemented in the logic fab- guage. The conversion process is currently a manual ric of the FPGA as well as the emergence of devices decomposition of the design until the designer gets to a such as Xilinx’ Virtex II Pro which include one or even low enough point of abstraction such that a commer- multiple hard CPU cores embedded directly in the de- cially available translator allows the use of RTL synthe- vice itself. In systems such as these, use of an HLL sis. This process, even if done automatically, is prone based implementation language provides a good fit for to errors that are difficult to find [19]. implementing the entire job [24]. An increasing amount of system functionality is ex- 5 Handel-C pressed in embedded software; synthesis and layout are Handel-C [4] is both a subset and a superset of conven- linked into one process, and the typical hardware de- tional C. It does not include functional recursion, float- signer is forced by complexity to work at a high level ing-point data, or any of the Standard C runtime library [14]. S/he would use the ultimate design system, where functions for I/O or string operations. However, its you wouldn’t even care what goes into the hardware or integer type is augmented with a rich set of operators software; you’d write C/C++ code and everything else and declarations for field widths, a par construct for would just happen under the hood because of an intelli- expressing parallelism, semaphores and communication gent C/C++ compiler [1]. According to some industry channels as primitives, and multiple main() functions, experts, this future may present itself in 5 to 10 years, each with its own clock [12]. Because it is a variation and those whose career paths extend that far would do on C rather than on C++, Handel-C is closer to the well to anticipate it [14]. hardware than SystemC [18]. Handel-C provides a rich set of code structures includ- 4.1.5 C Based Languages ing functions, arrays of functions, inline functions, SystemC. SystemC is an open source language that is macro procedures, and macro expressions. These facili- more a structured class library than a language. An ar- ties allow the student to explore time-space tradeoffs in gument for SystemC is that the C language lacks the a design. Handel-C is not tied to any particular family object-oriented facilities that some complex system of target devices, although it is clearly aimed at FPGA designs require [19]. SystemC was developed to sup- development in general [13]. port system level design. Its class libraries add hard- The Handel-C development environment supports cycle ware design-specific modeling constructs that increase accurate simulation, allowing students to see multiple the power of the language to meet the needs of hard- statements being executed in parallel using a debugging ware design [3]. The class libraries provide data types user interface fully reminiscent of traditional software appropriate for fixed-point arithmetic, communication IDEs. Compiling generates an industry standard channels, which behave like pieces of wire (signals), (EDIF) netlist, which is then imported into the FPGA and modules to break down a design into smaller parts. vendor’s toolkit, where VHDL or Verilog based mod- In addition, the class library contains a simulation ker- ules can be integrated and simulated with the Handel-C nel - a piece of code that models the passing of time, part of the design if desired. The vendor’s tools then and calls functions to calculate their outputs whenever perform place and route, and generate a bit stream for their inputs change [10]. The syntax is simple and downloading to the target device. [26]. close enough to C++ that students should find it easily digestible. Handel-C appears to be an ideal development language for CS students with limited experience in hardware SystemC partially addresses the problem that C lan- design. But adopting it for laboratory use introduces guage design presents by creating a number of classes tradeoffs that need to be considered. In particular, pro- that mimic hardware primitives and time-domain events totyping kits that take full advantage of the language’s [20]. Although at present it offers only modeling sup- ability to generate complex systems can add considera- port, SystemC is moving towards broader capabilities in bly to the cost of laboratory seats. For example, one synthesis [5]. Future versions of the class library will such kit is the RC200 from Celoxica, which includes a be extended to cover modeling of operating systems, to standalone prototyping board with a 1M gate Xilinx

61 FPGA, audio, video, networking, and memory subsys- [5] Clark, Peter. “IP99: Designers see little need tems and peripherals such as a camera and touchscreen. to move away from HDLs”. EE Times. 4 Nov. 1999. Fully equipped, this kit costs as much as a complete [6] Clark, Peter. “Startup to field next-generation midrange PC. design language”. EE Times. 31 May. 1999. 6 Conclusion [7] Cohen, Ben. Verification Guild. Vol. 1, No. 17. 14 Aug. 2000. janick.bergeron.com/guild. Trying to evaluate software development toolchains and/or target platforms can be as daunting a task as [8] Cummings, Clifford E. Verification Guild. trying to track emerging trends in design languages. Vol. 1, No. 17. 14 Aug. 2000. jan- With the recent emergence of FPGA devices so power- ick.bergeron.com/guild. ful and fast they challenge the one-time undisputed [9] Davidmann, Simon. “It’s time for a rethinking supremacy of ASICS for high-end designs, inexpensive of system-on-a-chip design”. EE Times. 25 Oct. 1999. FPGA-based systems, such as those available from Xess and Digilent, emerge as appealing vehicles for CS [10] Doulos Ltd. A Brief introduction to SystemC. programs interested in offering students exposure to www.doulos.com/knowhow/systemc_guide/tutorial/intr mainstream technologies of the day. And the main oduction. FPGA vendors, such as Altera and Xilinx provide stu- [11] Downtown, A.C., Fleury, M., Self, R. P., dent versions of their development platforms on very Sangwine, S. J., and Noakes, P. D. Hardware/Software reasonable terms for universities. Co-Design: A Short Course for Unbelievers. But logic design using VHDL or Verilog is not as at- www.celoxica.com/technical_library/files/”CEL- tractive an option for CS students as C-based develop- CUPACPGENHardware Software Co-Design - A short ment languages. We found the Handel-C development Course For Unbelievers-01002.pdf.” environment from Celoxica Ltd. particularly appealing. [12] Downtown, A.C., Fleury, R. P., and Noakes, Hardware is specified in Handel-C, and the resulting P. D. Future directions in computer architectures cur- netlist is then imported into an FPGA project (using ricula: Silicon compilation for hardware/software co- Altera or Xilinx tools, depending on the target), where design. HDL modules, including IP cores, can be integrated if www.essex.ac.uk/ese/research/mma_lab/Handelc/21CC desired. While inexpensive prototyping kits are avail- omputer.pdf. able that provide support for logic designs of modest complexity, we believe the options possible using Han- [13] Gaffar, A. A. “A Survey on the Handel-C del-C and more complex prototyping platforms like Language” Surprise Project 1999. Celoxica’s RC200 are more suitable for a CS laboratory www.iis.ee.ic.ac.uk/~frank/surp99/article1/amag97 in computer architecture. [14] Goering, Richard. “Rank and file don’t like We are in the process of setting up a CS laboratory C”. EE Times. 15 Nov. 1999. based on Handel-C and RC200 development kits and [15] Goering, Richard. “Standardization nears for will be offering the first class using the lab during the next-generation Verilog”. EE Times. 14 Nov. 2001. Fall 2003 semester. A major challenge for us is to de- velop a set of laboratory exercises that guide students in [16] Goodman, S. G. and Vickery, C. A Laboratory the effective use of this complex environment in a for Computer Organization and Architecture. NSF meaningful way. We look forward to sharing our ex- DUE-9950364, 1999. periences. [17] Hamblin, J. O. and Furman, M. D. Rapid Pro- totyping of Digital Systems: A Tutorial Approach. 7 References Kluwer, 2001. [1] Aldec, Inc. Evita: Advanced Verilog Tutorial [18] Hammes, Jeffrey P. A High Level, Algo- with Applications. www.aldec.com/Downloads. rithmic Programming Language and Compiler for Re- [2] Altium Ltd. CircuitMaker Student Edition. configurable Systems. www.circuitmaker.com. www.cs.colostate.edu/cameron/Publications/hammes_e nregle.pdf. [3] Bartlett, Joan. “The case for SystemC”. EEDesign. 7 March 2003. [19] Moretti, Gabe. “Get a handle on design lan- guages”. EDN Magazine. 5 July 2002. [4] Celoxica Ltd. Handel-C Language Reference Manual. Document Number RM-1003-3.0. 2002. [20] Moretti, Gabe. “System-level design merits a closer look.” EDN Magazine. 21 Feb. 2002

62 [21] Motorsabbath. Hardware design in JHDL. [24] Prophet, Graham. “System-level design lan- www.slashdot.org, 16 Jan. 2002. guages: to C or not to C?” EDN Europe. 14 Oct. 1999. [22] Murdocca, M. J. and Heuring, V. P. Princi- [25] Shen, J. P. and Lipasti, M. H. Modern Proces- ples of Computer Architecture. Prentice Hall, 2000. sor Design. McGraw-Hill, 2003. [23] Patt, Y. and Patel, S. Introduction to Digital [26] Turley, Jim. “The Death of Hardware Engi- Systems. McGraw-Hill, 2001. neering”. Embedded.com. 28 Feb. 2002.

63 Activating Computer Architecture with Classroom Presenter Beth Simon† Richard Anderson* Steven Wolfman* †Math & Computer Science, U. of San Diego *Computer Science & Engineering, U. of Washington San Diego, CA 92110 Seattle, WA 98195-2350 [email protected] {anderson,wolf}@cs.washington.edu Abstract term, Presenter aims to enhance learning and teaching In this paper we discuss our experiences using a Tablet PC- through new technologies and software for the classroom. based presentation system in an undergraduate computer The key components of the current system are the use of an architecture class. The system allowed us to integrate instructor Tablet PC (with high-quality inking support), PowerPoint slides with high quality pen-based writing and wireless network connectivity, and a data projector. to separate the instructor's view of the materials from the In this paper we focus on the presentation issues found in an students’ view. This allowed a more natural and interactive undergraduate Patterson and Hennessey-style architecture development of class concepts and content. course. We show how the interactive nature of inking on The system that we used was Classroom Presenter which empty (or intentionally incomplete) slides allows students was developed at University of Washington and Microsoft to participate in the microarchitecture design process, rather Research. The system has received substantial use at than having it presented to them “fait accompli”. University of Washington, being used in approximately 15 Specifically, we investigate Presenter’s ability to support large courses since Autumn 2002. The successful the in-class development and modification of datapath deployment at the University of San Diego in a small diagrams and active student participation in problem undergraduate course is interesting since the developers of solving. Additionally, we preview future Presenter support the system viewed Classroom Presenter as most appropriate for sharing tablet-based in-class group work. for large lectures and for distance courses. The deployment at the University of San Diego explored new ground in usage of the system. In this work we present an overview of the system and discuss particular uses and advantages of the system in an undergraduate architecture class setting.

1. Introduction Presentation technology impacts the structure and delivery of lectures. Different technologies support different instruction styles and provide various mechanisms for engaging an audience. In university classrooms predominant presentation technologies include blackboards, whiteboards, overhead projectors, and computers with data projectors. Each of these technologies has properties that maymakethemmoreorlesssuitabletospecificinstructors or course material. In particular, delivering a computer- based lecture has both advantages and disadvantages. Figure 1. A screenshot of the instructor’s Tablet PC Advantages include the ability to structure material in while using Presenter. The slide is minimized to provide advance, prepare high-quality examples and illustrations, extra writing space. The filmstrip is along the left of the and to share and re-use material[3]. But, these advantages figure allowing preview of and navigation among slides. come at the expense of flexibility during presentation – (CSE582, Univ. of Washington, Autumn 2002) especially in an undergraduate architecture class where The rest of the paper is organized as follows. In Section 2 we’d like students to experience for themselves the we describe the Presenter system and note three key tradeoffs inherent in the microarchitecture design process. features that arose in its design process. In Section 3 we Classroom Presenter (hereafter, Presenter) is a system describe an initial offering of an undergraduate computer developed and deployed by the University of Washington architecture class utilizing Presenter for class lecturing in a as part of the Conference XP conferencing experience small classroom setting (10-15 students). In Section 4 we project. The immediate goal of Presenter is to provide an describe upcoming Presenter features that empower improvement to the computer-based lecturing environment additional classroom interaction and group activities in both – offering, at a minimum, the benefits of prepared slides the small and large classroom environments. Section 5 and extemporaneous writing and diagramming. In the long describes related work and Section 6 concludes.

64 2. Presenter System tablet pen to write notes or diagrams directly over the slide, Figure 2 depicts the basic architecture of the Presenter as shown in Figure 1. The instructor can also shrink the system. The instructor loads a presentation composed of an visible slide and writing, creating new writing space around ordered deck of slides onto a mobile tablet computer. She the slide. The ability to write in the context of the slides can write on the slides with the tablet’s pen and control the maintains the connection between extemporaneous writing presentation—advancing slides, changing pen color, etc.— and the prepared content. Sustaining this link enhances the using controls displayed on the tablet. The tablet wirelessly slides’ value as a support structure for communication – a transmits control information and writing to a computer “mediating artifact” [16] − in the classroom. Additionally, driving a data projector, synchronously displaying slides if the instructor has even more to say, she can jump to a and writing to the entire class. In a distance class, a remote “whiteboard” slide to work an impromptu sample problem site would have its own computer and projector controlled or continue discussion beyond the context of the prepared by the tablet via the Internet. slide. Second, writing in Presenter is represented with high- quality ink, which renders in real-time and looks and feels natural. This is enabled by the high pen sampling rates and resolution on recent Tablet PCs and Tablet PC software support for smooth curves and pressure-sensitive line thickness. High-quality writing allows full use of the available resolution on the display, increases instructor comfort with writing and eases student comprehension of hand-written text. Finally, Presenter separates the instructor view of the presentation from the projected display that students see. Actually, Presenter supports three viewing modes: instructor (seen on the “primary” tablet), projector, and student. Instructor and projector modes are described here, while student mode will be further discussed in Section 4. The instructor uses the instructor view on her tablet while the projector machine ships the display view to the public Figure 2. The architecture of Presenter in the screen. This separation allows the instructor view to classroom. An instructor controls the presentation from include a wide array of tools—such as pen color and style a mobile Tablet PC. The tablet is wirelessly connected controls—and information displays—such as the filmstrip to a machine driving the display of the presentation on a pane on the left side of the display, showing miniatures of data projector. the slides immediately preceding and following the current slide. Furthermore, with no tether to the data projector, the tablet can go completely wireless, giving the instructor Presenter transmits and displays writing and control freedom to control her presentation from anywhere in the information in real-time over an 802.11b wireless network. classroom or even to pass the tablet to a student. In-class use of Presenter has been tested with most known brands of Tablet computers currently available (including Additionally, Presenter supports “instructor mode objects” Acer,Toshiba,HP/Compaq,Fujitsu,NEC,andMotion − text or drawings visible only on the instructor tablet view Computing models). The machine controlling the data and not shown on the projector view. These objects can projector must either have an internet connection or be contain reminders, notes, or hints to the instructor of issues connected to the same wireless network as the instructor’s to discuss in relation to the slide or questions to ask the tablet (no live internet connection required). Assuming a students. These objects can also encapsulate information classroom has already been outfitted with a computer and that the students will be asked to actively derive in-class – data projector, using Presenter would cost about $2000 for in contrast to more traditional static “here’s the resulting the Tablet PC and $150 for a wireless base station. Both of answer” treatments. Pictures, graphs, or diagrams can be these could be shared across classes, or the tablet could be annotated with circles, lines, or other drawing objects that used as a personal machine by an instructor. the instructor can “draw over” in class to highlight important areas or show modifications. Three key features of Presenter and, we believe, for lecture presentation systems in general, emerged from our in-class One unique capability of the Presenter system is that it experiences with our system. First, Presenter integrates facilitates the creation of an artifact from a given lecture. writing directly on top of slides. The instructor can use the Inked notes created in class can be saved in conjunction

65 with the slides from the class and viewed at a later time. This has implications for allowing instructors to review, in greater detail, the material and discussions covered in a given class period. Students could also be given access to inked notes from class discussions, at the discretion of the instructor.

3. Presenter for Undergraduate Architecture We discuss one semester’s experimentation using Presenter in a small-class undergraduate Patterson and Hennessey- style computer architecture class. We give examples of the various usages of Presenter system components in creating a more interactive lecture while still maintaining the organization and re-use features of an electronic presentation. Many of these examples echo recommended practices of modern pedagogy, e.g., active learning [9] and Classroom Assessment Techniques [2]. A survey of the Figure 3(a). Projector view with key points emphasized class found strong student approval of the Tablet PC-based via circling and highlighting. Additional notes at system, despite occasional technical issues involved with bottom of screen emphasize what was, hopefully, made clear in verbal lecture. beta-testing. Inking-Over for Emphasis, Notes to Mention Perhaps the most often used form of interaction enabled by the Presenter system is a simple circling or highlighting of a word or phrase on a slide. This can allow the instructor to visibly drive home an important concept or emphasize a term students should understand. In Figure 3(a) we see a projector view that might result after a discussion of execution time versus throughput. These circles were added at the same time a “verbal clue” was given to the students – showing emphasis or distinguishing from previously discussed concepts. Additionally, instructor- only objects (shown in Figure 3(b) in rounded text boxes) can remind the instructor of additional comments to make or simply encourage the instructor to prompt the class for a verbal response. Another instructor using Presenter combined inking for Figure 3(b). Instructor view after discussion. The emphasis with a simple feature of Presenter to develop a rounded text boxes are instructor objects, not seen on new discussion style. His discussion of a slide would focus the projected display. These objects can hold reminders on certain features of the material (emphasizing these in ink of points to emphasize in class. with highlights, circles, or other marks), next he would erase the ink with the “chalkboard eraser” button in class discussion, and Figure 4(c) shows the projector view Presenter’s top toolbar, and then he would discuss the slide after discussion. again from a different perspective and with different markings. The rapid erase feature enabled this new style This slide wraps up a discussion of benchmarking as a and tempo of discussion. manner of evaluating performance. Students are encouraged to recall a previous concept then apply it to the Culling Participation from the Class given problem. Specifically, students are asked to explain Next we show an example where the class will be shown why the doubling of the clock rate doesn’t produce a two graphs and asked to propose various conclusions that doubling of performance (circles on the left graph remind can be drawn. Figure 4(a) shows the instructor view before the instructor where to draw student attention). Instructor class discussion, Figure 4(b) shows the instructor view after notes at the bottom of the slide prompt the instructor to write, one more time, the ET = IC * CPI * CT equation and provide a color-coded reminder of the main topics students should bring up.

66 Note that, in class, the instructor can “draw over” the circles and arrow instructor objects – either at the direction of an astute student, or as a hint to the class if no suggestion is forthcoming. If a student brings up some issue other than those “expected” by the instructor, the instructor is free to explore that topic, ignoring his own notes. If, after that discussion concludes, he wants to return to a “clean” version of the slide to discuss the planned topics, he can erase all ink at once using the chalkboard eraser icon on the top toolbar. If he wants to perform a partial erase of certain words, the pencil eraser erases ink one stroke at a time. Interactive, But Planned, Problem Solving Figure 5 shows one example of interactive problem solving where the students can get a first experience with applying Amdahl’s Law. In order to be sure to cover all the “basics”, Figure 4(a). Instructor view before discussion. The there are instructor notes to encourage the instructor to fully “hand drawn” circles and lines, arrow, and text box are set up the equation and to relieve him of the need to instructor objects – not seen on projected slide. concentrate on simple math. A separate instructor note shows an additional calculation that can be discussed or omitted as time allows. A scroll bar on the instructor view allows the instructor to “scroll up” the ink (as on an overhead projector) of the Amdahl’s Law solution to provide additional room to solve the speedup equation (alternately, he can shrink the current slide to ¾ size and show additional work around the edges). In Figure 5(b), we see the projector version after the instructor has “scrolled up” some inked notes to solve an additional problem. Providing Unexpectedly Needed Review “You all know how to convert from decimal to binary don’t you?” When it becomes clear that one has misjudged the background knowledge of the class, Presenter allows one to easily “break out” of a planned lecture sequence. This can be done either by jumping to a backup slide (perhaps stored Figure 4(b) Instructor view after discussion. In-class at the end of the slide deck and accessed through the inking has occurred overtop of “instructor object” filmstrip view) or to a blank “whiteboard” slide to provide a inking as issues are raised in class. Some “notes” at quick review or to recommend a reference for student use. bottom have been “copied” for students. Summarizing What We’ve Learned Presenter can add new life to the usual “here’s what’s important from Chapter X” conclusion slides. Simply converting current summary bullets to an instructor object (not seen by students) can force students to take notes as the instructor “overwrites” key topics or allow the class to brainstorm their opinions of the most important material as in the “Empty Outline” Classroom Assessment Technique [2] pp.138-141. Adding an Instruction to a Single Cycle Datapath The freedom of instructor mode objects (rather than just instructor mode text) is especially useful when explaining and modifying charts, graphs, or diagrams. The slide shown in Figure 6 was developed as an in-class review of a Figure 4(c). Projector view after discussion. This is homework assignment where several students had produced what the students see. confused answers. They had been asked to modify the

67 4. Upcoming Features and Future Work

Additional Instructor Control Features Currently, all instructor notes must fit within the available real estate on the slide, and the built-in notes from PowerPoint are ignored. The on-slide notes offer extra flexibility—shapes, figures, etc. as notes rather than just text; however, off-slide notes would ease space management issues for instructors. In future versions, an optional extra pane will display PowerPoint notes. Furthermore, instructor notes are currently distinguished from public slide elements by a shadow beneath the note, allowing instructors to quickly determine which slide elements students see and which are invisible to them. However, some instructors prefer other mechanisms such as Figure 5(a). Instructor view where a pre-planned making instructor object text all one color, or using only the practice problem has been solved in-class. Text in rounded box shape for notes. We plan to support a broader bubbles are instructor objects and do not appear on range of mechanisms for distinguishing instructor notes. projected slide. Instructor can “trace over” instructor object equations to avoid skipping through solution too Instructor-Only Inking quickly. Notes in bottom instructor object bubble can Future plans for “instructor-only” inking would allow be discussed or skipped as time permits. instructors to make private inked notes during class (visible only on the instructor tablet). These notes could reflect anything that pops into mind in class that the instructor wants to remember afterward. Possibilities include comments on the efficacy of certain slides, points of confusion, and possible homework or test problem ideas. Tablets for Student Interaction in the Small Classroom While in-class group problem solving is often viewed by students as very instructional, instructors often feel the class time spent on these group activities comes at the cost of lecture presentation time. Specifically, if students are to benefit from the evaluation of other students’ work, then one must ask different groups to present their results to the class in some form (at the board, etc.). This adds yet more time to the group activity. Future versions of Presenter will support an additional, Figure 5(b). Projector view of 5(a) after “scrolling up” “student view” that will be wirelessly transmitted to Tablet first equation work to make room for new discussion. PCs scattered throughout the class. While not every student This new ink addresses the bottom instructor object may have a tablet, for the purposes of group work, each bubble in 5(a). group (or a subset of groups) can be given a tablet on which MIPS single cycle datapath (developed in Patterson and to record their work. The instructor tablet will have a Hennessey, chapter 5) to support only lw and sw method of previewing the various student tablet screens, instructions that had no displacement. In Figure 6(a) we and selecting one to be projected by the data projector. In see the instructor view before discussion. The datapath has this way, a group can “show their work” instantaneously. been “drawn over” with instructor object lines in different The group can be asked to describe their work, possibly colors. Notes are scattered around the slide as reminders of using additional ink (circling, etc) to emphasize points in the format of the instruction and as a guide to an ordering the discussion. for discussing the datapath modifications. In class, we see Some of the things students will be able do include working (Figure 6(b)) that the instructor has inked over the on a “blank screen”, solving a problem proposed on a slide, instructor objects as discussion of the problem progresses. modifying a datapath diagram, or filling in an empty cache. Figure 6(c) shows the much less cluttered projected version.

68 Wireless Data Projectors While current implementations require a separate machine to drive the data projector (so as not to tether down the instructor), future versions may discard this requirement through the use of wirelessly enabled data projectors. While still in their infancy, wireless data projectors could set up a connection with the instructor tablet to project only the projector view version of a slide.

Figure 6(a). Instructor view before discussion. Many instructor objects are present including text boxes, lines drawn over the datapath, and values for control lines.

Figure 6(b). Instructor view after discussion. Datapath lines have been “inked over” in the order recommended in an instructor object text note. The class was asked to supply control line values, which could be “checked” against instructor note values.

5. Related Work There have been a number of related efforts to deploy technology in the classroom to enhance learning, and to capture the lecture for later playback. eClassroom (formerly Classroom 2000) [1] is a premier project for incorporating technology in the classroom to facilitate note taking, capture, playback, and presentation. While eClassroom includes some effort to improve presentation facilities for the instructor, our work focuses directly on this aspect. Classroom Presenter also differs from eClassroom in that our goal is to deploy in a general data projector- enabled classroom, as opposed to basing our design on a dedicated facility. The Pebbles system [10] was one of the first projects to explore steering a presentation from wireless devices. Our emphasis on writing as part of presentation relates to the broad literature on pen computing and electronic whiteboards [11]. In this stage of Figure 6(c). Projector view of modifications to support our work we are not attempting a semantic interpretation of lw without displacement. Pen color changed to show the ink, as in the Back of the Envelope project [6]. Work which parts of the datapath had to be altered to on zoomable interfaces has relevance to our work, both in accommodate the new instruction.

69 suggesting alternative ways to view the display surface and [8] Lowry, R. B. Electronic presentation of lectures -- effect upon the presentation [5]. student performance. University Chemistry Education, 3 (1), 18- 21. 1999. The importance of actively involving students in classroom activities at regular intervals is supported by studies on [9]McConnell, Jeffrey J. Active Learning and Its Use in Computer Science. SIGCSE/SIGCUE Conference on Integrating student attention spans [2][13]. There has been some Technology into Computer Science Education (Barcelona, Spain educational work attempting to evaluate the use of June 2-5, 1996), also published as SIGCSE Bulletin, Vol. 28 PowerPoint in university classrooms [7][8][14]. The Special Issue, 1996, pp. 52-54. overall results have been ambiguous with respect to [10]Myers, Brad A. and Stiel, Brad A. and Gargiulo, learning outcomes, but the papers have some perceptive Robert. Collaboration using multiple PDAs connected to a comments on the use of PowerPoint and indicate a PC. In Proceedings of CSCW’98: ACM Conference on favorable student response. There has also been an active Computer-Supported Cooperative Work, pages 285–294, debate on the lecture style supported by slides with November 1998. polemics on all sides [15][12][4]. [11]Mynatt, E., Igarashi, T., Edwards, W. K., and LaMarca 6. Conclusions A. Flatland: new dimensions in office whiteboards. Proceedings of ACM Human Factors in Computing (CHI This work describes the Classroom Presenter lecture 99). New Your: ACM, pp 346-353. 1999. presentation system developed at the University of Washington. We highlight some of the specific utilities of [12]Rocklin, Tom. PowerPoint is Not Evil! National the system in the context on an undergraduate computer Teaching and Learning Forum Newsletter, 1997. architecture course. The main benefits of Presenter stem http://www.ntlf.com/html/sf/notevil.htm from wireless, high-quality inking over slides during lecture [13]Stuart, John and Rutherford, R. J. Medical Student combined with a separation of views between instructor and Concentration During Lectures. The Lancet, September 2, projector. These features have enabled high levels of 1978, pp. 514-516. spontaneity and interactivity in an undergraduate [14]Szabo, Atilla and Hastings, Nigel, Using IT in the architecture class. Specifically, the ability to use instructor- undergraduate classroom: should we replace the blackboard only visible objects to annotate diagrams and graphs can with PowerPoint? Computers & Education, 35 175-187, encourage the instructor to develop designs jointly with the 2000. class rather than presenting them as problems already solved. [15]Tufte, E., "The Cognitive Style of PowerPoint", www.edwardtufte.com, 2003. References [16]Vygotsky, L.S. Mind in Society. Cambridge, MA: [1]Abowd, G. D. Classroom 2000: an experiment with the Harvard University Press, 1978. instrumentation of a living educational environment. IBM Systems Journal, 38(4), 1999. Appendix: Classroom Presenter Feature List [2]Angelo, Thomas A. and Cross, K. Patricia. Classroom The Filmstrip. The Filmstrip is a “preview strip” of slides Assessment Techniques. Jossey-Bass Publishers, San surrounding the currently displayed slide. The filmstrip Francisco, 1993. facilitates non-linear slide navigation order, which can [3]Bligh, D. A. What’s the use of lectures? Jossey-Bass allow faculty to react to the development of ideas and Publishers, San Francisco, 2000. discussion in class. [4]Creed, Tom. PowerPoint No, Cyberspace Yes. The National Filmstrip preview. Another benefit of the filmstrip view is Teaching & Learning Forum, 1997, to allow the instructor to make appropriate concluding http://www.ntlf.com/html/sf/cyberspace.htm comments based on the content of the next slide to be [5]Good, Lance and Bederson, Benjamin B. CounterPoint: displayed. Filmstrip preview makes this more viable by Creating Jazzy Interactive Presentations. HCIL Tech Report showing an instructor-visible “zoomed in” version of a #2001-03. University of Maryland, College Park, MD filmstrip slide when the tablet pen is “waved” over a 20742, 2001. portion of the filmstrip. [6]Gross, Mark D., and Do, Ellen Yi-Luen. Drawing on the The Toolbar. Back and forward buttons are placed at both Back of an Envelope: a framework for interacting with ends to allow easy movement one slide in either direction of application programs by freehand drawing. Computers & the current slide. Four inking colors are supported as well Graphics, 24 pp. 835-849, 2000. as two ink “tips”: a square and a round tip. The next three [7]Hozl, J. Twelve tips for effective PowerPoint buttons select “regular pen” inking, highlighting, or stroke- presentations for the technologically challenged. Medical based erasing. The following three buttons control the Teacher, 19, 175-179, 1997. view: full slide, ¾ size slide, or blank whiteboard (you can

70 jump from the whiteboard back to your current slide by clicking on the “full slide” button). The chalkboard eraser erases all ink on the current slide. An upcoming feature will be “undo” which can undo the last selection (particularly important for the full erase).

ACKNOWLEDGMENTS: We thank the University of Washington CS Education and Educational Technology Group for their support and insights.

71 The Liberty Simulation Environment as a Pedagogical Tool

Jason Blome Manish Vachharajani Neil Vachharajani David I. August Departments of Computer Science and Electrical Engineering Princeton University {blome, manishv, nvachhar, august}@cs.princeton.edu

Abstract tecture’s high-level structure. This paper describes how the Liberty Simulation Envi- An approach that leads to a much better understanding of ronment (LSE) and its graphical visualizer can be used in a a microarchitecture is to have the students design the hard- computer architecture course. LSE allows for the rapid con- ware for a machine and run programs on it in a simulated struction of simulators from models that resemble the struc- environment. This way students will discover, on their own, ture of hardware. By using and modifying LSE models, stu- the intricacies of how different parts of the architecture in- dents can develop a solid understanding of and learn to rea- teract to facilitate the correct program behavior. The insight son about computer architecture. Since LSE models are also gained from this process of design, test, and debugging is relatively easy to modify, the tool can be used as the basis often deeper than any knowledge gained in lecture. Unfor- of meaningful assignments, allowing students to explore a tunately, specifying the hardware, even in a synthesizable variety of microarchitectural concepts on their own. In lec- hardware description language like VHDL or Verilog (as tures where block diagrams are typically displayed, LSE’s opposed to a gate level description), can take many weeks. visualizer can be used instead to not only show block dia- As a result, when this method is employed, it is typically grams, but to demonstrate the machine in action. As a result, limited to a single course-length project. While a project of LSE can ease the burden of conveying complex microarchi- this type is better than no design experience, it only provides tectural design concepts, greatly improving the depth of un- insights about the techniques employed in one particular de- derstanding a computer architecture course provides. sign, which is often a small subset of the techniques taught in the class. 1. Introduction A promising alternative to specifying the hardware is us- The goal of a computer architecture course is to teach ing, building, and modifying higher-level simulation tools students how microprocessor hardware operates and to give for the microarchitecture. Assignments could consist of ask- them an opportunity to experiment with microprocessor de- ing students to modify a simulator to incorporate new behav- sign. To do this, the students need to learn about existing mi- ior. Unfortunately, current simulation environments are too croarchitecture design techniques ranging from simple con- difficult to modify to make this practical for periodic home- cepts such as pipelining to advanced organizations such as work assignments. Furthermore, the most common method out-of-order machines including features such as specula- of building a simulator (coding it by hand in C or C++) does tion, branch prediction, and register renaming. little to convey the actual hardware structure or the func- Unfortunately for the student, the expanse of the com- tionality of its components [1]. Consequently the process of puter architecture design space is vast and complex. Within reasoning about and building the simulator is very different a single design, each component plays an important role in from the way in which a computer architect would design a facilitating the correct and efficient execution of a program, microprocessor thus making it unsuitable as a pedagogical however, correct execution is only ensured when interaction tool. Students should think like architects, not like simulator of all the components is carefully orchestrated. These com- writers. ponent interactions are often subtle making it difficult to To be effective for use in assignments, the simulation sys- convey enough information in lecture to foster a deep un- tem should have simulator descriptions that reflect the hard- derstanding. ware being modeled. Components used in modeling should To remedy this, courses are augmented with periodic as- correspond to hardware blocks and they should be intercon- signments that encourage the students to discover some of nected via communication channels like hardware blocks. the complexities on their own. Typically, these assignments On the other hand the simulation environment should not involve drawing pipeline sketches and evaluating block di- impose, upon the student, the burdens that hardware descrip- agrams. Unfortunately, these assignments do little to foster tion languages like VHDL or Verilog often do. Instead, it an understanding of the complex dynamic interactions and should allow rapid construction and modification of models instead reinforce the students’ understanding of the archi- so that working with an executable model can be a part of

72 regular assignments. LSE is a simulator construction tool that meets the requirements outlined above. In this paper we give an Module overview of the Liberty Simulation Environment (LSE) and Library describe how it can be used in a course to enhance student understanding of computer architecture. In the next section we describe the Liberty Simulation Environment. In Sec- tion 3 we describe the LSE visualizer and how it visualizes LSS Liberty the LSE descriptions. Then, in Section 4 we give specific Machine Simulator Description Constructor examples of how to use LSE in a course. Finally, we con- clude in Section 5.

2. The Liberty Simulation Environment Simulator The Liberty Simulation Environment (LSE) is an excel- C Code or Executable lent tool for students to learn about and explore microarchi- tecture. LSE descriptions resemble the hardware they model and are easy to modify. This section describes enough about Figure 1: Overview of main LSE components. LSE so that it is possible to understand how LSE can be used for instructional purposes. Details of how LSE enables rapid scription. Parameters can control simple configuration op- specification while still resembling the modeled hardware as tions (e.g. the cache line size or whether a 2-level branch well as details of all the concepts described in this section predictor has a global or per-address predictor table). Fur- can be found elsewhere [1]. ther, parameters can also be used to allow control of algo- As shown in Figure 1, LSE consists of three main parts: rithms allowing users to customize complex behavior. For the Liberty Structural Specification Language (LSS), a com- example, the branch predictor has a parameter that allows ponent library, and the Liberty Simulator Constructor. To users to override the predictor state-machine code to imple- use the system, the user describes a machine by specifying, ment a custom predictor if none of the provided predictor in the LSS language, a set of interconnected instances of options is suitable. Parameters can even control the instanti- components. These components, called modules, are typi- ation of hardware structures in lower levels of the hierarchy. cally taken from the module library although custom mod- 2.2. Communication Channels ules can be created if necessary. The user then invokes the simulator constructor, and the constructor reads the specifi- Modules specify a communication interface for module cation and the code from the module library and builds an instances by declaring ports. Each instance may have one or executable simulator for the described machine. This sec- more port instances per port. Each port instance is a com- tion will discuss in more detail the properties of modules, munication channel and may have exactly one value sent on module communication, and collection of data from a run it per cycle. For example, the register file module may have of the simulator executable. an input port on which register read requests are made. Each 2.1. Modules port instance would accept one register read request per cy- cle. If two register reads per cycle were needed, there would Each module is a parameterized template that is instan- be 2 port instances of the register read request port, and two tiated in an LSS machine description to create a module in- instances of the output port on which these read requests stance (or simply instance). Much like components in hard- were returned. Another example is the tee module which ware design, modules can be leaves of a hierarchy, or they is used to fanout a given value to multiple receivers. The can be constructed hierarchically by grouping collections tee duplicates the value received on its input port instances of other interconnected module instances. Like hardware on multiple output port instances. blocks, module instances execute concurrently [2] and com- Users specify how modules communicate by intercon- municate with other instances by passing data across com- necting port instances from one module to port instances munication channels. on the same or other modules. While details regarding However, unlike hardware design, the details of instance ports and the communication system can be found in [1], behavior (hierarchical or leaf) can be customized via module other work describes LSE’s execution and messaging se- parameters. When a user instantiates a module in a machine mantics [2]. description, the user specifies values for the parameters de- 2.3. Data Collection clared by the module (or accepts the default value specified by the module). These parameters are used to customize To allow modularity and flexibility even for data collec- the behavior of the module instance for the particular de- tion, LSE provides a data collection mechanism that avoids

73 Figure 2: Simple source to sink description. Figure 3: Simple x + x description. the pitfalls of embedding instrumentation code directly into the simulator code. Each LSE module may declare that and Blackhole. its instances emit certain events during the execution of the Figure 3 shows a screenshot of a slightly more sophis- simulator. Each event includes data related to the event and ticated machine configuration. Here, the datasource a dynamic identifier (dynID) that represents the system level module instantiated as Generator is connected to an instance object that caused the event to occur. Orthogonal to the dec- of the tee module named Tee. The Tee in turn fans out the laration of events, users may associate, with any event, a data originating from Generator into port instances of ports data collector which captures the event and records data or op1 and op2 of the instance ALU. ALU then computes the computes statistics. sum of the values passed into it on these port instances and For example, a branch predictor module may emit an sends the result to Blackhole to be thrown out. The function event every time it makes a prediction. The event could in- of this machine is simply to compute the value of x + x, clude information about what prediction was made and what where x is the value generated by Generator, and then throw predictor made that prediction. The dynID for the event away the result. would identify the dynamic instruction instance that caused In this diagram, there are a few interesting features to the prediction to occur. A user could hook this event with a note. First, notice that Tee’s dest port is connected twice, data collector to count the number of predictions made or to meaning that there are two port instances of the dest port. calculate a branch misprediction rate for example. Also notice that the Tee and ALU instances have been given In addition to recording data or computing statistics, the custom shapes for their visual representation. In general LSE visualizer (described in Section 3) hooks these events each module instance can be given a custom shape. This to visualize the flow of data through the machine at runtime. feature allows the visualized modules to be recognizable An example of this is described in Section 4. on sight instead of having each module be a nondescript blue rectangle. We use this feature in the next section to 3. Visualization make the machine visualizations resemble diagrams found The LSE Visualizer provides a means to view LSS de- in computer architecture textbooks. scriptions as block diagrams. In addition, the LSE Visual- In addition to the above schematic rendering features, the izer provides an interface for compiling an LSS design into visualizer can interface the generated simulator executable an executable simulator, and it provides tools for observing, and display execution information as it occurs. This is use- via animation, the execution of the simulator. In this section ful for following instructions as they flow through a pipeline we will describe the visualizer in enough detail so that it is or observing the status of ports in the system. Screenshots possible to understand the discussion of how the visualizer of the visualizer interacting with the generated simulator are can be used in a computer architecture course as described shown in the next section. in Section 4. Figure 2 is an LSE Visualizer screenshot showing the 4. Applications block diagram of a simple system. In this system, a mod- In this section, we will give examples of how LSE can ule instance, called Generator, sends data to another module be used in lecture to illustrate computer architecture con- instance, called Blackhole, which discards it. Generator is cepts and how LSE can be used to formulate assignments an instance of the datasource module, and Blackhole is that allow students to explore the myriad of interactions be- an instance of the sink module. Both the datasource tween architectural techniques. All the examples are cen- and sink modules are provided by the LSE module library. tered around a simple Tomasulo-style [3] machine that exe- During simulator execution, a unit of data will be transfered cutes the DLX [4] instruction set. from Generator to Blackhole in each and every cycle until the simulation is terminated manually. 4.1. LSE in the Classroom In Figure 2 the module instances are represented by the Standard presentation tools do a fine job of illustrating large boxes, while their ports are represented by the small the static aspects of a design. However, dynamic interac- boxes. The single line between the box labeled dest and tions are generally only briefly described or illustrated with the box labeled src represents a connection between the static pipeline diagrams. The LSE system and its visualizer, respective port instances on the module instances Generator however, can demonstrate the dynamic behavior of the ma-

74 chine by displaying, over time, events produced by the ex- can be given in which the student is required to modify an ecutable machine model. In a lecture environment, this can existing configuration to produce a new configuration. For be used to show the flow of data and update of state through example, students may be asked to modify a Tomasulo-style the modeled architecture. machine that does not execute loads and stores to one that To illustrate this we will show a few screenshots of the does execute loads and stores in order, in 2 clock cycles. Visualizer showing the flow of instructions through a simple As the following example will demonstrate, this problem is Tomasulo-style pipeline. A screen shot of the Visualizer is certainly tractable for students in a week long assignment. shown in Figure 4. Notice that the structure of the machine Figure 4, described earlier, shows a Tomasulo-style ma- is fairly obvious. The block labeled Register File is chine that does not execute loads and stores. Figure 6 shows the register file, horizontally stacked tall vertical blocks are that same machine with a load store unit added. Adding this the reservation stations, the ALU looks like an ALU, and load store unit is relatively straightforward. the shifter, LSU, and branch unit are clearly labeled. The First, the reservation station module needs to be aug- machine does not support precise exceptions or speculation mented to force instructions to be issued in order. This aug- and so there is no need for a reorder buffer. mented module will form the load-store issue queue (LSQ). Figure 5 shows a screen shot of the visualizer displaying This hierarchical module, shown in Figure 7 is built by tak- a table showing instruction arrival at various stages in the ing the reservation station module and connecting it so that pipeline and reservation station occupancy of the Tomasulo- all the slots of the reservation station go to a serializer style machine shown in Figure 4. This table is dynamically module, called serialize in the figure, followed by an updated with data from the running simulator. aligner module, called align. The serialize and In Figure 5 we can clearly see the or instruction that suc- align instances, combined with the default control seman- ceeds the jump instruction stall in the fetch stage starting at tics in LSE, force instructions to come out of the align in- cycle 5 while the machine resolves the branch (recall that stance in order. Both the serializer and aligner are the sample Tomasulo-style machine does not support spec- available in the standard LSE module library, and the reser- ulation). We can also see the sll instruction stuck in the vation station is part of the original Tomasulo-style config- reservation station awaiting operands during cycle 3. In cy- uration. cle 4, we see the sll instruction issue to the EX stage but Next, several additional module instances (created from subseqently lose arbitration for the common data forcing a modules in the library) are connected to the output of the re-issue in cycle 5. The instruction once again loses arbi- LSQ and are used to extract the destination register (rd) from tration and re-issues in cycle 6 and finally writes back in the data output by the reservation station, compute the load cycle 7. or store address, and generate the control signal that decides The table is constructed by specifying the appropriate if the request will be a read or write. The specific fields that data collectors in the simulator description. The visualizer the module instance extracts and the function it performs then monitors the output of these collectors to generate the are specified via algorithmic parameters (discussed in Sec- table as the simulator runs. The table is completely generic tion 2) provided by the modules. and thus users of LSE may specify the column headings The output of these module instances is then connected and how the table entries get filled via the specific messages to a latch to end the first cycle of memory instruction ex- emitted by the data collectors. ecution. The output of this latch is then connected to the As discussed in the literature, the power of this kind of request ports of the data memory. Another module instance demonstration is invaluable since both the static machine then combines the output of the data memory (generated for structure and its dynamic behavior can be seen simultane- load requests) with the destination register field from the ously [5]. With the Liberty Simulation Environment, these reservation station (arriving via the latch) and sends them demonstrations can easily be constructed for many different off to the common data bus arbiter. types of machines so that students can easily understand the All of these modifications were performed in a few hours. differences in the architectural techniques presented. Students moderately familiar with LSE should be able to complete such an assignment fairly easily. Furthermore, in 4.2. LSE for Student Exploration the configuration just described, the default control seman- As was described in Section 1, designing and implement- tics in LSE would allow students to vary the latency of the ing a machine with an RTL level description is too time con- memory module (while keeping the initiation interval fixed suming to do regularly throughout an architecture course. at 1) and have the load-store logic stall waiting for the mem- On the other hand, block diagrams do little to cement un- ory. Students could then explore the merits of their own de- derstanding of the dynamic elements of an architecture. The sign in the presence of different core-memory latencies with Liberty Simulation Environment, however, provides an ex- very little additional effort. cellent middle ground between hand-drawn hardware block When used in this way, LSE enables instructors to give diagrams and RTL level descriptions. Regular assignments regular assignments that require students to build executable

75 Figure 4: Simple Tomasulo-style pipeline that executes the DLX ISA.

Figure 5: Table showing instruction arrival and reservation station occupancy in a Tomasulo-style DLX machine

76 Figure 6: A Tomasulo-style DLX machine with a load-store capability.

77 Figure 7: Load-Store issue queue. models to verify that their understanding of an architectural together with an easy to use dynamic and graphical visual- concept is sufficient (i.e. the model runs programs cor- ization system. rectly). The students can learn about most of the techniques presented in class with hands-on projects, instead of only a References handful they would see by doing a single class project. [1] M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. As a further example, students can explore machines not August, “Microarchitectural exploration with Liberty,” in Proceedings of the 35th International Symposium on Microarchitecture, November described in lecture by having them add architectural mech- 2002. anisms to existing designs. For example, students could be [2] D. Penry and D. I. August, “Optimizations for a simulator construction asked to add rename logic to a scoreboarded machine before system supporting reusable components,” in Proceedings of the 40th discussing advanced scoreboarded machines. In this way Design Automation Conference, June 2003. students can appreciate the relationship between renaming [3] R. M. Tomasulo, “An efficient algorithm for exploiting multiple arith- and WAR hazards and why scoreboards stall in circum- metic units,” IBM Journal of Research and Development, vol. 11, stances where Tomasulo’s machine does not. LSE makes pp. 25–33, January 1967. this kind of exploration feasible in week long assignments. [4] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quan- tatative Approach. San Francisco, CA: Morgan Kaufmann, 1996. 5. Conclusion [5] C. T. Weaver, E. Larson, and T. Austin, “Effective support of simula- To understand computer architecture, students must un- tion in computare architecture instruction,” in Proceedings of the 2002 derstand the dynamic interactions of all the hardware com- Workshop on Computer Architecture Education (WCAE), May 2002. ponents in a microarchitecture. Unfortunately, conveying the many subtleties of this interaction during lecture is diffi- cult. For many students, static illustrations and assignments do not build intuition about dynamic systems. Class projects which require students to build RTL simulation models are extremely useful, but the overhead in low-level model con- struction and modification often limits the scope of concepts explored. Modifying or writing a high-level simulator in a sequential language such as C allows students to avoid get- ting bogged down in irrelevant low-level hardware details, but it does so by obscuring the model. Students spend much of their time dealing with sequential language simulator is- sues rather than thinking about computer architecture. In this paper, we have shown that the Liberty Simula- tion Environment (LSE) is an alternative to tools currently used in lecture and take-home assignments. LSE’s simulator description resembles hardware, allowing students to think about hardware rather than simulator design issues. LSE descriptions are relatively easy to modify and use, allow- ing students to study the dynamic execution behavior of a wide range of machines. Furthermore, the LSE Visualizer improves LSE’s use as a pedagogical tool by tying this all

78 Multimedia components for the visualization of dynamic behavior in computer architectures

Peter Marwedel, Birgit Sirocic Dept. of Computer Science, University of Dortmund, 44221 Dortmund, Germany [email protected]

Abstract since it requires the simulation of hardware structures. This can be a challenging task which cannot be solved Understanding modern processors requires a good within the time-frame available for preparing a course. knowledge of the dynamic behavior of processors. Tra- Why not just use available hardware simulators? These ditional media like books use text for describing the simulators are frequently designed for optimum simu- dynamic behavior of processors. Visualization of this lation speed and complex design projects. Ease of use, behavior, however, is impossible, due to the static na- excellent visualization and portability have normally not ture of books. In this paper, we describe multime- been top goals for simulator design. Also, powerful sim- dia components for visualizing the dynamic behavior of ulators are typically proprietary and come at high costs, hardware structures, called RaVi (abbreviation for the preventing their widespread deployment to classrooms German equivalent of “computer architecture visualiza- and into the hands of students. tion”). Available RaVi components1 include models of Therefore, we tried to design RaVi models for the a microcoded MIPS architecture, of a MIPS pipeline, simulation-based visualization of the dynamic behavior of scoreboarding, Tomasulo’s algorithm and the MESI of hardware architectures. In contrast to available mod- multiprocessor cache protocol. els, emphasis is on visualization. This paper is structured as follows: a short description of related work is provided in section 2. Section 3 de- 1 Introduction scribes the multimedia units developed so far. Section 4 discusses some design consideration regarding the avail- ability and access-ability to various groups of students. The presented project aims at facilitating understanding Section 5 contains some of the results. The final section the dynamics of modern processor architectures, thereby comprises a conclusion. overcoming an important limitation of books. Videos tapes and video distribution techniques have made it possible to show non-interactive media elements to stu- 2 Related work dents. However, video tapes have to be accepted by teachers and users on an “as-is” basis. It is not possi- Simulators provide information about the dynamic be- ble to use instruction streams other than those employed havior of computing systems. Plenty of simulators are for the production of the video. Also, it is not possi- available either commercially or in the form of public ble to modify hardware structures in order to see the ef- domain tools. They have been used for decades already. fect of hardware changes on the dynamic behavior. In However, these simulators have hardly been designed short, videos are very inflexible and cannot provide in- for class room use. For such use, the limited resolu- teractiveness (except the simple type of interactiveness tion of screens must be taken into account. These days, possible with DVDs). it is also required that the simulators can be given into Providing this interactiveness, however, is difficult, the hands of students. Expensive commercial simula- tors cannot be used for this reason. Also, feature-rich 1We gratefully acknowledge the funding of the RaVi-project (which is a subproject of the SIMBA-project) by the German ministry simulators requiring special training are not appropri- of research and development (BMBF). ate for this type of application. The target group for

79 this material includes first year students. It would be unnecessary barriers for the students. impossible to teach these students how to use a hard- Experimentation with this architecture is possible. For ware description language: teaching the syntax of com- example, the contents of the register file Reg as well as plex languages and to use tools such as Modelsim [6] the contents of the main memory Mem can be changed. would take too much time in a course which also has to A small dedicated assembler is provided such that as- cover a number of other important computer engineering sembly language programs can be assembled and loaded subjects. The effort of generating models, for example into the main memory. in VHDL, should not be underestimated. Hence, most of the available simulators do not provide the required Modifications of the wiring are possible, using the in- functionality. Notable exceptions include the JCachesim tegrated schematic editor. A number of standard com- [1]. JCachesim is a simulator for cache architectures. ponents are provided. These include multiplexers, reg- However, JCachesim focusses on generating quantita- isters, memories and ALUs. Modifications using these tive data (statistics etc.). In contrast, the work in this standard components can be done by the user without paper focusses of giving insight into how computer sys- any programming. Adding new components not yet tems work. available in the library requires programming the behav- ior of these components in Java, however. This possibil- ity is rarely used, except by the designer of the multime- 3 Available multimedia units dia units.

3.2 MIPS-Pipeline 3.1 Microcoded version of MIPS

The operation of the MIPS-pipeline is described in the Architectural models capable of executing a reasonable book by Hennessy and Patterson [4]. Several pages of subset of some instruction set require a certain complex- the book are used for showing the different states the ity of the model. The program counter, main memory, pipeline can be in. Nevertheless, this technique for ex- register file, ALU, control logic and a number of multi- plaining the operation of the pipeline has its limits: it is plexers all have to be included in the model. Otherwise, difficult to imagine, which situations arise for other code it would be impossible to demonstrate how instructions sequences. This is especially true for stall cycles. From are executed. Many of these hardware components are available descriptions, it is difficult to understand which connected. According to our observation, it is typically of the pipeline stages are stalled when. difficult for the students to understand how all the wires Furthermore, it would be nice to use interactive elements in a computer architecture are used. Also, the function in education. For example, students can be motivated to of multiport memories seems to be a problem for stu- think about the behavior of the architectures by letting dents grown-up with von-Neumann languages. them “play around” with it. Courses on computer architecture typically follow the All this is possible with RaVi models of the pipeline. sequence of Hennessy/Patterson’s book for undergradu- There are essentially three models: ates [4]. Consequently, a microprogrammed version of the MIPS-machine is the first hardware structure which • The first model is a simple model without any by- is introduced. It has to be introduced in such a way that passing. It can be used to demonstrate the wrong students are able to comprehend how it works. We have implementation of the instruction set. therefore designed a multimedia unit highlighting the paths which are used during a certain micro-step (see • The second model includes bypassing, but does not fig. 1). have a separate adder for branches. This model can be used for demonstrating the advantage of bypass- Just color-coding the values on the wires would lead to ing. an abundance in color-coding and it would be difficult to find out, which of the lines are actually important. Also, this model implements two phase clocking. Therefore, only those paths leading to non-redundant Using appropriate color coding, it can be shown inputs are marked. Lines printed in bold in fig. 1 cor- that the register file is updated as a result of falling respond to the paths used in the final state of the store clock edges. word instruction. The address input of memory Mem is The same model can be used to demonstrate the driven by the computed effective address, as stored in problems with branches if no special comparator temporary register T. The value stored is coming from for the instruction fetch stage and no special adder the register file Reg. General simulators would typically for calculating branch target addresses are added. not implement such a feature and would therefore create Large branch delay penalties can be shown.

80 Figure 1. Microprogrammed version of the MIPS machine (segment of a screenshot)

Figure 2. Segment from screen-shot from pipeline unit

• The third model includes the special hardware cir- All instructions are color-coded so that it is easy to see cuits for reducing branch delay penalties (see fig. how instructions propagate down the pipeline. Imple- 2). mented models support all major opcodes as well as mi-

81 nor opcodes in the register-to-register class (major op- machines. We found that students realized much faster code 0). A full implementation of all opcodes as well that, once the shared state is reached, there is no way as exception handling is not consistent with the goal of back to the exclusive state (in hardware, there is usually keeping things simple so that students understand the no signal which would allow going back to state exclu- models. Accordingly, function registers (like EPC)are sive except through state invalid). not implemented. The same applies for special regis- ters HI and LO. Irregular multiply instructions leaving their results in these registers (e.g. mult) have been re- 3.4 MESI-protocol for the entire cache placed by their more regular pseudo instruction counter- parts supported by the MIPS assembler (e.g. mul). Oth- After demonstrating the behavior of the four state MESI erwise, too many hardware components would have to FSM for a single block, we are typically explaining the be on the screen. full MESI model for a number of cache blocks, also including tag bits. Fig. 4 shows a screen-shot of that 3.3 MESI-protocol for a single cache block model. Read and write requests can be generated in- teractively. Addresses and data for all read and write requests can be changed by using the context menue of The MESI protocol is typically included in the educa- the processors (shown at the top). tion of computer scientist in their third year. Accord- ing to this protocol, single read requests for certain ad- We found that students were surprised about the behav- dresses cause the corresponding cache line to be in the ior of that model in case the same index bits but differ- exclusive state. Subsequent reads by other processors ent tag bits are used in accesses to the different caches. will cause the same cache line to be in the shared state. Also, students did not expect the complexity of the op- Writes in one processor will set the state in other caches erations on the bus. to invalid. Due to its distributed nature, it is more diffi- cult to understand than algorithms for mono-processors. 3.5 Scoreboarding We have therefore developed two multimedia units help- ing students to understand this protocol. The first unit shows the behavior of just a single cache block, of which Scoreboarding is known as one of the early techniques copies may be available at four different machines (see for increasing processor speeds. Due to the distributed fig. 3). The three state finite state machine used by Hen- nature of the algorithm, we found that students had prob- nessy/Patterson [5] is replaced by the commonly used lems with understanding the algorithm exactly. In order 4-state FSM. to change this situation, we have developed a multime- dia unit for this algorithm as well. In order to let students make experiments with the model, different instruction streams can be used and the effect of the resulting paral- lelism can be studied. Fig. 5 shows a screen-shot. We found that the resolution of currently available pro- jection equipment puts a tight constraint on the level of detail that can be shown for this algorithm.

3.6 Tomasulo algorithm

The Tomasulo algorithm is a more advanced algorithm for speeding up processor architectures. The Tomasulo algorithm employs a more decentralized control, making it even more difficult to understand the overall behav- ior. The corresponding RaVi unit avoids this problem. Figure 3. RaVi visualization of the MESI Again, the students can “play” around with different in- protocol for a single block struction streams and observe the behavior of the archi- tecture. Functional components can be deleted by the user (lecturer or student) and new components can be By generating read and write requests, the lecturer or added. No programming is required as long as standard the student can explain the behavior of these finite state components are added.

82 Figure 4. Segment of a screen-shot from RaVi cache protocol unit (Memory omitted)

Figure 5. Screen-shot from RaVi scoreboard unit

83 4 Implementation aspects 5Results

4.1 Availability The RaVi project led to several results:

• We found that the generation of the multimedia The RaVi system is built on top of the HADES visual- units required significantly more time than ex- ization framework for computer structures [3]. HADES pected. Due to using HADES, first versions could is implemented in Java. The entire RaVi model follows be designed rather quickly, requiring production ef- the object-oriented paradigm. Every RaVi component is forts of a few weeks at most. However, the use of an instance of the corresponding hardware component these units in the classroom led to requirements for class. improving the units. Only almost perfect units can Due to being implemented in Java, RaVi can be used be used in the classroom environments and given at a variety of platforms. We decided to make RaVi into the hands of students. Fine tuning of the units freely available on the Internet in order to promote its required as much work as their original design. A use. Initial versions of RaVi required a download of the total of about 2 person years have been spent on the software. Current versions are available as an applet and project so far. can be used without any software installation effort (pro- • It is good scientific practice to try to measure by vided Java is already installed). RaVi is available from how much the quality of teaching can be improved //ls12.cs.uni-dortmund.de/ravi. by using the multimedia units. Following the ad- vice by researchers from social sciences, we tried 4.2 Gender-specific aspects to get quantitative information on the level of un- derstanding achieved through the use of these units. Even though we had two large groups of students One of the goals of RaVi is to motivate also female stu- (about 200 each) which could be compared, no dents to study computer engineering. A number of con- quantitative conclusions could be drawn. A number siderations (see e.g. Fisher et al. [2]) have been taken of other effects (date and time of the teaching, char- into account during the design of RaVi: acteristics of the students etc.) resulted in a wide variation of the results and prevented any meaning- • Before enterering the University, women typically ful conclusions. According to more recent advice have less hands-on-experience with computers in from an expert in the area [7], attempts to quan- general and with computer engineering in particu- titatively measure the effect of multimedia-based lar, compared to most men. Therefore, a very care- education are in fact bound to fail and a waste of ful definition of all technical terms must be used in time. One cannot expect more than just qualitative the accompanying technical material. information on the improvements achieved. Ac- cording to this qualitative information, the goals of • Educational material should avoid unjustified the project have been reached. stereotypic views of computer users. For example, female computer users also include scientists and • Students really like the presented units and appre- not only secretaries (in contrast, for example, to the ciate their availability. They are typically highly cliparts provided by Microsoft). motivated trying out these units at home and ask for download options. Also, colleagues typically comment very positively on the availability of these 4.3 Limitations units. The most important argument is the added value of the units. While online-versions of static Simulation in the underlying HADES library is based material provide only limited added value, if com- on a VHDL-like two-phase simulation of synchronous pared to books, visualization of dynamic properties architectures. Communication is based on explicit inter- adds a completely new quality. connections (which can be hidden on the screen). Simu- • Visualization of the dynamic behavior has proven lation is less suited for applications in which explicit in- being indeed one of the key technologies for im- terconnections are difficult to use. Nevertheless, it was proving the teaching further and for exploiting possible to use this simulation approach for demonstrat- modern equipment. ing search in binary trees. Visualization is focussing on 2D models. 3D models are beyond the scope of the cur- • Simulation based on the HADES simulation frame- rent approach. work was found to be appropriate for various kinds

84 of digital circuits. While is was possible to use HADES for visualizing algorithms like tree-search, it is less appropriate of analog and time-continuous simulations. Simulation speed is sufficient even in applet-based versions of RaVi.

6Conclusion

In the RaVi project, we have demonstrated how a defi- ciency of classical media for teaching computer archi- tecture can be removed. We have shown that the visual- ization of computer architecture dynamics is appreciated by the students and helps them to understand the sub- jects. In general, RaVi units seem to improve the moti- vation of students. Unfortunately, it seems to be impos- sible to measure the effect of the new teaching aids on the student’s success. In the future, we will be extended to approach to other areas of computer engineering. For example, we have started designing similar material to complement a book on embedded system design, which is currently being written at Dortmund.

References

[1] I. Branovic, R. Giargi, and A. Prete. Web-based training on computer architecture: The case of jcachesim. Pro- ceedings of the workshop on computer architecture edu- cation, pages 56–60, 2002. [2] A. Fisher and J. Mangolis. Unlocking the clubhouse. SIGCSE bulletin, Vol. 34, no. 2, Women and Computing, pages 79–83, 2002. [3] N. Hendrich. A Java-based framework for simulation and teaching. Proceedings of the 3rd European Workshop on Microelectronics Education, pages 285–288, 2000. [4] J. L. Hennessy and D. A. Patterson. Computer Organiza- tion – The Hardware/Software Interface. Morgan Kauf- mann Publishers Inc., 1995. [5]J.L.HennessyandD.A.Patterson. Computer Architec- ture – A Quantitative Approach. Morgan Kaufmann Pub- lishers Inc., 1996. [6] Model Technology. home page. //www.model.com, 2003. [7] C. Moreau. Universite de Compiegne. Oral communica- tion, 2003.

85 Didactic Architectures and Simulator for Network Processor Learning

Henrique Cota de Freitas1, Carlos Augusto P. S. Martins2 Postgraduate Program in Electrical Engineering Pontifical Catholic University of Minas Gerais, Brazil [email protected], [email protected] http://www.inf.pucminas.br/projetos/pad-r/r2np.html

Abstract (processing time and throughput) are essential features that the Network Processor has to be capable to In our university, we are developing a project about implement. Reconfigurable Network Processors (RNP). There are Network processors [19,20] appeared during the four important results: Reconfigurable CISC Network 1990’s to replace some GPP’s and ASIC’s in network Processor (RCNP) architecture, Reconfigurable RISC equipments. These processors were developed using Network Processor (R2NP) architecture, Network architecture models like ASIP (Application Specific Processor Simulator (NPSIM), and a performance Processor) and SoC (System-on-Chip) [29] adding to analytical model for the ISA (Instruction Set RISC (Reduced Instruction Set Computing) [24] Architecture). The architectures and the simulator are technique for a better computing performance. These not commercial products, but conceptual models. This processors have a dedicated ISA (Instruction Set paper shows the main functionality of those four results Architecture) model for network operations. Thus, the and the their applicability on the Network Processor instruction set and the architecture of Network learning. As our Network Processor architectures and Processors are specific to execute typical operations in simulator are simpler than commercial products, their a data communication network [28]. conceptual models can aid students to learn network In Post-graduation Program in Electrical processors concepts, as a first step to understand other Engineering, we have a project called RNP complex architectures. (Reconfigurable Network Processor). The research goal is the development of a conceptual model of network Keywords: Reconfigurable Network Processors, processor using SoC and Reconfigurable Computing Didactic Architectures and Simulator, Learning [17] techniques to improve computing performance and Process. flexibility. The partial results are: Reconfigurable CISC Network Processor (RCNP) architecture [10], 1. Introduction Reconfigurable RISC Network Processor (R2NP) architecture [11], Network Processor Simulator Until the 1990’s, network equipments used the (NPSIM) [12,13] and the performance analytical model traditional general-purpose processor (GPP) to process for the ISA (between RCNP and R2NP). During this many types of packets and management services. The paper, these four results will be presented. main advantage was flexibility. The software was Our main objective in this paper is to present capable to define many functions and applicability for didactic models of Network Processor architectures and the GPP’s, but the performance was very harmed. a simulator to aid students to learn simple Network Another solution to solve the performance problem Processor architecture concepts. This is a first step to was the use of dedicated hardware. Using Application understand some details and complex features. Specific Integrated Circuit (ASIC), the processing We searched for documents about words like speed increases enough, but the flexibility was harmed. learning and didactic models. However, nothing related So, there are two very important features: flexibility with Network Processors was discovered. Thus, our and performance. Nowadays, the Internet [28] is the motivation is present a simple way to learn the main main type of network, and the Quality of Service (QoS) features of Network Processors using didactic is very important. For this reason, a best approach architecture models and a simulation tool. between those two features is necessary in network equipments. For example, a router is concentration point or a bottleneck in a network. The flexibility to process any kind of packets and the performance

86 2. Network Processors Overview During the developing process of Network Processors some companies joined among them we In this section we will describe the state-of-the-art remark: Lucent / Agere [1], Motorola / C-Port [5] and of Network Processors. The main architecture features, Sitera / Vitesse [25]. Below, the main Network the main functionalities, some related researches and Processors and the companies are: companies. 9IXP 1200 – Intel Corporation [16]; The main logic blocks (figure 1) of a Network 9NP4GS3 – IBM Corporation [15]; Processor are: 9C-5 Family – Motorola / C-Port [5]; 9Multiple RISC processors, co-processors or 9ASI/RSP/FPP – Lucent / Agere [1]; programmable ASIC’s; 9IQ2000 Family – Sitera / Vitesse [25]; 9Dedicated hardware for network operations; 9AnyFlow 5400/5500 – MMC Networks [23]; 9High speed of memory interface; 9NP-1 – EZChip Technologies [8]; 9High speed of I/O interface; 9NetVortex – Lexra Inc. [18]; 9General-purpose processors interface. 9CS2000 – Chameleon Systems [3]. Each Network Processor has a typical architecture The Chameleon Systems was the first company to and uses some or all blocks showed. A Network produce a Network Processor using the Reconfigurable Processor can use one RISC processor and co- Computing technique. This is an important processors like the packet processors, or only multiple characteristic. Reconfigurability is a technique that can RISC processors. If the SoC technique is used, possibly be used in the NP architecture to improve flexibility. dedicated hardwares like switching fabric and memory Some researches about Reconfigurable Network can be in the architecture. However, GPP interface like Processors developed in universities are: PCI and I/O interface always appear. It’s an important 9“Reconfigurable Network Processors Based detail, because a Network Processor needs to on Field Programmable System Level communicate to other processors (to help in system Integrated Circuits”, University of Patras, management) and the network (the main of Greece [22]; functionality). 9“Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic”, University of California, Los Angeles [9]; 9“Design and Analysis of a Dynamically Reconfigurable Network Processor”, University of Florida [14]. After section 1 and 2, it is possible to say that flexibility and performance are two important features during network processing. Thus, we conclude that some concepts are very important, and so students must know them before study a commercial Network Figure 1 – Architecture Reference Processors: 9CISC and RISC models; The main functions of a Network Processor are: 9The concepts of ASIC’s and ASIP’s; 9To analyze and classify the contents of head 9The concepts of SoC’s; fields of a packet; 9The concepts of Reconfigurable Computing; 9To find in tables association rules related to 9The main logic blocks of Network Processor head fields; architecture; 9To solve the destination path or QoS 9The main functions of Network Processor. requirements; The next sections will present the didactic models of 9If necessary, to modify the packet (type of RNP project and the results that can aid students to service or Diffserv, for example). understand the functioning of Network Processors, Nowadays, the active networks [6] are very based on the features above. important for QoS requirements, and equipments like active routers [27] appeared to improve performance 3. Didactic Architecture Models and quality for Internet. The Network Processors have dedicated functionalities that provide flexibility and This section presents two architecture models: CISC performance. For this reason, it has a large application model (RCNP) [10] and RISC model (R2NP) [11]. in many network equipments. Both architectures were developed and simulated using

87 Reconfigurable Computing [17] and SoC [29] concepts The RCNP architecture was developed as a System- and techniques to increase flexibility and performance. on-Chip. Memory, I/O ports and crossbar are placed Reconfigurable Computing: Input Ports and internally. Crossbar has more flexibility in time execution. Buffer The Reconfigurable Computing appears in sizes and topologies can be created dynamically. Permanent Buffers and Crossbar. Thus, in execution System-on-Chip: Functional blocks, that are found time the size of the buffers and topologies (defined by externally, as memory, I/O ports and switching fabric, crossbar) modifies dynamically. are internally in the same chip. Like hierarchical The main features of instruction set are: memory, the proximity between functional blocks 9General-purpose instruction set reduces processing time and increases performance. x Arithmetic instructions (Ex.: ADD and SUB); The use of didactic architectures (RCNP and R2NP) x Logic instructions (Ex.: AND and OR); is presented in section 5. Subsection 3.1 and 3.2 x Memory access instructions (Ex.: LOD and presents only technical features. We will implement STO); both architectures using VHDL (VHSIC Hardware x Branch instructions (Ex.: JMP and JNZ); Description Language) [21] and FPGA (Field 9Dedicated network instructions Programmable Gate Array) [21] in the future. x Input port reading (Ex.: ENT); x Output port writing (Ex.: SAI); 3.1 RCNP (Reconfigurable CISC Network x Crossbar control (Ex.: SEC); Processor) Architecture x Status register control (Ex.: SRS and LRS); The RCNP architecture was not designed with The basic features of RCNP [10] architecture are the pipeline technique. For this reason, all instructions are following (figure 2): executed sequentially. In section 7, the performance Eight input ports; 9 analytical model for the ISA shows the impact of the x Temporary buffers (one static buffer for each architecture without pipeline. port); Like all CISC projects, other instructions (different x Permanent buffers (dynamic buffers, of load and store) access memory. The general-purpose reconfigurable size buffers); instruction set of RCNP is not optimized. There are 256 9Eight output ports; instructions that can be found in the project homepage 9Reconfigurable Crossbar; (http://www.inf.pucminas.br/projetos/pad-r/). The 9Direct Access Memory (DMA); simulation tool (NPSIM) also has the instructions 9Eight general-purpose registers (8 bits); described in figure 9. 9Data bus (8 bits) and address bus (24 bits); 9Maximum of size memory (16Mbytes)

Figure 2 – RCNP Architecture

88 3.2 R2NP (Reconfigurable RISC Network Processor) Architecture

Figure 3 – R2NP Architecture

The evolution of RCNP is the R2NP [11]. This The instruction set of R2NP is more optimized than architecture uses the RISC model, pipeline and other RCNP. Based on the RISC model, the instruction reconfigurable blocks. The figure 3 shows the R2NP format is fixed and only load and store instructions architecture. access the memory. We present in table 1 the The basic features of RCNP architecture are the instruction set of R2NP. follows: 9Eight input ports; Table 1 – Instruction Set of R2NP x Reconfigurable Multiplex; General-purpose x Programmable Microengines (one ADD A,B,C MOV A,B SPUSH A CONV SUB A,B,C INC A LPOP A Network microengine for each port); MUL A,B,C DEC A JMP A FCX A,B,C x Permanent buffers (dynamic buffers, DIV A,B,C LOD A,End32 JZ A LOB A reconfigurable size buffers); AND A,B,C LDA A,End16 JMZ A BRC A 9Reconfigurable Crossbar; OU A,B,C LOX A,B JMI A SAI A,B 9Eight output ports; XOR A,B,C LDI A,Imed16 JNZ A LRS A NEG A STO End32,A JNI A SRS A 9Internal memory; ROD A STR End16,A CALL A SEC A,B 9Main RISC processor with data cache and ROE A STX A,B RET ENT A,B,C instruction cache; 9Direct Access Memory (DMA), dedicated There are two kinds of store and load instructions: hardware; with internal and with external memory access. 9256 registers (64 bits); The internal memory is smaller and the instructions 9Data bus (32 bits) and address bus (32 bits); number 16 (Ex.: LDI A,Imed16) use sixteen bits to 9Maximum of size memory (16Gbytes) access the 64kbytes memory. The instructions number In R2NP project we add two important network 32 (Ex.: LOD A,End32), access only the external blocks: Reconfigurable Multiplex and Microengines. memory. If the instruction has 32 bits of address, two Microengines: Are responsible for the first analysis fetch cycles will be necessary. on the packet head. In this case the packet can be The network instructions (table 2) are very similar forward to output ports with no intermediary copies to with the RCNP network set. However, by optimization, buffers or memory. some differences appear in the instructions format. Reconfigurable Multiplex: If you lost one The pipeline of R2NP is showed in figure 4. This is microengine or need to use it in other function, the very similar with the conceptual model of pipeline [24], multiplex connects two or more ports to one but the difference is the Buffer stage (together microengine. memory). One instruction that access buffer does not access memory.

89 x Input Packets (network packet edition box – figure 6) x Internal Crossbar (commutation array) – (*). x DMA Registers (Direct Memory Access) – Figure 4 – Pipeline Stages (*). (*) These modules are not shown in this paper. In The stages mean: figure 5, the number 1 shows where other modules can 1. Fetch of instruction (B); be found. For more details see the references [12,13]. 2. Decoding of instruction. Reading of register bases (D); 3. Execution of instruction (E); 4. Reading or writing in memory of reconfigurable buffers (M/BF); 5. Results. Writing in register bases (R); The performance analytical model for the ISA, in section 7, will show how the pipeline project increases performance.

4. Didactic Network Processor Simulator

This tool [12,13] was constructed with C++, and the main interfaces are capable to aid and guide the student in the learning of Network Processor theory and Figure 5 – Main Module (Assembler) functioning. The simulator has six interfaces and it simulates main logic blocks as memory, registers, buffers, crossbar switch, DMA, I/O ports and others that are responsible to store, process, receive and transmit data. The student can modify and visualize the status and movement of the data inside and between logic blocks. There are two edition boxes, a program assembler and an editor of network packets. This tool simulates the RCNP architecture and is available to download (http://www.inf.pucminas.br/projetos/pad-r/r2np.html) in two languages (idioms): Portuguese and English. It makes functional tests in all logic blocks of the processor. Through this tool, it is possible to write and execute many algorithms (assembly programs) and visualize the execution and the results in objects like: Figure 6 – Input Packets registers, stacks and arrays represented in components of C++ Builder 5.0 (used to construct and compile the In this section, we only describe the edition modules simulator). like the assembler and input packets. The figure 10 and 11, show the part of the Temporary Buffers and The user interface has one main module and six Crossbar modules, and its application as a way to learn other modules: Network Processor concepts. x Memory, Registers and Fast Access Buttons With this simulator, it is possible to write and (compose the main module – figure 5) simulate routing algorithms (section 7), study the x Assembler (assembly program window – functioning of CISC network processor (RCNP) and figure 5) understand the functioning of the Network Processors, x Permanent Buffers (reconfigurable buffers) – described in section 5. (*). Other information about this simulator can be found x Temporary Buffers (eight buffers for each in the papers: Simulation Tool of Network Processor input) – (*). for Learning Activities [12] and NPSIM: Simulador de

90 Processador de Rede (NPSIM: Network Processor (reconfiguration) [17] and performance (ASIC’s). We Simulator) [13]. present in table 2 these concepts:

5. Using RNP Project to Learn NP Concepts Table 2 – Concepts of RCNP blocks and Functioning Functional Blocks RCNP Concepts Input Ports Reconfigurable ASIC (Buffers) Output Ports ASIC This section will show how RNP project (didactic Internal Crossbar Reconfigurable ASIC architectures and simulator) can help the students to Internal Memory and External ASIC learn network processor functioning and concepts. Memory Interface The figures 7 and 8 show interfaces of NPSIM, Communication Interface ASIC Typical and dedicated CISC ASIP which RCNP architecture and technical information. processor blocks These interfaces aid students to understand the NPSIM modeling of RCNP proposal architecture. Basic The instruction set of RCNP can be visualized features and important blocks as buffers and crossbar through the NPSIM interface. The figure 9 shows the are described. Thus, concepts can be read and instructions. This interface also can be found in the functional blocks visualized before the software “About” option (figure 5, number 2). execution. These interfaces can be found in the The figure 10 shows interface modules that “About” option (figure 5, number 2). represent Temporary Buffers (inside Input Ports) and Internal Crossbar together Output Ports. A network packet sent by the Packet Interface (figure 6), arrives in Temporary Buffers and the behavior can be analyzed by students through control registers (figure 6, number 1). The behavior of routing algorithms and the destination of packets are showed through buffers, registers, crossbar, inputs and outputs. The buffers receive and allocate packets from inputs, the registers aid visualize the manipulation and data behavior, and the crossbar (figure 10) shows the way from input to output.

Figure 7 – RCNP Architecture

Figure 9 – Instruction Set of RCNP

Figure 8 – Technical Information These interfaces aid students to understand basic functions of Network Processors. Algorithms that The RCNP architecture has important blocks execute functions described in section 2, as analysis described in the architecture reference (section 2). and modification of contents, search for association Through the diagram architecture of RCNP we can rules, destination resolution, and QoS requirements can visualize these functional blocks that represent be found in NPSIM. important concepts of Network Processor, as flexibility

91 The R2NP has data and instruction cache and RCNP has not. The Temporary Buffers were replaced by Microengines. In RCNP, packets could be store in Temporary Buffers, but in R2NP the microengines that also have static buffers, analyze and decide the destination of a packet, with no packet allocation. There are three routes: through crossbar and output ports, in the reconfigurable buffers or memory. In R2NP project, the main processor analyzes packets in buffers and memory.

6. Commercial Architectures of Network Figure 10 – Interface Modules Processors

Although, the RCNP has many features of a Some commercial architectures of Network Network Processor, one main characteristic does not Processors are presented and related with the reference exist, the RISC technique. RISC processors have better architecture, also described in RNP project. The main performance than CISC processors. Instruction format features are numbered and appear in each figure. It’s and pipeline are very important to increase processing important to say that each commercial example speed and reduce processing time. represents details, features or concepts presented in our R2NP is the evolution of RCNP project. In this proposal, proving the real capability of RNP project as project, the goal is add RISC concepts and optimize the a didactic environment to learn Network Processors. architecture and instruction set. The main difference is NetVortex Architecture [18] (figure 12): Each the pipeline and the instruction format. In section 7, the NetVortex is composed of many packet processors. It relation will be described. uses multi-threading in hardware and has the same The R2NP project is robuster than RCNP, and we instruction set of MIPS. Some features related to present in table 3 some concepts related with Network reference are: Processors. 1. Encryption Coprocessor: This architecture uses coprocessors for specific applications; Table 3 – Concepts of R2NP blocks 2. Crossbar Switch: Also uses dedicated hardware Functional Blocks R2NP Features (ASIC) to increase performance; Reconfigurable ASIC (Buffers) Reconfigurable ASIC 3. Packet Processor: Specific processors for Input Ports (Microengines) packet processing. Reconfigurable ASIC (Multiplex) Output Ports ASIC Internal Crossbar Reconfigurable ASIC Internal Memory and External ASIC Memory Interface Direct Access Memory ASIC Communication Interfaces ASIC Typical and dedicated RISC ASIP processor blocks The figure 11 shows the project evolution, based in hierarchical memory [24].

Figure 12 – NetVortex Architecture

IQ2000 Architecture [25] (figure 13): The IQ2000 Network Processor has four scale processors inside the chip. It has native support for MIPS, PowerPC and others RISC processors. There are specific coprocessors and hardware support for Quality of Service (QoS). Some features related to reference are: 1. Multiples CPU´s: The IQ2000 uses parallel Figure 11 – Hierarchical Memory processing based in multiples processors;

92 2. QoS Engine: Dedicated hardware (ASIC) to Each block has Datapath Units, Local Memories, increase performance. Multipliers and Control Logic Unit.

Figure 15 – Reconfigurable Fabric of CS2000 Figure 13 – IQ2000 Architecture This section presented some features of RNP IXP1200 [16] (figure 14): The IXP1200 is composed project, how to learn Network Processors using it and of seven RISC processors. The first processor four commercial Network Processors. During all the (StrongARM) is responsible for managing the network description we related the features of RNP project and and for complex processing. The other six processors commercial NP to the architecture reference. The next (the microengines) are responsible for processing and section will present the experimental results from routing packets. Some features related to reference: simulations and analytical model that contribute to 1. StrongARM Processor: The main processor validate the evolution of RNP project. responsible for complex processing. 2. PCI Unit: Dedicated communication hardware 7. Experimental Results using NPSIM (ASIC). 3. Multiples microengines: For parallel processing The simulation results and the performance of network packets. analytical model for the ISA were based in three topologies. For each topology was written three algorithms. These simulations were very important to validate the concept of RCNP. Using the results, an analytical model was proposed to verify the performance between ISA of RCNP and ISA of R2NP. The topologies (figure 16) are the follow: Hypercube topology: Where each vertex is a simulated network processor. The routing algorithm is based in different bit resulted by XOR operation between source address and destination address. Unidirectional ring topology: Constructed using the internal crossbar. The unidirectional ring program shows how internal crossbar can construct a topology. Balanced Tree: Where each vertex is a simulated network processor. In this case the routing program uses the standard address by each vertex. The addresses grow from left to right. Figure 14 – IXP1200 Architecture

Reconfigurable Fabric of CS2000 [3] (figure 15): This figure shows the reconfigurable block of CS 2000. This block is divided in four slices with three blocks.

93 RCNP proposal Npi = 12, Ncpc = 56, Cpi = 56 / 12 = 4,666 Tp = 4,666 / 500 10E6 = 0,112 µs R2NP proposal Npi = 15, Ncpc = 19, Cpi = 19 / 15 = 1,266 Tp = 19 / 500 10E6 = 0,038 µs Pf = 0,112 / 0,038 = 2,94 The R2NP is 2,94 faster than RCNP for this simulation. Through this analytical model, the students can understand how RISC processor can be faster than CISC processors, using project techniques as pipeline, for example.

8. Conclusions

Nowadays, there is a great need of high Figure 16 – Simulated Topologies performance in the data communication network [2,28]. The study of various equipments [4,27] and their The metrics defined to analyze performance for ISA functions, influenced in the project, and development of are: dedicated processors, that can supply the need of Cf Æ Clock Frequency (Hz) performance and quality. Thus, the Network Processors Tp Æ Time of Processor were initially developed to contribute with the increase Ncpc Æ Number of cycles of program clock of speed and quality of service in the communication Cpi Æ Cycles per instructions systems. Npi Æ Number of program instructions In this paper we presented a project called Pf Æ Performance factor Reconfigurable Network Processor (RNP) that has a We can related through these equations: main goal: to aid students to learn and know initial Cpi = Ncpc / Npi basic concepts of Network Processors, as a first step to Tp = Npi * Cpi / Cf understand commercial products. RCNP [10] and R2NP [11] architectures, and It’s important to say that the RCNP model does not NPSIM [12,13] simulator were described with many use pipeline, the instructions are executed sequentially. options to understand the reference architecture and the The RCNP and R2NP does not exist physically, for this basic network processors functioning. In section 5, the reason, the clock frequency is 500Mhz for definition. architectures and NPSIM were shown for the student to compare the learning possibilities. The same features in For the Unidirectional Ring topology, the results are reference architecture appear in RNP project. Using the follows: these didactic proposals it is possible to learn the basic RCNP proposal concepts. Four commercial architectures were Npi = 45, Ncpc = 191, Cpi = 191 / 45 = 4,244 presented and related with the reference to show the use Tp = 191 / 500 10E6 = 0,382 µs of didactic models before the studying of commercial R2NP proposal Npi = 38, Ncpc = 43, Cpi = 43 / 38 = 1,131 Network Processors. Tp = 43 / 500 10E6 = 0,086 µs Didactic models and simulator were looked for, but Pf = 0,382 / 0,086 = 4,44 they were not found anywhere. However, one correlate The R2NP is 4,44 faster than RCNP for this simulation. paper was presented in NP1, “A Methodology and Simulator for the Study of Network Processors” [7]. For the Hypercube topology, the results are the But they have different goals. That paper describes a follows: model of the Cisco Toaster architecture and show RCNP proposal simulated performance results of a Diffserv Npi = 17, Ncpc = 73, Cpi = 73 / 17 = 4,294 Tp = 73 / 500 10E6 = 0,146 µs implementation. It describes a commercial product and R2NP proposal simulates performance. Our goals in this paper are Npi = 17, Ncpc = 21, Cpi = 21 / 17 = 1,235 present a didactic model to introduce the main concepts Tp = 21 / 500 10E6 = 0,042 µs of Network Processors before the study of complex Pf = 0,146 / 0,042 = 3,47 The R2NP is 3,47 faster than RCNP for this simulation. architectures. A paper or research with didactic features for NP’s, were not found. The main presented results of our research, are the For the Balanced Tree topology, the results are the RCNP architecture, R2NP architecture, NPSIM follows:

94 simulator and experimental results. Those results [12] H. C. Freitas, C. A. P. S. Martins, “Simulation Tool of validated our goals and showed how conceptual models Network Processor for Learning Activities”. Frontiers can aid students to understand complex architectures of in Education Conference (FIE 2002), Boston, MA, Network Processors. USA, November 2002, Session S2F, pp.1-6 Thus, our main contribution, in this paper, is present [13] H. C. Freitas, C. A. P. S. Martins, “NPSIM: Simulador didactic architectures and simulator for beginning de Processador de Rede”. XXVIII Latin-American Conference on Informatics, CLEI’2002, Montevideo, process of Network Processors learning. Uruguay, November 2002 (in portuguese) Our future works are: To simulate R2NP using [14] I. A. Troxel, A. D. George, S. Oral, “Design and Rconf_KMT (Reconfigurable Simulation Tool) [26] Analysis of a Dynamically Reconfigurable Network and VHDL (VHSIC Hardware Description Language) Processor”, IEEE Conference on Local Computer [21], prototype using FPGA (Field Programmable Gate Networks (LCN), Tampa, Florida, November 6-8, 2002 Array) [21], simulate it in a real network system [2,28], [15] IBM PowerNP NP4GS3 Databook, http://www.ibm.com and to develop didactic environment to learn Network [16] Intel, “IXP 1200 - Network Processor”, Datasheet, May Processors. 2000, http://www.intel.com [17] K. Compton, S. Hauck, “Reconfigurable Computing: A 9. References Survey of Systems and Software”, ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171-210 [1] Agere System, Fast Pattern Processor (FPP) Product Brief, April 2001, http://www.agere.com [18] Lexra, NetVortex Network Communications System Multiprocessor NPU, http://www.lexra.com [2] Buya, R., High Performance Cluster Computing, Volume 1, Prentice Hall, 1999 [19] Lucent Technologies, Building for Next Generation Network Processors, September 1999 [3] Chameleon Systems, “CS2000 Reconfigurable Communications Processor”, Family Product Brief, [20] Lucent Technologies, The Challenge for Next 2000 Generation Network Processors, September 10, 1999 [4] Cisco Systems White Paper, “The Evolution of high- [21] M. Glesner, A. Kirschbaum, “State-of-the-Art in Rapid end Router Architectures-Basic Scalability and Prototyping”, XI Brazilian Symposium on Integrated Performance Considerations for Evaluating Large-Scale Circuit Design, SBCCI’98, Búzios, Rio de Janeiro, Router Designs”, 2001, http://www.cisco.com 1998, pp.60-65 [5] C-Port, C5e Network Processor Product Brief, January [22] M. Iliopoulos, T. Antonakopoulos, “Reconfigurable 2002, http://www.motorola.com Network Processors Based on Field Programmable System Level Integrated Circuits”, Field-Programmable [6] D. L. Tennenhouse, J. M. Smith, W. D. Sincoskie, D. J. Logic and Applications, The Roadmap to Wetherall, G. J. Minden, “A Survey of Active Network Reconfigurable Computing, 10th International Research”, IEEE Communications Magazine, Volume Workshop, FPL 2000, Villach, Austria, August 27-30, 35, No 1, pp.80-86, 1997 2000, pp. 39-47 [7] D. Suryanarayanan, G. T. Byrd and J. Marshall, “A [23] MMC Networks, “EPIF-105, EPIF-200, GPIF-207, Methodology and Simulator for the Study of Network XPIF-300, Packet Processors”, http://www.mmcnet.com Processors”, Workshop on Network Processor (NP1 at HPCA 8), Cambridge Massachusetts, February 2-6, [24] Patterson, D. A., J. L. Hennessy, Computer 2002 Organization and Design: The Hardware/Software Interface, Morgan Kaufmann Publisher, 1997 [8] EZChip Network Processors, http://www.ezchip.com [25] Sitera IQ2000, Network Processor Product Brief, [9] G. Memik, S. O. Memik, W. H. Mangione-Smith, http://www.sitera.com “Design and Analysis of a Layer Seven Network [26] T. H. Medeiros, C. A. P. S. Martins, “Reconf_KMT, Processor Accelerator Using Reconfigurable Logic”, th Uma Ferramenta Reconfigurável para a Simulação de The 10 Annual IEEE Symposium on Field- Microprocessadores”, III Workshop de Sistemas Programmable Custom Computing Machines Computacionais de Alto Desempenho, WSCAD’2002, FCCM’02, Napa, California, 21-24 April, 2002 Vitória, ES, Brasil, pp. 32-38 (in portuguese) [10] H. C. Freitas, C. A. P. S. Martins, “Processador de [27] T. Wolf and J. Turner, “Design Issues for High Rede com Suporte a Multi-protocolo e Topologias Performance Active Routers”, International Zurich Dinâmicas”, II Workshop de Sistemas Computacionais Seminar on Broadband Communications, Zurich, de Alto Desempenho, WSCAD’2001, Pirenópolis - GO, Switzerland, 2000, pp. 199-205 Brasil, pp.31-38 (in portuguese) [28] Tanembaum, A. S., Computer Networks, Prentice-Hall, [11] H. C. Freitas, C. A. P. S. Martins, “R2NP: Processador 1996 de Rede RISC Reconfigurável”, III Workshop de Sistemas Computacionais de Alto Desempenho, [29] W. D. Mensch. Jr. and D. A. Silage, “System-on-chip WSCAD’2002, Vitória, ES, Brasil, pp. 60-67 (in Design Methodology in Engineering Education”, portuguese) International Conference on Engineering Education, ICEE2000 (IEEE/CS), Taipei, Taiwan, August 2000, pp. 224-228

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102 Use of HDLs in Teaching of Computer Hardware Courses

Zvonko Vranesic and Stephen Brown University of Toronto {[email protected]}

Abstract While everybody agrees that the students must learn about logic functions and their implementation, arith- A modern treatment of an introductory course on the design of metic circuits, multiplexers, decoders, flip-flops, coun- logic circuits should include an early introduction of a hard- ters, finite-state machines, and other standard circuits, ware description language (HDL). This can done without sac- there is less agreement about the means used to expose rificing the emphasis on fundamental concepts of logic circuit students to this material. In particular, when and how design. An example of how this may be achieved is given. should the students discover CAD tools, and what lab- oratory exercises provide the best learning experience? Today it is highly advisable to introduce a hardware 1 Introduction description language (HDL) as soon as possible. With- out an HDL it is impossible to exploit properly the This presentation focuses on the use of hardware de- capabilities of CAD tools and FPGA-based laboratory scription languages and design automation tools in the equipment. A prudent choice of HDL is either Verilog teaching of courses on logic circuits and computer ar- or VHDL. It should be noted that Verilog is winning the chitecture. It is based on the experience gained at the battle in the industrial environment of North America, University of Toronto, which involved courses in Com- so it is likely that it will gain greater favor with aca- puter Engineering, Electrical Engineering, and Com- demics in the near future. puter Science programs. Our experience shows that the HDL can be intro- While there has been considerable debate about the duced surprisingly early. Moreover, the instructor need optimal way of structuring the courses that teach the not spend an inordinate amount of time teaching the in- concepts of computer hardware, a traditional sequence tricacies of the language. Students are keen to learn based on an introductory course in the design of logic and use the HDL because of its obvious practical value, circuits and a subsequent course in computer organi- hence they are willing to learn on their own many de- zation (architecture) is still a very attractive option. It tails that are illustrated in examples given in the text- is even better if these courses are followed by a more book. During lectures, the instructor has to focus on advanced course in computer architecture. This is the explaining the important differences between the HDL structure at the University of Toronto. Each course is and computer programming languages that students are accompanied by a laboratory in which students develop familiar with. For example, explaining the key differ- a real understanding of the key concepts and the various ences between Verilog and C can lead to fascinating ways in which they may be implemented in practice. lectures. Since the HDL will be used in laboratory ex- For the purposes of this discussion, we will assume just ercises, which requires a certain amount of homework the basic two-course sequence. preparation, the material that should be taught in the classroom may be covered in as little as three to four lectures. This approach is particularly viable if the text- 2 Logic Circuits book integrates efficiently the discussion of logic circuit concepts and their possible HDL descriptions. A course in logic circuits can be taught effectively as soon as the students have acquired an understanding of some high-level programming language and have 3 Introducing HDL - A Practical learned the fundamentals of good programming prac- Approach tices. The course should emphasize the important con- cepts which include the notions of implementability, A good understanding of computer hardware must be cost, optimization, timing, stability, and performance. based on a good understanding of underlying logic The amount of material that can be covered depends on circuits. An HDL, particularly when used at the the length of the course, the ability of the students, and behavioral level, can mask many important aspects of the quality of the supporting facilities comprising labo- logic circuits. Therefore, it is important to find a good ratories and CAD tools. balance between teaching the students the essence of

103 xn – 1 yn – 1 x1 y1 x0 y0

c1 cn FA cn – 1 c2 FA FA c0

sn – 1 s1 s0 MSB position LSB position

Figure 1: An n-bit ripple-carry adder. circuits and the efficiency of design using the HDL and module adder4 (carryin, X, Y, S, carryout); CAD tools. It is particularly important that using the input carryin; HDL does not obscure the existence of fundamental input [3:0] X, Y; logic blocks such as gates and flip-flops. To illustrate output [3:0] S; this notion, we will consider an example based on a output carryout; ripple-carry adder, using Verilog as the HDL [1]. wire [3:1] C;

Figure 1 shows the general structure of an n-bit fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]); ripple-carry adder, comprising a cascade of full-adder fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]); circuits. Knowing that the full-adder is defined by the fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]); logic expressions fulladd stage3 (C[3], X[3], Y[3], S[3], carryout); s = x ⊕ y ⊕ Cin endmodule Cout = x · y + x · Cin + y · Cin it is easy to visualize the functionality of the cascaded Figure 3: A four-bit adder. circuit, as well as the propagation delay due to the rippling of the carry. Using these expressions, the full-adder can be defined in Verilog as shown in Figure for k =0, 1,...,n− 1. A Verilog specification of the 2. adder based on these expressions is given in Figure 4. It is apparent that this approach also implements the cas- caded adder structure. Next, the students should learn module fulladd (Cin, x, y, s, Cout); that Verilog includes higher-level constructs for specifi- input Cin, x, y; cation of commonly used circuits. One such construct output s, Cout; uses the arithmetic assignment statement, which allows ∧ ∧ the adder to be specified as shown in Figure 5. We can assign s=x y Cin; add to this circuit the capability to produce the carry-out assign Cout = (x & y) | (x & Cin) | (y & Cin); and arithmetic overflow signals as presented in Figure 6. The expressions for these two signals are endmodule carryout = xn−1yn−1 + xn−1sn−1 + yn−1sn−1 overflow = carryout ⊕ xn−1 ⊕ yn−1 ⊕ sn−1 Figure 2: Verilog code for the full-adder. They can be derived as a useful exercise. A more elegant way of specifying the same circuit is Now, we can specify a ripple-carry adder structurally given in Figure 7. It uses an (n +1)-bit vector named as indicated in Figure 3. To keep the example simple, Sum. The extra bit, Sum[n], becomes the carry-out from this specification defines the inputs X and Y ,aswell bit position n − 1 in the adder. To make the addends as the sum S, as four-bit vectors. The internal carries n +1bits long, the vectors X and Y have a zero con- are defined as a three-bit vector C. The structure of the catenated on the left side. This conveniently introduces resulting circuit is the same as in Figure 1. the Verilog concatenate operator. It also ensures that the This would be an awkward way of describing a larger students see X and Y as bits in a circuit rather than just n-bit adder, so we can use a generic specification in- numbers. stead. The ripple-carry adder in Figure 1 can be de- Having introduced the idea of concatenation in Ver- scribed using the expressions ilog, our circuit can be defined more compactly as shown in Figure 8. Finally, at this point the students s = x ⊕ y ⊕ c k k k k can see that even the full-adder circuit can be defined ck+1 = xkyk + xkck + ykck behaviorally as depicted in Figure 9.

104 The progressive sequence of showing the students of the HDL use. More specifically, is the knowledge different ways in which Verilog code can specify an gained in the introductory logic course sufficient to deal n-bit adder teaches a number of important aspects of successfully with more ambitious designs needed in this Verilog. It shows the difference between structural and laboratory. behavioral approaches in defining circuits. It illustrates Instructors habitually complain that the students do how a for loop generates a cascade by replicating a not know as much as they should. Specifically, given a subcircuit n times. It indicates that powerful state- rather limited exposure to the HDL in the logic course, ments, such as the arithmetic assignment statement, ex- they cannot immediately tackle more demanding tasks ist which lead to simple and easily understandable code. in the computer organization laboratory. Indeed, this It also shows how clever ideas, exploiting the notion of may be true, particularly in the case of weaker students. concatenation in our example, can be used to good ef- However, with just a single refresher tutorial on DOs fect. and DON’Ts of the HDL the students can be brought to It is important to understand that a behavioral spec- a level where they can handle the requirements of the ification will not necessarily lead to a circuit structured laboratory. As with most subjects, an early exposure in the form that the designer may envisage, perhaps as to the HDL, followed by a short review and subsequent learned from a textbook. When the Verilog compiler of intensive use in the follow-on course, will leave the stu- a given CAD tool encounters a construct used to define dents with reasonable competence and a great deal of a commonly used circuit, it will attempt to use a pre- self-satisfaction. defined module from a library of parameterized mod- The described approach has been successful in our ules provided with the CAD tool. Moreover, if the de- practice. It has led to the development of three books signed circuit is to be implemented in a technology such [1-3]. The feedback from our students has been very as an FPGA, then the final implementation will be in positive. the form of logic elements used in a particular FPGA device. Thus, the implementation may not involve the basic gates that one saw in the lectures! 5 References

1. S. Brown and Z. Vranesic, Fundamentals of Digi- 4 Computer Organization tal Logic with Verilog Design, McGraw-Hill, 2002. 2. S. Brown and Z. Vranesic, Fundamentals of Digi- A good laboratory is essential for conveying the essence tal Logic with VHDL Design, McGraw-Hill, 2000. of the various structures found in computer systems. The students should learn what a computer looks like 3. V.C. Hamacher, Z. Vranesic and S. Zaky, Com- through the eyes of a programmer interested primarily puter Organization, ed. 5, McGraw-Hill, 2002. in using the machine and a designer intent on develop- ing the hardware needed to build systems. At the Uni- versity of Toronto we use the Ultragizmo board, which is a custom board containing a Motorola 68000-based microcontroller device, an FPGA device and a variety of interfaces that allow the board to be connected to our main laboratory system which includes a full net- working capability. We also use Altera’s UP-1 boards, which include programmable logic devices, to provide additional capability. Typical experiments include investigation of simple I/O using parallel and serial ports, interrupts, adding SRAM chips, DMA controllers, design of arithmetic circuits, A/D and D/A interfaces, and various applica- tions such as processing of sound and controlling simple Lego-implemented robots. At the end of our courses, we tend to have a three-week project for which students may implement anything that the instructor deems inter- esting. The project may entail even designing a simple processor, or building an interesting system based on an existing soft-core processor that may be instantiated in the FPGA. The FPGA device makes it possible to quickly im- plement relatively complex circuits needed in specific experiments. Of course, these circuits have to be spec- ified in the HDL. This raises an interesting question about the necessary competence of students in terms

105 module addern (carryin, X, Y, S, carryout); parameter n = 32; input carryin; input [n−1:0] X, Y; output [n−1:0] S; output carryout; reg [n−1:0] S; reg carryout; reg [n:0] C; integer k;

always @(X or Y or carryin) begin C[0] = carryin; for (k = 0; k < n; k = k+1) begin S[k] = X[k] ∧ Y[k] ∧ C[k]; C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]); end carryout = C[n]; end

endmodule

Figure 4: A generic specification of a ripple-carry adder.

module addern (carryin, X, Y, S); parameter n = 32; input carryin; input [n−1:0] X, Y; output [n−1:0] S; reg [n−1:0] S;

always @(X or Y or carryin) S=X+Y+carryin;

endmodule

Figure 5: Specification of an n-bit adder using arithmetic assignment.

106 module addern (carryin, X, Y, S, carryout, overflow); parameter n = 32; input carryin; input [n−1:0] X, Y; output [n−1:0] S; output carryout, overflow; reg [n−1:0] S; reg carryout, overflow;

always @(X or Y or carryin) begin S = X + Y + carryin; carryout = (X[n−1] & Y[n−1]) | (X[n−1] & ∼S[n−1]) | (Y[n−1] & ∼S[n−1]); overflow = carryout ∧ X[n−1] ∧ Y[n−1] ∧ S[n−1]; end endmodule

Figure 6: An n-bit adder with carry-out and overflow signals.

module addern (carryin, X, Y, S, carryout, overflow); parameter n = 32; input carryin; input [n−1:0] X, Y; output [n−1:0] S; output carryout, overflow; reg [n−1:0] S; reg carryout, overflow; reg [n:0] Sum;

always @(X or Y or carryin) begin Sum = {1’b0, X} + {1’b0, Y} + carryin; S = Sum[n−1:0]; carryout = Sum[n]; overflow = carryout ∧ X[n−1] ∧ Y[n−1] ∧ S[n−1]; end

endmodule

Figure 7: A different specification of n-bit adder.

107 module addern (carryin, X, Y, S, carryout, overflow); parameter n = 32; input carryin; input [n−1:0] X, Y; output [n−1:0] S; output carryout, overflow; reg [n−1:0] S; reg carryout, overflow;

always @(X or Y or carryin) begin {carryout, S} =X+Y+carryin; overflow = carryout ∧ X[n−1] ∧ Y[n−1] ∧ S[n−1]; end

endmodule

Figure 8: Simplified complete specification of an n-bit adder.

module fulladd (Cin, x, y, s, Cout); input Cin, x, y; output s, Cout; reg s, Cout;

always @(x or y or Cin) {Cout, s} =x+y+Cin;

endmodule

Figure 9: Behavioral specification of a full-adder.

108