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Series 3000 Reference Manua inter Series 3000 Family Of Computing Elements - The Total System Solution. Since its introduction in September, 1974, the Series 3000 family of computing elements has found acceptance in a wide range of high performance applications from disk controllers to airborne CPU's. The Series 3000 family represents more than a simple collection of bipolar components, it is a complete family of computing elements and hardware/software support that greatly simplifies the task of transforming a design from concept to production. The Series 3000 Component Family A complete set of computing elements that are designed as a system requiring a minimum amount of ancillary circuitry. 3001 Microprogram Control Unit. 3002 Central Processing Element. 3003 . Look-Ahead Carry Generator. 3212 Multi-Mode Latch Buffer. 3214 Interrupt Control Unit. 3216/26 Parallel Bi-directional Bus Driver. ROMs/PROMs A complete set of bipolar ROMs and PROMs. RAMs A Complete family of MOS and bipolar RAMs. rhe Series 3000 Support A comprehensive support system that assists the designer in writing microprograms, debugging hardware and microcode, and programming prototype and production PROMs. CROMIS Cross microprogram assembler. MDS-800 Microcomputer development system with TTY/CRT, line printer, diskette, PROM programmer and high speed paper tape reader facilities. ICE-30 In-circuit emulation for the 3001 MCU. ROM-SIM ROM simulation for all of Intel's Bipolar ROMs and PROMs. Application Central processor and disk controller designs and Notes system timing considerations. Customer Comprehensive 3 day course covering the component Course family, CPU and controller designs, microprogramming and the MDS-800, ICE-30 and ROM-SIM operation. The Series 3000 family is designed to provide a Total System Solution: high performance, minimum package count and total commitment to support. Contents INTRODUCTION ........................ 1-1 Series 3000 COMPONENT FAMILY .................. 2-1 Reference 3001 Microprogram Control Unit ....... 2-1 3002 Central Processing Element ...... 2-15 Manual 3003 Look-Ahead Carry Generator .... 2-31 3212 Multi-Mode Latch Buffer ......... 2-39 3214 Interrupt Control Unit . .. .. 2-49 3216/3226 Parallel Bi-Directional Bus Driver. .. 2-61 APPLICATIONS ......................... 3-1 3000 Family System Timing ............ 3-1 Disk Controller Designed With Series 3000 Computing Elements. .. 3-9 Central Processor Designs Using The Intel® Series 3000 Computing Elements . .. 3-19 ORDERING AND PACKAGING INFORMATION ......................... 4-1 Ordering Information .................. 4-1 Package Outlines ...................... 4-2 Series 3000 Family INTRODUCTION A family architecture To reduce component count as far as practical, a busses to be formed simply by connecting inputs and multi-chip LSI microcomputer set must be designed as a outputs together. complete, compatible family of devices. The omission of Each CPE represents a complete two-bit slice through a bus or a latch or the lack of drive current can multiply the data-processing section of a computer. Several CPES the number of miscellaneous SSI and MSI packages to a may be arrayed in parallel to form a processor of any dismaying extent-witness the reputedly LSI mini­ desired word length. The MCU, which together with the computers now being offered which need over a hun­ microprogram memory, controls the step-by-step oper­ dred extra TIL packages on their processor boards to ation of the processor, is itself a powerful micro­ support one or two custom LSI devices. Successful inte­ programed state sequencer. gration should .result in a minimum of extra packages, Enhancing the performance and capabilities of these and that includes the interrupt and the input/output two components are a number of compatible computing systems. elements. These include a fast look-ahead carry gener­ With this objective in mind, the Intel Schottky bipo­ ator, a priority interrupt unit, and a multimode latch lar LSI microcomputer chip set was developed. Its two buffer. A complete summary of the first available mem­ major components, the 3001 Microprogram Control bers of this family of LSI computing elements and mem­ Unit (MCU) and the 3002 Central Processing Element ories is given in the table on this page. (CPE), may be combined by the digital designer with standard bipolar LSI memory to construct high-per­ 3001 Microprogram control unit formance controller-processors (Fig.!) with a minimum 3002 Central processing element of ancillary logic. 3003 Look.-ahead carry generator Among the features that minimize package count and 3212 Multimode latch buffer improve performance are: the multiple independent 3214 Priority interrupt unit 3216 Noninverting bidirectional bus driver data and address busses that eliminate time multiplex­ 3226 Inverting bidirectional bus driver ing and the need for external latches; the three-state 3601 256-by-4-bit programable read-only memory output buffers with high fanout that make bus drivers 3604 512-by-8-bit programable read-only memory unnecessary except in the largest systems, and the sepa­ 3301 A 256-by-4-bit read-only memory rate output-enable logic that permits bidirectional 3304A 512-by-8-bit read-only memory . CONTROL TO MEMORY DATA BUS MEMORY 110 AOORESS BUS TO MEMORY MICRO NE~T PROGRAM ADDRESS MEMORY CONTROL CLOCK 181T 1 BIT 8 BITS FROM EXTERNAL DATA IN FROM 110 DEVICES MEMORY 1. Bipolar microcomputer. Block diagram shows how to implement a typical 16-bit controller-processor with new family of bipolar computer elements. An array of eight central processing elements (CPEs} is governed by a microprogram control unit (MCU} through a separate read-only memory that carries the microinstructions for the various processing elements. This ROM may be a fast, off-the-shelf unit. Intll Corporation ...mll no responsibility for the u. of any circuitry or microprogram other than circuitry or microprograms embodied in an Intel product. No other circuit patent licenas Ire implied. 1-1 Series 3000 Family ePEs form a processor Each CPE (Fig. 2) carries two bits of five independent Unlike earlier MSI arithmetic-iogic units, which con­ busses. The three input busses can be used in several tain many functions that are rarely used, the micro­ different ways. Typically, the K-bus is used for micro­ function decoder selects only useful CPE operations. program mask or literal (constant) value input, while Standard carry look-ahead outputs, X and y, are gener­ the other two input busses, M and I, carry data from ex­ ated by the CPE for use with available look-ahead de­ ternal memory or input/output devices. D-bus outputs vices or the Intel 3003 Look-ahead Carry Generator. In­ are connected to the CPE accumulator; A-bus outputs dependent carry input, carry output, shift input, and are connected to the CPE memory address register. As shift output lines are also available. the CPES are wired together, all the data paths, registers, What's more, since the K-bus inputs are always and busses expand accordingly. ANDed with the B-multiplexer outputs into the arith­ Certain data operations can be performed simply by metic function section, a number of useful functions connecting the busses in a particular fashion. For ex­ that in conventional MSI ALUs would require several ample, a byte exchange operation, often used in data­ cycles are generated in a single CPE microcycle. The communications processors, may be carried out by wir­ type of bit masking frequently done in computer control ing the D-bus outputs back to the I-bus inputs, ex­ systems can be performed with the mask supplied to the changing the high-order outputs and low-order inputs. K-bus directly from the microinstruction. Several other discretionary shifts and rotates can be Placing the K-bus in either the aU-one or all-zero accomplished in this manner. state wiU, in most cases, select or deselect the accumula­ A sixth CPE bus, the seven-line microfunction bus, tor in the operation, respectively. This toggling effect of controls the internal operation of the CPE by selecting the K-bus on the accumulator nearly doubles the CPE's the operands and the operation to be performed. The repertoire of microfunctions. For instance, with the arithmetic function section, under control of the micro­ K-bus in the all-zero state, the data on the M-bus may function bus decoder, performs over 40 Boolean and be complemented and loaded into the CPE's accumula­ binary functions, including 2's complement arithmetic tor. The same function selected with the K-bus in the and logical AND, OR, NOT, and exclusive-NOR. It incre­ all-one state will exclusive-NOR the data on the M-bus ments, decrements, shifts left or right, and tests for zero. with the accumulator contents. MEMORY AOORESS BUS OUTPUTS MEMORY DATA BUS MEMORY ADDRESS EA ENABLE CARRYLOOK-AHEAD {_jx __ --========~lL-l=t:==~==TTll OUTPUTS y --:-------------1 !+--+-+--+-+--j:>---CARRY INPUT RIPPLE CARRY -- CLIO-~-----------+t"'T'"T""" _____ SHIFT RIGHT OUTPUT ./ -r-.-J OUTPUT SHIFT RIGHT./" CLK.....I I INPUT vee .-J MICRO- {;;O-i II FUNCTION;' FUM~g~N INPUTSBUS F,' DECOOER I F, ~ I L __ _ __.-J M, Mo ~ ~--.--­ MEMORY OATA EXTERNAL MASK BUS BUS INPUTS BUS I NPUTS INPUTS 2. Central processing element. This element contains all the circuits representing a two-bit-wide slice through a small com­ puter's central processor. To build a processor of word width N, all that's necessary is to connect an array of NI2 CPEs together. 1-2 Series 3000 Family Threelnnovatlonl The power and versatility of the CPE are increased by other approach would require some type of program three rather novel techniques. The first of these is the counter. To simplify its logic, the MCV (Fig. 4) uses the use of the carry lines and logic during non-arithmetic classic approach and requires address control informa­ operations for bit testing and zero detection. The carry tion from each microinstruction. This information is circuits during these operations perform a word-wide not, however, simply the next microprogram address.
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