C-Ware Software Toolset Tutorial Workbook

Total Page：16

File Type：pdf, Size：1020Kb

User Guide C-WARE SOFTWARE TOOLSET TUTORIAL WORKBOOK C-WARE SOFTWARE TOOLSET VERSION 2.2 CSTTW-UG/D Rev 00 C-Ware Software Toolset Tutorial Workbook C-WARE SOFTWARE TOOLSET, VERSION 2.2 CSTTW-UG/D Rev 00 Copyright © 2003 Motorola, Inc. All rights reserved. No part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Motorola. Motorola reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of Motorola to provide notification of such revision or change. Motorola provides this documentation without warranty, term, or condition of any kind, either implied or expressed, including, but not limited to, the implied warranties, terms or conditions of merchantability, satisfactory quality, and fitness for a particular purpose. Motorola may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. C-3e, C-5, C-5e, C-Port, C-Ware, Q-3, and Q-5 are all trademarks of C-Port, a Motorola Company. Motorola and the stylized Motorola logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. CSTTW-UG/D Rev 00 CONTENTS About This Guide Guide Overview . 9 Using PDF Documents . 10 Guide Conventions . 11 References to CST Pathnames . 12 Revision History . 13 Related Product Documentation . 14 LESSON 1 Workbook Overview Overview . 17 Lessons . 17 Lessons in This Workbook . 18 CST High-Level Directories . 18 Building C-5 Applications From Programs . 18 Simulating the Execution of C-5 Programs . 19 Debugging C-5 RC Programs . 19 Generating Simulated Ingress Traffic . 20 Post-Processing Simulated Egress Traffic . 20 Programming the C-5 Serial Data Processors . 21 Modifying the Gigabit Ethernet Switch Application . 21 CST Helpful Hints . 22 Referring to CST Directory Pathnames . 22 Windows NT™ File Completion . 23 Setting the CST Environment Variables . 23 Text Editors . 24 LESSON 2 Examining the Toolset’s Top-Level Directories Goals . 25 Prerequisites . 25 MOTOROLA GENERAL BUSINESS INFORMATION CSTTW-UG/D REV 00 4 CONTENTS Top-Level Directory Contents . 25 alliance\ . 26 apps\ . 27 bin\ . 29 contrib\ . 30 diags\ . 30 Documentation\ . 30 drivers\ . 30 libperl\ . 30 mingw\ . 31 services\ . 31 Tools\ . 32 Summary . 32 Exercises . 33 LESSON 3 Building C-Ware Applications Goals . 35 Prerequisites . 35 Source Files Correspond to Network Processor Embedded Processors . 36 Automated Building of Packages . 37 More About Package Files and Build Target Variants . 38 Compiling the Application’s Programs . 39 XPRC Programs . 39 CPRC Programs . 40 Microcode Programs . 40 Dependency Checking . 42 Building Programs That Perform Offline Support for Applications . 43 Summary . 43 Exercises . 44 LESSON 4 Simulating the Execution of a C-Ware Application Goals . 45 Prerequisites . ..

184

Copy Link

Recommended publications

System Design for a Computational-RAM Logic-In-Memory Parailel-Processing Machine
System Design for a Computational-RAM Logic-In-Memory ParaIlel-Processing Machine Peter M. Nyasulu, B .Sc., M.Eng. A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Doctor of Philosophy Ottaw a-Carleton Ins titute for Eleceical and Computer Engineering, Department of Electronics, Faculty of Engineering, Carleton University, Ottawa, Ontario, Canada May, 1999 O Peter M. Nyasulu, 1999 National Library Biôiiothkque nationale du Canada Acquisitions and Acquisitions et Bibliographie Services services bibliographiques 39S Weiiington Street 395. nie WeUingtm OnawaON KlAW Ottawa ON K1A ON4 Canada Canada The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Library of Canada to Bibliothèque nationale du Canada de reproduce, ban, distribute or seU reproduire, prêter, distribuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la forme de microficbe/nlm, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts fkom it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation. Abstract Integrating several 1-bit processing elements at the sense amplifiers of a standard RAM improves the performance of massively-paralle1 applications because of the inherent parallelism and high data bandwidth inside the memory chip.
[Show full text]
Dop – a Cpu Core for Teaching Basics of Computer Architecture
DOP – A CPU CORE FOR TEACHING BASICS OF COMPUTER ARCHITECTURE Milos Becvar, Alois Pluhacek and Jiri Danecek Department of Computer Science and Engineering Faculty of Electrical Engineering Czech Technical University in Prague, Abstract: A simple 16-bit processor core called DOP and its teaching environment is presented. The DOP processor illustrates the basic principles of computer organization and is therefore used in the introductory hardware course. Its major features are simplicity, availability of an FPGA implementation and a C compiler. This paper presents the description of the core, HW and SW tools and teaching methodology. computing performance. The DOP processor core was 1. INTRODUCTION developed at our department together with various SW and HW visualization tools (Danecek et al., 1994a). An introductory computer hardware course should teach students to the fundamental principles of computer The goal of this paper is to describe this processor core internal functionality. Students, who are familiar with and its learning environment for teaching basics of programming in high-level languages, are required to computer organization. The paper is organized as understand the interaction between a processor, a follows - section 2 outlines the introductory course and memory and I/O devices, an internal organization of characterizes the students, section 3 describes the DOP processor, computer arithmetic and basics of digital processor core, section 4 describes the SW and HW design. Our experience has shown that it is not an easy tools supporting this processor and finally section 5 task for most of them. The functionality of the processor outlines the use of the DOP in our introductory course.
[Show full text]
10. Assembly Language, Models of Computation
10. Assembly Language, Models of Computation 6.004x Computation Structures Part 2 – Computer Architecture Copyright © 2015 MIT EECS 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #1 Beta ISA Summary • Storage: – Processor: 32 registers (r31 hardwired to 0) and PC – Main memory: Up to 4 GB, 32-bit words, 32-bit byte addresses, 4-byte-aligned accesses OPCODE rc ra rb unused • Instruction formats: OPCODE rc ra 16-bit signed constant 32 bits • Instruction classes: – ALU: Two input registers, or register and constant – Loads and stores: access memory – Branches, Jumps: change program counter 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #2 Programming Languages 32-bit (4-byte) ADD instruction: 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 opcode rc ra rb (unused) Means, to the BETA, Reg[4] ß Reg[2] + Reg[3] We’d rather write in assembly language: Today ADD(R2, R3, R4) or better yet a high-level language: Coming up a = b + c; 6.004 Computation Structures L10: Assembly Language, Models of Computation, Slide #3 Assembly Language Symbolic 01101101 11000110 Array of bytes representation Assembler 00101111 to be loaded of stream of bytes 10110001 into memory ..... Source Binary text file machine language • Abstracts bit-level representation of instructions and addresses • We’ll learn UASM (“microassembler”), built into BSim • Main elements: – Values – Symbols – Labels (symbols for addresses) – Macros 6.004 Computation Structures L10: Assembly Language, Models
[Show full text]
Programmable Digital Microcircuits - a Survey with Examples of Use
- 237 - PROGRAMMABLE DIGITAL MICROCIRCUITS - A SURVEY WITH EXAMPLES OF USE C. Verkerk CERN, Geneva, Switzerland 1. Introduction For most readers the title of these lecture notes will evoke microprocessors. The fixed instruction set microprocessors are however not the only programmable digital mi• crocircuits and, although a number of pages will be dedicated to them, the aim of these notes is also to draw attention to other useful microcircuits. A complete survey of programmable circuits would fill several books and a selection had therefore to be made. The choice has rather been to treat a variety of devices than to give an in- depth treatment of a particular circuit. The selected devices have all found useful ap• plications in high-energy physics, or hold promise for future use. The microprocessor is very young : just over eleven years. An advertisement, an• nouncing a new era of integrated electronics, and which appeared in the November 15, 1971 issue of Electronics News, is generally considered its birth-certificate. The adver• tisement was for the Intel 4004 and its three support chips. The history leading to this announcement merits to be recalled. Intel, then a very young company, was working on the design of a chip-set for a high-performance calculator, for and in collaboration with a Japanese firm, Busicom. One of the Intel engineers found the Busicom design of 9 different chips too complicated and tried to find a more general and programmable solu• tion. His design, the 4004 microprocessor, was finally adapted by Busicom, and after further négociation, Intel acquired marketing rights for its new invention.
[Show full text]
The Hpc C Compiler 2.1 Introduction
™ MICROCONTROLLER DEVELOPMENT SUPPORT ( MOLE HPC™ C COMPILER USER'S MANUAL ( ( ( ( ~ National Semiconductor Corporation Customer Order Number 424410883-001 NSC Publication Number 424410883-001C October 1988 HPC™ C Compiler User's Manual @l 1988 National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara. California 95052-8090 CONTENTS Chapter 1 OVERVIEW 1.1 INTRODUCTION............................. 1-1 1.2 MANUAL ORGANIZATION. .. 1-2 1.3 DOCUMENTATION CONVENTIONS. .. 1-2 1.3.1 General Conventions . .. 1-2 1.3.2 Conventions in Syntax Descriptions ............. 1-2 1.3.3 Example Conventions. .. 1-3 1.3.4 Additional Conventions .................... 1-3 Chapter 2 THE HPC C COMPILER 2.1 INTRODUCTION............................. 2-1 2.2 COMPILER COMMAND SYNTAX 2-1 Chapter 3 BASIC DEFINITIONS 3.1 INTRODUCTION............................. 3-1 3.2 NAMES.................................. 3-1 3.3 CONSTANTS............................... 3-1 3.4 ESCAPE SEQUENCES . .. 3-2 3.5 COMMENTS............................... 3-3 3.6 DATA TYPES. .. 3-3 3.7 PREPROCESSOR DIRECTIVES . .. 3-4 3.8 PROGRAM ORGANIZATION. .. 3-4 3.9 INITIALIZATION OF VARIABLES . .. 3-4 3.10 OPERATORS . .. 3-5 3.11 IN-LINE MICROASSEMBLER CODE . .. 3-5 Chapter 4 IMPLEMENTATION-DEPENDENT CONSIDERATIONS 4.1 INTRODUCTION............................. 4-1 4.2 MEMORy................................. 4-1 4.3 STORAGE CLASSES . .. 4-1 4.3.1 Storage Class Modifiers. .. 4-1 4.4 C STACK FORMAT . .. 4-3 4.5 USING IN-LINE MICROASSEMBLER CODE. .. 4-4 4.6 EFFICIENCY CONSIDERATIONS . .. 4-6 4.6.1 Declaration Syntax . .. 4-9 4.7 STATEMENTS AND IMPLEMENTATION .............. 4-10 4.8 RUN-TIME NOTES ........................... 4-11 v Appendix A CCHPC SPECIFICATIONS Appendix B CONVERTING BETWEEN STANDARD C AND CCHPC Appendix C INVOCATION LINE SYNTAX C.l INTRODUCTION............................
[Show full text]
WCAE 2003 Workshop on Computer Architecture Education
WCAE 2003 Proceedings of the Workshop on Computer Architecture Education in conjunction with The 30th International Symposium on Computer Architecture DQG 2003 Federated Computing Research Conference Town and Country Resort and Convention Center b San Diego, California June 8, 2003 Workshop on Computer Architecture Education Sunday, June 8, 2003 Session 1. Welcome and Keynote 8:45–10:00 8:45 Welcome Edward F. Gehringer, workshop organizer 8:50 Keynote address, “Teaching and teaching computer Architecture: Two very different topics (Some opinions about each),” Yale Patt, teacher, University of Texas at Austin 1 Break 10:00–10:30 Session 2. Teaching with New Architectures 10:30–11:20 10:30 “Intel Itanium floating-point architecture,” Marius Cornea, John Harrison, and Ping Tak Peter Tang, Intel Corp. ................................................................................................................................. 5 10:50 “DOP — A CPU core for teaching basics of computer architecture,” Miloš BeþváĜ, Alois Pluháþek and JiĜí DanƟþek, Czech Technical University in Prague ................................................................. 14 11:05 Discussion Break 11:20–11:30 Session 3. Class Projects 11:30–12:30 11:30 “Superscalar out-of-order demystified in four instructions,” James C. Hoe, Carnegie Mellon University ......................................................................................................................................... 22 11:50 “Bridging the gap between undergraduate and graduate experience in
[Show full text]
Series 3000 Reference Manua
inter Series 3000 Family Of Computing Elements - The Total System Solution. Since its introduction in September, 1974, the Series 3000 family of computing elements has found acceptance in a wide range of high performance applications from disk controllers to airborne CPU's. The Series 3000 family represents more than a simple collection of bipolar components, it is a complete family of computing elements and hardware/software support that greatly simplifies the task of transforming a design from concept to production. The Series 3000 Component Family A complete set of computing elements that are designed as a system requiring a minimum amount of ancillary circuitry. 3001 Microprogram Control Unit. 3002 Central Processing Element. 3003 . Look-Ahead Carry Generator. 3212 Multi-Mode Latch Buffer. 3214 Interrupt Control Unit. 3216/26 Parallel Bi-directional Bus Driver. ROMs/PROMs A complete set of bipolar ROMs and PROMs. RAMs A Complete family of MOS and bipolar RAMs. rhe Series 3000 Support A comprehensive support system that assists the designer in writing microprograms, debugging hardware and microcode, and programming prototype and production PROMs. CROMIS Cross microprogram assembler. MDS-800 Microcomputer development system with TTY/CRT, line printer, diskette, PROM programmer and high speed paper tape reader facilities. ICE-30 In-circuit emulation for the 3001 MCU. ROM-SIM ROM simulation for all of Intel's Bipolar ROMs and PROMs. Application Central processor and disk controller designs and Notes system timing considerations. Customer Comprehensive 3 day course covering the component Course family, CPU and controller designs, microprogramming and the MDS-800, ICE-30 and ROM-SIM operation.
[Show full text]
Micro Machine·Independent Microassembler
MICRO MACHINE·INDEPENDENT MICROASSEMBLER 11 July 1980 ... by. Edward Fiala Peter Deutsch Butler Lampson Xerox Palo Alto Research Center 3333 Coyote Hill Rd. Palo Alto, CA. 94304 Filed on: [Maxcl]<AltoDOCS>Micro.Press Sources on: [Ivy]<DoradoSource)MicroMemo.Dm This manual describes a machine-independent microassembly language originally developed for the Maxcl computer and since used for the Maxc2, Dorado, and DO computers as well as for several smaller projects. This manual is the property of Xerox Corporation and is to be used solely for evaluative purposes. No part thereof may be reproduced, stored in a retrieval system transmited, disseminated, or disclosed to others in any form or by any means without prior written permission of Xerox. Micro: Machine-Independent MicroAssembler 11 July 1980 2 TABLE OF CONTENTS 1. Introduction . .. 3 2. Assembly Procedures . .. 3 3. Error Messages. .. 6 4. Assembly Listings ..............'. .. 7 5. Cross Reference Listings. .. 8 6. Comments .................................... 9 7. Statements.................................... 10 7.1 Builtins.................................. 11 7.2 Defining Symbols . ............... 11 7.3 Tokens.................................. 13 7.4 Neutrals and Tails ........................... 14 7.5 Clause Evaluation ........................... 16 7.6 Treatment of Arguments ...................... 16 7.7 Undefined Symbols. .. 17 7.7.1 Destination Addresses .................... 18 7.7.2 Octal Numbers ......................... 18 7.7.3 Literals .............................
[Show full text]
Parallel Processing Implementations of a Contextual Classifier for Multispectral Remote Sensing Data Howard J
Purdue University Purdue e-Pubs LARS Technical Reports Laboratory for Applications of Remote Sensing 1-1-1980 Parallel Processing Implementations of a Contextual Classifier for Multispectral Remote Sensing Data Howard J. Siegel Philip H. Swain Bradley W. Smith Follow this and additional works at: http://docs.lib.purdue.edu/larstech Siegel, Howard J.; Swain, Philip H.; and Smith, Bradley W., "Parallel Processing Implementations of a Contextual Classifier for Multispectral Remote Sensing Data" (1980). LARS Technical Reports. Paper 51. http://docs.lib.purdue.edu/larstech/51 This document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact [email protected] for additional information. PARALLEL PROCESSING IMPLEMENTATIONS 060380 OF A CONTEXTUAL CLASSIFIER FOR MULTISPECTRAL REMOTE SENSING DATA HOWARD JAY SIEGEL J PHILIP H. SWAIN J AND BRADLEY W. SMITH Purdue University ABSTRACT pIer algorithms used for remote sensing data analysis) typically require large a Contextual classifiers are being de mounts of computation time. One way to veloped as a method to exploit the spati reduce the execution time of these tasks al/spectral context of a pixel to achieve is through the use of parallelism. Vari accurate classification. Classification ous parallel processing systems that can algorithms such as the contextual classi be used for remote sensing have been fier typically require large amounts of built or proposed. The Control Data Cor computation time. One way to reduce the poration Flexible Processor system is a execution time of these tasks is through commercially available multiprocessor sys the use of parallelism. The applicability tem which has been recommended for use in of the CDC Flexible Processor system and remote sensing [4,5].
[Show full text]
Are Central to Operating Systems As They Provide an Efficient Way for the Operating System to Interact and React to Its Environment
1 www.onlineeducation.bharatsevaksamaj.net www.bssskillmission.in OPERATING SYSTEMS DESIGN Topic Objective: At the end of this topic student will be able to understand: Understand the operating system Understand the Program execution Understand the Interrupts Understand the Supervisor mode Understand the Memory management Understand the Virtual memory Understand the Multitasking Definition/Overview: An operating system: An operating system (commonly abbreviated to either OS or O/S) is an interface between hardware and applications; it is responsible for the management and coordination of activities and the sharing of the limited resources of the computer. The operating system acts as a host for applications that are run on the machine. Program execution: The operating system acts as an interface between an application and the hardware. Interrupts: InterruptsWWW.BSSVE.IN are central to operating systems as they provide an efficient way for the operating system to interact and react to its environment. Supervisor mode: Modern CPUs support something called dual mode operation. CPUs with this capability use two modes: protected mode and supervisor mode, which allow certain CPU functions to be controlled and affected only by the operating system kernel. Here, protected mode does not refer specifically to the 80286 (Intel's x86 16-bit microprocessor) CPU feature, although its protected mode is very similar to it. Memory management: Among other things, a multiprogramming operating system kernel must be responsible for managing all system memory which is currently in use by programs. www.bsscommunitycollege.in www.bssnewgeneration.in www.bsslifeskillscollege.in 2 www.onlineeducation.bharatsevaksamaj.net www.bssskillmission.in Key Points: 1.
[Show full text]
A Programming Environment for Network Processors
A Programming Environment for Network Processors Michael E. Kounavis, Andrew T. Campbell, Stephen T. Chou and John B. Vicente COMET Group, Columbia University, New York, NY 10025, USA Abstract There is growing interest in network processor technologies capable of processing packets at line rates. In this paper, we present the design, implementation and evaluation of NetBind, a programming environment for constructing data paths in network processor-based routers. NetBind balances the flexibility of network programmability against the need to process and forward packets at line speeds. To support dynamic binding of components with minimum addition of instructions in the critical path, NetBind modifies the machine language code of components at run time. To support fast data path composition, NetBind reduces the number of binding operations required for constructing data paths to a minimum set so that binding latencies are comparable to packet forwarding times. Data paths constructed using NetBind seamlessly share the resources of the same network processor. The NetBind source code described and evaluated in this paper is freely available on the Web [15] for experimentation. 1. Introduction Recently, there has been a growing interest in network processor technologies [1-4] that can support software-based implementations of the critical path while processing packets at high speeds. Network processors use specialized architectures that employ multiple processing units to offer high packet- processing throughput. We believe that introducing programmability in network processor-based routers is an important area of research that has not been fully addressed as yet. The difficulty stems from the fact network processor-based routers need to forward minimum size packets at line rates and yet support modular and extensible data paths.
[Show full text]
Netbind: a Binding Tool for Constructing Data Paths in Network Processor-Based Routers
NetBind: A Binding Tool for Constructing Data Paths in Network Processor-Based Routers Andrew T. Campbell, Stephen T. Chou, Michael E. Kounavis, Vassilis D. Stachtos and John Vicente network processors because these techniques introduce Abstract-- There is growing interest in network processor considerable overhead in terms of additional instructions in technologies capable of processing packets at line rates. In this the critical path. One solution to this problem is to optimize paper, we present the design, implementation and evaluation the code produced by a binding tool, once data path of NetBind, a high performance, flexible and scalable binding composition has taken place. Code optimization algorithms tool for dynamically constructing data paths in network can be complex and time-consuming, however, and thus not processor-based routers. The methodology that underpins NetBind balances the flexibility of network programmability suitable for applications that require fast data path against the need to process and forward packets at line speeds. composition, (e.g., data path composition on a packet-by- Data paths constructed using NetBind seamlessly share the packet basis). We believe that a binding tool for network resources of the same network processor. We compare the processor-based routers needs to balance the flexibility of performance of NetBind to the MicroACE system developed network programmability against the need to process and by Intel to support binding between software components forward packets at line rates. This poses significant running on Intel IXP1200 network processors. We evaluate challenges. these alternative approaches in terms of their binding In this paper, we present the design, implementation and overhead, and discuss how this can affect the forwarding evaluation of NetBind, a high performance, flexible and performance of IPv4 data paths running on IXP1200 network processor-based routers.
[Show full text]