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ADVANCED POWER ELECTRONICS PACKAGING SEMINAR (Pdf)

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ADVANCED POWER ELECTRONICS PACKAGING SEMINAR (Pdf) Integrated Packaging Techniques Douglas C. Hopkins, Ph.D. Dir., Electronic Power and Energy Research Laboratory Assoc. Dir. Electronic Packaging Laboratory University at Buffalo 332 Bonner Hall Buffalo, NY 14620-1900 607-729-9949, fax: 607-729-7129 www.DCHopkins.Com APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins OUTLINE Part I - Introduction & Housekeeping Part II - Framework • Understanding interdependencies of electrical, thermal and mechanical circuits. Analogs and equivalents • Board to floor packaging of mW to MW, the same technical issues. Part III - Power Electronic Challenges • Understanding parasitic effects • Component and substrate interactions Part IV - Module Packaging • Methods and approaches to power packaging (mW to MW) • Organics (PCBs) to Heavy Metals (bus bars) • Kilo-Volts and Kilo-Amps packaging • Selecting and integrating multiple packaging approaches Part V - Advanced topics • Extended temperature packaging for <250C • High temperature packaging for >250C APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Integrating power on-board and beyond The Point-of-Load Alliance (POLA) was formed by Artesyn, Texas Instruments and Astec Power in June 2003 Full Brick 4.6”X2.3” HB 2.4”X2.28” QB 2.28”X1.45” EB … 2.28”X0.8” 84-85 90-91 94-95 2002 05-07 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Integrating onto Level-0 PSiP - Power Supply in Package PwrSoC - Power Supply on Chip Study by Power Sources Manufacturers Assoc. (PSMA) 25Jan’08 • Phase-I Report - “Market and Technical Report on Power-Supply-in-a- Package and Power-Supply-on-a-Chip” • Phase-II underway at Tyndall, Cork, Ireland APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Int’l Technology Roadmap - Semiconductors: 2006 Low cost/hand held (A) 2.8 3.3 3.3 3.8 4.3 5.0 5.0 5.0 6.0 Cost performance (A) 101 123 148 184 194 238 238 249 274 High performance (A) 324 406 449 556 583 817 858 800 960 Harsh (A) 13 15 15 17 17 18 22 24 28 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Realizing physical systems - Integrating Energy Processes in the Physical World “If you are not processing information, you are processing power…” APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Comprehensive Packaging Approach The “Energy Packaging Framework” shows that all technical challenges come from managing energy flow along interconnect paths and between packaging levels. Interface & Pathway Packaging Level Energy Form The term “energy” in packaging is used in the broadest context to concurrently include chemical, electrical, mechanical and thermal energies. APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins First focus: Energy Forms A physical realization of the system integrates an: Chemical circuit, Electrical circuit, Mechanical circuit, Thermal circuit, etc. I&P “Energy circuits” have: 1.Components 2.Topologies 3.Controls Energy Advancing one form, impacts, usually negatively, other Forms forms P.L. Barriers in one form may be overcome in other forms APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Components for every energy form Form Components Characteristics Transmission Line Mode Electrical R, L, C Lumped/Distributed Para. Resonance Mass, Spring, Dash-pot(tension, Resonance Mechanical compression) (see Acoustics) Air Mass, Material elasticity Acoustic (vacuum, compression) Thermal Mass Resonance? APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Analogies Form Parameters V Volts Electrical V, I, [R] R = [ ] " I Aamps [ ] o T(temperature), T C Thermal R = [ ] q(heat flow), [R!] " q Watts ! [ ] 2 Mechanical " N m " (stress), #(strain) E = [ ] (elastic modulus) # m m ! [ ] APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins ! Pressure, Flow & CTE Symmetric Structure # & R = "% L ( Asymmetric Structure $ t •W' (potato chipping) " If L = W, then Rsq = t APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins ! Levels of Packaging Lvl-0:System - on - Chip • (silicon integration) Lvl-1:Chip -in- package • (component packaging) Lvl-2:Package -on- Board • (board level packaging) I&P Lvl-3:Board -in- Rack • (box level packaging) Packaging E.F. Levels APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins PSMA Special Project PSiP2PwrSoC Objective Undertake first detailed study of the evolution in products and technology from Power Supply in Package to Power Supply on Chip (PwrSoC) Scope High-end Consumer Non-isolated 1Watt to 30Watts (30Amps) 6.5m ! 2m! Sync. FET Programme Outline Phase 1: July 2007 to Dec 2007. Phase 2: Mar 2008 to Dec 2008. Phase 2 Sponsorship – 50/50 – PSMA / Member Companies Crane Aerospace & Electronics, Fairchild Semiconductor Corporation. Leader Electronics, Murata Power Solutions, ON Semiconductor Corporation. APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins PSiP - Power Supply in Package 2 Number of Components 7 13 25 35 33 Source: PSMA PSIP2PwrSoC Phase 2 Study -2009 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins PSiP - Power Supply in Package Power ASIC + Custom Inductor/Integrated Leadframe Paving the way to PwrSoC 12 x 10 x 1.85mm Source: PSMA PSIP2PwrSoC Phase 2 Study -2009 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins PSiP - Power Supply in Package Paving the way to PwrSoC Power ASIC + Chip Inductor on Leadframe 6 x 4 x 0.85mm Source: PSMA PSIP2PwrSoC Phase 2 Study -2009 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Efficiency Trends for Products PSiP Efficiency Trend 100% 95% 90% 85% 80% 75% 70% 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 Source: PSMA PSIP2PwrSoC Phase 2 Study -2009 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Switching Frequency Trend for Products Switching Frequency Trend 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 2001 2003 2005 2007 2009 Year Introduced Source: PSMA PSIP2PwrSoC Phase 2 Study -2009 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Current Density Trend -+$$"'(%."'/0(1%2$"'* "!!! &%!! &$!! &#!! &"!! &!!! %!! $!! #!! "!! ! "!!" "!!' "!!# "!!( "!!$ "!!) "!!% "!!* "!&! "!&& !"#$%&'($)*+,"* Source: PSMA PSIP2PwrSoC Phase 2 Study -2009 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Switching Frequency vs. Current Density 9000 PSiP 8000 7000 6000 5000 4000 3000 2000 1000 0 0 500 1000 1500 Current Density (A/in2) Source: PSMA PSIP2PwrSoC Phase 2 Study -2009 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Level 1 and 1.5 Power ASIC chip on board with wire bonding Level 1: Component(s) in Package. (Module) Level 1.5: Chip on Board PQFN 3x3 APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Level 2 Level 2: Package on Board STANDARD SIPS 5/12V INPUT; 5A, 10A, 15A APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Level 3 Level 3: Board in Rack 1600W Front-ends 4.8kW shelf APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Levels 4-5... Level 4: Rack in Cabinet. Level 5: Multiple Cabinets (in room) 6: Room in building 7: Building in community APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Addressing multiple packaging levels Level-2: Board-level or “floor- Level-1: Component in Package level” packaging have common physics of gradients, e.g. high Single components or voltage field gradients across air, Mutichip power ceramic or organic dielectrics. modules Level-2: Package on Board APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins The technical driver - Energy Flow All technical issues are found at the “interfaces” and in the “pathways” of ENERGY flow Any technical issue is subdivided Interfaces & into the four+ energy forms Mapping technologies to address Pathways an issue in one energy form impacts (usually negatively) the other energy forms •(e.g. higher temperature solders are E.F. more brittle and induce greater stress.) P.L. APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Levels of Packaging - Strategy Each level has Components and Topologies. Strategy - combine levels downward for • Decreased: cost, thermal resistance, stress • Increased: density, reliability, manufacturability Module vs Partition Modularization is subdividing circuit functionality for repeated use in multiple products. Circuit Partitioning is subdividing circuit fabrication along packaging levels to improve manufacturability. APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins ‘Interfaces and Pathways’ (I&P) All technical issues are reduced to I&P Interface issues occur for energy transfer between levels, Pathway issues occur for energy transfer within a level. Allows concurrent investigation of all concerns APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins I&P at the interface Example: Interface (between levels) for Level-2 (package on board) I&P ISSUES Electrical solder impedance of components Magnetic proximity of components Mechanical component adhesion Thermal heatsink attach APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Grouping Requirements Characteristic Unspoken Expectations Articulated Needs Unexpected Features Taxonomy Technical Environmental Financial Legal MATRIXED Social APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Leading to specifications Characteristics s e i m o n Technical Characteristics o x a Energy Forms T Conditions Start-up Shut-down Normal operation Fault operation APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Understanding the Power Electronics Challenge second - The physical circuit APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Typical Electrical Structure Lead Inductance Finite resistance Skin Effect Inter-Conductor Capacitance Coupled Capacitance APEC’09, Washington, DC [email protected] © 2009, D. C. Hopkins Conductor Resistance -Sheet Resistance l t l R = " l / (t ! w) w let l / w = 1 = “one square” Rsheet = " / t [ ! / sq.
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