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DLX Instruction Set Arch Itectu Re DLX Instruction Set Arch itectu re HE DLX is a 32-bit RISe architecture which manages with only three T instruction formats. The core of the architecture is the fixed point unit FXU, but there also exists a floating point extension. A.1 DLX Fixed-Point Core: FXU HE DLX fixed point unit uses 32 general purpose registers RO to R3I, T each of which is 32 bits wide. Register RO always has the value o. The FXU also has a few 32-bit special purpose registers mainly used for handling interrupts. Table A.I lists these registers as well as a brief description of their usage. For more details see chapter 5. Special move instructions transfer data between general and special purpose registers. Load and store operations move data between the general purpose reg­ isters and the memory. There is a single addressing mode: the effective memory address ea is the sum of a register and an immediate constant. Except for shifts, immediate constants are always sign-extended to 32-bits. The memory is byte addressable and performs byte, half-word or word accesses. All instructions are coded in four bytes. In memory, data and instructions must be aligned in the following way: Half words must start at even byte addresses. Words and instructions must start at addresses divisible by 4. These addresses are called word boundaries. Appendix A DLX INSTRUCTION Table A.1 Special purpose registers of the DLX fixed point core SET I register II usage ARCHITECTURE PC program counter points to the next instruction SR status register holds interrupt masks (among others) CA cause register records pending interrupts EPC, exception registers on a jump to the interrupt service rou- ESR, tine they backup the current value of ECA, PC, SR, CA respectively the current EMAR memory address 6 5 5 16 I-type opcode RSl RD immediate 6 5 5 5 5 6 R-type opcode RSl RS2 RD SA function 6 26 J-type opcode PC offset Figure A.1 The three instruction formats of the DLX design. The fields RS 1 and RS2 specify the source registers, and the field RD specifies the destination regis­ ter. Field SA specifies a special purpose register or an immediate shift amount. Function field is an additional 6-bit opcode. A.I.1 Instruction Formats All three instruction formats (figure A.I) have a 6-bit primary opcode and specify up to three explicit operands. The I-type (Immediate) format spec­ ifies two registers and a I6-bit constant. That is the standard layout for instructions with an immediate operand. The J-type (Jump) format is used for control instructions. They require no explicit register operand and profit from the larger 26-bit immediate operand. The third format, R-type (Regis­ ter) format, provides an additional 6-bit opcode (junction). The remaining 20 bits specify three general purpose registers and a field SA which spec­ ifies a 5-bit constant or a special purpose register. A 5-bit constant, for example, is sufficient as shift amount. 520 Appendix A Table A.2 J-type instruction layout; sxt(imm) is the sign-extended version of the FLOATING-POINT 26-bit immediate called PC Offset. EXTENSION I IR[31 :26] II mnemonic I effect Control Operation hx02 j PC = PC + 4 + sxt(imm) hx03 jal R31 = PC + 4; PC = PC + 4 + sxt(imm) hx3e trap trap = 1; Edata = sxt(imm) hx3f rfe SR=ESR; PC = EPC; DPC=EDPC A.1.2 Instruction Set Coding Since the DLX description in [HP90] does not specify the coding of the instruction set, we adapt the coding of the MIPS R2000 machine ([PH94, KH92]) to the DLX instruction set. Tables A.2 through A.4 specify the instruction set and list the coding; the prefix "hx" indicates that the number is represented as hexadecimal. The effects of the instructions are specified in a register transfer language. A.2 Floating-Point Extension ESIDES THE fixed point unit, the DLX architecture also comprises a B floating point unit FPU, which can handle floating point numbers in single precision (32-bits) or in double precision (64-bits). For both preci­ sions, the FPU fully conforms the requirements of the ANSIlIEEE standard 754 [lns85]. A.2.1 FPU Register Set The FPU provides 32 floating point general purpose registers FPRs, each of which is 32 bits wide. In order to store double precision values, the registers can be addressed as 64-bitfloating point registers FDRs. Each of the 16 FDRs is formed by concatenating two adjacent FPRs (table A.5). Only even numbers (0,2, ... ,30) are used to address the floating point reg­ isters FPR; the least significant address bit is ignored. In addition, the FPU provides three floating point control registers: a I-bit register FCC for the floating point condition code, a 5-bit register IEEEffor the IEEE exception flags and a 2-bit register RM specifying the IEEE rounding mode. 521 Appendix A DLX INSTRUCTION Table A.3 R-type instruction layout. All instructions increment the PC by four. SET SA is a shorthand for the special purpose register SPR[SAj; sa denotes the 5-bit ARCHITECTURE immediate shift amount specified by the bits IR[1O:6]. I IR[31:26] I IR[5:0] II mnemonic I effect Shift Operation hxOO hxOO slli RD = sl1(RS 1, sa) hxOO hx02 srli RD = srI(RSl, sa) hxOO hx03 srai RD = sra(RS 1, sa) hxOO hx04 sl1 RD = sl1(RS 1, RS2[4:0]) hxOO hx06 srI RD = srI(RS 1, RS2[4:0]) hxOO hx07 sra RD = sra(RSl, RS2[4:0]) Arithmetic, Logical Operation hxOO hx20 addo RD = RS 1 + RS2; ovf signaled hxOO hx21 add RD = RS 1 + RS2; no ovf signaled hxOO hx22 subo RD = RS 1 - RS2; ovf signaled hxOO hx23 sub RD = RS 1 - RS2; no ovf signaled hxOO hx24 and RD = RSI J\ RS2 hxOO hx25 or RD=RSI VRS2 hxOO hx26 xor RD=RSI $RS2 hxOO hx27 lhg RD = RS2[15:0] 016 Test Set Operation hxOO hx28 elr RD = (false ? 1 : 0); hxOO hx29 sgr RD = (RS 1 > RS2 ? 1 : 0); hxOO hx2a seq RD = (RS 1 = RS2 ? 1 : 0); hxOO hx2b sge RD = (RS 1 ~ RS2 ? 1 : 0); hxOO hx2c sIs RD = (RSI < RS2 ? 1 : 0); hxOO hx2d sne RD = (RSI :f: RS2 ? 1 : 0); hxOO hx2e sle RD = (RS 1 ~ RS2 ? 1 : 0); hxOO hx2f set RD = (true ? 1 : 0); Special Move Instructions hxOO hxlO movs2i RD=SA hxOO hxll movi2s SA=RSI A.2.2 FPU Instruction Set The DLX machine uses two formats (figure A.2) for the floating point instructions; one corresponds to the I-type and the other to the R-type of the fixed point core. The FI-format is used for loading data from memory 522 Appendix A Table A.4 I-type instruction layout. All instructions except the control instruc- FLOATING-POINT tions also increment the PC by four; sxt(a) is the sign-extended version of a. EXTENSION The effective address of memory accesses equals ea = (GPR[RS1)} + (sxt(imm)) , where imm is the 16-bit intermediate. The width of the memory access in bytes is indicated by d. Thus, the memory operand equals m = M[ea+d -1]'··· ,M[ea]. I IR[31 :26] II mnemonic I d I effect Data Transfer hx20 lb 1 RD = sxt(m) hx21 lh 2 RD = sxt(m) hx23 lw 4 RD=m hx24 lbu 1 RD=OZ4m hx25 lhu 2 RD=016m hx28 sb 1 m =RD[7:0] hx29 sh 2 m =RD[15:0] hx2b sw 4 m=RD Arithmetic, Logical Operation hx08 addio RD = RS 1 + imm; ovf signaled hx09 addi RD = RS 1 + imm; no ovf signaled hxOa subio RD = RS 1 - imm; ovf signaled hxOb subi RD = RS 1 - imm; no ovf signaled hxOc andi RD = RSI /\ sxt(imm) hxOd ori RD = RSI V sxt(imm) hxOe xori RD = RS 1 EB sxt(imm) hxOf lhgi RD=imm016 Test Set Operation hx18 cIri RD = (false ? 1 : 0); hx19 sgri RD = (RSI > imm ? 1 : 0); hxla seqi RD = (RS 1 = imm ? 1 : 0); hxlb sgei RD = (RSI ~ imm ? 1 : 0); hxlc slsi RD = (RS 1 < imm ? 1 : 0); hxld snei RD = (RSI # imm ? 1 : 0); hxle slei RD = (RSI ~ imm ? 1 : 0); hxlf seti RD = (true ? 1 : 0); Control Operation hx04 beqz PC = PC + 4 + (RS 1 = 0 ? imm: 0) hx05 bnez PC = PC + 4 + (RSI # 0 ? imm: 0) hx16 jr PC =RSI hx17 jalr R31 =PC +4; PC=RSI 523 Appendix A DLX INSTRUCTION Table A.5 Register map of the general purpose floating point registers SET floating point ARCHITECTURE floating point registers general purpose registers single precision (32-bit) double precision (64-bit) FPR31[31 : 0] FDR30[63 : 32] } FDR30[63 .0] FPR30[31 : 0] FDR30[31 : 0] . FPR3[31 : 0] FDR2[63 : 32] } FDR2[63 . 0] FPR2[31 : 0] FDR2[31 : 0] . FPRl[31 : 0] FDRO[63 : 32] } FDRO[63 . 0] FPRO[31 : 0] FDRO[31 : 0] . 6 5 5 16 FI-type Opcode I Rx FD Immediate 6 5 5 5 3 6 FR-type Opcode FS1 IFS2/Rxi FD 100lFmti Function I Figure A.2 Floating point instruction formats of the DLX. Depending on the pre­ cision, FS 1, FS2 and FD specify 32-bit or 64-bit floating point registers. RS specifies a general purpose register of the FXU. Function is an additional 6-bit opcode. Fmt specifies a number format. into the FPU respectively for storing data from the FPU into memory. This format is also used for conditional branches on the condition code flag FCC of the FPU.
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