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Implementation and Verification of Risc Processor on Fpga Using Chipscope

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Implementation and Verification of Risc Processor on Fpga Using Chipscope IMPLEMENTATION AND VERIFICATION OF RISC PROCESSOR ON FPGA USING CHIPSCOPE PRO TOOL 1Prof Ruckmani Divakaran, 2Srinivas Babu .N, 3Shashi Kiran .S, 4Byrareddy .H.C 1 Head of Department, Department of Electronics and Communication, Dr. TTIT, KGF, [email protected] 2 Assistant Professor, Department of Electronics and Communication, Dr. TTIT, KGF, [email protected] 3 Assistant Professor, Department of Electronics and Communication, Dr. TTIT, KGF, [email protected] 4 PG Scholar, M.Tech in Digital Communication and Networking, Dr. TTIT, KGF, [email protected] Abstract concerning previous similar architecture The advanced microprocessors are widely with improvements. used for most of the complex systems. A Key words: RISC Processor, ALU Unit, silicon chip of fingernail-size may exhibit Execution, Fetching, decoding, Verification, entire high performance guaranteed FPGA processor, higher cache memory and logic needed for interfacing with external devices. I. INTRODUCTION Reduced Instruction Set Computing (RISC) The earlier days of the processor design has is a CPU (Central Processing Unit) design witnessed a quest for higher performance in mechanism based on the vision in which computer models and architectures. To achieve exhibits basic instruction set and yields significant performance, technology better performance after comparison with advantages, better architecture and optimization microprocessor architecture and it has the in the compiler technology. As per this capacity to perform the instructions through technology, the machine performance can be microprocessor cycles per instruction. In this increased in proportion with the technology paper, the Cost-effective and efficient RISC enhancement which can be available for Processor is designed. The RISC Processor everyone. design includes Fetching, decoding, Data and The design of the processor is manufactures instruction memory, and Execution units. using semiconductor devices, the printed circuit The Execution unit contains ALU board (PCB), etc. The operation of any (Arthematic and Logical Unit) Operations. processor depends on the instructions used in it. The RISC Processor design is synthesized These instructions include the and implemented using Xilinx ISE Tool and computation/manipulation of the data values by simulated using Modelsim6.5f. The using the registers, changing/retrieve the values implementation is done by Artix-7 FPGA of the read/write memory, performing the device and the physically debugging of the relational test among the data values and to RISC Processor, and ALU Units are verified have the control over the program flow. using Chipscope pro tool. The performance The design of a processor considers the areas results are analyzed in terms of the Area like: (i) data paths like ‘Arithmetic Logic-Unit (Slices, LUT’s), Timing period, and (ALU) and pipelines’, (ii) a control unit which Maximum operating frequency. The helps in controlling the data paths, (iii) comparison of the RISC Processor is made considers the register files (memory components), (iv) clock circuits, (v) library of ISSN (PRINT): 2393-8374, (ONLINE): 2394-0697, VOLUME-6, ISSUE-6, 2019 DOI: 10.21276/ijcesr.2019.6.6.12 59 INTERNATIONAL JOURNAL OF CURRENT ENGINEERING AND SCIENTIFIC RESEARCH (IJCESR) logic gates for logic implementation and (vii) includes transceiver circuits is represented in The section 2 discuss about the existing figure 1. works of RISC Processor and ALU Designs and Problems finding. The section 3 explains about the proposed RISC Processor with detailed descriptions. The results and analysis of the Data Paths Control Units work is elaborated in section 4. Finally concludes the overall system with improvements with future work in section 5. Memory Clock II. RELATED WORKS Components Circuits The review of the existing work on RISC Processor architectures and ALU Units are described in below session. Library of Transceiver The implementation of field programmable Logic Gates Circuits gate array (FPGA) is successively has been done in 8-bite Reduced instruction set Gal et al. discussed computer (RISC) [6]. The introduction of (FPGA) implementation and Figure.1 Design areas of processor working experience of the 8-bit microcontroller is to provide in this given work. The uses of a The processor's designs for high microcontroller are on a big demand in an performance demanding applications require the industrial application; the primary goal of the custom designs in above-stated items to get implementation in RISC is to decrease the power dissipation, frequency, etc., while for low number of instruction and produced a smaller performance demanding applications uses the and faster processor. less number of items. The RISC architecture deals with more Nowadays technologies are entered in precisely their trade-offs and interaction [1]. human beings dally life and demand for The working function of instructions in RISC is machine and computer technology is increased simple. Hence, the execution time required for day by day. For the full fill of demand Khazaee each installation can be minimized, and a et al. [7] have presented a Java programming number of cycles can be narrowed. The language as Java virtual machine (JVM), but the execution time for instruction can be divided given JVM is not enough capacity in speed or into machine cycles, machine processing, and storage. The problem of low speed and memory operation of instruction sets. The operation of overhead is carried out by Tomar et al. [8] in the instruction can be performed in a pipelined which discussed the working progress of RISC manner [2, 3]. with the connecting of the digital signal The pipelined process includes five different processor (DSP) it can perform effectively in stages, i.e., instruction fetching (IF), Instruction several operations. decoding (ID), execution (EX), memory Cernazanu et al. [9] have discussed the accessing (MA) and write back (WB). The possibility of generating an energy profile of overlapping of different instruction in a RISC by the implementation of FPGA. Energy pipelined manner. RISC performs its inherent is consumed by the following of group parallel execution which is responsible for instruction like memory access instruction, performance enhancement than CISC. The arithmetic and logic instruction (ALU), RISC aims to achieve execution of single cycle compare and move instruction; these are the per instruction, i.e., CPI = 1.0 with no more energy consumed instruction. The work of interruption where pipelining take place. The power consumption is carried out in the next selection of addressing modes and instruction in section by Murthy et al. [10] have focused on RISC can be performed and tailored on the the power consumption of the 32-bit RISC core basis of recently used instruction resulting in processor. For solving this more power significant execution of RISC pipeline [4, 5]. consumption problem a DLX (32-bit ISSN (PRINT): 2393-8374, (ONLINE): 2394-0697, VOLUME-6, ISSUE-6, 2019 DOI: 10.21276/ijcesr.2019.6.6.12 60 INTERNATIONAL JOURNAL OF CURRENT ENGINEERING AND SCIENTIFIC RESEARCH (IJCESR) architecture). Power consumption and power environments and lack optimizations. In order management work are continues in the next to verify the hardware designs with real-time segment, in which Kumar et al.[11] have data, it is difficult without using the simulation focused on the capability of dynamic power testbench. The Unit under Test (UUT) is the management and to maintain the consumption design module is incorporated in the testbench proposed a low power embedded system. The to verify the designs. But it lacks with development of 8-bit RISC processor is possible observability and controllability in real time. by the implementation of HDL on the board of FPGA. Jeemon et al. [12] have presented a Proposed Solution: pipeline RISC processor for the improvement of The proposed RISC Processor overcomes all the performance of the 8-bit RISC processor. the problems and improves processor The process of a bit is continued in a change performance. The processor Verification is done form of 32-bit, Singh et al. [13] have discussed quickly by using two intellectual property (IP) on the design of 32-bit re-configurable RISC cores. In that, the integrated logic Analyzer processor this processor is based on BETA (ILA) improves the observability, and virtual (lesson-by-lesson) instruction. The main reason input-output core (VIO) improves the behind the using of a 32-bit processor is that the controllability of the processor in real-time 32-bit processor is to provide flexibility and a verification. great extent to the developer. III. PROPOSED RISC PROCESSOR Work of the 32-bit processor is carried out This section describes about the proposed by Dennis et al. [14] have presented an RISC Processor and its working functionality. improvement of the fully synthesizable 32-bit The RISC Processor components have explained processor, and it is based on RISC-V. The an overview in the below section: primary goal behind this proposed technique is • Instruction Memory: It is the part of a to make a low cost embedded device and also control unit that stores the instructions and completed the verification and assembling, will be executed or decoded. testing all are at a limited cost. Rohit et al. [15] have presented a low power RISC processor • Instruction Fetch: It is loading with the using of stalling and forwarding of instruction or piece of data from memory process. A base of the architecture of the RISC into a CPU's register. All instructions must processor is based on million instruction per be fetched before they can be executed. second (MIPS) it is a non-interlocked pipeline • Instruction Decode: what the instruction has method. The work of Venkategowada et al. [16] to do, it has to be decoded. Part of the have concentrated on the plan of creating a decoding method fetches the input-operands. synthesized shared memory and QUAD-Core processor and put it on a working path to solve • Data Register: Data register is an array of the problem of processor verification, and processor-registers in a ‘CPU.' Modern multiprocessor interrupts management.
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