Design and Implementation of a Low-Power Low-Cost Digital

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Article Design and Implementation of a Low-Power ‡ Low-Cost Digital Current-Sink Electronic Load

1, , 1, 1, 2 2 Wei Jiang * † , Jieyun Wang †, Qianlong Wang †, Song Xu , Seiji Hashimoto and Zhong Liu 3

1 Department of Electrical Engineering, Yangzhou University, Yangzhou 225000, China 2 Division of Electronics and Informatics, Gunma University, Kiryu 376-8515, Japan 3 State Grid Yangzhou Power Supply Company, Yangzhou 225000, China * Correspondence: [email protected]; Tel.: +86-130-920-76085 Current address: No. 88 University Avenue, Yangzhou 225000, China. † This paper is an extended version of our paper published in the 2013 IEEE Power Electronics and Drive ‡ Systems Conference, Kitakyushu, Japan, 22–25 April 2013.

Received: 30 April 2019; Accepted: 4 July 2019; Published: 7 July 2019

Abstract: Electronic load (e-load) is essential equipment for power converter performance test, where a designated load profile is executed. Electronic load is usually implemented with the analog controller for fast tracking of the load profile reference. In this paper, a low-power low-cost electronic load is proposed. MOSFETs (metal-oxide-semiconductor field-effect transistors) are used as the power consumption devices, which are regulated to the active region as controlled current-sink. In order to achieve fast transient response using the low-cost digital signal controller (DSC) PWM peripherals, the interleaving PWM method is proposed to achieve active current ripple mitigation. To obtain the system open-loop gain for current-sink operation, an offline digital system identification method, followed by model reduction, is proposed by applying Pseudo-Random Binary Sequence (PRBS) excitation. Pole-zero cancelation method is used in the control system design and later implemented in a DSC. The prototype is built and tested, in which meaningful testing scenarios under constant current-sink mode, pulse current sink mode, and double line-frequency current mode are verified. The experimental results indicate that the proposed e-load can sink pre-programmed current profile with well-attenuated ripple for static and dynamic load testing, and is applicable to fully digitalized power testing equipment.

Keywords: electronic load; multi-phase; current mode; system identiﬁcation

1. Introduction and Objectives Electronic load (e-load) plays a key role in modern electronic systems, energy systems, and power distribution systems design ﬂow [1–4]. The e-load can sink power from the Unit Under Test (UUT) following the designated load pattern for power testing purposes [5–7]. The electric power generated by the UUT can be either sent back the grid or transferred to a dissipating load. There are two kinds of dissipative e-load, one is the switch-mode converter-based [8–10], which is shown in Figure1a. A switch-mode converter sinks power from the UUT by actively controlling the input port voltage or current proﬁles, the output of switching converter is connected a dummy load. This solution is widely available in nowadays market for medium and high power test; however, designing a tightly regulated switching converter is challenging, especially, for high-order power stages [8]; the switching noise and converter input impedance also introduce non-ideal conditions in the testing scenario hence complicate the testing condition [11].

Energies 2019, 12, 2611; doi:10.3390/en12132611 www.mdpi.com/journal/energies Energies 2019, 12, x FOR PEER REVIEW 2 of 13

loop response possible. However, power level of linear e-load is limited within kilo Watt range due to the concentrated heat spot issues of Silicon-based power devices. Therefore, the linear e-load are widely used in low-power converter testing. A linear and switch-mode combined solution is presented in [14], linear transistors are used to shape the transient response of the switch-mode e-load such that both power level and transient response can be achieved. Current-sink mode is widely used in the load test due to the fact that most of the available dc power supplies are designed for constant voltage regulation. A well-designed e-load can profile the static and dynamic characteristics of a power supply systems using the following basic testing methods. • Constant current-sink. This method can test the static performance of the power supply systems, such as power level and dc output impedance. • Pulsed/step current-sink. This test mode, UUT output voltage response is tested under step load current; the dynamic performance of the power supply systems can be evaluated by examining the voltage response. • Programmed current-sink. Programmed current sink can test the performance of the power Energies 2019 12 supply, , 2611 under nonlinear load excitation. This test mode is of increasing demand as the2 grid-tie of 14 inverters become more prevalent and introduce disturbances back into the dc systems.

(a) (b)

FigureFigure 1. Electronic 1. Electronic load load types types (a) switching (a) switching e-load e-load (b) linear(b) linear e-load. e-load

LinearThe power conventional dissipative approach e-load, asto shownelectronic in Figure load 1cob,ntrol with is field realized e ffect transistorby the analog (FET) circuits. generate The lessanalog-based voltage and currentcontrol ripplecan guarantee during operationprecise regulation [12,13]; theand input tracking characteristics of certain load of a FETprofiles, device, which althoughare generated nonlinear, by issignal close synthetization to a zero-order blocks. system The in smalldigital signal controller, domain, which which is capable makes of fast providing loop responseflexible possible. and advanced However, control power solution, level of linearis gaining e-load a islot limited of attentions within kilonowadays. Watt range The due fully to loaded the concentratedcontrol and heat communication spot issues of peripherals Silicon-based of powerthe DSC devices. can yield Therefore, very low the component-count. linear e-load are widelyHowever, usedin in electronic low-power load converter application, testing. digital A linear control and switch-modeis challenging; combined in order solution to drive is the presented MOSFET in[ 14device], linearinto transistors the active are region, used gate to shape charge the has transient to be co responsentrolled of based the switch-mode on the sampled e-load current such thatfeedback. both In powerorder level to andaccomplish transient the response same task can beas achieved.the analog controller, the digital values generated from the digitalCurrent-sink controller mode can isbe widely converted used to in the loadanalog test values due to using the fact digital-to-analog that most of the converter available (DAC), dc powerwhich supplies introduce are designed excessive for cost constant as well voltageas the sampling-and-hold regulation. A well-designed effect. This e-load effect can is undesirable profile the as staticit will and dynamicintroduce characteristics current/voltage of aripples power and supply act systemssimilarly using to a switching the following e-load. basic testing methods. In this paper, a linear electronic load using low-cost digital Pulse Width Modulation (PWM) Constant current-sink. This method can test the static performance of the power supply systems, • peripherals is proposed. Wide Safe Operation Area (SOA) MOSFETs are regulated into the active regionsuch asas power the current level and sink. dc The output interleaving impedance. PWM scheme is proposed for passive current ripple mitigation;Pulsed/step through current-sink. device This selection, test mode, driver UUT circ outputuit design voltage and response layout de issign, tested 4-phase under stepmultiplexed load • current-sinkcurrent; the is dynamic implemented performance with only of theone power feedback supply current systems sensor. can System be evaluated identification by examining method is proposedthe voltage to response.obtain the power stage model by supplying Pseudo-Random Binary Sequence (PRBS) excitationProgrammed under current-sink. close-loop. The Programmed improved design current is sinkimplemented can test thelater performance on with the identified of the power model. • Thesupply prototype under is nonlinear built and loadtested excitation. for a variety This of test current-sink mode is of modes increasing for verification demand as the the effectiveness grid-tie ofinverters the proposed become design. more prevalent and introduce disturbances back into the dc systems.

The conventional approach to electronic load control is realized by the analog circuits. The analog-based control can guarantee precise regulation and tracking of certain load proﬁles, which are generated by signal synthetization blocks. The digital controller, which is capable of providing ﬂexible and advanced control solution, is gaining a lot of attentions nowadays. The fully loaded control and communication peripherals of the DSC can yield very low component-count.

However, in electronic load application, digital control is challenging; in order to drive the MOSFET device into the active region, gate charge has to be controlled based on the sampled current feedback. In order to accomplish the same task as the analog controller, the digital values generated from the digital controller can be converted to the analog values using digital-to-analog converter (DAC), which introduce excessive cost as well as the sampling-and-hold effect. This effect is undesirable as it will introduce current/voltage ripples and act similarly to a switching e-load. In this paper, a linear electronic load using low-cost digital Pulse Width Modulation (PWM) peripherals is proposed. Wide Safe Operation Area (SOA) MOSFETs are regulated into the active region as the current sink. The interleaving PWM scheme is proposed for passive current ripple mitigation; through device selection, driver circuit design and layout design, 4-phase multiplexed current-sink is implemented with only one feedback current sensor. System identification method is proposed to obtain the power stage model by supplying Pseudo-Random Binary Sequence (PRBS) excitation under close-loop. The improved design is implemented later on with the identified model. The prototype is built and tested for a variety of current-sink modes for verification the effectiveness of the proposed design. Energies 2019, 12, x FOR PEER REVIEW 3 of 13

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2. Digital Electronic Load System Design

2.1. System Structure As per discussed in Section1, if the digital controller is used in the electronic load system, the DAC is required to convert the digital control values into analog form, which is not considered as optimal in terms of the conversion speed and the cost. Therefore, another option is explored in this research. PWM module is the common peripheral in off-the-shelf DSCs. PWM signal filtered by a low-pass filter will remain its average value. Therefore, it is viable and economical to use PWM signals to generate the gate voltage. However, attenuation effect of the filter is no way to be perfect, the gate voltage ripple will propagate to the load current and cause load current ripple. As can be found from the datasheet of a FET device, the input characteristics of the active region is nonlinear and concave in shape, which means that a small deviation from the desired gate voltage will incur a large swing of drain current. If the filtered PWM signal is used, a method of ripple mitigation has to be proposed in order to reduce the drain current ripple. The diagram of the proposed digital electronic load is shown in Figure2. The power stage of the e-load consists of 4 power MOSFET in parallel, which is individually driven by the filtered PWM signal. In order to mitigate the current ripple induced by the remained ac components in the filtered PWM signal, each PWM signal is 90◦ phase-shifted to each other. The four channels of drain current are multiplexed in time domain, resulting in smaller current ripple. For load current regulation, single current loop is designed without active power sharing among the MOSFET devices. The total drain current is measured, conditioned and converted to the digital form; the digital control routine compares the real time current value with the current reference profile, amplifies the error signal, and loads the PWM with new duty cycle values. A gate driver circuit is connected in order to amplify the gate signals to a compatible level for MOSFET gate driver; a low-pass filter is used to eliminate the PWM ripples and generate a dc voltage to drive the MOSFETs.

UUT

+ -

filter filter filter filter

DSC

ADC PWM

control

FigureFigure 2. 2. SySystemstem structure. 2.2. Power Devices and Drivers 2.2. Power Devices and Drivers Semiconductor device can be used as the power sink due to its fast response to control input. FieldSemiconductor eﬀect transistor device device can be can used be driven as the into power active sink region due byto its applying fast response proper gateto control voltages; input. Fieldwhile effect bipolar transistor transistor device devices can be can driven be driven into ac intotive linear region region by applying with proper proper base gate current voltages; injection. while bipolarIn thetransistor proposed devices design, can the be wide driven Safe Operationinto linear Area region (SOA) with MOSFET proper IXTH80N20Lbase current frominjection. IXYS isIn the used as the power sink device. The breakdown voltage of the device is 200 V and I is 80 A. proposed design, the wide Safe Operation Area (SOA) MOSFET IXTH80N20L from 25IXYS◦C is used as The drain-source voltage and drain current will be controlled such that the operation point of the load the power sink device. The breakdown voltage of the device is 200 V and I25 ℃ is 80 A. The locates in the SOA. drain-source voltage and drain current will be controlled such that the operation point of the load The power MOSFET has a positive temperature coeﬃcient (PTC), therefore, it is feasible to parallel locates in the SOA. multiple MOSFETs for high load current. Although switching at high frequency, there is no periodical chargeThe power and discharge MOSFET of MOSFEThas a positive gate capacitor temperature for full capacity,coefficient the (PTC), current ratingtherefore, of the it gate is feasible driver to parallel multiple MOSFETs for high load current. Although switching at high frequency, there is no periodical charge and discharge of MOSFET gate capacitor for full capacity, the current rating of the gate driver circuitry can be selected to a low value. The gate driver is implemented with discrete Energies 2019, 12, x FOR PEER REVIEW 4 of 13 Energies 2019, 12, 2611 4 of 14

Energies 2019, 12, x FOR PEER REVIEW 4 of 13 circuitry can be selected to a low value. The gate driver is implemented with discrete components as Energiesindicated 2019 in, 12 Figure, x FOR 3PEER. To REVIEW attenuate gate voltage ripple, a single-stage low pass filter (LPF) with 324 of kHz 13 cut-off frequency is applied to filter PWM voltage ac components. components as indicated in Figure 3. To attenuate gate voltage ripple, a single-stage low pass filter (LPF) with 32 kHz cut-off frequency is applied to filter PWM voltage ac components.

Figure 3. MOSFET gate drive. Figure 3. MOSFET gate drive. The dsPIC33FJ DSC is chosen for control system implementation, which includes six pairs ofThe complementary dsPIC33FJ DSC high-resolution is chosen for PWM control and 16system channels implementation, of 10-bit ADC. which The PWM includes signals six are pairs of complementarysynchronized in high-resolution 90◦ phase-shift as indicatedPWM and in Figure16 chan4. 200nels kHz of is selected10-bit ADC. as the switchingThe PWM frequency signals are synchronizedin order to achieve in 90° better phase dynamic-shift as performance. indicated Figurein Figure5 shows 4. the200 PWM kHz signalis selected propagation as the within switching frequencythe gate drivein order circuit to (GDC) achieve referring better to Figuredynamic3, the performance. GDC o ﬀers fast Figure ampliﬁcation 5 shows of the the DSC PWM signal, signal which can meet the design criterion. Figure6 shows the ac coupled MOSFET gate voltages, as can propagation within the gate drive circuit (GDC) referring to Figure 3, the GDC offers fast be clearly seen, the drive signals are multiplexed in time, which can contribute to drain current amplification of the DSC signal, which can meet the design criterion. Figure 6 shows the ac coupled ripple attenuation. MOSFET gate voltages, as can be clearly seen, the drive signals are multiplexed in time, which can contribute to drain current ripple attenuation. PWM-A

90° PWM-B

90° PWM-C

90° PWM-D

FigureFigure 4. 4. FFour-phaseour-phase interleaving interleaving PWM PWM signals. signals.

FigureFigure 5. Gate 5. Gate signal signal propagation propagation (CH1- (CH1- test test point point A voltage,voltage, CH2- CH2- test test point point B voltage,B voltage, CH4- CH4- test test pointpoint C voltage). C voltage). Energies 2019, 12, x FOR PEER REVIEW 5 of 13

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=+ VVBiv kI· (1) Figure 6. FFour-phaseour-phase signal (AC coupled). The output of the hall-effect sensor is conditioned by a first-order passive RC LPF for noise 2.3. Sensing and Conditioning suppression.2.3. Sensing and By Conditioning applying small signal perturbation, the transfer function of the transducer network can beA found wide bandwidth as (80 kHz) open loop hall-effect sensor is used in the design. The output voltage A wide bandwidth (80 kHz) open loop hall-effect sensor is used in the design. The output and input current relation is given in Equation (1), wherek VB is the sensor bias voltage and kiv is the voltage and input current relation is given inHs Equation()= (1),iv where VB is the sensor bias voltage and(2) kiv voltage to current ratio of the sensor. i + is the voltage to current ratio of the sensor. RCs 1 V = VB + kiv I (1) where the LPF is designed using a 100 Ω resistor=+ and· 1nF ceramic capacitor, and kiv = 66 mV/A VVBiv kI· (1) accordingThe output to the sensor of the data-sheet. hall-effect sensor is conditioned by a first-order passive RC LPF for noise suppression.The output By applyingof the hall-effect small signal sensor perturbation, is conditioned the transferby a first-order function ofpassive the transducer RC LPF for network noise can2.4.suppression. Model be found Identification By as applying and small Control sign Loopal perturbation, Design the transfer function of the transducer network kiv can be found as H (s) = (2) Although the device manufacturer hasi specifieRCs +d 1the static transfer characteristics of the whereMOSFET the device, LPF is the designed drain current using avaries 100 Ω withresistor device and ktemperature,iv 1nF ceramic gate capacitor, voltage andas wellk =as66 the mV load/A Hs()= iv (2) accordingcondition. toTherefore, the sensor static data-sheet. mapping of the gatei voltageRCs and+ 1 drain current is not possible for current sinking operation, the close loop control has to be implemented for the e-load to work under 2.4.current-mode.where Model the IdentificationLPF is designed and Control using Loopa 100 Design Ω resistor and 1nF ceramic capacitor, and kiv = 66 mV/A according to the sensor data-sheet. The control block diagram is shown in Figure 7. The Gid is the control-to-current transfer Although the device manufacturer has specified the static transfer characteristics of the MOSFET function of the power MOSFET, in this case, is the MOSFET input admittance. The Hi(s) is the small device,2.4. Model the Identification drain current and varies Control with Loop device Design temperature, gate voltage as well as the load condition. signal gain of the current transducer circuit. Ci(s) is the current controller. FM is the PWM Therefore, static mapping of the gate voltage and drain current is not possible for current sinking modulationAlthough gain the and device LPF converts manufacturer PWM signals has specifie into smoothedd the static gate biastransfer voltages. characteristics of the operation, the close loop control has to be implemented for the e-load to work under current-mode. MOSFETAn initial device, design the drain of the current current varies control with loop device in s-domain temperature, is carried gate out. voltage Firstly, as wellthe small as the signal load The control block diagram is shown in Figure7. The G id is the control-to-current transfer function gaincondition. of the Therefore, MOSFET staticGid is mappingobtained ofby the differentiating gate voltage theand input drain admittance current is not curve possible of the for MOSFET current of the power MOSFET, in this case, is the MOSFET input admittance. The Hi(s) is the small signal gain numericallysinking operation, at 75 °C the at 9close A. Then, loop acontrol PID contro has llerto [15]be implemented is used for reference for the trackinge-load to with work kp = under1, ki = of the current transducer circuit. Ci(s) is the current controller. FM is the PWM modulation gain and 200,current-mode. kd = 10−4, as shown in Figure 8, a cross-over frequency of 15 kHz and phase margin of 70° is LPF converts PWM signals into smoothed gate bias voltages. achievedThe incontrol the theoretical block diagram design isprocess. shown in Figure 7. The Gid is the control-to-current transfer function of the power MOSFET, in this case, is the MOSFET input admittance. The Hi(s) is the small Iref signal gain of the current transducer circuit. Ci(s) is the current controller. FM is the PWM modulation gain and LPF converts PWM signals into smoothed gate bias voltages. t ~ ~ An initial design of the current+ control loop in s-domaind is carriedi out. Firstly, the small signal Ci(s) FM LPF Gid gain of the MOSFET Gid is obtained- by differentiating the input admittance curve of the MOSFET numerically at 75 °C at 9 A. Then, a PID controller [15] is used for reference tracking with kp = 1, ki = Hi(s) 200, kd = 10−4, as shown in Figure 8, a cross-over frequency of 15 kHz and phase margin of 70° is achieved in the theoretical design process. Figure 7. CurreCurrentnt control loop.

An initial design of the current control loop in s-domain is carried out. Firstly, the small signal gain of the MOSFET Gid is obtained by diﬀerentiating the input admittance curve of the MOSFET numerically at 75 ◦C at 9 A. Then, a PID controller [15] is used for reference tracking with kp = 1, 4 ki = 200, kd = 10− , as shown in Figure8, a cross-over frequency of 15 kHz and phase margin of 70 ◦ is achieved in the theoretical design process. Energies 2019, 12, 2611 6 of 14 Energies 2019, 12, x FOR PEER REVIEW 6 of 13

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Figure 8. Frequency response of PID compensated open-loop transfer function. Figure 8. Frequency response of PID compensated open-loop transfer function. The bilinear transformation is applied to discretize the designed s-domain controller. The sampling Thefrequency bilinear is transformation set to 50 kHz and digitalis applied controller to updatesdiscretize at each the ADC designed interrupt routine.s-domain controller. The sampling frequencyFigure9 shows is set the to initial50 kHz experimental and digital results controller of a 4-phase updates e-load. at each As indicated ADC interrupt in Figure9 a,routine. µ Figureunder 9 PIDshows close-loop the initial control, experimental e-load can track results the current of a command4-phase (stepe-load. from As 4 Aindicated to 8 A) in 400in Figures 9a, with attenuated current ripple. However, oscillation occurs after the reference change, which indicates under PIDweak close-loop system stability. control, The e-load pulsed currentcan track sink the experiment current is command also conducted, (step in whichfrom the4 A e-load to 8 actsA) in 400μs with attenuatedas the periodic current current ripple. sink with However,∆ILoad = 4.48 oscill A foration transient occurs test purposes.after the Thereference test waveform change, in which indicatesFigure weak9b system shows e ﬀstability.ective tracking The ofpulsed pulsed current reference, sink the UUT experiment voltage is showingis also conducted, expected variation in which the e-load actsunder as pulsed the periodic load. However, current the sink waveform with showsΔILoad a = similar 4.48 mannerA for transient of oscillation test upon purposes. reference The test waveformchange, in Figure which is9b not shows desirable effective for the ﬁeld tracking test. of pulsed reference, the UUT voltage is showing expected variation under pulsed load. However, the waveform shows a similar manner of oscillation upon reference change, which is not desirable for the field test.

(a) (b)

FigureFigure 9. Test 9. Test results results with with PID PID controller ( a(a)) step step response response from from 4 A 4 to A 8 to A, 8 (b A,) 60 (b Hz) 60 pulse Hz currentpulse current sink sinkmode mode (10 (10 ms ms/div)./div).

TheThe parameters parameters of ofthe the PID PID controller controller is is adjusted adjusted in order toto eliminateeliminate the the oscillation; oscillation; further further test test resultsresults indicate indicate that that systemsystem response response becomes becomes more mo sluggishre sluggish as the steady as the state steady oscillation state is oscillation attenuated. is attenuated.Therefore, Therefore, a more precise a more plant precise model is plant required mode in orderl is required to improve in theorder system to performance.improve the system performance. The parameters of the PID controller is adjusted in order to eliminate the oscillation; further test Pseudo-Random Binary Sequence (PRBS) has wide power spectrum, which is suitable for the results indicate that system response becomes more sluggish as the steady state oscillation is model identification [16]. In this research, the 9th order PRBS with 5% of full duty cycle is used as the attenuated.excitation Therefore, signal as indicateda more inprecise Equation plant (3) model is required in order to improve the system performance. = +Δ  Pseudo-Random Binary Sequence (PRBS)un Unhas  wide usn· power  spectrum, which is suitable(3 )for the modelwhere identification U[n] is the [16]. output In thisof the research, current controllerthe 9th orde at nthr PRBS sampling with time, 5% of Δ ufull is the duty amplitude cycle is ofused the as the excitationPRBS signal signal, ass[n] indicated is the binary in Equationbit generated (3) by a 9th order PRBS generator with a period of 511. The data probe is placed at the input and output of the plant respectively as shown in Figure 10, = +Δ in which case are the gate voltage andun drain current Un  of usnMOSFET.·   The input and output data for (3) where U[n] is the output of the current controller at nth sampling time, Δu is the amplitude of the PRBS signal, s[n] is the binary bit generated by a 9th order PRBS generator with a period of 511. The data probe is placed at the input and output of the plant respectively as shown in Figure 10, in which case are the gate voltage and drain current of MOSFET. The input and output data for Energies 2019, 12, 2611 7 of 14

Pseudo-Random Binary Sequence (PRBS) has wide power spectrum, which is suitable for the model identiﬁcation [16]. In this research, the 9th order PRBS with 5% of full duty cycle is used as the excitation signal as indicated in Equation (3)

u[n] = U[n] + ∆u s[n] (3) · Energies 2019, 12, x FOR PEER REVIEW 7 of 13 where U[n] is the output of the current controller at nth sampling time, ∆u is the amplitude of the PRBS signal, s[n] is the binary bit generated by a 9th order PRBS generator with a period of 511. The data probe is placed at the input and output of the plant respectively as shown in Figure 10, Energies 2019, 12, x FOR PEER REVIEW 7 of 13 in which case are the gate voltage and drain current of MOSFET. The input and output data for system systemidentification identification is plotted is inplotted Figure in 11 Figure with actual11 with analog actual units. analog The units. coherence The coherence between thebetween input andthe inputoutput and signal output is plotted signal in is Figure plotted 12. in In orderFigure to 12 improve. In order the to coherence improve under the coherence desired system under cross-over desired systemfrequency, cross-over a 10th orderfrequency, decimation a 10th filterorder is decimation applied to filter the data. is applied As indicated to the data. in the As figure, indicated decimated in the figure,signal hasdecimated improved signal coherence has improved at the low coherence frequency at region the low below frequency 100 kHz region for linear below controller 100 kHz design, for linearwhich controller is sufficient design, for the which targeted is sufficient application. for the targeted application.

Iref ~ ~ PRBS d i t + + Iref Ci(s) FM LPF Gid - +

Hi(s)

FigureFigure 10. 10. PPlantlant identification identiﬁcation using using PRBS PRBS under under close-loop close-loop conditions. conditions.

Figure 11. Plant input and output signals for identification (AC coupled). Figure 11. Plant input and output signals for identification (AC coupled). Based on the ARX model, the system identification can be carried out by using the decimated input-output data. To decide the system model, the cross-validation method is introduced, in which case 29th order is selected. The bode plot of the 29th order model presents strong second order properties under the half of the switching frequency as shown in Figure 13. To facilitate the controller design, order reduction is performed using balanced realization method. The bode plot for the reduced order model is also presented in Figure 13, it can be observed that under 100 kHz, no significant Energies 2019, 12, x FOR PEER REVIEW 7 of 13

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variation exists between the high order and low order model. Therefore, the obtained 2nd order model can be used in the design. The transfer function of the plant can be found as in Equation (4)

2 2 s + 2ξnωns + ω G = k n (4) id 2 + + 2 s 2ξdωds ωd

where the parameters are listed in Table1. As the high frequency characteristics are of less interest in this design, further simpliﬁcation is performed by eliminating the second order s-domain polynomials 2 on the numerator, which results in a canonical second order system with a constant gain kωn on Energiesthe 2019 numerator., 12, x FOR PEER REVIEW 8 of 13

significant variation exists between the high order and low order model. Therefore, the obtained 2nd order model can be used in the design. The transfer function of the plant can be found as in Equation (4)

ss22++2ξ ωω Gk= nn n (4) id 22++ξ ωω ss2 dd d

where the parameters are listed in Table 1. As the high frequency characteristics are of less interest in this design, further simplification is performed by eliminating the second order s-domain polynomials on the numerator, which results in a canonical second order system with a constant 2 gain kωn on the numerator. In order to validate the identified model, the comparison between the experimental signal and the identified model with the PRBS excitation, which is not used for identification, is carried out. Figure 14 shows good agreement between simulation results with the identified model and the experimental data. Figure 12. Coherence plot between system input and output signal. Figure 12. Coherence plot between system input and output signal.

Based on the ARX model, the system identification can be carried out by using the decimated input-output data. To decide the system model, the cross-validation method is introduced, in which case 29th order is selected. The bode plot of the 29th order model presents strong second order properties under the half of the switching frequency as shown in Figure 13. To facilitate the controller design, order reduction is performed using balanced realization method. The bode plot for the reduced order model is also presented in Figure 13, it can be observed that under 100 kHz, no

FigureFigure 13. 13. IdIdentifiedentified model bode bode plots. plots. Table 1. Parameters of the plant model. Table 1. Parameters of the plant model. K ξn ξd ωn ωd 0.56K 0.4ξn ξd 0.22 ω1.1n 106 ωd 1.8 105 × × 0.56 0.4 0.22 1.1 × 106 1.8 × 105 In order to validate the identified model, the comparison between the experimental signal and the identifiedZero-pole model cancelation with the PRBSmethod excitation, is used which in isth note usedcurrent for identification,mode control is carried system out. design; Figure 14a 4th controllershows is good proposed agreement in Equation between simulation (5), where results k is the with static the identified gain, the model first 2nd and order the experimental polynomial data. cancel the plant dynamics, the second 2nd order polynomial with double zero ωz1 cancel the poles of redesigned two stage LPF before the MOSFET gate, a pole at zero provide zero steady state error while the other three poles locating at 100 kHz provide switching ripple attenuation.

2 ks()22ωξω+++211 s() s ω = ddd z1 Cs() (5) ()+ ω 3 ss1 p

With the proposed controller, the compensated open-loop transfer function can be obtained. The bode plot of the transfer function is shown in Figure 15; the crossover frequency is 15.4 kHz with phase of 57°. Energies 2019, 12, 2611 9 of 14 Energies 2019, 12, x FOR PEER REVIEW 9 of 13

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FigureFigure 14. 14. SimSimulationulation results results and and experimental data data comparison. comparison. Zero-pole cancelation method is used in the current mode control system design; a 4th controller is proposed in Equation (5), where k is the static gain, the ﬁrst 2nd order polynomial cancel the plant dynamics, the second 2nd order polynomial with double zero ωz1 cancel the poles of redesigned two stage LPF before the MOSFET gate, a pole at zero provide zero steady state error while the other three poles locating at 100 kHz provide switching ripple attenuation. 2 2 + + ( + )2 k s /ωd 2ξds/ωd 1 1 s/ωz1 C(s) = (5) 3 s 1 + s/ωp

Figure 15. Simulation results and experimental data comparison. Figure 15. Simulation results and experimental data comparison.

3. Experimental Results and Analysis A 50 W 4-phase e-load prototype is built as shown in Figure 16, the micro-controller dsPIC33FJ64GS606 with high resolution PWM peripheral is used. In order to prevent the thermal runaway due to possible uneven power sharing, the MOSFET batch, the drivers’ parameters and the PCB layout have been carefully selected, designed and finally verified based on the power device case temperature differences. The UUT is a linear bench power supply with 30 V 10 A capability. The experimental verification is carried out for current (sink) mode, in which the UUT is supplying a variable dc voltage and the proposed e-load sinks current in a programmed manner. The test is conducted under a maximum sink current of 9 A under a variable UUT output voltage around 5 V. Energies 2019, 12, x FOR PEER REVIEW 9 of 13

Energies 2019, 12, 2611 10 of 14

3. Experimental Results and Analysis A 50 W 4-phase e-load prototype is built as shown in Figure 16, the micro-controller dsPIC33FJ64GS606 with high resolution PWM peripheral is used. In order to prevent the thermal runaway due to possible uneven power sharing, the MOSFET batch, the drivers’ parameters and the PCB layout have been carefully selected, designed and finally verified based on the power device case temperature differences. The UUT is a linear bench power supply with 30 V 10 A capability. The experimental verification is carried out for current (sink) mode, in which the UUT is supplying a variable dc voltage and the proposed e-load sinks current in a programmed manner. The test is conducted under a maximum sink current of 9 A under a variable UUT output voltage around 5 V.

Energies 2019, 12, x FOR PEER REVIEW 10 of 13 Figure 16. Figure 16. LowLow-power-power electronic load load test test bed. bed. Figure Figure17 shows 17 shows the thewaveforms waveforms of thethe 4-phase 4-phase PWM PWM (AC coupled)(AC coupled) signals ﬁlteredsignals by filtered an improved by an improved double-stage LPF; one can easily find that voltage ripple is reduced from 450 mVpp to 100 double-stage LPF; one can easily ﬁnd that voltage ripple is reduced from 450 mVpp to 100 mVpp. mVpp.

FigureFigure 17. 17. 4 M4 MOSFETOSFET gate gate voltages voltages (AC coupledcoupled 100 100 mV, mV, 1 µ 1s /μdiv).s/div) The steady state test waveforms for constant current sink mode are presented in Figure 18a for The10% steady load (1 state A) and test Figure waveforms 18b for 100% for constant load (9 A); curr as shownent sink in themode ﬁgure, are the presented load current in Figure ripple is 18a well for 10% load (1 A) and Figure 18b for 100% load (9 A); as shown in the figure, the load current ripple is attenuated and load current ILoad can be controlled at the desired level, which indicates that the e-load well attenuatedcan perform and static load test current without ILoad introducing can be controlled excessive loadat the disturbances. desired level, The which case temperature indicates that of the the e-load canMOSFET perform is measured static test with without infrared introducing devices, which excessive shows tolerableload disturbances. temperature The diﬀ erencecase temperature with 1 ◦C. of the MOSFET is measured with infrared devices, which shows tolerable temperature difference with 1 °C.

Figure 19 shows the constant current sink mode (ILoad = 6.5 A) regulation when input source voltage (VLoad) is undergoing a large swing. It can be observed from the figure that the load current keeps constant with random input voltage variations. Energies 2019, 12, x FOR PEER REVIEW 10 of 13

Figure 17 shows the waveforms of the 4-phase PWM (AC coupled) signals filtered by an improved double-stage LPF; one can easily find that voltage ripple is reduced from 450 mVpp to 100 mVpp.

Energies 2019, 12, 2611 11 of 14

(a)

(b)

Figure 18. Constant current sink test (a) 10% load current (1 ms/div), (b) 100% load current (1 Figure 18. Constant current sink test (a) 10% load current (1 ms/div), (b) 100% load current (1 ms/div). ms/div).

Figure 19 shows the constant current sink mode (ILoad = 6.5 A) regulation when input source Figure 19 shows the constant current sink mode (ILoad = 6.5 A) regulation when input source voltage (VLoad) is undergoing a large swing. It can be observed from the ﬁgure that the load current voltage (VLoad) is undergoing a large swing. It can be observed from the figure that the load current keeps constant with random input voltage variations. Energieskeeps 2019 ,constant 12, x FOR with PEER random REVIEW input voltage variations. 11 of 13

Figure 19. ConstantConstant current current sink with inpu inputt voltage variat variationion (2 s/div). s/div). Figure 20 shows the pulse current sink test results, where a pre-programmed pulse current proﬁle Figure 20 shows the pulse current sink test results, where a pre-programmed pulse current is set up in the micro-controller. This mode of operation emulates the conditions of the intermittent profile is set up in the micro-controller. This mode of operation emulates the conditions of the load. As can be seen from Figure 20a, the load current ILoad is pulsating from 10% to full load with intermittent load. As can be seen from Figure 20a, the load current ILoad is pulsating from 10% to full a frequency of 50 Hz. Comparing to the previous results, the oscillation during the steady state is load with a frequency of 50 Hz. Comparing to the previous results, the oscillation during the steady eliminated due to more precise modeling of the plant. The output voltage of UUT (VLoad) is showing state is eliminated due to more precise modeling of the plant. The output voltage of UUT (VLoad) is periodical voltage variation due to its output impedance, which indicates that the regulation speed of showing periodical voltage variation due to its output impedance, which indicates that the the UUT could not follow the load variation. 500 Hz pulse current load is also tested, the waveform is regulation speed of the UUT could not follow the load variation. 500 Hz pulse current load is also presented in Figure 20b. The rising edge of the pulse current is shown in Figure 20c. With the designed tested, the waveform is presented in Figure 20b. The rising edge of the pulse current is shown in digital control loop, 123 µs of rise time is achieved, the load current overshoot is limited to 1%, which is Figure 20c. With the designed digital control loop, 123 μs of rise time is achieved, the load current suﬃcient for most of the linear power supply tests. A commercial bench-mark electronic load (BK8500) overshoot is limited to 1%, which is sufficient for most of the linear power supply tests. A is also tested in the mean time for the same operation condition, the rise time is found to be 1.6 ms. commercial bench-mark electronic load (BK8500) is also tested in the mean time for the same The proposed digital e-load is found to have a much faster response. operation condition, the rise time is found to be 1.6 ms. The proposed digital e-load is found to have Finally, the nonlinear load condition is emulated. The well-known 100 Hz ripple injection scenario a much faster response. from a single-phase grid-tie inverter load is emulated. Under the assumption that the UUT has a large Finally, the nonlinear load condition is emulated. The well-known 100 Hz ripple injection scenario from a single-phase grid-tie inverter load is emulated. Under the assumption that the UUT has a large output dc capacitor, a 100 Hz rectified sinusoidal current is drawn from the UUT. Figure 21 shows this testing scenario when the load current (ILoadRMS = 3.4 A) is of rectified sinusoidal shape. As expected, the UUT terminal voltage presents a disturbed dc voltage with 100 Hz ripple component. Energies 2019, 12, x FOR PEER REVIEW 11 of 13

Energies 2019, 12, 2611 12 of 14 output dc capacitor, a 100 Hz rectiﬁed sinusoidal current is drawn from the UUT. Figure 21 shows this testing scenario when the load current (ILoadRMS = 3.4 A) is of rectiﬁed sinusoidal shape. As expected, the UUT terminal voltage presents a disturbed dc voltage with 100 Hz ripple component.

(a)

EnergiesEnergies 2019 2019, 12, ,12 x , FORx FOR PEER PEER REVIEW REVIEW (b) 12 12of 13of 13

(c ) Figure 20. Pulse current sink mode (a) 50 Hz pulse current test (10 ms/div), (b) 500 Hz pulse current Figure 20. Pulse current sink mode (a) 50 Hz pulse current test (10 ms/div), (b) 500 Hz pulse current test (2 ms/div), (c) step response (200 μs/div). test (2 ms/div), (c) step response (200 µs/div).

Figure 21. 100100 Hz Hz inverter inverter loa loadd current emulation test (10 ms/div). ms/div).

4. Conclusions In this paper, a linear electronic load using digital pulse width modulation is proposed. To solve the high current ripple problem in a digital PWM system, a multi-phase and double-stage LPF scheme is used. Low-cost single current loop without additional active power sharing is designed. System identification methods based on PRBS excitation is applied to obtain the power stage model, which is later verified by simulation results. The control system is designed using pole-zero cancelation technique and implemented in a digital signal controller. The experimental results on constant current sink mode, pulse current sink mode, and inverter current sink mode show satisfactory steady state performance and stable transient response. The proposed system can achieve commensurate performance with benchmark e-load under current sink mode, which indicates its potential for the fully digitalized power testing equipment in the near future.

Author Contributions: conceptualization, W.J.; methodology, W.J. and S.H.; software, W.J. and S.H.; validation, W.J., J.W. and S.X.; formal analysis, W.J.; investigation, J.W.; resources, Q.W.; data curation, J.W.; writing—original draft preparation, W.J.; writing—review and editing, Q.W. and Z.L.; visualization, W.J.; supervision, W.J.; project administration, W.J.; funding acquisition, W.J. and Z.L.

Funding: This research was jointly supported by National Natural Science Foundation of China (Grant No. 31571765), Natural Science Foundation of Jiangsu Province, China (Grant No. BK20170503) and Yangzhou City-Yangzhou University joint Grant (No. SCX2017020021)

Acknowledgments: The conference version of this paper is published in the IEEE PEDS 2013, titled “Digitally controlled multi-phase electronic current sink” coauthored by W.J., S.W., S.K., L.X., S. H. However, in the fully extended journal version, we report on the methodology of designing a fast and low-cost electronic load using improved digital modulation, model identification, and control.

Conflict of interest: The authors declare no conflict of interest.

References Energies 2019, 12, 2611 13 of 14

4. Conclusions In this paper, a linear electronic load using digital pulse width modulation is proposed. To solve the high current ripple problem in a digital PWM system, a multi-phase and double-stage LPF scheme is used. Low-cost single current loop without additional active power sharing is designed. System identiﬁcation methods based on PRBS excitation is applied to obtain the power stage model, which is later veriﬁed by simulation results. The control system is designed using pole-zero cancelation technique and implemented in a digital signal controller. The experimental results on constant current sink mode, pulse current sink mode, and inverter current sink mode show satisfactory steady state performance and stable transient response. The proposed system can achieve commensurate performance with benchmark e-load under current sink mode, which indicates its potential for the fully digitalized power testing equipment in the near future.

Author Contributions: Conceptualization, W.J.; methodology, W.J. and S.H.; software, W.J. and S.H.; validation, W.J., J.W. and S.X.; formal analysis, W.J.; investigation, J.W.; resources, Q.W.; data curation, J.W.; writing—original draft preparation, W.J.; writing—review and editing, Q.W. and Z.L.; visualization, W.J.; supervision, W.J.; project administration, W.J.; funding acquisition, W.J. and Z.L. Funding: This research was jointly supported by National Natural Science Foundation of China (Grant No. 31571765), Natural Science Foundation of Jiangsu Province, China (Grant No. BK20170503) and Yangzhou City-Yangzhou University joint Grant (No. SCX2017020021) Acknowledgments: The conference version of this paper is published in the IEEE PEDS 2013, titled “Digitally controlled multi-phase electronic current sink” coauthored by W.J., S.W., S.K., L.X., S.H. However, in the fully extended journal version, we report on the methodology of designing a fast and low-cost electronic load using improved digital modulation, model identification, and control. Conflicts of Interest: The authors declare no conflict of interest.

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