Instruction Set Architecture

Instruction Set Architecture • Specification of a microprocessor design ECE473 Computer Architecture and • Interface between human and machine’s functionality Organization HLL Front-end compiler Instruction Set Architecture IR Exposed to software Backend compiler (e.g. code generator, scheduler, IR optimizer) ISA Lecturer: Prof. Yifeng Zhu Binary execution, Transparent microarchitecture, to software Fall, 2007 dynamic optimizer HW Packaging, cooling Portions of these slides are derived from: ECE473 1 ECE473 2 Dave Patterson © UCB Instruction Set Architecture ISA State • What states are there? – User-level • Defines what state exists » Registers • General purpose • Defines what operations exist on that state • Program counter (PC) • Memory • Addressing/Indexing • Typically implies a sequential ordering – Other – Classic serial fetch-execute (von Neuman) » Virtual memory support (TLB, page descriptors, …) » Kernel (special registers, memory) » I/O ECE473 3 ECE473 4 Operand Locations in Four ISA Classes Manipulating the State GPR • Must have instructions that – Access state (read and write) – Implement control flow (jump, branch, etc.) – Perform ALU operations (add, multiply, etc.) • Largest difference among instructions is in how you access your state – Operand location » stack, memory, register – Addressing modes » computing the location (addresses) of the state ECE473 5 ECE473 6 Code Sequence C = A + B for Four Instruction Sets CISC vs. RISC (1970s – 80s) Stack Accumulator Register Register (load- CISC RISC (register-memory) store) Push A Load A Load R1, A Load R1,A IBM VAX Xerox IBM Berkeley Stanford Push B Add B Add R1, B Load R2, B 370/168 11/780 Dorado 801 RISC1 MIPS Year 1973 1978 1978 1980 1981 1983 Add Store C Store C, R1 Add R3, R1, R2 introduced Pop C Store C, R3 # 208 303 270 120 39 55 instructions Microcode 54KB 61KB 17KB 0 0 0 Instruction 2 to 6 B 2 to 57 B 1 to 3 B 4B 4B 4B size Execution Reg-reg Reg-reg Stack Reg-reg Reg-reg Reg-reg model Reg-mem Reg-mem Mem-mem Mem- mem memory memory Source: Andy Tanenbaum’s Structured Computer Organization 7 8 ECE473 acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2 ECE473 From CISC to RISC IA32 (x86) Processor Design Defined by Colwell et al. 85 • For CISC to weed out misleadings – Memory are expensive and CISC RISC slow back then • Intel P6/Netburst or AMD Athlon – Reduce Semantic Gap by Variable length instructions Fixed-length instructions, single- Cramming more functions cycle operation – CISCy skin (x86 ISA) into one instruction – Using microcode ROM Abundant instructions and Fewer instructions and – RISCy heart (μROM) for “complex” addressing modes addressing modes operations » Each x86 instruction is translated into “micro-op”(μop) or “MacroOP” or “RISC-op” on-the-fly • Justification for RISC Longer decoding Easier decoding » Internal microarchitecture resembles RISC design – Complex apps are mostly Contain mem-to-mem Load/store architecture composed of simple operations philosophy assignments Use on-core microcode No microinstructions, directly » Processor dynamically reschedule based on μops – RAM speed catching up executed by HW logic – Compiler (human) getting smarter and sophisticated Closer semantic gap (shift Needs smart compilers, more – Frequency↑⇒ shorter pipe complexity to microcode) compiler effort stages, more pipelineable IBM 360, DEC VAX, Intel IA32, IBM 801, MIPS, RISC I, IBM Mot 68030 RS6000, Sun Sparc ECE473 9 ECE473 10 64-bit Extensions to IA32 X86 is a big stack of cruft… But it gets the job done! CPU architect IA32+64-bit exts IA32 (Taken from Bob Colwell’s Eckert-Mauchly Award Talk, ISCA 2005) ECE473 11.

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