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Lecture 09: RISC-V Pipeline Implementa8on

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Lecture 09: RISC-V Pipeline Implementa8on Lecture 09: RISC-V Pipeline Implementa8on CSE 564 Computer Architecture Summer 2017 Department of Computer Science and Engineering Yonghong Yan [email protected] www.secs.oakland.edu/~yan 1 Acknowledgement • Slides adapted from Computer Science 152: Computer Architecture and Engineering, Spring 2016 by Dr. George Michelogiannakis from UC Berkeley 2 Introduc8on • CPU performance factors – InstrucNon count • Determined by ISA and compiler Instructions Cycles Time – CPI and Cycle Nme CPU Time = * * Program Instruction Cycle • Determined by CPU hardware • Three groups of instrucNons – Memory reference: lw, sw – ArithmeNc/logical: add, sub, and, or, slt – Control transfer: jal, jalr, b* • CPI – Single-cycle, CPI = 1 – 5 stage unpipelined, CPI = 5 – 5 stage pipelined, CPI = 1 An Ideal Pipeline stage stage stage stage 1 2 3 4 • All objects go through the same stages • No sharing of resources between any two stages • PropagaNon delay through all pipeline stages is equal • The scheduling of an object entering the pipeline is not affected by the objects in other stages These condi+ons generally hold for industrial assembly lines, but instruc+ons depend on each other! 4 Review: Unpipelined Datapath for RISC-V PCSel br RegWriteEn MemWrite WBSel rind jabs pc+4 0x4 Add Add clk we Br Logic Bcomp? rs1 clk rs2 PC addr rd1 we inst wa addr wd rd2 ALU clk Inst. GPRs rdata Memory Data Imm Memory Select wdata ALU Control OpCode WASel ImmSel Op2Sel 5 Review: Hardwired Control Table Opcode ImmSel Op2Sel FuncSel MemWr RFWen WBSel WASel PCSel ALU * Reg Func no yes ALU rd pc+4 ALUi IType12 Imm Op no yes ALU rd pc+4 LW IType12 Imm + no yes Mem rd pc+4 SW BsType12 Imm + yes no * * pc+4 BEQ true BrType12 * * no no * * br BEQfalse BrType12 * * no no * * pc+4 JAL * * * yes PC rd jabs JALR * * * no no yes PC rd rind Op2Sel= Reg / Imm WBSel = ALU / Mem / PC PCSel = pc+4 / br / rind / jabs 6 Pipelined Datapath 0x4 Add we rs1 rs2 PC addr rd1 we rdata IR wa addr wd rd2 ALU GPRs rdata Inst. Data Imm Memory Memory Select wdata write fetch decode & Reg-fetch execute memory -back phase phase phase phase phase Clock period can be reduced by dividing the eXecuNon of an instrucNon into mulNple cycles tC > max {tIM, tRF, tALU, tDM, tRW} ( = tDM probably) However, CPI will increase unless instruc+ons are pipelined 7 Technology Assump8ons • A small amount of very fast memory (caches) backed up by a large, slower memory • Fast ALU (at least for integers) • MulNported Register files (slower!) Thus, the following Nming assumpNon is reasonable tIM ~= tRF ~= tALU ~= tDM ~= tRW A 5-stage pipeline will be focus of our detailed design - some commercial designs have over 30 pipeline stages to do an integer add! 8 5-Stage Pipelined Execu8on 0x4 Add we rs1 rs2 PC addr rd1 we rdata IR wa addr wd rd2 ALU GPRs rdata Inst. Data Imm Memory Memory Select wdata Write -Back I-Fetch Decode, Reg. Fetch Execute Memory (WB) (IF) (ID) (EX) (MA) +me t0 t1 t2 t3 t4 t5 t6 t7 . instrucNon1 IF1 ID1 EX1 MA1 WB1 instrucNon2 IF2 ID2 EX2 MA2 WB2 instrucNon3 IF3 ID3 EX3 MA3 WB3 instrucNon4 IF4 ID4 EX4 MA4 WB4 instrucNon5 IF5 ID5 EX5 MA5 WB5 9 5-Stage Pipelined Execu8on Resource Usage Diagram 0x4 Add we rs1 rs2 PC addr rd1 we rdata IR wa addr wd rd2 ALU GPRs rdata Inst. Imm Data Select Memory Memory wdata Write -Back I-Fetch Decode, Reg. Fetch Execute Memory (WB) (IF) (ID) (EX) (MA) +me t0 t1 t2 t3 t4 t5 t6 t7 . IF I1 I2 I3 I4 I5 ID I1 I2 I3 I4 I5 EX I1 I2 I3 I4 I5 Resources MA I1 I2 I3 I4 I5 WB I1 I2 I3 I4 I5 10 Pipelined Execu8on: ALU Instruc8ons 0x4 IR Add IR IR we rs1 rs2 A PC addr rd1 we inst IR wa ALU addr wd rd2 Y Inst GPRs B rdata Memory Data R Imm Memory Select wdata MD1 MD2 Not quite correct! We need an Instruc+on Reg (IR) for each stage 11 Pipelined RISC-V Datapath without jumps F D E M W IR IR IR 0x4 Add RegWriteEn we ALU MemWrite rs1 Control WBSel rs2 A PC addr rd1 we inst IR wa ALU addr wd rd2 Y Inst GPRs B rdata Data Memory Imm R wdata Memory Select wdata MD1 MD2 ImmSel Op2Sel Control Points Need to Be Connected 12 Instruc8ons interact with each other in pipeline • An instrucNon in the pipeline may need a resource being used by another instrucNon in the pipeline à structural hazard • An instrucNon may depend on something produced by an earlier instrucNon – Dependence may be for a data value à data hazard – Dependence may be for the neXt instrucNon’s address à control hazard (branches, excep+ons) 13 Resolving Structural Hazards • Structural hazard occurs when two instrucNons need same hardware resource at same Nme – Can resolve in hardware by stalling newer instrucNon Nll older instrucNon finished with resource • A structural hazard can always be avoided by adding more hardware to design – E.g., if two instrucNons both need a port to memory at same Nme, could avoid hazard by adding second port to memory • Our 5-stage pipeline has no structural hazards by design – Thanks to RISC-V ISA, which was designed for pipelining 14 Data Hazards x4 ← x1 … x1 ← … 0x4 Add IR IR IR we rs1 rs2 A PC addr rd1 we inst IR wa ALU Y addr wd rd2 Inst GPRs B rdata Memory Data Imm Memory R Select wdata MD1 MD2 ... x1 ← x0 + 10 x4 ← x1 + 17 x1 is stale. Oops! ... 15 How Would You Resolve This? • Three opNons – Wait (stall) – Bypass: ask them for what you need before his/her final deliverable – Speculate on values to read 16 Resolving Data Hazards (1) Strategy 1: Wait for the result to be available by freezing earlier pipeline stages è interlocks 17 Interlocks to resolve Data Hazards Stall Condition 0x4 bubble IR IR IR Add we rs1 rs2 A PC addr rd1 we inst IR wa ALU Y addr wd rd2 Inst GPRs B rdata Memory Data Imm Memory R wdata ... Select wdata MD1 MD2 x1 ← x0 + 10 x4 ← x1 + 17 ... 18 Stalled Stages and Pipeline Bubbles time t0 t1 t2 t3 t4 t5 t6 t7 . (I1) x1 ← (x0) + 10 IF1 ID1 EX1 MA1 WB1 (I2) x4 ← (x1) + 17 IF2 ID2 ID2 ID2 ID2 EX2 MA2 WB2 (I3) IF3 IF3 IF3 IF3 ID3 EX3 MA3 WB3 (I4) stalled stages IF4 ID4 EX4 MA4 WB4 (I5) IF5 ID5 EX5 MA5 WB5 time t0 t1 t2 t3 t4 t5 t6 t7 . IF I1 I2 I3 I3 I3 I3 I4 I5 ID I I I I I I I I Resource 1 2 2 2 2 3 4 5 EX I - - - I I I I Usage 1 2 3 4 5 MA I1 - - - I2 I3 I4 I5 WB I1 - - - I2 I3 I4 I5 - ⇒ pipeline bubble 19 Interlock Control Logic stall ws Cstall rs2 ? rs1 0x4 bubble Add IR IR IR we rs1 rs2 A PC addr rd1 we inst IR wa ALU Y addr wd rd2 Inst GPRs B rdata Memory Data Imm Memory R Select wdata MD1 MD2 Compare the source registers of the instruction in the decode stage with the destination register of the uncommitted instructions. 20 we: write enable, 1-bit on/off ws: write select, 5-bit register number Interlock Control Logic re: read enable, 1-bit on/off ignoring jumps & branches rs: read select, 5-bit register number wsW stall weW Cstall rs1 ? weM wsM rs2 weE wsE re1 re2 Cdest Cdest C 0x4 re bubble IR Add IR IR we rs1 rs2 A PC addr rd1 we inst IR wa ALU addr wd rd2 Y Inst GPRs B rdata Memory Data Imm R wdata Memory Select wdata MD1 MD2 Should we always stall if an rs field matches some rd? not every instrucNon writes a register => we not every instrucNon reads a register => re 21 In RISC-V Sodor Implementa8on 22 Source & Des8na8on Registers func7 rs2 rs1 func3 rd opcode ALU immediate12 rs1 func3 rd opcode ALUI/LW/JALR imm rs2 rs1 func3 imm opcode SW/Bcond Jump Offset[19:0] rd opcode source(s) des+na+on ALU rd <= rs1 func10 rs2 rs1, rs2 rd ALUI rd <= rs1 op imm rs1 rd LW rd <= M [rs1 + imm] rs1 rd SW M [rs1 + imm] <= rs2 rs1, rs2 - Bcond rs1,rs2 rs1, rs2 - true: PC <= PC + imm false: PC <= PC + 4 JAL X1 <= PC, PC <= PC + imm - rd JALR rd <= PC, PC <= rs1 + imm rs1 rd 23 Deriving the Stall Signal C Cdest re ws = rd re1 = Case opcode ALU, ALUi, we = Case opcode LW, SW, Bcond, ALU, ALUi, LW, JALR =>on JALR =>on ... =>off JAL =>off re2 = Case opcode ALU, SW, =>on Bcond ... ->off Cstall stall = ((rs1D == wsE) && weE + (rs1D == wsM) && weM + (rs1D == wsW) && weW) && re1D + ((rs2D == wsE) && weE + (rs2D == wsM) && weM + (rs2D == wsW) && weW) && re2D 24 Hazards due to Loads & Stores Stall Condi+on What if X1+7 = X3+5 ? 0x4 bubble IR Add IR IR we rs1 rs2 A PC addr rd1 we inst IR wa ALU addr wd rd2 Y Inst GPRs B rdata Memory Data Imm R wdata Memory Select wdata MD1 MD2 ... M[X1+7] <= X2 Is there any possible data hazard X4 <= M[X3+5] in this instruc+on sequence? ... 25 Load & Store Hazards ... M[X1+7] <= X2 X1+7 = X3+5 => data hazard X4 <= M[X3+5] ... However, the hazard is avoided because our memory system completes writes in one cycle ! Load/Store hazards are someNmes resolved in the pipeline and someNmes in the memory system itself.
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