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Characterization of On-Chip Interconnections and Capacitive Characterization of On-chip Interconnections and Capacitive Coupling Effect on CMOS Operational Amplifier Yujeong Shim, Junso Pak, Andrew Kim and Joungho Kim Terahertz Interconnection and Package Lab., School of EECS, Korea Advanced Institute of Science and Technology, 373-1 Guseong, Yuseong, Daejeon 305-701, South Korea [email protected] Abstract— The operational amplifier is one of the most capacitive coupling effects on the DC output voltage offset of important circuits to compose ADCs, DACs and active filters. the OpAmp in order to ensure reliable operation and the Now, there are many papers which deal with noise characters of associated analog blocks. op amps. Most of them are focused on the input signal noises which flow into circuits without account about noise source. In this paper, we study the capacitive effect on the Capacitive coupling is one of the most frequent sources of signal OpAmp. In order to model the effect, characterization of on- noise. The capacitive coupling is inevitable because of high chip interconnection and coupling mechanism between lines integration. This paper investigates mechanism of input noises are deemed. Therefore, we propose the scalable models to flowing into the op amp and effects of capacitive coupling on the characterize on-chip interconnections. By combining the op amp as on-chip interconnection modeling and analytical scalable models of on-chip interconnections and the analytical model of the DC output offset voltage of the OPamp are model of the OpAmp, we can realize the capacitive effect on proposed. Furthermore, the models are verified by experimental the OpAmp. And then, the DC output offset voltage is derived measurement. when the digital signal is assigned to the close signal line. I. INTRODUCTION In order to validate the proposed hybrid model, we have Recently, CMOS technology is continuously scaled down designed and fabricated a CMOS negative feedback OpAmp and more and more devices are highly integrated in a chip [1]. chip, and have mounted it on a package substrate with wire- And as operational frequency increases, various noises are bonding interconnections. The OpAmp chip was fabricated generated and couples to circuits. On chip, coupling is one of using a TSMC 0.25 um CMOS process, and the OpAmp chip the most common reasons making a signal worsen. And as and package were assembled using a COB technology. We integration of circuit increases, coupling among then measured the capacitive coupling effect onto the DC interconnections is not avoidable. The on-chip coupling among output voltage offset of the CMOS OpAmp and compared the interconnections affects circuit performance and deteriorates measurement results with the estimations obtained using the signal integrity. The dominant coupling is capacitive on the suggested modeling approach. For the validation of the chip [2]. The capacitive coupling effects on delay time and proposed models, we have measured the DC output offset jitter performance of digital circuits. Furthermore, it adds voltage by sweeping the aggressor’s frequency from 10MHz noises on the signal lines and then, deteriorates output of the up to 3GHz. We successfully demonstrated that the analog circuits. experimental results coincide well with the expectations The closely located signal can be easily coupled to noise induced from the proposed model. These results demonstrate sensitive circuits in the analog chips such as OpAmps, PLL, the necessity of co-modeling and analysis of the LNA, ADC, and DAC, resulting in severe degradation of interconnection and the circuit. performance and reliability in the wireless communication system. Especially, the OpAmp is the most commonly used circuit among analog blocks such as ADCs, DACs, and active II. CHARACTERIZATION OF ON-CHIP INTERCONNECTIONS filters, which are essential analog building blocks for In this paper, the on-chip interconnection is modeled in R, implementing the mixed-mode signal systems [3][4]. There are L, G, C networks with balanced structure. Each R, L, G, C many publications about noise effect on op amp operations [4]- models is obtained analytically. If the length of interconnection [9], which successfully present and model the noise effect. is not short and the frequency is high, inductance is not However, these previous works model and verify without negligible as shown in Fig.. 1. There are two return current account of the RFI source. In the OpAmp, one of the most paths. The one is the nearest ground or power metal line. The crucial properties for determining the performance of the other one is the silicon substrate highly dopped. The dominant OpAmp is the DC output voltage offset that can lead to fatal path is determined by the frequency and distance between system errors or a failure. The most probable mechanism signal and ground. generating this DC output voltage offset in the OpAmp is radio frequency interference (RFI) coupled to a signal input path to the OpAmp circuit. Consequently, it is essential to investigate Signal Routing with PCB interconnections. Cfs and Cfc can be derived from [10]. P-substrate Inductance can be derived as bellows. μ ⎛ 1 d ⎞ Global Routing for Ground L = + ln (6) l π ⎜ + ⎟ (a) ⎝ 4 W t ⎠ = μ hL (7) L p Signal Routing W Rs CL The signal lines are nearly placed and they have an effect on each other. The coupling capacitance can be obtained using eq (2) and (4). The capacitive coupling effect is dominant on P-substrate the chip [2]. From impedance profile, we can make a decision of the dominant factor. In this case, the capacitance is Global Routing for Ground dominant up to 10GHz. The model is verified with 3D filed solver as shown in Fig. 3. (b) -10 0 Fig.. 1 (a) Conceptual diagram of the single-ended on-chip interconnection. -15 (b) The models of the on-chip interconnection. R is the source resistance of S11 (dB) -1 s S21 (dB) the signal source and CL is the load capacitance (input capacitance of the -20 driver). -2 -25 3D field solver 3D field solver W Model Model t -30 -3 002 4 6 810 2 4 6 810 d Cfs Cs Cfs Frequency (GHz) Frequency (GHz) (a) 0 -10 -10 S33 (dB) W S31 (dB) -15 -20 t S Ci -30 -20 Cfi 3D field solver 3D field solver (b) -40 Model Model W -50 -25 0 2 4 6 810 0 246810 t Frequency (GHz) Frequency (GHz) Cfc Fig. 3 Comparison of the 3D field solver and the model. The solid lines shows the results of the model and the dash lines indicate 3D field solver. h Cfc 0.12 (c) 0.1 Fig. 2 Capacitance model. (a) Capacitance between a signal metal line and wide metal. Cs is the face to face capacitance and Cfs is the fringing Coupling Ratio 0.08 capacitance. (b) Capacitance between a signal line and a signal line. Ci is the face to face capacitance and Cfi is the fringing capacitance. (c) Cfc is the fringing capacitance between edge an edge. 0.06 WL tL C = ε , C = ε (1) (2) 0.04 s d i s 0.02 L ⎛ d + t + t 2 + dt ⎞ (3) C = ε ln⎜ ⎟ fs π ⎜ s ⎟ 0 ⎝ ⎠ 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Frequency (GHz) L ⎛ s + 2W ⎞ C = ε ln⎜ ⎟ (4) fi π s Fig. 4 Capacitive coupling coefficient depending on frequency. The coupling ⎝ ⎠ coefficient is the ratio of transfer impedance and self impedance of the aggressor. W ⎛ h + t + t 2 + ht ⎞ C = ε ln⎜ ⎟ (5) fc π ⎜ h ⎟ The capacitive coupling ratio versus frequency is shown in ⎝ ⎠ Fig. 4. If the resistance is small, the capacitive coupling The fringing effect should be considered because the width coefficient is constant for every frequency [11]. But the load of the on-chip interconnection is relatively small compared resistance is large, the coupling effect is dependent on frequency. The coupling ratio is the ratio of transfer impedance and self impedance. Port 1 is the signal source of |Vgs1(ω)| is not equal to |Vgs2(ω)| , we find that it can create the the aggressor and port 4 which is the input of the OPamp is DC voltages offsets at the input and output nodes of the the victim. OpAmp as shown in Eq. (17). In other words, the imbalance of Z ( f ) the gate-source voltage in M1 and M2 can produce ΔVDCoffset. It k ( f ) = 41 , V = k ( f )V ( f ) (8) c Z ( f ) c c in is obvious that the DC voltage offset, ΔVDCoffset, can be 11 described as a function of v and v . gs1 gs2. Δ = Δ ⋅ + (17) VDCoffset I (R1 R2 ) III. DC OUTPUT OFFSET VOLTAGE BT INPUT NOISE In this section, we will use analytical equations to show Fig. 5 indicates the equivalent circuit model to analyze the that the noise coupled to the OpAmp input can create the DC output offset voltage. ΔVDCoffset. First, the Drain current I1 and I2 of M1 and M2 will be derived. The current of the Drain node at the CMOS transistor is expressed using Eq.(9) [12]. = 1 W − 2 + λ (9) iD k (vGS (t) Vth ) (1 vDS (t)) 2 L Since the crosstalk noise can be expressed as an AC noise signal, the Gate-Source voltage can be represented as the sum of a DC bias signal, VGS, and an AC coupled noise signal, vgs . = + , = − (10)(11) vGS (t) VGS vgs (t) VT VGS Vth = ω ω vgs (t) |Vgs ( ) | cos t (12) Fig. 5 Equivalent circuit model to analyze the DC output offset voltage We use Eq. (10) to simplify the equations, while VT is the DC voltage difference between the DC bias voltage of the First, we obtain the Gate-Source voltage, vgs1(t) and vgs2(t).
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