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Programming Technologies

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Programming Technologies Overview Part 1 - Implementation Technology and Logic Design Design Concepts and Automation • Fundamental concepts of design and computer-aided design techniques Logic and Computer Design Fundamentals The Design Space • Technology parameters for gates, positive and negative logic and design tradeoffs Chapter 3 – Combinational Design Procedure • The major design steps: specification, formulation, optimization, technology Logic Design mapping, and verification Technology Mapping Part 2 – Programmable Implementation • Mapping from AND, OR, and NOT to other gate types Verification Technologies • Does the designed circuit meet the specifications? Charles Kime & Thomas Kaminski Part 2 - Programmable Implementation Technologies Read-Only Memories, Programmable Logic Arrays, Programmable © 2004 Pearson Education, Inc. Array Logic Terms of Use • Technology mapping to programmable logic devices (Hyperlinks are active in View Show mode) 1 2 Overview Why Programmable Logic? Facts: Why programmable logic? It is most economical to produce an IC in large Programmable logic technologies volumes Many designs required only small volumes of ICs Read-Only Memory (ROM) Need an IC that can be: Programmable Logic Array (PLA) Produced in large volumes Programmable Array Logic (PAL) Handle many designs required in small volumes VLSI Programmable Logic Devices - covered in A programmable logic part can be: VLSI Programmable Logic Devices reading supplement made in large volumes programmed to implement large numbers of different low-volume designs 3 4 Programmable Logic - Additional Advantages Programming Technologies Many programmable logic devices are field- programmable, i. e., can be programmed outside of the manufacturing environment Programming technologies are used to: Most programmable logic devices are erasable and Control connections reprogrammable. Build lookup tables Allows “updating” a device or correction of errors Allows reuse the device for a different design - the ultimate Control transistor switching in re-usability! The technologies Ideal for course laboratories Control connections Programmable logic devices can be used to prototype • Mask programming design that will be implemented for sale in regular • Fuse ICs. • Antifuse Complete Intel Pentium designs were actually prototype • Single-bit storage element with specialized systems based on large numbers of VLSI programmable devices! 5 6 1 Programming Technologies Technology Characteristics Permanent - Cannot be erased and reprogrammed • Mask programming The technologies (continued) • Fuse Build lookup tables • Antifuse • Storage elements (as in a memory) Reprogrammable Transistor Switching Control Volatile - Programming lost if chip power lost • Stored charge on a floating transistor gate • Single-bit storage element – Erasable Non-Volatile – Electrically erasable • Erasable – Flash (as in Flash Memory) • Electrically erasable • Storage elements (as in a memory) • Flash (as in Flash Memory) 7 8 Technology Characteristics Programmable Configurations Read Only Memory (ROM) - a fixed array of AND gates and a programmable array of OR gates Build lookup tables Programmable Array Logic (PAL) - a programmable • Storage elements (as in a memory) array of AND gates feeding a fixed array of OR gates. Transistor Switching Control Programmable Logic Array (PLA) - a programmable array • Stored charge on a floating transistor gate of AND gates feeding a programmable array of OR – Erasable gates. – Electrically erasable Complex Programmable Logic Device (CPLD) /Field- – Flash (as in Flash Memory) Programmable Gate Array (FPGA) - complex enough to • Storage elements (as in a memory) be called “architectures” - See VLSI Programmable Logic Devices reading supplement 9 10 PAL is a registered trademark of Lattice Semiconductor Corp. ROM, PAL and PLA Configurations Read Only Memory Read Only Memories (ROM) or Programmable Read Only Fixed Programmable Programmable Memories (PROM) have: Inputs AND array Outputs OR array (decoder) Connections N input lines, M output lines, and (a) Programmable read-only memory (PROM) 2N decoded minterms. Fixed AND array with 2N outputs implementing all N-literal minterms. Programmable Inputs Programmable Fixed Outputs Programmable OR Array with M outputs lines to form up to M Connections AND array OR array sum of minterm expressions. A program for a ROM or PROM is simply a multiple-output truth (b) Programmable array logic (PAL) device table If a 1 entry, a connection is made to the corresponding minterm for the corresponding output Programmable Programmable Inputs Programmable Programmable Outputs If a 0, no connection is made Connections AND array Connections OR array Can be viewed as a memory with the inputs as addresses of data (output values), hence ROM or PROM names! (c) Programmable logic array (PLA) device 11 12 2 Read Only Memory Example Programmable Array Logic (PAL) Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output The PAL is the opposite of the ROM, having a programmable lines) set of ANDs combined with fixed ORs. The fixed "AND" array is a D7 X X X Disadvantage “decoder” with 3 inputs and 8 D6 ROM guaranteed to implement any M functions of N outputs implementing minterms. D5 X X X inputs. PAL may have too few inputs to the OR gates. The programmable "OR“ D4 A A2 D3 Advantages array uses a single line to D2 X B A1 D1 X X For given internal complexity, a PAL can have larger N and M represent all inputs to an X C A0 D0 OR gate. An “X” in the Some PALs have outputs that can be complemented, adding POS functions array corresponds to attaching the minterm to the OR No multilevel circuit implementations in ROM (without external connections from output to input). PAL has Read Example: For input (A ,A ,A ) 2 1 0 F3 F2 F1 F0 outputs from OR terms as internal inputs to all AND = 011, output is (F3,F2,F1,F0 ) = 0011. terms, making implementation of multi-level circuits easier. What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A )? 0 13 14 Programmable Array Logic Example Programmable Logic Array (PLA) AND gates inputs 0 1 2 3 4 5 6 7 8 9 Compared to a ROM and a PAL, a PLA is the most flexible 4-input, 3-output PAL X Product 1 term having a programmable set of ANDs combined with a X with fixed, 3-input OR X 2 F1 programmable set of ORs. terms 3 Advantages What are the I 15 A X A PLA can have large N and M permitting implementation of X equations for F1 4 X equations that are impractical for a ROM (because of the number of X 5 X F2 inputs, N, required X through F4? X A PLA has all of its product terms connectable to all outputs, F1 = A’B’ + C’ 6 I25 B overcoming the problem of the limited inputs to the PAL Ors X F2 = A’BC’ + AC + AB’ 7 X Some PLAs have outputs that can be complemented, adding POS X F3 = ? 8 X F3 functions F4 = ? 9 X Disadvantage I35 C Often, the product term count limits the application of a PLA. X 10 X Two-level multiple-output optimization reduces the number of X X 11 F4 product terms in an implementation, helping to fit it into a PLA. 12 X I4 15 16 0 1 2 3 4 5 6 7 8 9 Programmable Logic Array Example Terms of Use A . What are the equations for F1 and F2? B . Could the PLA implement the functions without the XOR gates? © 2004 by Pearson Education,Inc. All rights reserved. The following terms of use apply in addition to the standard C Pearson Education Legal Notice. X X 1 X X A B Permission is given to incorporate these materials into classroom presentations and handouts only to instructors X X 2 X B C X Fuse intact adopting Logic and Computer Design Fundamentals as the Fuse blown course text. X X 3 X A C Permission is granted to the instructors adopting the book to post these materials on a protected website or protected ftp X X 4 X A B site in original or modified form. All other website or ftp X postings, including those offering the materials for a fee, are C C B B A A 0 X 1 prohibited. 3-input, 3-output PLA F1 You may not remove or in any way alter this Terms of Use with 4 product terms notice or any trademark, copyright, or other proprietary notice, including the copyright watermark on each slide. F2 17 Return to Title Page 18 3.
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