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PDF 19308 Kb ADSP-Bf50x Blackfin ® Processor Hardware Reference ADSP-BF50x Blackfin® Processor Hardware Reference Revision 1.2, February 2013 Part Number 82-100101-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu- ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli- cation or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-KIT Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual .................................................................. li Intended Audience .......................................................................... li Manual Contents ........................................................................... lii What’s New in This Manual ........................................................... lv Technical Support .......................................................................... lvi Supported Processors .................................................................. lviiii Product Information .................................................................. lviiii Analog Devices Web Site ...................................................... lviiii EngineerZone .......................................................................... lix Notation Conventions .................................................................... lx Register Diagram Conventions ...................................................... lxi INTRODUCTION General Description of Processor ................................................... 1-1 Portable Low-Power Architecture ............................................. 1-3 System Integration ................................................................... 1-3 Peripherals .................................................................................... 1-4 ADSP-BF50x Blackfin Processor Hardware Reference iii Contents Memory Architecture .................................................................... 1-4 Internal Memory ..................................................................... 1-6 External Memory .................................................................... 1-6 I/O Memory Space .................................................................. 1-7 DMA Support .............................................................................. 1-8 General-Purpose I/O (GPIO) ........................................................ 1-9 Two-Wire Interface ..................................................................... 1-10 RSI Interface .............................................................................. 1-11 General-Purpose (GP) Counter ................................................... 1-12 3-Phase PWM Unit .................................................................... 1-13 Parallel Peripheral Interface ......................................................... 1-14 SPORT Controllers .................................................................... 1-16 Serial Peripheral Interface (SPI) Ports .......................................... 1-18 Timers ........................................................................................ 1-18 UART Ports ............................................................................... 1-19 Controller Area Network (CAN) Interface ................................... 1-21 ACM Interface ........................................................................... 1-22 Internal ADC ............................................................................. 1-22 Watchdog Timer ......................................................................... 1-23 Clock Signals .............................................................................. 1-23 Dynamic Power Management ...................................................... 1-24 Full-On Operating Mode—Maximum Performance ............... 1-24 Active Operating Mode—Moderate Dynamic Power Savings .. 1-24 Sleep Operating Mode—High Dynamic Power Savings .......... 1-25 iv ADSP-BF50x Blackfin Processor Hardware Reference Contents Deep Sleep Operating Mode—Maximum Dynamic Power Savings ............................................................................... 1-26 Hibernate State—Maximum Static Power Savings ................... 1-26 Instruction Set Description ......................................................... 1-27 Development Tools ..................................................................... 1-28 MEMORY Memory Architecture .................................................................... 2-1 L1 Instruction SRAM .................................................................... 2-2 L1 Data SRAM ............................................................................. 2-3 L1 Data Cache .............................................................................. 2-4 Boot ROM ................................................................................... 2-4 External Memory .......................................................................... 2-4 Processor-Specific MMRs .............................................................. 2-5 DMEM_CONTROL Register ................................................. 2-5 DTEST_COMMAND Register ............................................... 2-6 CHIP BUS HIERARCHY Chip Bus Hierarchy Overview ....................................................... 3-1 Interface Overview ........................................................................ 3-2 Internal Clocks ........................................................................ 3-2 Core Bus Overview .................................................................. 3-4 Peripheral Access Bus (PAB) ..................................................... 3-5 PAB Arbitration .................................................................. 3-6 PAB Agents (Masters, Slaves) ............................................... 3-6 PAB Performance ................................................................ 3-7 ADSP-BF50x Blackfin Processor Hardware Reference v Contents DMA Access Bus (DAB), DMA Core Bus (DCB), DMA External Bus (DEB) .............................................................. 3-7 DAB, DCB, and DEB Arbitration ....................................... 3-7 DAB Bus Agents (Masters) .................................................. 3-9 DAB, DCB, and DEB Performance ..................................... 3-9 External Access Bus (EAB) .................................................... 3-10 Arbitration of the External Bus .............................................. 3-10 DEB/EAB Performance ......................................................... 3-10 SYSTEM INTERRUPTS Specific Information for the ADSP-BF50x ..................................... 4-1 Overview ...................................................................................... 4-1 Features .................................................................................. 4-2 Description of Operation .............................................................. 4-2 Events and Sequencing ............................................................ 4-2 System Peripheral Interrupts .................................................... 4-4 Programming Model ..................................................................... 4-7 System Interrupt Initialization ................................................. 4-8 System Interrupt Processing Summary ..................................... 4-8 System Interrupt Controller Registers .......................................... 4-10 System Interrupt Assignment (SIC_IAR) Register .................. 4-11 System Interrupt Mask (SIC_IMASK) Register ...................... 4-12 System Interrupt Status (SIC_ISR) Register ........................... 4-12 System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12 vi ADSP-BF50x Blackfin Processor Hardware Reference Contents Programming Examples ............................................................... 4-13 Clearing Interrupt Requests ................................................... 4-13 Unique Information for the ADSP-BF50x Processor .................... 4-15 Interfaces .............................................................................. 4-15 System Peripheral Interrupts .................................................. 4-18 EXTERNAL BUS INTERFACE UNIT EBIU Overview ............................................................................ 5-1 Block Diagram ........................................................................ 5-3 Internal Memory Interfaces ...................................................... 5-4 Registers .................................................................................. 5-4 Error Detection ....................................................................... 5-5 AMC Overview and Features ........................................................
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