Application-Guided Power Gating Reducing Register File Static Power Hamed Tabkhi, Student Member, IEEE, Gunar Schirner, Member, IEEE
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, VOL. ??, NO. ?, ?? 2014 1 Application-Guided Power Gating Reducing Register File Static Power Hamed Tabkhi, Student Member, IEEE, Gunar Schirner, Member, IEEE, Abstract—Power and energy efficiency are on the top priority show that RFs are consuming 15%-36% of overall processor list in embedded computing. Embedded processors taped out in core power [6], [7], [8], [9], [10], and up to 42% of core data- deep sub-micron technology have a high contribution of static path [11]. Power assessments considerably differ based on RF power to overall power consumption. At the same time, current embedded processors often include a large Register File (RF) to size, processor complexity, and also the running application. increase performance. However, a larger RF aggravates the static As one example, 20% of the core power (including data power issues associated with technology shrinking. Therefore, and instruction caches) in a Blackfin processor (in 120nm approaches to improve static power consumption of large RFs technology) is attributed to the RF itself [9]. In addition to are in high demand. high contribution to total core power, RFs are also identified as In this paper, we introduce AFReP: an Application-guided Function-level Registerfile Power-gating approach to efficiently one of the main hot-spots [12], [13], [14], [15]. The high power manage and reduce RFs static power consumption. AFReP density (power per area) in an RF can cause severe reliability is an interplay of automatic binary analysis and instrumenta- issues such as transient faults, violation of circuit timing tion at function-level granularity supported by ISA and micro- constraints, and reduce the overall lifespan of the circuit [12].
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