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ADSP-21535 Blackfin DSP High Performance for Networking and Digital Imaging

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ADSP-21535 Blackfin DSP High Performance for Networking and Digital Imaging AD-4902 ADSP21535 9/9/02 3:48 PM Page 1 ADSP-21535 Blackfin DSP High Performance for Networking and Digital Imaging Key Features • High performance 300 MHz 16-bit dual-MAC DSP core • Flexible, software controlled Dynamic Power Management • Optimized RISC instruction set for high code density and programming in C/C++ languages • Enhanced media instructions to process audio, image, and video for multimedia applications • Integrated system peripherals including USB device, PCI, serial ports, UARTs, SPIs, 32-bit timers, and more Blackfin DSP Architecture Highlights Blackfin DSPs Utilize At the heart of Blackfin DSPs is ADI’s most advanced 16-bit DSP core architecture. • Single processor core This new core, developed jointly between Analog Devices and Intel Corporation, has three primary objectives: • Single instruction set High Performance • Single programming model Blackfin DSPs employ a dual-MAC DSP that also includes efficient RISC MCU • Single set of development system control functionality and multimedia processing capabilities. All are tools combined into one simple, optimized instruction-set architecture. Target Applications Dynamic Power Management • Automotive Blackfin DSP’s Dynamic Power Management offers a flexible, software controlled • Broadband access environment that delivers just the required amount of performance to the processor via independent, dynamic variation of both voltage and frequency. Blackfin DSPs Central office/network switch • also employ a gated clock scheme and multiple power-down modes for minimal • Digital imaging and printing power consumption. • Global positioning systems Ease of Use Blackfin DSPs employ both an optimized compiler and architecture to support • Industrial signal processing software development in high level languages (HLL), e.g. C/C++, thus delivering • Instrumentation/telemetry comparable code densities of traditional microcontrollers. The architecture also has • Internet appliances embedded features to support efficient use of a Real-Time Operating System (RTOS). • Modem solutions Blackfin DSPs represent a revolutionary change to the traditional trade-offs that programmers and system architects were forced to make in the past. Blackfin DSPs Personal branch exchanges • incorporate the world’s first truly high performance DSP combined with MCU control (PBX) functionality, all integrated into a single architecture that is easy to develop a system • POS terminals around. With Blackfin DSPs, OEMs can achieve lower costs and higher performance that will enable the next generation of embedded digital communication and connected • Telecommunications media appliances. • Video conferencing • VoIP phone solutions AD-4902 ADSP21535 9/9/02 3:48 PM Page 2 System Development Blackfin DSP System Environment Blackfin DSP’s core performance and architectural partitioning allow for development of a complete, high performance DSP system that could incorporate either ADI’s VisualDSP Kernel (VDK) RTOS or many other industry recognized Real-Time Operating Systems—all within a single processor environment. Low latency real-time DSP code can be run on the Blackfin core and enhanced by utilizing the expandability and flexibility of VisualDSP Component Software Engineering (VCSE) capabilities now offered in the latest version of VisualDSP++™ for Blackfin DSP. Additionally, higher latency control tasks can be simultaneously scheduled and execut- ed, allowing the Blackfin DSP to be at the heart of many embedded systems. Optimized and Configurable Memory Structure The Blackfin DSP processor core is a highly parallel, fully interlocked pipeline architecture that allows users to achieve the most work possible per cycle. To complement this, Blackfin DSPs utilize a very powerful and flexible L1 and L2 memory hierarchy. Both L1 instruction and data memories can be dynamically configured as SRAM, cache, or a combination of both—all depending on how the processor core is to be used for the given task. Blackfin DSPs can also include an integrated, unified instruction and data L2 SRAM for larger storage needs. Both the L1 and L2 memories are dual-ported so that information can be simultaneously incoming and outgoing for maximum throughput with minimal core processor impact. Blackfin DSP Memory Hierarchy AD-4902 ADSP21535 9/9/02 3:48 PM Page 3 Portable Low Power Architecture Blackfin DSP Dynamic Power Management Blackfin DSPs use Dynamic Power Management to control critical power consumption and performance parameters, thus allowing system designers to fully optimize the design for the intended application. Blackfin DSPs are designed WITHOUT DYNAMIC POWER MANAGEMENT to achieve the most work per cycle to maximize WITH DYNAMIC POWER MANAGEMENT the computational processing power per required mW. Applications may independently vary both POWER SAVINGS = P2 – P1 frequency of operation and voltage of operation of the DSP core, resulting in significantly lower overall power consumption. This translates into P2 longer battery life for portable applications. System Integration ADSP-21535, the first Blackfin DSP, is a highly integrated system-on-a-chip (SoC) solution for NORMALIZED POWER the next generation of digital communication and connected media applications. By combining industry-standard communication interfaces with a high performance DSP core, OEMs can develop P1 cost-effective solutions quickly and effectively without the need for costly external components. The ADSP-21535 system peripherals include NORMALIZED WORKLOAD UARTs, SPIs, serial ports, general-purpose timers, a real-time clock, watchdog timer, USB device, and PCI bus interfaces for further peripheral expansion. ADSP-21535 Block Diagram Tools and Support Software Blackfin DSPs are supported by ADI’s CROSSCORE™ development tools, which include the industry leading VisualDSP++ development environment, evaluations kits and emulators. The VisualDSP++ environment consists of a full range of tools such as a C/C++ compiler, linker, debugger, simulator, statisitical profiling, the VisualDSP++ kernel and more. The EZ-KIT Lite™ evaluation system provides an easy way to investigate the power of ADI’s family of DSPs and begin application development. ADI emulators, among other tasks, allow you to load code, set breakpoints, observe variables, observe memory, and examine registers. ADI also has a large third-party development community, the DSP Collaborative™, supporting signal processing applications. Please consult your ADI representative for selection and availability of products. AD-4902 ADSP21535 9/9/02 3:48 PM Page 4 ADSP-21535 Blackfin DSP Features DSP Support Email: In the U.S.A.: [email protected] Processor Core Peripherals In Europe: 300 MHz high performance DSP core 32-bit 33 MHz PCI V2.2 compliant bus interface [email protected] • • Fax: In the U.S.A.: with both master and slave support 781 461 3010 • Dual 16-bit MACs, supporting 600 MMACs In Europe: of sustained performance • USB device V1.1 compliant controller 49 89 76903 557 supporting up to eight endpoints www.analog.com/dsp • Two 32-bit ALUs Worldwide • Event handler Headquarters • Two 40-bit accumulators One Technology Way • Two UARTs with auto baud capability (one UART P.O. Box 9106 • Four 8-bit video ALUs ® Norwood, MA includes support for IrDA ) 02062-9106, U.S.A. • Parallel address computational DAGs for circular Tel: 781 329 4700 • Four 32-bit timer/counters—three of which (1 800 262 5643, buffer and bit reversed addressing support support PWM, pulsewidth, and event U.S.A. only) Fax: 781 326 8703 • 40-bit shifter for bit manipulation and count modes Japan data interleaving • Two SPI compatible ports Headquarters New Pier Takeshiba • Flexible software controlled Dynamic Two dual-channel, full-duplex synchronous South Tower Building • 1-16-1 Kaigan, Power Management serial ports (SPORTS) Minato-ku, Tokyo 105-6891, Japan • RISC-like register and instruction model for ease • 12-channel DMA controller and memory DMA Tel: 813 5402 8200 of programming and compiler-friendly support controller capable of internal, external, Fax: 813 5402 1063 and PCI transfers Southeast Asia • Enhanced multimedia instructions for media Headquarters 4501 Nat West Tower rich processing • Real-time clock Times Square One Matheson Street • Advanced debug, trace, and performance • Watchdog timer Causeway Bay monitoring support Hong Kong, PRC • 16 general-purpose I/O Tel: 852 2 506 9336 Fax: 852 2 506 4755 Memory • Debug/JTAG interface • 768 Mbytes unified address memory map • On-chip PLL capable of 1ϫ to 31ϫ • 308 Kbytes of on-chip memory frequency multiplication - 16 Kbytes of dual-ported L1 instruction Other SRAM/cache • 260-lead (19 mm ϫ 19 mm) PBGA package 32 Kbytes of dual-ported L1 data - • 1.5 V VDD with 3.3 V I/O capability SRAM/cache • 300 MHz commercial temperature - 4 Kbytes of high speed Scratchpad SRAM range offering - 256 Kbytes of full speed, low latency, • 200 MHz industrial temperature range offering dual-ported L2 SRAM CROSSCORE Development Tools • Memory management unit providing • VisualDSP++ memory protection - VisualDSP Kernel (VDK) RTOS • Memory controller providing glueless connection - VisualDSP Component Software Engineering to multiple banks of SDRAM, SRAM, FLASH, (VCSE) or ROM • ADSP-21535 EZ-KIT Lite™ • Flexible memory initialization capability (boot • PCI and USB based emulators from SPI, serial port, external memory source, or second stage PCI load) www.analog.com/blackfin-dsp © 2002 Analog Devices, Inc. The Analog Devices logo, Blackfin, Blackfin logo, CROSSCORE, DSP Collaborative, and VisualDSP++ are trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service DSP SOLUTIONS THAT MAKE YOUR marks of their respective owners. DESIGN CHALLENGE EASIER™ Printed in the U.S.A. H02469-5-8/02(A).
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