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Blackfin Processor Programming Reference Iii Blackfin® Processor Programming Reference (includes ADSP-BF5xx and ADSP-BF60x Processors) Revision 2.2, February 2013 Part Number 82-000556-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu- ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli- cation or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-KIT Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual .............................................................. xxvii Intended Audience ...................................................................... xxvii Manual Contents ....................................................................... xxviii What’s New in This Manual .......................................................... xxx Technical Support ......................................................................... xxx Supported Processors .................................................................... xxxi Product Information .................................................................... xxxi Analog Devices Web Site ....................................................... xxxii EngineerZone ........................................................................ xxxii Notation Conventions ................................................................ xxxiii Register Diagram Conventions ................................................... xxxiv INTRODUCTION Core Architecture .......................................................................... 1-2 Memory Architecture .................................................................... 1-5 Internal Memory ..................................................................... 1-5 External Memory .................................................................... 1-6 I/O Memory Space .................................................................. 1-6 Blackfin Processor Programming Reference iii Contents Event Handling ............................................................................ 1-7 Core Event Controller (CEC) .................................................. 1-8 System Interrupt Controller (SIC) ........................................... 1-8 Syntax Conventions ...................................................................... 1-8 Case Sensitivity ....................................................................... 1-8 Free Format ............................................................................ 1-9 Instruction Delimiting ............................................................ 1-9 Comments ............................................................................ 1-10 Notation Conventions ................................................................ 1-10 Behavior Conventions ................................................................. 1-12 Glossary ..................................................................................... 1-12 Register Names ..................................................................... 1-13 Functional Units ................................................................... 1-14 Arithmetic Status Bits ........................................................... 1-14 Fractional Convention .......................................................... 1-16 Saturation ............................................................................. 1-17 Rounding and Truncating ..................................................... 1-19 Automatic Circular Addressing .............................................. 1-21 COMPUTATIONAL UNITS Using Data Formats ...................................................................... 2-2 Binary String .......................................................................... 2-3 Unsigned ................................................................................ 2-4 Signed Numbers: Two’s-Complement ...................................... 2-4 Fractional Representation: 1.15 ............................................... 2-4 iv Blackfin Processor Programming Reference Contents Register Files ................................................................................. 2-5 Data Register File .................................................................... 2-6 Accumulator Registers ............................................................. 2-7 Register File Instruction Summary ........................................... 2-8 Data Types .................................................................................. 2-10 Endianess .............................................................................. 2-12 ALU Data Types .................................................................... 2-12 Multiplier Data Types ............................................................ 2-13 Shifter Data Types ................................................................. 2-14 Arithmetic Formats Summary ................................................ 2-14 Using Multiplier Integer and Fractional Formats .................... 2-16 Rounding Multiplier Results .................................................. 2-18 Unbiased Rounding .......................................................... 2-18 Biased Rounding ............................................................... 2-21 Truncation ........................................................................ 2-22 Special Rounding Instructions ............................................... 2-22 Using Computational Status ........................................................ 2-23 ASTAT Register .......................................................................... 2-24 Arithmetic Logic Unit (ALU) ...................................................... 2-25 ALU Operations .................................................................... 2-25 Single 16-Bit Operations ................................................... 2-26 Dual 16-Bit Operations ..................................................... 2-27 Quad 16-Bit Operations .................................................... 2-27 Blackfin Processor Programming Reference v Contents Single 32-Bit Operations .................................................. 2-28 Dual 32-Bit Operations .................................................... 2-29 ALU Instruction Summary .................................................... 2-30 ALU Division Support Features ............................................. 2-34 Special SIMD Video ALU Operations ................................... 2-34 Multiply Accumulators (Multipliers) ........................................... 2-35 Multiplier Operation ............................................................. 2-35 Placing Multiplier Results in Multiplier Accumulator Registers ........................................................................ 2-36 Rounding or Saturating Multiplier Results ........................ 2-37 Saturating Multiplier Results on Overflow ............................. 2-37 Multiplier Instruction Summary ............................................ 2-38 Multiplier Instruction Options .......................................... 2-40 Multiplier Data Flow Details ................................................. 2-42 Multiply Without Accumulate ............................................... 2-44 Special 32-Bit Integer MAC Instruction ................................. 2-45 Dual MAC Operations .......................................................... 2-46 Barrel Shifter (Shifter) ................................................................ 2-48 Shifter Operations ................................................................. 2-48 Two-Operand Shifts ......................................................... 2-48 Immediate Shifts .......................................................... 2-49 Register Shifts ............................................................... 2-49 Three-Operand Shifts ....................................................... 2-50 Immediate Shifts .......................................................... 2-50 Register Shifts ............................................................... 2-50 vi Blackfin Processor Programming Reference Contents Bit Test, Set, Clear, Toggle ................................................ 2-51 Field Extract and Field Deposit ......................................... 2-52 Packing Operation ............................................................ 2-53 Shifter Instruction Summary .................................................. 2-54 OPERATING MODES AND STATES User Mode .................................................................................... 3-3 Protected Resources and Instructions ....................................... 3-4 Protected Memory ................................................................... 3-5 Entering User Mode
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