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Blackfin DSP Instruction Set Reference Contents Instruction Set Reference Preliminary Edition, November 2001 Part Number 82-000410-14 Analog Devices, Inc. DSP and Systems Products Group Three Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2001 Analog Devices, Inc. and Intel Corporation. ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Ana- log Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo is a registered trademark; and Blackfin and the Blackfin logo are trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. Development Information Blackfin DSPs are based on the Micro Signal Architecture, jointly developed by Analog Devices, Inc. and Intel Corporation. ii Blackfin DSP Instruction Set Reference Contents 1 Introduction...............................................................................................................................1-1 1.1 Manual Organization...................................................................................................1-2 1.2 Syntax Conventions....................................................................................................1-2 1.3 Notation Conventions .................................................................................................1-3 1.4 Behavior Conventions.................................................................................................1-4 1.5 Glossary......................................................................................................................1-4 1.6 Related References....................................................................................................1-8 1.7 Document Errata Sightings.........................................................................................1-9 2 Program Flow Control ..............................................................................................................2-1 2.1 Jump...........................................................................................................................2-2 2.2 Conditional Jump........................................................................................................2-4 2.3 Call..............................................................................................................................2-6 2.4 Return.........................................................................................................................2-8 2.5 Zero-Overhead Loop Setup......................................................................................2-11 3 Load / Store..............................................................................................................................3-1 3.1 Load Immediate..........................................................................................................3-2 3.2 Load Pointer Register.................................................................................................3-4 3.3 Load Data Register.....................................................................................................3-6 3.4 Load Half-Word – Zero-Extended...............................................................................3-9 3.5 Load Half-Word – Sign-Extended .............................................................................3-12 3.6 Load High Data Register Half ...................................................................................3-15 3.7 Load Low Data Register Half....................................................................................3-18 3.8 Load Byte – Zero-Extended......................................................................................3-21 3.9 Load Byte – Sign-Extended......................................................................................3-23 3.10 Store Pointer Register ..............................................................................................3-25 3.11 Store Data Register ..................................................................................................3-27 3.12 Store High Data Register Half ..................................................................................3-30 3.13 Store Low Data Register Half ...................................................................................3-33 3.14 Store Byte.................................................................................................................3-36 4 Move.........................................................................................................................................4-1 4.1 Move Register.............................................................................................................4-2 4.2 Move Conditional........................................................................................................4-6 4.3 Move Half-Word – Zero-Extended ..............................................................................4-8 4.4 Move Half-Word – Sign-Extended ............................................................................4-10 4.5 Move Register Half ...................................................................................................4-12 4.6 Move Byte – Zero-Extended.....................................................................................4-17 4.7 Move Byte – Sign-Extended .....................................................................................4-19 Blackfin DSP Instruction Set Reference iii 5 Stack Control............................................................................................................................5-1 5.1 Push ...........................................................................................................................5-2 5.2 Push Multiple ..............................................................................................................5-4 5.3 Pop .............................................................................................................................5-6 5.4 Pop Multiple................................................................................................................5-9 5.5 Linkage .....................................................................................................................5-14 6 Control Code Bit Management.................................................................................................6-1 6.1 Compare Data Register..............................................................................................6-2 6.2 Compare Pointer ........................................................................................................6-5 6.3 Compare Accumulator................................................................................................6-7 6.4 Move CC.....................................................................................................................6-9 6.5 Negate CC................................................................................................................6-12 7 Logical Operations ...................................................................................................................7-1 7.1 AND ............................................................................................................................7-2 7.2 NOT (1’s Complement)...............................................................................................7-4 7.3 OR ..............................................................................................................................7-6 7.4 Exclusive-OR..............................................................................................................7-8 7.5 Bit-Wise Exclusive-OR .............................................................................................7-10 8 Bit Operations ..........................................................................................................................8-1 8.1 Bit Clear......................................................................................................................8-2 8.2 Bit Set .........................................................................................................................8-4 8.3 Bit Toggle ...................................................................................................................8-6 8.4 Bit Test .......................................................................................................................8-8 8.5 Bit Field Deposit .......................................................................................................8-10 8.6 Bit Field Extraction....................................................................................................8-15 8.7 Bit Multiplex ..............................................................................................................8-20 8.8 Ones Population Count ............................................................................................8-24
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