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Sunit Rikhi 2014 IDF Session Presentation

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Sunit Rikhi 2014 IDF Session Presentation Leading at the edge of Moore’s Law with Intel Custom Foundry Sunit Rikhi General Manager, Intel Custom Foundry Vice President, Technology and Manufacturing Group SPCS011 Agenda • Overview • Platform Offerings • Summary 2 Intel Custom Foundry: Flexible Business Models 3 Intel Custom Foundry: Flexible Business Models Customer Intel and Custom Design Third Party IP Product 4 Intel Custom Foundry: Flexible Business Models Customer Intel and Custom Design Third Party IP Product Intel Standard Customer and Semi-Custom Product Design Third Party IP Product 5 Intel Custom Foundry: Flexible Execution Models Front-end Physical Wafer Packaging Masks Design Design Manufacturing and Test Delivering value beyond a traditional foundry model 6 Intel Custom Foundry: Flexible Execution Models Front-end Physical Wafer Packaging Masks Design Design Manufacturing and Test Customer Owned Tooling (COT) Delivering value beyond a traditional foundry model 7 Intel Custom Foundry: Flexible Execution Models Front-end Physical Wafer Packaging Masks Design Design Manufacturing and Test Customer Owned Tooling (COT) Full Service (ASIC) Delivering value beyond a traditional foundry model 8 Business & Execution Models Matrix Custom Semi-Custom Product Product Customer Owned Tooling Full Service (ASIC Model) 9 Intel Custom Foundry: Design Ecosystem Design Services Soft IP Advanced IP Foundation IP Design Tools & Flows 10 Note: Logos in alphabetical order.. Intel Custom Foundry: Worldwide Assets 11 7 Intel Custom Foundry: Worldwide Assets Oregon Ireland Dalian Israel Arizona New Mexico Wafer Fabs 12 7 Intel Custom Foundry: Worldwide Assets Oregon Ireland Dalian Israel Arizona New Mexico Chengdu Vietnam Costa Rica Penang Kulim Wafer Fabs Assembly/Test 13 7 Intel Custom Foundry: Worldwide Assets Oregon Ireland Toronto Dalian California Israel Arizona New Mexico Chengdu Vietnam Costa Rica Bangalore Penang Kulim Wafer Fabs Assembly/Test Foundry Platform Dev & Support 14 7 Intel Custom Foundry: Announced Customers 15 Note: This list of customers does not include those who choose not to disclose relationship with Intel Custom Foundry. Logos are in alphabetical order. Agenda • Overview • Platform Offerings • Summary 16 Intel Custom Foundry Platform Offerings 17 Intel Custom Foundry Platform Offerings Technology Platform Silicon Package Test 18 Intel Custom Foundry Platform Offerings Design Design Platform Kits IP Services Technology Platform Silicon Package Test 19 Intel Custom Foundry Platform Offerings Manufacturing Platform Engineering Services Production Services Design Design Platform Kits IP Services Technology Platform Silicon Package Test 20 Intel Custom Foundry Platform Offerings Online Service Platform Information Exchange Service Transactions Manufacturing Platform Engineering Services Production Services Design Design Platform Kits IP Services Technology Platform Silicon Package Test 21 Intel Custom Foundry Platform Offerings Online Service Platform Information Exchange Service Transactions Manufacturing Platform Engineering Services Production Services Design Design Platform Kits IP Services Technology Platform Silicon Package Test 22 The Wide Moving Edge of Moore’s Law 65 nm 45 nm 32 nm 22 nm 14 nm Server 1x Computing Client 0.1x Computing 0.01x Mobile Lower Leakage Power Leakage Lower Computing 0.001x Mobile Always-On Circuits Higher Transistor Performance (switching speed) Delivering performance/watt improvement to a wide range of products 23 Intel Custom Foundry: Silicon Technology Platform Offerings 22nm 14nm 10nm General General General Cloud/Infrastructure Purpose Purpose Purpose In Dev Client/Consumer Low Power Low Power In Dev 24 SOC Features in 14nm technology High Q Inductors High Density MIMCAP Precision Resistors RF Transistors Low Leakage, Long L Transistors High Voltage I/O Transistors Si Substrate Full featured technology enables integration of system functions on a chip 25 26 Cost per Transistor Intel Intel nmcontinues 14 deliver to lower cost per transistor $ / mm2 mm2 / Transistor $ / Transistor (normalized) (normalized) (normalized) 100 1 1 10 0.1 0.1 1 0.01 0.01 32 nm 32 nm 90 nm 14 nm 22 90 nm90 nm65 nm45 nm22 nm14 nm10 nm65 nm45 nm32 nm22 nm10 nm90 nm65 nm45 nm32 nm14 nm10 130 nm 130 nm 130 nm Confident Pursuit Graphene III-V Materials Synthesis 3-D Future EUV Expect More Technology From Interconnects Nanowires Options Moore Dense Memory Photonics Future options subject to change Source: Intel 27 Intel Custom Foundry Platform Offerings Online Service Platform Information Exchange Service Transactions Manufacturing Platform Engineering Services Production Services Design Design Platform Kits IP Services Technology Platform Silicon Package Test 28 Intel’s Flip Chip Package Portfolio Cloud/Infrastructure • Package-on-Package Client • Ultra-thin • Small Form Factor Chip Scale Packages SOC/Consumer Serving the requirements of multiple market segments 29 Intel’s Flip Chip Package Portfolio • Thin Core Substrate • Multi-chip packages Cloud/Infrastructure • Enhanced thermal • Embedded and solutions • LGA socket surface passives Client Desktop Mobile SOC/Consumer Serving the requirements of multiple market segments 30 Intel’s Flip Chip Package Portfolio Cloud/Infrastructure Server HPC • High pin count LGA sockets • Very High pin count LGA • Optimized for high speed sockets Client signaling • Very large footprint BGA • Large die • Reticle size die assembly SOC/Consumer Serving the requirements of multiple market segments 31 Introducing: Embedded Multi-die Interconnect Bridge (EMIB) Die 2 Die 1 Die 3 FCBGA Substrate W/ EMIB An elegant approach to in-package high density interconnect of heterogeneous die 32 EMIB Wafer Process Compared to Typical 2.5D Typical 2.5D Interposer Process EMIB Bridge Wafer Process Starting Wafer Starting Wafer TSV Formation & Fill Not Required! BEOL Metallization Wafer Thinning TSV Reveal & Not Required! Backside Surface EMIB wafer fabrication is simpler than typical silicon interposer 33 EMIB Assembly Process Compared to Typical 2.5D Typical 2.5D Interposer Process Flow EMIB Process Flow Die 2 Die 1 Die 3 Assembly A Die 2 Die 1 Die 3 Assembly B Assembly EMIB Requires Less Assembly Processing Than typical Silicon Interposer Assembly 34 EMIB Assembly Process Compared to Typical 2.5D Typical 2.5D Interposer Process Flow EMIB Process Flow Die 2 Die 1 Die 3 Die 2 Die 1 Die 3 Assembly EMIB Requires Less Assembly Processing Than typical Silicon Interposer Assembly 35 EMIB Assembly Process Compared to Typical 2.5D Typical 2.5D Interposer Process Flow EMIB Process Flow Die 2 Die 1 Die 3 Die 2 Die 1 Die 3 EMIB Requires Less Assembly Processing Than typical Silicon Interposer Assembly 36 EMIB Progress Die 2 Die 1 EMIB Package (Cross Section) Available for sampling in 2015 37 Intel Custom Foundry Platform Offerings Online Service Platform Information Exchange Service Transactions Manufacturing Platform Engineering Services Production Services Design Design Platform Kits IP Services Technology Platform Silicon Package Test 38 Introducing High Density Modular Test (HDMT) Engineering Module Production Module • Common Architecture - Fast TTM Engineering Module - >30 sites with parallel, asynchronous operation in production module • Flexible Architecture - Enables standard instrumentation integration (PXI) • Low Cost - > 2X Cost improvement over conventional test platforms 39 Intel Custom Foundry Platform Offerings Online Service Platform Information Exchange Service Transactions Manufacturing Platform Engineering Services Production Services Design Design Platform Kits IP Services Technology Platform Silicon Package Test 40 Foundry Design Kit (FDK) Analog / Mixed Signal Flows Design Tool Drivers: Technology files Digital Flows DFM Templates: Device, Layout, Fill Design Rules: Run-sets LVS1, DRC2, RV3 Primitive Libraries Models: Simulation and RC4 Extraction Process Collaterals 41 1 Layout connectivity verification system 2 Design Rule Checking 3 Reliability Verification 4 Resistance * Capacitance Foundry Design Kit (FDK) Analog / Mixed Signal Flows Full Chip Integration Collateral Library 1 Digital Flows Memory (SRAM ) Cell Library Analog Primitive Library2 Primitive Libraries Process Collaterals 42 1 Static Random Access Memory 2 Capacitors, resistors, inductors, etc. Foundry Design Kit (FDK) Analog / Mixed Signal Flows Logic Synthesis Floor Planning / Place & Route Digital Flows Design for Test / Test Pattern Generation Timing and Noise Analysis Primitive Libraries Physical Verification Reliability Verification: EM1/SH2/IR3 Drop RC4 Extraction Process Collaterals Design for Manufacturing: Fill 43 1 Electro-migration 2 Self Heat 3 Voltage (Multiplication of current and resistance) drop 4 Resistance * Capacitance Foundry Design Kit (FDK) Analog / Mixed Signal Flows Schematic Capture Digital Flows Circuit Simulation Custom Routing Custom Layout Libraries Physical Verification Reliability Verification: EM1/SH2/IR3 Drop RC4 Extraction Process Collaterals Design for Manufacturing: Fill 44 1 Electro-migration 2 Self Heat 3 Voltage (Multiplication of current and resistance) drop 4 Resistance * Capacitance FDK: Digital Flows Breadth of Industry Standard Tools Logic Synthesis Floor Planning / Place & Route Test Pattern Generation Timing and Noise Analysis Physical Verification Reliability Verification RC1 Extraction Design for Manufacturing: Fill 45 1 Resistance * Capacitance FDK: Analog Mixed Signal Flows Breadth of Industry Standard Tools Schematic Capture Circuit Simulation Custom Routing Custom Layout Physical Verification Reliability
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