Appendix 1 Asynchronous Sequential Logic Design

Appendix 1 Asynchronous Sequential Logic Design In this appendix a design method for asynchronous sequential logic design will be described. This method can be used to solve the problem specified in section 3.3, but as this is complicated the technique will be explained first using a simpler example, and then used on the more complex problem. This simpler example is a logic problem involving dynamic RAMs. These RAMs can perform a normal memory cycle (where data are read or written) or a refresh cycle. The two address strobes, RAS and CAS", determine which cycle is occurring, according to the following: If RAS goes low and then 'CAJ goes low, a normal memory cycle is instigated and continues while both strobes remain low. If'CAJ goes low and then RAS goes low, a refresh cycle is instigated and continues while both strobes remain low. A circuit is required which determines which cycle, if any, the RAM is operating. A suitable design technique for this problem is given below, though more detail can be found in Design of Logic Systems by D. Lewin. Al.l Sequentiallogic A normal combinational logic circuit is one whose outputs are determined by its current inputs. The outputs of a sequential logic circuit are deter mined by the current and the past inputs to the circuit. Inherent, therefore, in a sequential logic circuit is memory. A block diagram of a sequential circuit or machine is shown in figure Al.l. Inputs ===! Combinational I==:> Outputs Logic Memory Internal States ~----------~ Figure Al.l A sequential machine 191 192 Micro Systems Using the STE Bus There are two forms of sequential logic machines: synchronous and asynchronous. In a synchronous machine there is a timing signal, normally called a clock, which determines when the outputs of the machine change. Typically on, say, the rising edge of that clock, the state of the current and past inputs are processed and the outputs changed accordingly. At other times the inputs can change, but they have no effect on the outputs. An asynchronous sequential machine, however, is free running: any change in input is processed immediately and the outputs changed then. Synchronous sequential machines are described in appendix 2; here we will concentrate on asynchronous machines. When the inputs to an asynchronous machine are constant, the machine does not change: it is in a particular state. When an input changes, the machine is likely to change and so enter a different state. It is possible that the machine will pass through a number of intermediate states before reaching a stable state; this is reasonable. However, it is also possible to make the machine oscillate between two or more states, which is not good; but such problems should not occur if the following design method is used. Note that the inherent assumption in the method is that at most only one input can change at any one time. Al.2 The design method The first stage in the design is to manipulate the problem so that it is in a form which can be processed by the design algorithm. The object is to describe the problem in a tabular form. This flow table lists all the states that the machine can be in, the outputs of the machine when it is in each state, and the combinations of inputs which cause the machine to move to a different state. Sometimes the problem is sufficiently simple that the flow table can be written down immediately, but usually an intermediate stage is needed. This involves drawing a timing diagram or a state diagram, or both. Such diagrams for the dynamic RAM problem are given in figure A1.2. The timing diagram shows what happens to the outputs of the machine as and when its inputs change. The state diagram shows all the states, the conditions of the inputs which cause the machine to transfer to another state, and the outputs of the machine in that new state. One advantage of the state diagram is that the information therein is in a form closer to that required for the flow table. Also, it is easier to see that all possible combinations of input have been considered. Appendix 1 193 RAS CAS Mem Ref u u 1 2 3 4 1 4 5 2 1 1 4 5 2 3 4 1 (a) Timing Diagram RAS CAS I Ref Mem (b) State Diagram Figure A1.2 Diagrams for dynamic RAM circuit In this example there are two inputs, hence there are four possible combinations of input. The system remains in any state if the inputs have a particular value, for example, the system remains in state 1 while the inputs are both '1 '. Given that only one input can change at any one time, there are two possible transitions from state 1: if RAS goes to '0', or if~ goes to '0'. By examining the state diagram one can see that both transitions have been considered, hence the state diagram is a complete description of the machine. The numbers written on the timing diagram are the states. The next stage is to transfer the information from the state diagram to the flow table. The resulting primitive flow table is shown below: 194 Micro Systems Using the STE Bus Next State (Inputs RAS CAS) Outputs State 00 01 11 10 Ref Mem 1 X 2 1 4 0 0 2 3 2 1 X 0 0 3 3 2 X 4 0 1 4 5 X 1 4 0 0 5 5 2 X 4 1 0 This shows for each state, the combinations of inputs that cause a transition to another state and the outputs of that state. An x in the next state columns indicates a don't care which means this combination of input cannot occur. For example in state 2, if the inputs are both '0', the machine will go to state 3, if the inputs are RAS = '0' and 'CAS = '1 ', the machine will stay in state 2, RAS = '1' and m ='0' cannot occur' etc. The machine has five states, and this could be implemented directly in logic. However, it is possible to reduce the number of states. This is often a good idea as it can result in less logic circuitry. The number of states can be reduced by merging two or more states together. This technique was developed by Hoffman. Two states can be merged if, in each of their next state columns, there is no contradiction (and don't care can mean anything). In this case, states 1 and 2 can be merged: 3 does not contradict x, 2 is the same as 2, 1 the same as 1 and 4 does not contradict x. However, states 3 and 4 cannot be merged: in their first column there is a 3 for state 3 and a 5 for state 4. Figure Al.3 Merger diagram So, each state is compared with each other state to see if they can be merged, and this information is put in a merger diagram. This consists of a series of nodes, one for each state, with lines drawn between those states which can be merged. The merger diagram for this problem is shown in figure A1.3. In order that two or more states can be merged, all of those Appendix 1 195 states must be connected on the merger diagram. In this example, states 1, 2, 3 can be merged and states 1, 4, 5. As state 1 cannot be in both, it is arbitrarily assigned to the first group. Hence the machine can be reduced to two states, A and B, where state A contains the states 1,2 and 3, and state B is made up of states 4 and 5. The reduced flow table is shown below: Next State (RAS CAS) Outputs Ref Mem (RAS CAS) State 00 01 11 10 00 01 11 10 A A A A B 01 00 00 00 B B A A B 10 00 00 00 Note that as a result of the merge, different outputs are possible in each state. Hence the actual output depends both on the state that the machine is in and on the current inputs. In state A, the outputs are both 0 if the inputs are 01 and 11, but the outputs are 01 if the inputs are both 00. (When the input is 10, the machine will change to state B, so the output is undefined.) Thus, in this case, the reduced flow table has more columns than in the primitive flow table. The machine has two states, and these could be represented by two bistables. However, one bistable can be used: if it is '0' then the machine is in state 'A', but if it is '1' the machine is in state 'B '. Let the bistable be called y. RAS RAS RAS RAS RAS RAS y~ vGiili:GJ vGiil:ili] y [ili.[il2] yr2TIID Y[ITiliEJ CAS CAS CAS CAS CAS CAS CAS CAS CAS y Ref Mem Figure Al.4 Karnaugh maps The reduced flow table can now be relabelled and so become a Karnaugh Map (K-map). In fact it becomes three such maps, one for deciding the state and one for each output. These are shown in figure A1.4. Note that this requires just relabelling of the flow table (and splitting the outputs into separate tables) because the combinations of inputs have been written in the Gray code order 00 01 11 10, which is what is required forK-maps. From these maps, the functions for y and the two outputs can be derived easily.

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