HIGH QUALITY RECORDING OF THE SURFACE ECG. DESIGN CONSIDERATIONS FOR A MODULAR BODY POTENTIAL MAPPING SYSTEM
Jizeng SHEN
A Thesis submitted to the University of New South Wales as a requirement for the Degree of Master of Engineering
August, 1993
Supervisor: Associate Professor Branko Celler UNIVERSIT Y OF UX>.\I. 2 M" .Y W UBRAR IBS. Certificate of Originality
I hereby declare that this submission is my own work and that, to the best of my knowledge and belief, it contains no material previously published or written by another person nor material which to a substantial extent has been accepted for the award of any other degree or diploma of the university or other institute of higher learning, except where due acknowledgement is made in the text.
‘oh&VA l 2^VV Jizeng Shen
-ii- Acknowledgments
Although completing this thesis was my own work, I would like to thank many people who helped me in the development of the thesis. Among those I wish to single out are Keith Smith and Kagay Lim, who assisted me in both the hardware design and software development.
Then I would like to thank my family, who have suffered long to support me in this process.
Finally, I'm deeply indebted to my supervisor, Associate Professor Branko Celler, who gave me a great source of motivation and guidance to make this thesis a success. Abstract
This report describes the design of an isolated instrumentation amplifier, developed to be used in a multichannel electrocardiogram (ECG) recording system, such as large body surface mapping system (256 channels), and a flexible interface to communicate between the recording system and the IBM PC host. After discussing the specific properties of ECG preamplifier, the difficulties of meeting the demands of high common-mode rejection ratio (CMRR) with a design based on the classical instrumentation amplifier using three operational amplifiers are reviewed. An analysis of the total CMRR for four cascaded stages preamplifier circuit is earned out and the effects of unmatched operational amplifiers as input stage on CMRR are measured and compared by using different operational amplifiers. The difficulty in achieving the required high CMRR and medical level isolation using commercially available operational amplifiers and optocouplers to build an isolated differential amplifier was discussed. A novel interface to link a multiple ECG body potential system based on the STEbus to a host PC for data analysis and display is also proposed. CONTENTS
Introduction...... 1
CHAPTER 1 - The Main Concept Of The Electrocardiograph...... 3 1.1 Background...... 3 1.2 Lead Systems...... 6 1.2.1 Bipolar Limb Leads...... 6 1.2.2 Unipolar Limb Leads...... 8 1.2.3 Augmented Unipolar Limb Leads...... 10 1.2.4 Unipolar Pericardial Leads...... 12 1.2.5 Frank Lead System...... 13 1.3 Interference And Reduction...... 16 1.3.1 Electrode Effects...... 16 1.3.2 Electromagnetic Effects...... 18 1.3.3 Magnetic Fields...... 19 1.3.4 Electric Fields...... 20 1.3.5 Influence of Common-mode Voltage...... 23 1.3.6 Reduction of Common-mode Voltage...... 25 1.4 Safely and Performance Standards...... 31
CHAPTER 2 - Preamplifier Consideration...... 42 2.1 Design Specification...... 42 2.1.1 Input protection circuit...... 42 2.1.2 Signal Buffering...... 43 2.1.3 Driven Right Leg Circuit...... 43 2.1.4 Instrumentation Amplifiers...... 44 2.1.5 Isolation circuit...... 48 2.2 Defibrillation Protection Circuit...... 49 2.3 Front End Amplifier...... 51 2.3.1 Circuit Gain Calculation...... 52 2.3.2 Circuit Transfer Function...... 54 2.3.3 The Common-mode Rejection Ratio Analysis...... 56 2.4 An Improved Front End Amplifier...... 63 2.4.1 Introduction...... 63 2.4.2 Circuit Transfer Function...... 67 2.4.3 Common-mode Rejection Ratio Calculation...... 69 2.4.4 Experimental Results And Discussion...... 78
CHAPTER 3 - Isolation Consideration...... 84 3.1 Introduction...... 84 3.1.1 Use of Digital Optocoupler...... 84 3.1.2 Linear Optical Isolation Methods...... 86 3.1.3 Bipolar Input Photovoltaic Isolation Amplifier...... 95
3.2 An Isolated Front End Amplifier...... 102
CHAPTER 4 - Design Details and Validation of Performance...... 106 4.1 Design Details...... 106 4.1.1 Devices Selection...... 106 4.1.2 Design of The Bipolar Photovoltaic Isolation Circuit...... 107
4.2 Testing Results...... Ill
-vi- 4.2.1 Common Mode Rejection Ratio of Isolation Preamplifier...... Ill 4.2.2 Preamplifier Frequency Response...... 113 4.2.3 50Hz Interference...... 114 4.2.4 Driven Right Leg...... 116
CHAPTER 5 - Interface Requirements for Body Potential System...... 118 5.1 Data Acquisition...... 118
5.2 Standard Bus Considerations...... 121 5.3 The Host Computer In The System...... 126 5.4 The Bridge...... 126
5.5 Programmable Input and Output Device...... 132
Conclusions...... 137 References...... 140 Appendix...... 147
-vii- INTRODUCTION
Introduction
The recording of an electrocardiogram is a routine medical examination on -the. which diagnosis of normal or abnormal function ofAheart is based. This might suggest an easy and straightforward relationship between the surface ECG signal and the heart's basic electrical activity and consequently a high accuracy of the diagnostic information derived from the recorded signals.
Traditionally electrocardiograms were recorded by standard 12-lead measuring system. However, in present ECG research recording systems with a large number of measuring channels are often required. For example, a body surface mapping system may use as many as 256 channels. Since the development of the microcomputer, the possibility of real time acquisition and the processing of the large amount of data gathered has emerged. However, The proper measurement and amplification of ECG signals in the analogue front end present some specific problems. General amplifier design techniques are well developed and extensively described in the literature. But in the design of multi-channel ECG amplifier much attention should be paid to two requirements to be simultaneously fulfilled, interference rejection and patient safety.
This thesis details the hardware design and analysis of 8 channel# isolation preamplifier which can be used as 8-channel module in the 256 channels body mapping system and also includes thoughts on the computer interface for processing large amount of data gathered in the system.
The thesis has five chapters. In the first chapter of the review the different lead systems and ECG measuring methods are discussed. Chapter 1 also consists of
-1- INTRODUCTION general consideration of various interferences occurring in the measurement and international safety standards that must be met in the design
Chapter 2 analyses the CMRR both in the classical instrumentation amplifier and the improved front end amplifier. To verify the CMRR discussed in theory three experiments were carried out in chapter 2.
Chapter 3 discusses the isolated barrier using optocouplers and analyses the linearity both of the photoconductive isolation amplifier and of the photovoltaic isolation amplifier.
Chapter 4 describes the prototype ECG system, design considerations and technical performance of the system.
Finally, in chapter 5 emphasis is placed on STEbus interface and the communication between the IBM PC and the STEbus interface devices through the
PCLINK, a hardware product supplied by ARCOM CONTROL SYSTEMS to provide a transparent interface for data transfer between the STEbus and the PC,
-2- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH
CHAPTER 1 - The Main Concept Of The Electrocardiograph
1.1 Background
Electrocardiograph is the study of electrical activity associated with the heart muscle, between points either measured directly or derived from points on the body's surface. To better understand the electrical activity of the heart muscle, a basic knowledge of cardiac electrophysiology is required, which is associated with the currents flow in and around cells of the heart.
During heart muscle activity, there are two major electrical processes, depolarisation (activation) and repolarisation (recoveiy). The QRS complex represents ventricular depolarisation and the T wave represents ventricular repolarisation . The process of myocardial cell depolarisation and subsequent repolarisation over the cardiac period results in the movements of charge in the myocardium. These movements of charge produce an electrical field surrounding the heart. The electrocardiogram is a record of the difference of electric potential between two points placed on the body surface in this electrical field.
state. At the resting stage, the myocardial cell is said to be polarised and the interior of the cell contains a high potassium and low sodium concentration [Sil83], [Foz89]. At this time, the cellular membrane prevents sodium ions from crossing but is permeable to the movement of potassium ions. Since the potassium ions cany a positive charge out of the cell, leaving relatively more negative charge inside, an electrical potential difference is created between the inside and outside of the cell. In the resting stage, an equal number of ionic charges of opposite polarity (negative and positive) are present on both sides of the membrane.
-3- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH
When the cell membrane is stimulated electrically and becomes permeable to an influx of sodium ions resulting in a rapid change of the potential difference across the cell membrane, depolarisation occurs. During depolarisation, positive ions precede negative ions, whereas negative ions precede positive ions during repolarisation. Repolarisation occurs immediately following the completion of depolarisation. The outside of the membrane recovers its resting positive charge during repolarisation (see Figure 1.1).
Voltmeter
Muscle strip
(Stimulus) Figure 1.1. This diagram represents the relationship between the spread of depolarisation and repolarisation of a small strip of myocardial muscle placed in a conducting volume and the resulting electrocardiogram recorded from two electrodes, a and b, at a distance from muscle ship. From Medical Physiology [Mil80]. Figure 1.1 shows the charge movements and their corresponding voltage deflections. During the depolarisation and repolarisation processes, the initial stimulus is applied to the left hand side of the ship and excitation spreads towards the right. The depolarisation of the myocardium occurs in a wavefront that can be 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH considered as a set of moving dipoles. The moving dipoles generate the potentials between two electrodes a and b which can be detected by electrocardiogram to show an upward deflection (see Figure 1.1). The magnitude of the voltage deflection is proportional the amount of charge movement represented by the wavefront with respect to time. After the muscle strip has depolarised, a wave of repolarisation is beginning to move from left to right. The direction of the spread of repolarisation is the same direction as the depolarisation but the voltage deflection of the repolarisation is downward. When the entire strip is repolarised, it has returned to S+wfe the resting stage The normal cardiac cycle reflects the sequence of depolarisation and repolarisation in all the muscle strips of the heart and comprises P, QRS and T waves as shown in Figure 1.2. The deflection labelled P is known as the P wave. It normally represents depolarisation of the atria. The duration of the P wave is normal 0.1 sec. The QRS complex follows the P wave by about 0.12 to 0.2 sec, and is generated by the depolarisation of the ventricles. The duration of the QRS complex is approximately 0.08 sec. Following the QRS complex there is a calm period of about 0.1 sec during which the ventricles stay depolarised. This period is known as the ST segment. After the ST segment there is slowly rising deflection called the T wave. The T wave represents repolarisation of the ventricles and is normally 0.2 sec in duration. In some instances the T wave is followed by a relatively small, slow U wave, the origin of which is unknown [Wil80]. Each of the values given above is considerably typically found in adult human subjects, but may vaiy considerable with age and heart rate. -5- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH R 1 i S T k i ! s EGMENf | -T- i• i P i i i • Am i: i As u ■BHInW —^ g i •i i IT Y i )Q t 1.V __ * p- R SJTE m S' —’__ in ! QRST:_ : interval] Q-T | INTERVAL it | | iiil1 1 1 .04 SEC .2 SEC Figure 1.2. Conventional terms for electrocardiographic deflections. 1.2 Lead Systems 1.2.1 Bipolar Limb Leads The electrocardiographic lead is defined as a set of two measuring points on the body's surface with designated polarity, each lead connected either directly or through a passive/active network to recording points. For historical reasons the most commonly used bipolar leads are the bipolar limb leads introduced by Einthoven [Einl3]. These limb leads are in such widespread use that they are referred to as the standard limb leads. -6- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Lead I Leadll Leadill Figure 1.3 The Einthoven Triangle Einthoven proposed that three bipolar limb leads named lead I, lead II and lead III form a triangle around the heart. It is called Einthoven triangle illustrated in Fig 1.3. Lead I is measured between the patient’s left ami (LA) electrode (positive) and his right arm (RA) electrode (negative). Lead II is measured between the patient's right arm electrode (negative) and his left leg (LL) electrode (positive). Lead III is measured between the patient's left arm electrode (negative) and his left leg electrode (positive). Figure 1.4 shows the simplified circuity associated with recording these leads. These three bipolar limb leads can provide potential differences Vn V1}, Vni which can be represented mathematically. Vy 1 =Vy LA -Vy RA V -V —V V11 V LL V RA v III -Vy LL -Vy LA where Vju is the potential measured on the patient's right arm. —— 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Vu is the potential measured on the patient's left arm. VLL is the potential measured on the patient's left leg. The sum of the above equations shows the voltage in lead II is equal to the sum of lead I and lead III, that is rVII -V' 1 +v' yII This is known in electrocardiography as Einthoven's law. Lead I Lead II Lead III Figure 1.4. Bipolar limb leads recording A simplified illustration of the circuitry required to record the three standard limb leads I, II and III. From Comprehensive Electrocardiology [MAC89]. 1.2.2 Unipolar Limb leads The unipolar leads measure the potential difference between an exploring electrode that can be placed anywhere on the body surface and a reference electrode -8- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH derived as the average potential generated in three limb electrodes of the Einthoven triangle. The reference electrode most widely used was introduced by Wilson [Wil34] and called Wilson central terminal. This Wilson central terminal is formed by connecting three limb electrodes through three equal resistors in parallel to a common point. The circuitry associated with this common point connects high input impedance amplifiers to low value resistors and the potential of this common point is mathematically zero. WCT Figure 1.5. Unipolar limb leads recording circuitry The circuitry used to record a unipolar lead in which it can be seen that the potential difference between a single point on the chest and the Wilson central teiminal (WCT) is obtained. From Comprehensive Electrocardiology [MAC89]. According to Kirchhoffs current law, the potential VWCT of Wilson central terminal shown in Figure 1.5 will be: y +y +y V — LA ' ' LL (1 1\ V WCT ^ V1’1/ Since the unipolar lead voltage is the potential difference between an exploring electrode and a reference electrode defined as above, the potential VP obtained from -9- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH the unipolar lead between the exploring electrode P located at the chest and Wilson central terminal can be written as yVP 1 -Vy P -Vv WCT (1.2) Substituting equation (1.1) into (1.2), the potential VP will be v +v +v VP =VP V RA ' y LA ' y LL (1.3) 3 The equation (1.3) describes that with a suitable exploring electrode unipolar leads may be recorded from varying points on the body surface. 1.2.3 Augmented Unipolar Limb Leads The Wilson central terminal is also used to record three augmented leads called aVR, aVL and aVF by placing the exploring electrode on right aim, left aim and left leg, respectively, in order to increase the potential measured by the standard limb leads. If the exploring electrode is placed on one of three limbs, then the reference electrode potential will be the average of the potentials at remaining two limbs. In the case shown in Fig 1.6, the potential of augmented unipolar lead aVR, according to Kirchhoff s current law, can be obtained as follow: -10- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH uyaVR 1K - vV RA -Vy GT (1.4) This means that the augmented leads produce 50% higher voltages than the standard limb leads and it contains the same information as the standard limb leads have. R GT £> Figure 1.6 Augmented limb leads recording circuity The circuity used to derive the augmented unipolar limb lead aVR. GT denotes the Goldberger terminal for this particular lead. Note that the right arm electrode, which is effectively the exploring electrode in this particular lead, is connected to the positive terminal of the galvanometer. From Comprehensive Electrocardiology [MAC89] 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH 1.2.4 Unipolar Pericardial Leads The unipolar precordial leads are measured between the exploring electrode placed on the anterior chest wall near the heart and the reference electrode connected to the Wilson central terminal. The most commonly used precordial leads are six unipolar chest leads named VI, V2, V3, V4, V5 and V6 which were selected by the American Heart Association Committee in order to standardise recording. Lead V1 is located in the fourth intercostal space at the right sternal border. Lead 2 is positioned similarly but to the left of the sternum. Lead V4 is located in the fifth intercostal space along the left midclavicular line. Lead V3 is positioned half way between V2 and V4. Lead V5 and V6 are in the fifth intercostal space along the left anterior and midaxillary lines, respectively. The position of the precordial leads are shown in Fig 1.7. Midclavicular j Anterior axillary Midaxillary Figure 1.7 A schematic of the chest wall viewed with the subject in a slight left anterior oblique position. The precordial locations of leads VI to V6 are illustrated. -12- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH The combination of the three bipolar limb leads I, II and III, the three augmented unipolar limb leads aVR, aVL and aVF, and the six unipolar precordial leads V1 to V6 is known as the standard 12-lead ECG system. Almost all ECGs recorded worldwide make use of these 12 leads. 1.2.5 Frank Lead System In order to detect the wave of cardiac electrical activity in three dimensional space, an approximate orthogonal lead set is necessary to establish the position and rotation in three dimensions of the cardiac vector over the cardiac period. The interpretation of the 'dynamics' of the ECG can be performed by this way. A number of investigators [Fra56], [Mcf50], [Scl86], [Wil47], [Gri52], proposed solutions for designing lead system which would measure the three orthogonal components of the in an cardiac vector. Some of these system use image spaceAattempt to compensate for distortion to the electric field due to the body's shape [Fra56], [Mcf50], [Scl86]. The result of Frank's studies was the development of a collected orthogonal lead system which implies that the lead vectors associated with the system were indeed orthogonal in three dimensional space. This system is probably the most popular lead system for vectorcardiography though it was derived from the image surface of the body of a man-like dummy filled with tap water. It is of interest to note that this system derived from the image surface of dummy may be difficult to apply electr odes properly in all patients as the dummy may not have been a very accurate model for different potentials for all the different body shapes of patients. In developing the image space of the body. Frank noted that some regions had large potential gradients, such as the left ami pit and shoulder. In order to avoid those regions of the body where small errors electrode placement could result in large -13- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH errors in the orientation of the corresponding image surface point, Frank used seven electrodes and a resistor network (see Figure 1.8). RIGHT J.27R 3.74 R |-----WWV4V----- front BACK 2.90 R Figure 1.8. Electrodes and circuitry of the Frank lead system For the electrode positions Frank initially indicated that the electrodes should be placed at a level corresponding to the electrical centre of the heart and described a mechanism for finding such a position [Fra56]. In early studies the fourth intercostal space was used [Dra64]. More recently, it has become accepted to use the fifth intercostal space [Nem78]. In Figure 1.8, A and I are positioned in the left and right midaxillary lines, respectively. E and M are positioned on the sternum and spine, respectively. C is positioned such that an angle of 45° is produced with respect to the centre of the thorax. H is placed on the back of the neck. Figure 1.9 shows how the three orthogonal leads were derived. It can be seen from these two figures the length of each lead vector is not the same, with the Y lead vector being the smallest. In order to have equal length of the lead vectors Frank used shunt resistor of 7.157? and 13.37? to reduce the gains of the X and Z -1 4- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH leads respectively so that each lead vector equalled 136 units (see Fig 1.8 resistor network) anatomic, space image space SAGITTAL 174- UNITS -loo IMAGE VECTOR Figure 1.9 Using image space to obtain the resistor network. From Frank [Fra56] The Frank leads system has been useful to determine that the path traced by the cardiac vector through its period tends to lie in a single plane in space. By rotating -1 5- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH the coordinate axes in space it is possible to view the cardiac vector along this principle plane. The intrinsic properties of the loop may then be studied and compared with any normal deviations of position from the plane. 1.3 Interference and Reduction The puipose of this section is to discuss the theoretical and practical problems associated with the technology of recording the electrocardiogram. As explained earlier, the electric depolarisation and repolarisation of myocardial cell results in movements of charge and an electrical field surrounding the heart. Such an electrical process within the heart can generate potential differences between different parts of the body's surface and the potential differences also can be measured by electrodes placed on the body. However, the signal picked up by electrodes is small and may be distorted by internal and external noise when it is fed into an amplifier for recording. The development of high-fidelity signals subject to low interference and minimum signal distortion is required. The following discussion is on interference and noise sources and how to reduce their influence. 1.3.1 Electrode Effects The electrode effects have been discussed by a number of investigators [Neu78], [Gat74], [Ged68], [Swa74]. They also described equivalent electric circuits for the complete electrode/skin interface, which can cause offset voltage and frequency dependent impedances. In considering the frequency range of interest for bioelectric signals (0.05-1000Hz), the complicated equivalent circuit of the electrode model can be greatly simplified. -16- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH In Figure 1.11, the equivalent resistor Req includes the electrolyte and the body fluid resistance, the resistance Rs represents the resistance of the skin-electrode interface, the capacitance Cs is a function of skin/electrolyte contact area, electrolyte concentration and skin condition, the voltage Vm is formed by the electrode potential at the metal-electrolyte interface and polarisation voltages. Figure 1.11. The simplified equivalent circuit of the skin electrode interface. Resistors and a capacitor form a frequency dependent impedance. From Comprehensive Electrocardiology [ZYW89] In this model, the parameters of different routine ECG electrodes, resistance and capacitance as well as voltage, can vary considerably. In the complete electrode/skin interface, electrode impedance mainly depends on skin preparation and offset voltages reflect only the differences of the electrode potentials. Obviously, the electrode impedance can be reduced by adequate skin preparation and offset voltages can be limited by using the same type of electrode, since differences in the production process may cause electrode potential differences. Zywietz [Zyw89] pointed out the silver/silver chloride electrode has the best performance because of offset voltages as low as around lOmV and electrode impedance between 50-100£0. -1 7- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH 1.3.2 Electromagnetic Effects The effect of coupling external electromagnetic source into the measurement circuit is called interference and the most common interference is from the 50Hz power line. Magnetic fields produced by alternating currents can cause an induced interference voltage in the loop formed by the measuring cables (see figure 1.12). Electric field Cpow ~L ac magnetic field ECG differential amplifier Loop area S isolated mplifier common Cisoi- non-isolated Ground Figure 1.12. Diagram of ECG measurements. The ECG measured on the body surface may be distorted by external noise. In a non isolated situation the amplifier common is connected to ground (switch closed). -18- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Electric fields produced by different electric potentials can cause a displacement current. This displacement current through the body to ground may cause an interference voltage across the body impedance between two measuring electrodes and it also produces a common-mode voltage between measuring electrodes and ground electrode. This common-mode voltage may be partly transformed into differential voltage by imbalance of the electrode impedances and limited common mode rejection ratio of the amplifier. 1.3.3 Magnetic Fields According to Faraday's law, an alternating magnetic field produced by alternating currents ijiay generates an electromotive force in any conductive loop and the magnitude of magnetically induced voltage is proportional to the loop area and the magnetic flux density. Obviously it is a easy way to suppress the magnetically induced interference voltage in ECG measurement by reducing the loop area as much as possible, which is formed by the measurement cables. The common way is bundling the lead cables and running the lead cables close to the body to reduce the loop area. But bundling the lead cables can not totally cancel out the loop area because the measuring cables connected to electrodes placed on different positions of the body will still have a considerable loop area. Another way to reduce the effect of magnetic field is to keep all magnetic sources, especially the alternating mains power with 50Hz, far from the patient and shielding the magnetic sources to lower the magnetic flux density. In practice, two methods mentioned above should be applied together in order to keep the magnetically induced interference voltage as small as possible. -19- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH 1.3.4 Electric Fields Electric fields caused by different electric potentials between power lines and the body, the body and ground, result in a displacement current. Because the stray capacitances exist between the different electric potentials, the displacement current z, enters directly into the body through the stray capacitance Cpow and pass through the impedance of ground electrode Zrl in a non-isolated system or pass through ZA and capacitance Ciso between the amplifier common and earth in an isolated system as shown in Figure 1.12. This current z, through the body will produce a high common-mode voltage. In non-isolated system (see Figure 1.13), the displacement current z, through the impedance Zrl can cause a common-mode voltage VCM and it also causes a differential voltage at body impedance Z, between two measuring electrodes A and B. Cpow zz sF Zib ;> Zia Figure 1.13. The non-isolated equivalent electric circuit of Figure 1.12. The ECG signal is picked up between electrodes A and B. Across the grounding impedance Zrl the common mode voltage VCM is produced -20- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH However, the body impedance which is approximately 100f2 is much smaller then the impedance Zrl which is approximately 50K. The differential voltage of body impedance can be neglected. Hence, the common-mode voltage VCM produced by current z'j can be described by following equations. V V V V CM r CM _j_ v CM _ j (1.5) z.rl zea +zla zebh +z.tbh 1 where Zia and Zib are input impedances, Zea and Zeh are electrode impedances. In most situation, it can be accepted that input impedances Zia, Zib is much greater than electrode impedances Zea,Zeb. So the equation (1.5) can be written as Vcm V,CM V,CM + z,„ + ■ z. = /, (1.6) If the input impedances Zia, Zih were complete balance, that is if Zxa - Zib = ZIN, then the common-mode voltage VCM is Z Z y - ^rl^lN • (1.7) CM ^INZ +2Z^ 1 In this equation (1.7), it can be seen that increasing input impedance Z1N will increase common-mode voltage VCM. Usually, the input impedance ZIN is much greater then Zrl. Thus, the common mode voltage in non-isolated system can be expressed as v CM —-il \^riZ (1.8) -21- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Equation (1.8) shows that low common mode voltages are possible if the impedance Zr/ is low and the displacement current q is small (the capacitance Cpow is small). But the low impedance path between body and earth will bring the patient into a potentially unsafe situation. The isolated system in which the amplifier common is not connected directly to ground (switch open in Fig. 1.12) is very safe if the capacitance Ciso between the amplifier common and ground is kept sufficiently small (in Fig 1.14 Zs is the impedance of capacitance Ciso). Cpow zz Zib > Zia Amp common 1.12. Figure 1.14. The isolated equivalent electric circuit of Figure-Sd*. In isolated system shown in Fig. 1.14, if the differential voltage of the body impedance can be neglected and input impedances Zja,Zjb are much greater then electrodes impedances Zea, Zeh as discussed above, the common-mode voltage VCM caused by displacement current q can be obtained -22- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH % 1 Z Z K __ i and CM z +z +z 1 (1.9) where Zfc is the impedance of stray capacitance Cbody and Zs is the impedance of capacitance Ciso between the amplifier common and ground. Comparing equations (1.9) and (1.8) it can be seen that the common-mode voltage VCM in the isolated system can be significantly lower then in the non-isolated system, if the impedance Zs is much greater then Zb, that is, the capacitance Ciso is much smaller then Cbody. 1.3.5 Influence of Common-mode Voltage Equation (1.8) and (1.9) shows that the displacement current il can produce common-mode voltages both in non-isolated system and isolated system. This common-mode voltage can be transformed into differential voltage due to the imbalance of the electrode impedances. In non-isolated system, see Fig. 1.13, this differential voltage VD can be calculated as follows v V - (___CM__w 1N] {zea +zla " v v - (_____ )Z IN2 ’V D -Vv IN\ -Vv IN2 -23- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH If the input impedances of amplifier were perfect, that is Zta - Zjb = ZIN, (Zeb-ZJZL VD = ■V,CM (Zea +ZlN)(Zeb+ZIN) In most situation, the input impedance ZIN is much greater then electrodes zeaizeb• The above expression can be further simplified as follows: (1.10) The equation (1.10) shows that the higher electrode impedances imbalance is, the larger interfering differential voltage will be transformed from common-mode voltage. Substituting equation (1.7) into equation (1.10), the differential voltage will be / Zebeh_____ ~ Z£„ 7 7 VD~ -)c >1 ^Z IN ^+2Z rl and w (Zeb Zea ) Zrl ■ (1.11) (ZIN +2Zrl) The equation (1.11) shows that a high input impedance ZJN may reduce this interfering differential voltage, though the high input impedance may cause a high common-mode voltage as shown in the equation (1.7). -24- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Since the common-mode rejection ratio CMRR of differential amplifier is limited, typically 60-120dB, a small part of common-mode voltage can be transformed into an interfering differential voltage by the differential amplifier itself. With the ability of the amplifier to reject common-mode voltage, the interfering differential voltage VD will be considered as follows, (z*-zt VD* + ■ CM KZ1N+2Zrl CMRR )K In isolated system shown in Fig. 1.14, the interfering differential voltage caused by common-mode voltage was analysed in detail by Pallas-Amey [Pal88]. In his work, this differential mode interference is mainly produced by two different sources. One is produced by the displacement current coming through the body impedance between two electrodes. Another is the differential voltage transformed by the common-mode voltage due to the imbalance in the front end of the amplifier. Hence, the interfering differential voltage can be written as ^b^rl Zeb Zea + Z{ VD*( zt + (1.12) + Z]N 1.3.6 Reduction of Common-mode Voltage As discussed above, the electrode impedance imbalance and limited common- mode voltage rejection ratio of amplifiers may transform the common-mode voltage into interfering differential voltage. The common-mode voltage is mainly generated by (i) the displacement current flowing from the power supply through the patient to ground and (ii) the interference current induced in the measurement cables, which is -25- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH caused by the capacitive coupling of the measurement cables with the power supply. If the common-mode voltage can be kept sufficiently low, the interfering differential voltage will be reduced significantly. Equation 1.8 shows that the common-mode voltage VCM is the function of impedance of ground electrode Zrl and the displacement current /,. So if the impedance Zrl can be reduced and the current q can be kept small, the common-mode voltage will be lower. There are three common methods to reduce this common-mode voltage. (a) One of the most practical and effective methods to reduce common mode voltage is driven-right-leg circuit shown in Fig. 1.15 which feeds back an average part of common-mode voltage came from limb lead electrodes to drive the patient carrying the same voltage as the voltage at the amplifier common. Thus, the voltage difference between patient and the amplifier common, that is the common-mode voltage, is reduced greatly. Usually, a reduction can be achieved from 10 to 50dB [Met90]. -26- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Input 2 Instrumentation Amplifier Amp Common Cs _i“ Ground Figure. 1.15 A typical driven-right-leg circuit in dotted line. Switch S, in the upper position will further reduce Vcm by compensating for the voltage loss that occurs across [Win83]. The driven right leg circuit has been analysed by Winter and Webster in detail [Win83]. Fig. 1.35 shows the driven right leg circuit connecting with the impedance of third electrode Zrl which is connected to patient right leg. Cs is the stray capacitance between the amplifier common and earth ground, and Ra is a current- limiting. resistor. The average input voltage of the driven right leg circuit is equal to the common-mode voltage VCM, if the front end of differential amplifier were perfect. From Fig. 1.15, the relationship between common-mode voltage and the displacement current can be described by following equations. va,-V*+Wi = v. (1.13) K = ~GVcm (1.14) -27- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH V-CMm = Z1+G',+R ° L2 V(1.15) > where, and the cunent i2 is nearly equal to the displacement current /, as the circuit provides a low impedance path and allows a safe amount of cunent to flow through the electrode. G is the gain of driven right leg circuit VQ is the output voltage of driven right leg circuit Comparing equation (1.15) with equation (1.8), it can be seen that the common mode voltage can be reduced significantly by driven right leg circuit, if the circuit has high gain G. But a high gain can cause the circuit instability because the closed loop system with driven right leg circuit may introduce a phase shift of -180°. In order to obtain a stable driven right leg circuit with high gain, Winter and Webster introduce a simple compensation of phase shift, that is, the driven right leg circuit is designed as an integrator, because the integrator will produce a phase shift of 90°. In Fig. 1.15, if the feedback resistor Rf is replaced by a capacitor, and the driven right leg circuit acts as an integrator. (b) Another method of reducing the common-mode voltage is by shielding the measurement cables to eliminate interference currents in the cables. A simple method to suppress directly the interference cunent in the cables is connecting the shields of cable to the amplifier common. This method enables the interference current to flow to the amplifier common without going through the differential amplifier. But it does not reduce any capacitance of shielded cable. However, the -28- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH shielded cable will present a large capacitance and this capacitance in parallel with the input impedance of the amplifier may reduce the input impedance (see Fig. 1.16). W-O------~T> A/VM3------Q Instrumentation Amplifier Common driven right leg amplifier Figure 1.16. Shields connected to amplifier common According to the equation (1.10), lower input impedance ZIN may increase the interfering differential voltage transformed from common-mode voltage. In the ECG measurement system with driven right leg circuit, this capacitance of shielded cable easily results in instability of the system since this capacitance introduces an RC stage with electrode resistance and results in a phase shift in the system. If a shield is driven with the input signals at the inner cable, the effect of capacitance of shielded cable can be negligible, since there is no potential difference between inner and outer cable. Hence, this method eliminates the effect of the input impedance caused by the capacitance of shielded cable and the system instability. It can be done by a extra amplifier feeding a positive part of the average signal picked up from the limb leads to the shielding or by a unity gain amplifier feeding back a signal obtained from one lead cable to the shielding for each cable shield separately, especially in multi-channel recording system (Fig 1.17). -29- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Input 2 ----W------(9------Input n 10K 100 Lav—A d Figure 1.17 Shielding multi-channel with unity gain buffer (c) From equation (1.8) and (1.9) it is clear that the common-mode voltage in both non-isolated and isolated systems is mainly introduced by a capacitive displacement current ix flowing through the patient. In non-isolated measurement the value of displacement current ix is largely determined by the capacitance Cpow (see Fig 1.12). If the capacitance Cpow can be minimised and the impedance Zrl is small, the common-mode voltage can be kept sufficiently low. However, the low impedance path between patient and ground will introduces a potentially unsafe situation. The problem associated with patient urfsafety can be overcome by use of patient isolation circuits. In equation (1.9) if the capacitance between the amplifier common and ground Ciso can be made low enough, and Ciso is much smaller than the capacitance between the patient and ground C, that is Zs is much larger than Zb, the common mode voltage will be small and much lower than in the non-isolated measurement, comparing equation.(1.9) with (1.8). -30- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH 1.4 Safety and Performance Standards All medical equipment should conform to the relevant national and international safety and performance standards before they are used in any clinical situation. This requires proper design with tolerance against electrical shock and suitable results for comparison with empirical results in diagnosis. Electrical defibrillation should not damage the preamplifier circuit for example, and a rapid system recovery is necessary for continuing the ECG recording within a reasonable time. For safety the patient must be protected from all kinds of electrical shocks which are potentially possible when the patient is being monitored. There are two main standard and recommendation documents for the device of electrocardiogram. One is the American Heart Association (AHA) recommendation of 1975 and the other is the Association for the Advancement of Medical Instrumentation, American National Standards Institute (AAMI/ANSI) of 1983. It is noteworthy that recommendations and standards are different when applied to a design. Recommendations are user desired performance requirements which do not necessarily conform to performance specifications of design. Consequently recommendations are proposed by national and international organisations like the committee on Electrocardiography of the AHA. However, standards are usually minimum performance requirements agreed on between different manufacturers and users. The recommendations and standards that are relevant to electrocardiography are summarised as follows: Input Dynamic Range AAMI/ANSI Value and Description -31- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH DEFINITION: The ECG device shall be capable of responding to and displaying differential voltage of +/-5mV vaiying at a rate of up to 320mV/sec from a DC offset voltage of +/-300mV applied to any lead. AHA Value and Description DEFINITION: 400mV/sec is assumed to be the maximum rate of change of an ECG, which must be reproduced to a 5% accuracy. +/-7mV signals with respect to the baseline must be reproduced accurately RATIONALE: The ECG preamplifier should be capable of amplifying the input differential signal ranging in amplitude up to +/- 5mV and handing the dc offset voltage of up to +/- 300mV, which is produced by electrode-skin interface. The preamplifier should also meet the maximum rate of change of input signal with a reproduced accuracy. Gain Accuracy AAMI/ANSI Value and Description DEFINITION: 5 percent, providing fixed gain selections of 20mm/mV, lOmm/mV and 5mm/mV. RATIONALE: For each position of the fixed gain selection the gain error should be less than +/- 5% of the selected gain. For example, if the gain is set at lOmm/mV, the gain error should not exceed +/- 0.5mm. -32- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH System error AAMI/ANSI Value and Description DEFINITION: In put signals limited in amplitude to +/-5mV and rate of change of 125mV/sec, shall be reproduced on the output recording with a maximum instantaneous deviation from the ideal of +/-10% or 50uV, whichever is greater. RATIONALE: This defines the maximum allowable overshoot in the pen recording system. Frequency Response AAMI/ANSI Value and Description DEFINITION: The instrument must meet the requirement of either A, B and C, or A, C, and D of table 1.1. Input Method Input Frequency & Waveform Output Response Amplitude A 1.0mV (P-P) 0.5 - 40 Hz sinusoidal +/- 10 % 1 B 0.5mV (P-P) 40- 100 Hz sinusoidal + 10 %, - 30 % 1 C 0.5mV (P-P) 100 - 500 Hz sinusoidal + 10 %, - 100 % 1 D 1.5mV (P-P) < = 1 Hz, 200msec, triangular + 0,-20 % 2 1 2 relative to 10 Hz output relative to 200 msec output For method A, B and C the output response is relative to that obtained at 10 Hz. For method D, the output response is relative to that obtained for a repetitive, -33- 1 -THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH triangular wave signal with a base width of 200msec and a repetition rate of 1 Hz or less as shown in Fig. 1.18 200mS ◄------► > = 1sec ◄------> Figure 1.18 - Triangular wave signal for method D AHA Value and Description DEFINITION: The frequency response should be from 0.05 Hz to 100Hz +0.5dB, -3dB. RATIONALE: Although the lowest clinically encountered heart rate is reported to be 30 beats per minute [Tay83], one decade low frequency cutoff of 0.05Hz will reduce phase distortion. In an input and output system, the transfer function consists of two components: the amplitude response and phase response. In order to obtain high fidelity reproduction of signal, an adequate phase response, that is a linear relationship between frequency and phase angle, is required. Usually this linear relationship changes at the cutoff frequencies and causes signal distortion. It is considered necessary to expand the bandwidth to eliminate the signal distortion. Step Response AAMI/ANSI Value and Description -34- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH DEFINITION: The device shall response to a step voltage input so as to provide a deflection of 10mm, with an allowable overshoot of 10% or less, and with decay time constant of 3 sec or greater, when measured during the first 320msec. RATIONALE: The ECG preamplifier system usually contains an equivalent capacitance, which can store energy. If a step voltage in the dc offset is applied to the input, the output voltage may have some delay. Hence, an acceptable recovery time is required for the preamplifier system when it is switched from one lead to another. Input Impedance AAMI/ANSI Value and Description DEFINITION: A single-ended input impedance of at least 2.5Mohm at 10Hz is required. RATIONALE: The input impedance is an important figure for the ECG preamplifier. Because of the voltage division between electrode impedance and amplifier input impedance, the electrode impedance imbalance can produce a differential interference at the amplifier input. In order to reduce this interference, a larger input impedance with respect to electrode impedance is required. The value of input impedance should ensure that the electrode impedance imbalance does not affect the input signal. -35- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Direct Current in Patient Electrode Connections AAMI/ANSI Value and Description DEFINITION: Not exceeding 0.2uA RATIONALE: The direct currents flowing in a patient between the applied part and other sources must be limited to values not intended to produce a physiological effect. The bias current of the biopotential amplifier which may cause DC offset voltages is one of the direct currents for example. Common Mode Rejection AAMI/ANSI Value and Description DEFINITION: The ECG device shall have the capability of rejecting 50/60Hz common mode interference voltages as encountered on the surface of the body. With all patient electrode connections connected to a common node and with the RL (OV) lead (if supplied), connected through 51Kohm resistor in parallel with a 47nF capacitor to the common node, a 60Hz, 20Vrms signal applied to the common node through a lOOpF capacitor shall not produce an output signal exceeding lmV p-p referred to input over a 60 sec period. This requirement shall be met with sequential shorting of the series-impedance-simulating lead imbalance in each active lead with a dc offset potential placed in series with any patient electrode connection as specified in (1). -36- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH RATIONALE: The common mode voltages are mainly introduced by capacitive displacement current flowing the patient through the stray capacitances between the patient and main power system. This common mode voltage can be reduced by driven right leg circuit, high amplifier input impedance and good matched electrode impedances. It also can be rejected by the design of the input preamplifier. System Noise AAMI/ANSI Value and Description DEFINITION: Noise due to all patient cables, all internal circuits and output displays shall not exceed 40uV p-p over any 60 second period, when all inputs are connected together through a 51Kohm resistor in parallel with a 47nF capacitor in series with each patient electrode connection. RATIONALE: Each electronic element including active and passive element like amplifier, resistor, capacitor, and so on, can cause noise itself. The noise level depends on bandwidth. The noise level recommended by the AAMI standard refers to a bandwidth of at least 0.5 - 100Hz. Channel Crosstalk AAMI/ANSI Value and Description DEFINITION: Input signals limited in amplitude and rate of change as per Dynamic Range Specification, applied to any lead of a multichannel device, with all other inputs connected to a patient reference through a 51Kohm resistor in parallel -37- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH with a 47nF capacitor, shall not produce unwanted output greater than 2% that of the channel to which the input is applied. RATIONALE: In multi-channel system, the change in any one lead driven by any other lead does not exceed the allowable value. Baseline Control and Stability AAMI/ANSI Value and Description DEFINITION: A IV p-p 60 Hz overload voltage shall be applied for at least 1 sec to any lead. After removal of this voltage, provision shall be available to restore a lmV p-p trace to the recording width of the display within 3 sec. The baseline drift at the output shall not exceed lOuV/sec RTI over any 10-sec period. In addition the total baseline drift shall not exceed 500uV RTI in any 2 minute period, the device shall incorporate means to return the output trace to within 3mm of the baseline within 1 sec of switching leads. RATIONALE: A stable baseline is necessaiy to avoid saturation of the write-out system as well as of any other data storage systems connected. The ECG amplifier should have a baseline drift control to correct the baseline drift. Defibrillator Overload Protection AAMI/ANSI Value and Description -38- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH DEFINITION: The device shall recover within 8 sec after exposure of any patient connector/lead combination to simulator discharges having a damped sinusoidal waveform. A 16uF, high voltage capacitor is charged to >=5000V(for an energy delivery of 360 joules), and the capacitor is discharged against the patient's chest through a lOOmH inductor and two large metal electrodes. The patient may be simulated by a 50 ohm resistor, with 400 ohms interposed between the 50 ohm defibrillator load and one connection of the ECG device. After this test, the device should continue to perform to the other standards. Pw.n’n| RATIONALE: A3 many clinical measurement the patient may need to be defibrillated. After the defibrillation the ECG measuring system should be able to recover the cardiac monitoring within 8 sec. Pacemaker Pulse Display Capability AAMI/ANSI Value and Description DEFINITION: The device shall have the capability of displaying the ECG signal in the presence of pacemaker pulses with amplitudes between 2 and 250mV, duration between 0.1 and 2.0msec and a rise time of less than lOOusec, and a frequency of 100 pulses/min. For pacemaker pulses having duration between 0.5 and 2.0 msec, an indication of the pulse should be visible on the recording with an amplitude of at least 0.2mV RTI. RATIONALE: These conditions simulate the effect of a pacemaker on the biopotential amplifier. The ECG measuring system must have the capability of recording the pacemaker's output. -39- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH Patient Risk Currents AAMI/ANSI Value and Description DEFINITION: No more than lOuA of direct current may flow through the patient in the event of various mains power faults, as specified in the European standard IEC 601.1. RATIONALE: Electrical microshock usually result from leakage currents in line-operated equipment or from voltage differences between grounding points in the grounding system. The problem is that at small contact area, small currents produce high current density at the point of contact. The end result could be anything from ventricular fibrillation to burning. Digital System Performance AAMI/ANSI Value and Description DEFINITION: Recommends 500Hz sampling with lOuV resolution, and <1 msec difference in simultaneous sampling of each channel. RATIONALE: The adequate sampling rate are mainly based on compromises between the amount of data to be processed and the desired signal resolution. According to the Nyquist sampling theorem the necessary sampling frequency for accurate digital representation of a signal should be equal or larger than twice the highest frequency component of the spectrum of the signal. However, it is difficult to estimate the highest frequency component of the ECG signal due to tiny -40- 1-THE MAIN CONCEPT OF THE ELECTROCARDIOGRAPH waveforms of the signal in amplitude containing high frequency components. So, with the bandwidth of 100Hz (see Frequency response recommended by AHA) a 500Hz sampling rate is enough. In multi-channel system the ECG waveforms are measured simultaneously. Actually any one processing element could not perform more than one process at any one time. Hence, if the processing element is switched from one channel to the other, a delay will be created. It is necessary to specify the maximum delay to ensure that all channel records can be compared. -41- 2-PREAMPLIFIER CONSIDERATIONS CHAPTER 2 - Preamplifier Considerations 2.1 Design Specification The development of electrocardiography as an indispensable diagnostic tool in cardiology requires relevant performance specifications to satisfy the appropriate Australian and International Medical Equipment Standards and to meet the flexible and high fidelity signal analysis tool that can be used for the real time electrocardiogram. The overall performance specifications are divided into five categories: input protection circuit specifications, signal buffering specifications, driven right leg circuit specifications, instrumentation amplifiers and analogue isolation barrier specifications. These specifications mentioned above will be discussed as follows. 2.1.1 Defibrillation protection circuit According to AS3200.1-1990, the instrument should be able to withstand large defibrillation voltages. Defibrillation is a kind of electric shock to the heart, which can be used to reestablish a more normal cardiac rhythm, and is earned out by passing current through electrodes placed directly on the heart. A typical defibrillator can deliver up to 400 Joules of energy and high voltages (5000V) which is greatly in excess of the common mode range of the input amplifier circuit. In order to ensure that the electrocardiograph can operate with a defibrillator without damaging the instrumentation, a protective circuit is required at the input of an electrocardiograph. In a basic arrangement of protective circuit, a series -42- 2-PREAMPLIFIER CONSIDERATIONS resistance will be required to limit the current through the preamplifier of the instrumentation and ensure that the least resistance path will be through the body, that is, the energy of defibrillation pulses is delivered to the patient and not the instrumentation. Limiting voltage devices should be also considered in the protective circuit to prevent very high voltage caused by defibrillator from damaging the instrumentation. 2.1.2 Signal Buffering Because of the high and unstable impedance of electrodes, a buffer amplifier should be attached directly to the electrode for transformation of the high and often unbalanced electrode impedance to a low level. Usually the gain of buffer is one. For the unipolar chest leads and the augmented limb leads a resistance network is required to obtain the Wilson central terminal (WCT) which presents a reference terminal at the input of the instrumentation amplifier. To eliminate the influence of impedance of electrode on the resistance network each input lead will require buffering so that a low impedance driven by the buffer amplifier will be presented at the input of the resistance network. A buffer amplifier with veiy high input impedance also provides minimal loading of the signal being measured to isolate the load from the source. 2.1.3 Driven Right Leg Circuit The common mode noise introduced from the environment, that is, from the mains-power system can heavily distort the ECG signal. Consequently in ECG -43- 2-PREAMPLIFIER CONSIDERATIONS measurements which do not adequately reject the common mode noise failure is guaranteed. Normally the common mode noise can be reduced by the differential instrumentation amplifier. But the amplifier itself does not operate ideally, having a finite common mode rejection ratio. One method of further reducing common mode to noise voltage isAcancel out the common mode voltage at the source itself. The driven right leg circuit can feed back an average common mode voltage picked up by limb lead electrodes onto the body and force the common mode voltage close to the isolated ground of the amplifier. Thus the source of common mode noise can be reduced significantly. The driven right leg circuit is also valuable in the safety purpose. If an abnormally high voltage presents between the patient and ground due to leakage current, the circuit will be saturated. If the current limiting resistor in the circuit is large enough, the patient will be safe. 2.1.4 Instrumentation Amplifiers The instrumentation amplifier as an essential part of ECG recording system is required to satisfy certain performance specifications. The most relevant performance specifications are summarised as follows. • Input voltage range and gain The amplitude of signal measured directly on the patient may range# from microvolts to millivolts. According to AAMI standards, the amplifier must be able to amplifier differential input voltages +/- 5mV. The DC offset caused by electrode- -44- 2-PREAMPLIFIER CONSIDERATIONS skin interface as pointed out in section 1.3.1 can reach up to several hundred millivolts. The AAMI standards recommends a maximum DC offset voltage of +/- 300mV. Hence, to prevent preamplifier saturation the ECG amplifier should be capable of cancelling such DC offset voltages. To provide the best signal amplitude to take advantage of the full dynamic range, the total gain of the ECG amplifier may be set a range from 500 to 1000 to provide 0.5 to 1.0V output voltage per millivolt input. • Input impedance The electrode skin interface has a complex impedance between 1 k£l and 1MQ at 50Hz [Alm70], [Ged72], [Gri83], [Ros88]. As has been pointed out in equations 1.10 and 1.12, large differences between the electrode skin impedances can cause a large interfering differential voltage which is transformed from common mode voltage. However, if the input impedance of amplifier is much larger than electrode impedance, the influence of imbalance of electrode impedance will be reduced. A high input impedance amplifier is also important with respect to distortion of the input signal. In Figure 1.13, if the input impedances Zia and Zib are equal to Z1N, the electrode impedances Zea and Zeh are equal to ZE, the voltage V1 at front of the amplifier can be expressed as: 'IN ( . ) K=( WiECG 2 1 Z,„ + 1E where VECG is the source of the ECG signal -45- 2-PREAMPLIFIER CONSIDERATIONS where VECG is the source of the ECG signal Equation 2.1 shows that because of voltage division the voltage Vj obtained at front of the amplifier depend on the ratio of electrode impedance to the amplifier input impedance. Hence, low input impedance of amplifier ZIN may cause input voltage reduction. Another effect of amplifier input impedance is due to the ZE and Z1N are frequency dependent impedance, the different frequency components of the ECG signal will cause signal distortion both from amplitude frequency response and phase response. So, the amplifier input impedance must be much higher with respect to electrode impedance to reduce such signal distortion. • AC coupling The DC offset voltage arising from electrode skin interface is normally much higher in magnitude than the expected signal to be measured. Furthermore, for a low noise design, it is important to have as much gain as possible in the first stage of the amplifier to obtain a high common mode rejection ratio. For these reasons, a AC coupling removing DC offset voltage to prevent saturation of amplifier must be taken into consideration. In order to transfer low frequencies of the ECG signal without serious distortion, particularly the STrT segment, AHA standards recommends that the lower -3dB comer frequency should be at 0.05Hz. Although the lowest clinically encountered heart rate is reported to be 30 beats per minute [Tay83] and the fundamental frequency for an ECG would be set at 0.5Hz, a low frequency cutoff of 0.05Hz at one decade down at 0.5Hz will reduce phase distortion. Because the transfer function of AC coupling introduces -46- 2-PREAMPLIFIER CONSIDERATIONS distortion. To solve this problem the bandwidth can be expanded. Therefore, it is necessary to ensure that the lower cutoff frequency of AC coupling does not exceed 0.05Hz. • Frequency response The term bandwidth means the difference between the highest and the lowest frequency component to be transferred. The amplifier bandwidth is defined as the range between the lower and upper cutoff frequency of an amplifier where the magnitude of the amplifier transfer function becomes below 0.707. A number of investigators [Ker53], [Lan60], [Sch78], [Ber66], [Nic85], [Rig79] have analysed in detail the frequency content of the ECG. As a result it can be concluded that for ECG amplifiers used in routine equipment a bandwidth of 0.05 to 1000Hz is sufficient. Note the frequency response of the amplifier is different from the frequency response of the complete electrocardiograph which is much lower than that of amplifier at the upper cutoff frequency. For modem amplifier technology, the desired frequency response of the amplifier is not a real problem. • Common mode voltage rejection In ECG measurement, the common mode voltage can be introduced from the environment due to measurement in the presence of 50Hz power line and other medical equipment operation. This common mode voltage can be reduced by differential instrumentation amplifiers, driven right leg circuit and cable shielding technique. -47- 2-PREAMPLIFIER CONSIDERATIONS The most widely used configuration of the differential instrumentation amplifier is made from three operational amplifiers. In such configuration, the input stage is a pair of coupled input buffer with gain that provides high differential gain and unity common mode gain. The output stage is a single-op-amp differential amplifier which is usually arranged for unity gain and is used to cancel out the common mode signal. This feature makes it possible to achieve a high common mode rejection ratio [Won76]. The common mode voltage can be further reduced by the driven right leg circuit and cable shielding technique as discussed in section 1.3.6. 2.15 Isolation circuit In ECG measurement, the electrical defibrillation should not damage the input circuit and the system should be able to recover within a reasonable time for continuing the ECG recording. It is also veiy important that the patient must be protected from all kinds of electrical shocks during the measurement. This requires proper design with isolation against electrical shocks. AS3200.1-1990 requires that the patient circuits should be isolated from the power supplies by isolation barrier which is capable of withstanding isolated voltages up to 3500. Often it is possible to achieve the standards requirement from the power supplies with appropriate screening of the mains power transformers in series with the dc-dc isolated power converter for the isolated circuit and proper signal isolation by means of isolation amplifier or optically coupled techniques. In the design of isolation circuit, it will ensure that under all conditions two isolated barriers, power supplies and signal, must meet the standards requirement. -48- 2-PREAMPLIFIER CONSIDERATIONS 2.2 Defibrillation Protection Circuit Input protection circuits are basically designed for protecting the measuring circuits, in that they can eliminate the high voltages electric shock coming through the patient's electrodes. A typical damped sinusoid defibrillator can introduce onto the patient a maximum energy of 400 Joules and a peak voltage of 9000 V [Neu78- 2], depending on the size of the capacitance of the defibrillator and the patient body impedance. During the defibrillation procedure the patient may present a relatively high voltages that can directly enter the electrocardiograph. These high voltages can easily damage the measuring circuit without input protection. Figure 2.1 shows a complete configuration of the input protection circuit. Figure 2.1 Input protection circuit. In figure 2.1 the resistance R} is a current limit resistor and the gas arrester GA has a characteristic with a breakdown voltage ranging from 80V to 120V [Sie88]. When input voltage exceeds the breakdown voltage of this gas arrester GA it will appear as a short circuit characteristic. The current will pass through the gas arrester with the series current limit resistor R}. Note that this current passes in parallel with a much lower body impedance. Thus only a limited current flows in the gas arrester -49- 2-PREAMPLIFIER CONSIDERATIONS circuit. Under these conditions, the voltage across the device GA cannot exceed the breakdown voltage because of the voltage drop across the series resistor Rx. However, when input voltage is lower than the breakdown voltage of the device GA it will appear as a open circuit characteristic, as the resistance of the GA is nearly infinite in the nonconducting stage. So the voltage drop across the device GA is approximately equal to the input voltage. High frequency noise possibly introduced from other electrical devices in the patient's environment can be cleaned by the passive lowpass RC filter. In figure 2.1 resistor R1 and capacitor Cx gives a simple RC lowpass filter with a -3dB point at approximately 160KHz, which is more than two decades above the highest frequency of interest of the ECG signal, in order to reject any high frequency in the megahertz range. When input voltage is lower than the breakdown voltage of the gas arrester but higher than 1.8V it will be clamped by a network consisting of diodes D1-D6, resistors R4 and R5. In this bias network, the diodes Dl, D3 and D4 are connected in series as one branch and diodes D2, D5 and D6 are connected as another branch. Note one branch has a polarity that is opposite to that on another branch so that when the input voltage exceeds 1.8V, it will be clamped by forward bias voltage of the series diodes due to one of the branches is forward bias and the other is reverse bias. If the input voltage is less than -1.8V, the function of the two branches are reversed and the voltage will be clamped at approximately -1.8V. The resistors R4 and R5 in the bias network should be large enough to maintain the bias without loading the isolated supplies. This clamp circuit is mainly used as input protection to prevent amplifier saturation for a high gain amplifier. The diode used in the bias -50- 2-PREAMPLIFIER CONSIDERATIONS network is BAV45 [Phi77] which is a picoamp leakage diode. The main advantage of low leakage diode is that it has low DC offset caused by leakage current. 2.3 Front End Amplifier An biosignal preamplifier used for recording ECG signal should satisfy certain demands: (a) differential recording capability. (b) ac coupling for suppressing electrode-skin offset potential. (c) very high common-mode input impedance to reduce the differential- mode voltage converted from input common-mode voltage. (d) veiy high differential-mode input impedance to minimise input voltage reduction and distortion (e) high differential voltage gain for amplifying microvolts input signal to several volts output signal. (f) high common-mode rejection ratio. The most popular employed instrumentation amplifier is based on the classical configuration with three amplifiers. See Fig.2.2 -51- 2-PREAMPLIFIER CONSIDERATIONS FIRST STAGE SECOND STAGE Figure 2.2. Classical instrumentation amplifier with three amplifiers. First stage is a pair of coupled input buffers with gain. Second stage is a differential amplifier using a single operational amplifier. 2.3.1 Circuit Gain Calculation The first stage of the circuit provides high differential gain with simple control and unity common-mode gain without any close resistor matching. It also has veiy high input impedances both differential and common-mode. The differential gain in the first stage is v — V Gf=^—± (2.2) K-v2 rules From the golden roles of amplifier behaviour and Kirchhoff s current law, it can be seen in Fig.2.2 that K-K J^-v* (2.3) 2 R.+R, -52- 2-PREAMPLIFIER CONSIDERATIONS According to equations (2.2) and (2.3) the differential gain GF can be reexpressed as (2.4) For the common-mode input voltage, that is Vx - V2, the two amplifiers Ax and A2 in the first stage will keep the voltage zero across the resistance Rx. So the relationship between the input voltages and the output voltages in the first stage will be (2.5) The equation (2.5) shows that the common-mode gain in the first stage is a unity gain without any resistor matching. The second stage of this circuit is a differential amplifier using a single operational amplifier. The relationship between input and output can be obtained by supeiposition. If Vb = 0, then the output voltage is (2.6) If Va - 0, the circuit is a noninverting amplifier. The output voltage is (2.7) -53- 2-PREAMPLIFIER CONSIDERATIONS According to the principle of superposition, the output voltage of the second stage (V0 = V01 +V02) will be K = ( (2.8) Rs+R( In order to obtain zero common-mode gain when same value is at two inputs of differential amplifier, it must be considered that R6 / R5 is equal to R4/ R3. Thus, the equation (2.8) can be simplified as K = %-(K-K) = Gs(K-K) (2.9) Where Gs = R4 / R3 is the gain of second stage. So the total differential gain of this instrumentation amplifier is (2.10) R\ R?> 2.3.2 Circuit Transfer Function Figure 2.2 shows the usual differential amplifier based on three operational amplifiers. According to the definitions for analysing differential amplifier the input voltages can be described as : K = Km +Vj / 2 V2 = Vcm -Vd 12 (2.11) -54- 2-PREAMPLIFIER CONSIDERATIONS To analyse the circuit clearly, the equivalent circuit of the first stage in Fig 2.2 is shown in Fig 2.3. R2 h V1 =Vcm+Vd/2 - V2=Vcm-Vd/2 M/ Figure 2.3 Equivalent circuit of the first stage of Fig 2.2 The output voltages of the first stage, Va and Vb, can be obtained from Fig 2.3. i = (Vl-V2)R,=VJRl (2.12) Va - Vcm + Vj/2 + iR2 = Vcm+(V2 + R1!R])Vd (2.13) V^V^-VJl-iR, = Fm-(l/2 + R2!R,)Vd (2.14) Substituting equations (2.13) and (2.14) into the equation (2.8), the output of the second stage will be -55- 2-PREAMPLIFIER CONSIDERATIONS Usually the second stage is selected to be unity gain, that is R^ = R4 = R5 = R6, the equation (2.15) can be simplified as (2.16) Substituting differential input Vd=Vl-V2 into the equation (2.16), the transfer function of the circuit shown in Fig 2.2 will be K = -v+^rW,-K) (2.17) R 2.3.3 The Common-mode Rejection Ratio Analysis The common-mode rejection ratio (CMRR) measures the ability to suppress the common-mode voltage. It is defined as the ratio of the output voltage produced by a differential voltage compared to the output voltage produced by a common-mode signal of equal amplitude [Sch71]. The CMRR of instrumentation amplifier with three operation amplifiers has been analysed by numerous researchers [Pal91-1], [Pal90], [Szy83], [Smi77] [Bai71] and summarised by Pallas-Areny [Pal91-1] [Pal90]. The instrumentation amplifier shown in Fig.2.2 can be described as a two- stage differential system. The first stage consists of a pair of coupled input buffers with gain and the second stage consists of a differential amplifier using a single operation amplifier. For good analysis, a two-stage differential system network is shown in Fig.2.4. -56- 2-PREAMPLIFIER CONSIDERATIONS Gdd1 Gcd1 Gdd2 Gcd2 Vd,Vc Vd'.Vc’ Vd",Vc" Vo Gdc1 Gcc1 Gdc2 Gcc2 Figure 2.4. Two-stage differential system network Referring to Fig.2.4, observe that the each stage actually consists of four possible transfer gains described as follows (a) the differential mode gain Gdd is the ratio of output differential mode signal to input differential mode signal without considering input common mode signal. (b) the common-mode gain Gcc is the ratio of output common-mode signal to input common-mode signal without considering input differential mode signal. (c) the differential mode to common-mode gain Gcd is the gain of output common mode signal caused by input differential signal. (d) the common-mode to differential mode gain Gdc is the gain of output differential signal caused by input common-mode signal. From Fig.2.4 it can be easily found the relationship of the first stage between input and output. -57- 2-PREAMPLIFIER CONSIDERATIONS (2.18) (2.19) where Vd is the differential output of the first stage Vc' is the common-mode output of the first stage Vd is the differential input of the first stage Vc is the common-mode input of the first stage Equation (2.18) shows that the differential output Vd' includes two terms, one consists of differential gain multiplying the original differential voltage and the other consists of common mode to differential gain multiplying the original common mode voltage. Equation (2.19) shows that the common mode output Vc' also has two terms, one consists of common mode gain multiplying the original common mode voltage and the other consists of differential mode to common mode gain multiplying the original differential voltage. According to the usual definitions for analysing differential amplifier the differential input Vd is Vd-V2- \\ and the common-mode input Vc is Vc = (F, + V2) / 2. The second stage in the Fig.2.4 is a differential amplifier using a single operational amplifier. Its differential input is Vd and common-mode input is Vc'. The relationship between input and output of the second stage can be obtained in a similar way as the first stage. (2.20) (2.21) -58- 2-PREAMPLIFIER CONSIDERATIONS V=Vode”+V" (2.22) where Vois the total output of the two cascaded stage Vd"\s the differential output of the second stage Ec"is the common-mode output of the second stage Equation (2.18) to (2.22) yield the total output of the two cascaded stage. Equation (2.22) can be written as Vo = (Gdd2Gddl + Gcd2Gdd\ + Gdc2Gcd\ +Gcc2Gcdl)Vd HGdd2Gdc\ +Gcd2Gdc\ +Gdc2Gcc\ + Gcc2Gcc\ )K (2.23) From equation (2.23) the total differential gain and common-mode gain of the instrumentation amplifier with three op-amp can be obtained respectively GD Gdd2Gdd\ + GcdlGdd\ ~>rGdc2Gcd\ + Gcc2Gcd\ (2.24) GC ~ Gdd2Gdc\ + Gcd2Gdc\ + Gdc2Gcc\ + Gcc2Gcc\ (2.25) According to the definition of CMRR, the overall CMRR of this instmmentation amplifier can be expressed as CMRR — = Gdd2Gdd\ + Gcd2Gdd 1 Gdc2Gcd\ Gcc2Gcd\ (2.26) G, Gdd2Gdc\ Gcd2Gdc\ Gdc2Gcc\ Gcc2Gcc\ -59- 2-PREAMPLIFIER CONSIDERATIONS Under the condition that the second stage were an ideal differential stage, that is, in the second stage there is no differential output due to the common-mode input (Gdc2 =0), no common-mode output due to the differential input (Gcd2 = 0) and no common-mode gain (Gcc2 =0), the CMRRt would be limited only by the first stage. According to equation (2.26), the CMRR of first stage will be obtained CMRR, = CMRR, I = Q®- (2.27) J t\Gda=O.Gc If the first stage were perfect, that is, in the first stage there is no differential output due to the common-mode input (Gdc] =0) and no common-mode output due to the differential input (Gcdl = 0), then the CMRR, would be limited only by the second stage. According to equation (2.26), the CMRR of second stage will be obtained. CMRRS = CMRR, _ ^dd2^dd\ + ^cd2^dd\ (2.28) Gcdl=°’Gdcl=° Gdcl^ccX +Gcc2Gccl In the equation (2.28) when Gdd2Gdd] »Gcd2Gdd] the equation can be further simplified as: CMRRS « ^dd2^dd\ (2.29) ('Gdc2 +Gcc2)Gcc\ where Gdd2 / (Gdc2 + Gcc2) is the CMRR for the second stage without considering the first stage. Gddx / Gccl is the CMRR for the first stage without considering the differential to common-mode gain and the common-mode to differential gain. -60- 2-PREAMPLIFIER CONSIDERATIONS The equation (2.29) shows that the CMRR of the second stage in the three op- amp instrumentation amplifier is not the same as in the differential amplifier (DA) using a single op-amp with four resistors, though the circuit is the same. It can be seen that if the differential gain Gdd] is much greater then the common-mode gain Gccl ,the CMRRs will be larger than the CMRR of DA. It is a very important factor in the design of the three-op-amp instrumentation amplifier that increasing the differential gain in the first stage will result in a high value for CMRR of the second stage. Comparing with the differential amplifier (DA) using single op-amp with four resistors the second stage op-amp needn't have exceptional CMRR and its resistor matching is not terribly critical. The CMRR of the differential amplifier (DA) using single op-amp with four resistors is well known as, ------= —£-»------+------(Z.3U) CMRRda Gd CMRRr cmrroa where CMRRr is the common-mode rejection ratio of the resistors, CMRRoa is the common-mode rejection ratio of the op-amp The equation (2.30) shows that the CMRRDA heavily depend on the CMRR of the resistors, if a high CMRR of the op-amp is selected. In other words the CMRRDA depend on the balance of the resistors. For the particular case when Gddfim»Gcdfiddv Gdc2Gcdl and GcaGcd] the equation (2.26) can be expressed as -61- 2-PREAMPLIFIER CONSIDERATIONS CMRRt = Gdd2Gdd\ 1 (Gdc2Gcc\ + GcclGcc\ ) (Gdd2Gdc\ + Gcd2Gdc\ / Gdc2Gcc\ + Gcc2Gcc\ ) + 1 ______Gdd2Gdd\ 1 (Gdc2Gcc\ + Gcc2 1 Gccl)______(2.31) (Gdc\ / ^ )(Gdd2Gdd\ + Gcd2Gdd\ 1 Gcc2Gcc\ + ^c2^cd ) + 1 Wta1 Gdd2Gddi »Gcd2Gddim& substituting equation (2.27) and (2.29) into the equation (2.31) the CMRRt can be written as CMRRs CMRRt « CMRRS / CMRRf +1 and _L______1___ 1 (2.32) CMRRt * CMRRf + CMRRs Equation (2.32) shows that in order to obtain high CMRRt, both the first stage and the second stage must have a high CMRR unless CMRRf is different from CMRRs in sign. Pallas-Arent in his work [Pal91-1] analyzed the first stage CMRR in the three op-amp instrumentation amplifier in detail and derived CMRRf as follows 1111 1 (2.33) CMRR f ~ Ad] Ad2 CMRR2 CMRR, where Adl and Ad2 is the differential gain of the input op-amps in the first stage. CMRRX and CMRR2 is the common-mode rejection ratio of the input op-amps in the first stage. 2-PREAMPLIFIER CONSIDERATIONS For the first stage, the equation (2.33) shows that the best way to obtain a high CMRRf is to use well matched input op amps not only for their common-mode rejection ratio, but also for their differential gain. A set of simple expressions of the CMRR of three op amps instrumentation amplifier has been analysed. These equations show that the instrumentation amplifier may achieve a high CMRR if well matched input op amps are used and the first stage has a high differential gain. 2.4 An Improved Front End Amplifier 2.4.1 Introduction When designing an instrumentation amplifier for recording ECG signal this amplifier needs an AC coupling to suppress the DC offset caused by electrode-skin interface before high gain amplification. The three op-amp instrumentation amplifier can provide high input impedance, high CMRR and necessaiy differential gain as discussed above, but it can't solve the AC coupling problem. ECG signals normally require voltage gain of 80dB and the possible DC offset can be up to 300mV. Hence, the three-op-amp instrumentation amplifier (IA) shown in Fig 2.2 cannot be used directly for recording ECG signal. Several designs are available for AC coupling ECG amplifier. One approach is to provide a RC filter stage in front of the instrumentation amplifier (IA) to block any DC offset shown in Fig 2.5(a). The other is to provide a RC filter stage by the -63- 2-PREAMPLIFIER CONSIDERATIONS succeeding IA shown in Fig 2.5(b). AC coupling is also possible by adding a series capacitor to the gain setting resistor in the input stage of IA shown in Fig 2.5(c). Fig 2.5(b) is a classical configuration to filter out the DC potentials. The first stage of this circuit is a common instrumentation amplifier (IA) based on three op- amps, and its advantages have been discussed above. The second stage is an RC filter stage to block any DC offset and the third stage is a gain stage. In Fig 2.5(b) because the AC coupling stage is placed after the instrumentation amplifier (IA) it must be considered to avoid the first stage (IA) saturation from DC offset by setting high gain in the first stage. For this reason a low-gain input stage is normally used. If the maximum DC offset and ECG signal is assumed to be 300mV and 5mV respectively, and the maximum output swing of the input stage is +/- 10V for example, the maximum gain of the input stage is about 33. It is far from the required gain (1000). The last stage in this circuit is a gain stage to obtain a normally required gain after the RC high-pass filter stage. However, according to the analysis in the section 2.3.3, in high CMRR design, it is important to have as much gain as possible concentrated in the first stage of the input stage. Hence, the classical configuration in Fig 2.5 (b) cannot achieve a high CMRR due to a low gain of the input stage. The circuit in Fig 2.5(c) is placing a capacitor (C,) in series with resistor (R,) to reduce the DC gain of the input stage. It also solves the problem occurring in Fig 2.5(b), that is, a large gain can be set in the first stage of the circuit to obtain a high CMRR. But this circuit requires large capacitance values if low-frequency signals are of interest. The AHA standards require the lower -3dB comer frequency be placed at 0.05Hz in the ECG amplifier. For example, if the required gain and the feedback resistor (i^) is assumed to be 1000 and \MO. respectively then the -64- 2-PREAMPLIFIER CONSIDERATIONS capacitor (C}) can be calculated as follows (the gain in the first stage can be considered as a midband differential gain. So the capacitor Cx is essentially a short circuit when the gain is calculated) From the equation (2.4), the resistor Rx will be = 0^2m 1 Gain-1 999 C -----i---- =------\------= 1591 uF 27jR\f-3dB 2 x ;rx 2 x 103Q x 0.05Hz The above calculation shows the circuit in Fig 2.5(c) is necessaiy to use rather high capacitor if a high gain is set in the first stage in order to obtain a high CMRR. An ideal solution shown in Fig 2.5 (a) is to place a RC high-pass filter in front of the instrumentation amplifier (IA) to block any DC offset before amplifying the ECG signal with high gain. The RC filter stage can be simply formed by a capacitor in series with a resistor. However, placed in front of the IA this RC stage will greatly decrease the input impedance of the system. It can cause large interference transformed from common-mode voltage, see equation (1.10) and (1.12). For this reason in Fig 2.5(a) a non-coupled unity gain buffer is normally used as the first stage to provide high input impedances both in differential and common-mode. -65- 2-PREAMPLIFIER CONSIDERATIONS R6a R6b First stage Second stage Third stage (b) -66- 2-PREAMPLIFIER CONSIDERATIONS R6a R6b Figure 2.5 Three ECG recording preamplifiers equipped with AC coupling. 2.4.2 Circuit Transfer Function Fig.2.5 (a) is the practical ECG recording amplifier equipped with AC coupling and input buffer circuit, based on three-op-amp IA. This circuit consists of three cascaded stages. The first stage is the non-coupled unity gain buffer stage. The second stage is the RC high pass filter stage. The third stage is the three-op-amp IA. In the last stage, instead of using the three-op-amp IA with an adjustable resistor in order to obtain high CMRRDA shown in equation (2.30), a high CMRR and high gain IC instrumentation amplifier can be used without any adjustment (see inlay). The first stage in Fig.2.5(a) is a non-coupled stage. Each unity gain buffer can be described by its own transfer function. Va=V,-H,{s) (2.34) V„=V2-H2(s) (2.35) -67- 2-PREAMPLIFIER CONSIDERATIONS The first stage is a differential input stage. According to the definitions of differential mode circuit (Vd = V2-Vx, Vc - (Tj + K,)/2), Tj and V2 can be described respectively as V] =VC-Vd /2 (2.36) V2=Vc+Vd 12 (2.37) where Vc is the common-mode input signal, Vd is the differential input signal. Substituting equation (2.36) and (2.37) into equation (2.34) and (2.35) respectively, the differential output and common-mode output of the first stage can be obtained as following VD=Vb-Va=Vd[H2{s) + Hx{s)]l2 + Vc[H2{s)-Hx{s)] (2.38) Vc =(K+Vb)/2 = Vd[H2(s) - H} (s)]/ 4 + Vc[H2(s) + Hx (5)]/ 2 (2.39) The second stage is also a non-coupled stage. The relationship of each RC filter stage between input and output can be written as VJ=V'-H,{s) (2.40) (2.41) The differential output VD' and common-mode output Vc' of the second stage can be derived from the similar method used in the first stage. They can be expressed as -68- 2-PREAMPLIFIER CONSIDERATIONS VD' = Vb'-Va'=VD[H4(s) + H3(s)V2 + Vc[H4{s)-H3{s)] (2.42) Vc'={Vb'Wa')l2 = VD[H4(s)-H3{s)y4 + VclH4(s) + H3{s)]l2 (2.43) The third stage, that is the last stage, is a three-op-amp IA stage which is differential stage with a single-ended output. It has a differential gain Gd and dependent common-mode gain Gc. Notice Gd and Gc are frequency dependence. The relationship of the last stage between input and output will be K=Gd-VD'+Gc-Vc' (2.44) The total transfer function of this circuit can be obtained from equation (2.38), (2.39), (2.42), (2.43) and (2.44). It can be written as K = {Gd [H4 (s) + H3 (s)][H2 (s) + Hx (5)] / 4 + Ge[HA (s) - H3(s)][H2 (s) + Hx (5)] / 8 +Gd[H4(5)-H3(s)][H2(s)-Hx(s)]/4 + Gc[H4(s) + H3(s)][H2(s) - Hx(5)]/S}Vd +{Gd[H4 (s) + H3 (s)][H2 (5) - Hx (5)] / 2 + Gc [H4 (s) - H3 (s)][H2 (s) - Hx (5)] / 4 +Gd [H4 (5) - H3 (,s)][H2 (s) + Hx(s)]/ 2 + Gc[H4 (5) + H3 (s)][H2 (s) + Hx (s)] / 4}VC 2.4.3 Common-mode Rejection Ratio Calculation In order to analyse the CMRR of the circuit shown in Fig 2.5(a) in detail the third stage, that is the instrumentation amplifier (IA) based on three op-amps, can be further divided into two stages. One consists of a pair of coupled buffers with gain. The other is a differential amplifier using a single op-amp with four resistors. Hence, the circuit shown in Fig 2.5(a) can be described as a differential system -69- 2-PREAMPLIFIER CONSIDERATIONS network with four cascaded stages, see Fig 2.6. The last stage of the circuit is a single-ended output stage. Gdd1 Gcd1 Gdd2 Gcd2 Gdd3 Gcd3 Gdd4 Gcd4 Va.Vb Va'.Vb' Va",Vb" Gdc1 Gcc1 Gdc2 Gcc2 Gdc3 Gcc3 Gdc4 Gcc4 Figure 2.6 Four cascaded stages differential system network By applying the foregoing definitions for the four transfer functions Gdd, Gcd, Gdc and Gcc, the relationship of the each stage between the output and input shown in the Fig.2.6 can be easily obtained. In the first stage the relationship will be K=GddlVd+GdclVc (2.45a) Vb=Gcdyd+Gayc (2.45b) In the second stage the relationship will be K'=Gdd2Va + Gdc2Vt (2.46a) Vb'=Gcd2Va+Gcc2Vb (2.46b) In the third stage the relationship will be K"= Gdd3Va' +Gdc,Vb 1 (2.47a) -70- 2-PREAMPLIFIER CONSIDERATIONS K"=Gcd3K'+Gcc 3Vb' (2.47b) The last stage is a single-ended output stage. Ideally, there is no common mode output voltage from the point of view of differential measurements. But considering the unbalanced resistances Ri,R4,R5 and R6 and the limited CMRR of op amp itself, there is conversion from common mode to differential mode and differential mode to common mode. Hence, in the last stage the relationship between input and output will be K = (Gdd 4 + Gcd4 )K"+(Gdc4+Gcc4)Vb" (2.48) From equation (2.45) to (2.48), the total relationship between input and output can be written as I I --- o § Gdd 4 Gdc4 Gdd 3 CO gM2 Gdd i Gdc i — (2.49) _Gcd4 Gcc 4_ Gcd 3 gcc3_ Gcd2 Gcc2 J Gcd! i y._ According to the definition of the common-mode rejection ratio, the complete expression of the common-mode rejection ratio is 1 1 e> Gdd 4 Gdc4 Gdd 3 Gdc 3 Gdd2 Gdcl T [i i] o 1 _ Gcd 4 Gcc4 _ _Gcd 3 Gcc3_ _ Gcd2 Gcc 2 _ 1 _0_ CMRRt (2.50) Gdd 4 Gdc4 Gdd 3 Gdc3 Gdd 2 Gdc 2 'o' [i i] _ Gcd 4 Gcc4 ^ _Gcd 3 Gcc3_ _ G cd2 Gcc2 _ 1 If the second stage, third stage and fourth stage were perfect, that is, in these three stages there are no common-mode gain, no differential mode to common-mode -71 - 2-PREAMPLIFIER CONSIDERATIONS gain and common-mode to differential mode gain (Gcd4=Gdc4=Gcc4=Gcd3=Gdc3=Gcc3= Gcd2=Gdc2=Gcc2=0). The CMRR of the system would be limited only by the first stage. According to the equation (2.50) the CMRR of the first stage is CMRRt = CMRRf = (2.51) * Gccl ~Gcd2~G If the first stage, third stage and fourth stage were perfect, that is, Gcdl=Gdcl=Gcd3 =Gdc3 ~ Gcc3 ~Gcd4—Gdc4 ~Gcc4 =0 the CMRR of the system would be limited only by the second stage. The CMRR of the second stage will be CMRRt = CMRRS G dd \ G dd2 (2.52) Gcd3=Gdci =Gccl = Gcd4 =Gdcl =Gcdl = ° Gcc\Gdc2 If the first stage, second stage and fourth stage were perfect, that is, Gcdx=GdcX = Gcd2=Gdc2=Gcd4=Gdc4=Gcc4=0 the CMRR of the system would be limited by the third stage. From the equation (2.50), it can be obtained CMRRt = cmrr3 G dd\ G ddl G ddh (2.53) 'Gdc\ ~Gcdl ~Gdel Gcd4 Gdc4 ~Gcc4 ~'0 Gcc\ Gcc 2 G dc3 If the first stage, second stage and third stage were perfect, that is, Gcd=Gdcl = Gcd2=Gdc2=Gcd3=Gdc3=0 the system would be limited by the fourth stage. According to the equation (2.50) the CMRR of the fourth stage will be Gdd 1G dd 2 G dd 2>Gdd 4 + Gdd\Gdd2Gdd3>Gcd4 CMRR, = cmrr4 (2.54) Gcdl ~Gdcl ~Gcdl ~Gdcl~Gcdi~GdcZ Gccficc2Gcc3Gdc4+Gcc]Gcc2Gcc3Gcc4 -72- 2-PREAMPLIFIER CONSIDERATIONS When Gdd4 » Gcd4 the equation (2.54) is simplified as CMRR4 = Gddl Gdd2 ^ddfiddA (2.55) Gcc\ GCC2 Gcc3 Gdc4 + Gcc] Gcc2 Gcc3 Gcc4 When Gdd»Gcd,Gdc,Gcc can be assumed the complete expression of the common-mode rejection ratio in equation (2.50) can be further simplified as (*dd4 G ddfi dd2^dd\ CMRRt » ^ccficcficc2^cc\ + ^dcficcficc2^cc\ (2.56) ddfiddfidd2^ dc\ “*■ ^dd4 dd 3 ^dc2 ^cc\ ^ddfidcficcficc\ . 1 ^ cc4^ccf~^cc2Gcc\ ^dc4^cc3^cc2^cc\ Substituting equation (2.51),(2.52), (2.53) and (2.55) into the equation (2.56) the total common-mode rejection ratio of the system is 11 1 1 1 (2.57) CMRR, ~ CMRRX + CMRR2 + CMRR3 CMRR4 This equation shows the total CMRR of differential circuit containing several cascaded-stages. It indicates that even though three stages have ideal CMRR, the other stage could cause serious degradation because the total CMRR is determined by adding the reciprocals of the CMRR of each stage unless they have different signs. In Fig 2.5(a) the first stage is a pair of unity gain buffers and the second stage is a pair of RC filters. They are all non-coupled stages which can be expressed by their own transfer functions. By using the equations (2.51), (2.52) and comparing the -73- 2-PREAMPLIFIER CONSIDERATIONS equations (2.38) to (2.43) with the equations (2.45) to (2.46), the common mode rejection ratio of the first stage CMRRf and second stage CMRRs will be CMRRf = = (2.58) r Gdcl 2H2(s)-H,(s) CMRR _ _ 1 ^4(*) + #30) (2.59) 5 GJ}m 2 Ha(s)-H,(s) In the first stage, buffering each electrode with a unity gain voltage follower can provide high input impedance to reduce the interference caused by electrode impedances as mentioned above. But these unity gain buffers may reduce the common mode rejection in the measuring system if they are not perfect unity gain buffer? Some designers use high open loop gain op amplifiers to achieve accurate unity gain buffers. However, the following equations show that in order to obtain ideal unity gain buffers for high CMRR in the first stage the op amps must be matched not only in differential gains but also in common mode gains without considering their open loop gain values. For the unity gain buffer in Fig 2.5(a), K = Adl(Vl-Va) + Acl(Vl+Va)/2 = (4i + 4i /2)K + (~4, + 4, /VK (2.60) where 4i is the differential mode gain and Acl is the common mode gain of the op amp A}. According to op amp data sheets both differential gain Ad and CMRR of op amp are frequency dependent. Ad usually begin to roll off at frequencies well below the -74- 2-PREAMPLIFIER CONSIDERATIONS CMRR comer frequency. For the AD708J, for example, Ad starts to decrease at 0.1Hz and CMRR starts to decrease at 10Hz. Hence, the transfer function of the unity gain buffer Ax is frequency dependence. From equation (2.60) the transfer function will be = K = Adl/Ae ,+1/2 (2.61) Vx (Adx / AcX-l/2) + l/ Acl CMRROAX +1/2 or Hx(s) = (2.62) (CMRRoax -1 / 2) +1 / AcX where CMRROA=Adx / AcX is the common mode rejection ratio of the op amp Ax From the same analysis, the transfer function of the unity gain buffer A2 will be CMRRoa2 + 1/2 H2(s) = (2.63) (CMRRoa2-\/2) + 1/Ac2 where Ac2 is the common mode gain and CMRROA2 is the common mode rejection ratio of the op amp A2. Substituting equations (2.62) and (2.63) into the equation (2.58) and assuming that Ad,CMRROA» 1, the common mode rejection of the first stage will be 1111 1 (2.64) CMRR f ~ Ad2 Adx CMRRoax CMRRoa2 Equation (2.64) shows that in order to achieve a high value of CMRR in the first stage both the differential gain and common mode gain must be matched for the -75- 2-PREAMPLIFIER CONSIDERATIONS unity gain buffers. Selecting a pair of well matched op amps for input unity gain buffers is difficult. Is it possible to compensate the unmatched unity gain buffers by trimming the resistor in the second stage to improve CMRR in the first and second cascaded stages? The answer is that improvement is possible but limited. In the second stage the transfer functions of two RC high pass filter are H,(s)= —— (2.65) s+coa H4(s) = ——— (2.66) s+ab where coa = 1 / CaRa and cob = 1 /CbRb. Substituting equations (2.65) and (2.66) into equation (2.59), the CMRR of second stage will be \RuCa+RbCb+2RuRbCaCbS CMRRS = (2.67) 2 RbCb-RaCa The equation (2.67) shows that a very high common-mode rejection in the second stage can be obtained at all frequencies by trimming the resistor R'b (Rb=Rb'+Rb" see the Fig 2.5(a)) to make RbCb-RaCa close to zero. However, in order to get high common-mode rejection of the whole system, all stages must have high CMRR as the total CMRRt is determined by the lowest CMRR in all stages, unless they have different signs, see equation (2.57). It is possible to obtain any desired value of common-mode rejection ratio in the second stage by trimming -76- 2-PREAMPLIFIER CONSIDERATIONS resistor 7^. However, if the resistor can be trimmed to obtain CMRR] = -CMRR2, then the CMRR including first and second stage would be infinite. Therefore, instead of seeking a high value for CMRR2 it is better to adjust it to compensate the unmatched op-amps in the first stage and achieve an optimal CMRR in the first and second stage. In order to analyse this possibility, it must be considered that the differential gain and common mode rejection ratio of the op amp are both frequency dependent. According to op amp data sheets, it can be assumed that the op amp open loop differential gain and CMRR have a first order low pass characteristic. They can be expressed as S+ (Dr (2.68) Ad ~ A CMRRoa = CMRRoa( 0)----=2- (2.69) where cod and coc are the comer frequencies of the open loop differential gain and CMRR of op amp respectively. A0 and CMRROA (0) are the open loop differential gain and CMRR of op amp at dc values respectively. Substituting the equations (2.68) and (2.69) into the equation (2.64), the following can be obtained -77- 2-PREAMPLIFIER CONSIDERATIONS 1 _ Aq2 — A0] | CMRROA2 (0) - CMRRoax (0) CMRRf A02A01 CMRRoa2 (0) • CMRROAl (0) i s^02 ^oi ^ | CA/RRp^fO) CMRROAl(Qi) co. (2 70) 4*4), CMRRoa2 (0) • CMRROA] (0) a;/7 From equation (2.70), the reciprocal of CMRRf is a complex function of frequency with a real and an imaginaiy part. CMRRf thus is also a complex function of frequency. If the complex function CMRRf is equal to the complex function -CMRRs, that is, the real part and imaginary part in the CMRRf are equal to that in the -CMRRs, then the total CMRR of the first stage and second stage can be infinite. However, it will not be possible to trim the resistor 7^ to make CMRRf =-CMRRs simultaneously both in the real part and imaginary part. Therefore, trimming resistor 7^ can achieve an optimal CMRR including first and second stage but not lead to obtain an infinite CMRR. In Fig 2.5(a) the third stage and fourth stage are the same as in the classical three op amps instrumentation amplifier which has been analyzed in previous section. 2.4.4 Experimental Results And Discussion In order to verify what degree of optimisation of the CMRR is possible in practice, several circuits were tested. At very low frequencies, the output of common mode voltage is so instable that the exact value for the CMRR cannot be measured and a lower limit value can be provided only. Hence, the results are presented in tabular instead of graphical form. -78- 2-PREAMPLIFIER CONSIDERATIONS The first circuit measured involves the connection of the second stage to the third stage shown in Figure 2.5(a) without considering input unity gain buffer stage, that is, the common mode signal is applied directly to the high pass filter RC stage not to the op-amp unity gain buffer stage. In the third stage, instead of using a differential amplifier based on three operation amplifiers with an adjustable resistor to obtain a high CMRR, a high gain and high CMRR IC instrumentation amplifier AD624CD is used without any adjustment. For the AD624CD, at 60Hz, a minimum CMRR of 130dB is quoted when the gain is set to 1000 and 80dB when the gain is set to one [AD624]. This confirms equation (2.29) that the higher gain a pair of coupled buffers with gain have, the larger is the CMRR of the differential amplifier in the output stage. The American Heart Association performance standards (see section 1.4 Technical Standard) require the lower -3dB comer frequency be placed at 0.05Hz in the ECG biopotential amplifier. Hence, in the high pass filter RC stage, the -3dB comer frequency is desired to be equal to or lower than 0.05Hz and in Figure 2.5(a) C, = C2 = 6.8wF’(5%), Ra = l.5MQ, Rb'=\.2MQ and Rb''=500KCl are chosen to ensure the comer frequency is lower than 0.05Hz. Experiment 1: CMRR of second stage and third stage in cascaded Table 2.1 shows the CMRR results of two circuit. One is the CMRR of the third stage which is a monolithic instrumentation amplifier AD624CD, the other is the CMRR of the circuit including second stage and third stage without considering unity gain input stage. In Table 2.1, it can be seen that at 50Hz it is possible to adjust the potentiometer Rb" to obtain CMRR of the circuit including second and third stage higher than that of the third stage only. As predicted by equation (2.67), the potentiometer Rb" can be brimmed to achieve a veiy high CMRR of the second stage, or to obtain an imbalance of the ratio of RC to compensate the other imbalance stage. -79- 2-PREAMPLIFIER CONSIDERATIONS f(Hz) 10 50 100 200 500 CMRRth (dB) (AD624CD) 144 135 129 123 115 CMRRs (dB) 121 143 132 124 115 Gd 1000 1000 1000 1000 1000 TABLE 2.1. Comparing the common mode rejection ratio of two circuits. One is the CMRRth of the third stage, the other is the CMRRsof the circuit including second and third stages in Figure 2.4. (Under test conditions where the third stage is an AD624CD, the differential mode gain Gd = 1000 and the potentiometer Rb" is adjusted to obtain a minimal V0 at 50Hz). Experiment 2: CMRR of first stage and third stage in cascaded The second circuit measured connects the first stage (input unity gain buffer stage) with the third stage (instrumentation amplifier stage with three op-amps) without considering the RC high pass filter stage in the Figure 2.5(a). First, a dual amplifier AD708J is used as unity gain input buffer stage. Then, a dual amplifier AD648CQ replaces the AD708J as unity gain input buffer stage. The third stage uses the same monolithic instrumentation amplifier AD624CD for measuring AD708J and AD648CQ in the circuit. According to the equation (2.57), the total CMRR of two cascaded-stages is determined by the first stage if the CMRR of the third stage is much greater than that of the first stage. The circuit used for comparing first stages using several different chips as unity gain amplifiers is reasonable because AD624CD as the third stage has a veiy high CMRR at low frequencies, see TABLE 2.1. For a dual amplifier AD708J, a minimum CMRR is -80- 2-PREAMPLIFIER CONSIDERATIONS given as 120dB and a typical open loop gain is 142dB [AD708]. The circuit was measured repeatedly for several different chips of AD708J. Some of them gave higher CMRR, others lower CMRR. TABLE 2.2 shows the results for the CMRR when using an AD708J and an AD648CQ, in which the AD708J is the worst one of several AD708J chips measured in the same circuit and the AD648CQ is selected randomly. It is noteworthy that AD708J is a bipolar op amp which has much lower input impedance both in differential and common mode, typically 108H and 2xlOnn respectively, than FET op amp AD648CQ which typically has 1012||3(Q||/?F) and 3 x 1012j|3(n||/?F). The high input impedance can reduce the interfering differential voltage caused by common mode voltage (see equation 1.10). From the point of view of CMRR measurement with ideal input signal the bipolar op amp AD708J can be used for comparison with AD648CQ in the same circuit. f(Hz) 10 50 100 200 500 CMRR (dB) 96.1 96.3 96.1 95.7 93.8 (AD648CQ) CMRR (dB) 92.2 92.2 91.4 90.5 87.1 (AD708J) Gd 1000 1000 1000 1000 1000 TABLE 2.2 CMRR achieved with two different dual amplifiers as unity gain input stage by using a monolithic instrumentation amplifier AD624CD as the third stage. One set of results are obtained by using AD648CQ dual amplifier, and the other by using the AD708J dual amplifier. The differential gain Gd of the circuit is 1000. -81- 2-PREAMPLIFIER CONSIDERATIONS It is somewhat suiprising that the common mode rejection ratio of the noncoupled unity gain buffers stage using the dual amplifier AD708J is only 92dB, this is lower than that using dual amplifier AD648CQ (96dB) which has a minimum CMRR of 86dB and a typical open loop gain 120dB (AD648) much lower than AD708J. The equation (2.64) for a pair of noncoupled unity gain buffers with different CMRR and different differential gain provides an explanation that in order to obtain a high value of CMRR for a pair of noncoupled unity gain buffers, two op amps must be matched not only for their CMRR, but also for their open loop differential gain, that is, two op amps should be matched not only for the ratio Ad / Ac, but also for the values of Ad and Ac. Hence, the op amps are not required to have very high CMRR or high differential gain. General purpose op amps can be used if they are matched. Experiment 3: CMRR of the total circuit The total circuit shown in figure 2.5(a) is measured for CMRR using dual amplifier AD648CQ as a pair of unity gain buffers and C, = C2 = 6.8wF(5%), Ra = 1.5Mfi, Rb'= 1.2Mfi and Rb"=500KQ (15tums) for RC high pass filters, and a monolithic instrumentation amplifier AD624CD as last stage. In order to verify what degree of the compensation of the CMRR is possible in the circuit, the potentiometer Rb" must be adjusted to obtain the optimisation of the CMRR. TABLE 2.3 is the results for comparing the CMRR of the overall circuit in figure 2.5(a) with the CMRR of the circuit including the first stage and the third stage without considering RC high pass filter stage. In these two circuits the chips are the same. -82- 2-PREAMPLIFIER CONSIDERATIONS f(Hz) 10 50 100 200 500 CMRR 96.1 96.3 96.1 95.7 93.8 (First and third) CMRR 96.7 97.8 96.4 96.1 94.7 (Overall circuit) Gd 1000 1000 1000 1000 1000 TABLE 2.3. Common mode rejection ratio of the circuit in figure 2.4, under two different conditions: (I) without the conclusion of RC high-pass circuit (first and third stage only), (II) with the conclusion of RC high-pass circuit and the potentiometer Rb" trimmed to obtain best CMRR at 50Hz. TABLE 2.3 shows that trimming the potentiometer Rb" to compensate for the unmatched unity gain buffers can improve the CMRR in the system but its effect is limited when the influence of the third stage is negligible as the AD624CD has a veiy high CMRR (135dB at 50Hz). The results in TABLE 2.3 support the theoretical predictions that the potentiometer enables some compensation for the mismatch in the input stage but it cannot cancel the mismatch out because trimming the potentiometer cannot make CMRRf = -CMRRS simultaneously both in the real part and imaginary part shown in equation (2.67) and (2.70). -83- 3-ISOLATION CONSIDERATIONS CHAPTER 3 - Isolation Considerations 3.1 Introduction The input protection circuits described in Section 2.2 are primarily used to protect the measuring circuits from high voltages presented on the patient during defibrillation or other surgical procedure. However, the measuring circuits can also introduce a risk to the patient. Hence, an isolation barrier between the patient circuits and the processing circuit which is connected to mains power must be established to protect the patient from potential electrical shock. The conventional methods for transmitting analog signals across a voltage isolation barrier involve isolation amplifiers based on magnetic coupling techniques, for example isolation amplifiers AD202, AD204, AD210, AD295 AD284J. These devices can provide high precision, high common mode rejection and DC performance. However, these devices are expensive, especially in a multi-channel recording system. 3.1.1 Use of digital optocoupler A less expensive method is using optocouplers as isolation barrier. Optocouplers have been used to provide isolation for digital signal for many years. They are particularly advantageous in digital systems. One possible solution for analog system is to convert the signals on the isolated side of the barrier with an analog-to- digital converter (ADC), and then to pass the digital data across the barrier using optocouplers (see figure 3.1). If a serial output A to D converter is used, the number of isolated lines can be reduced. In Figure 3.1 the Clock and Start Convert inputs control the A to D converter IC1 by using optocouplers IC2 and IC3 to pass these -84- 3-ISOLATION CONSIDERATIONS two signals across the isolated barrier. The serial output of the A to D converter is transmitted by the optocouplers IC4 to the non-isolated side. A suitable A to D converter IC1 could be the MAX170 which is a 12-bit resolution and linearity, serial output and low power A/D converter [Max90]. When driven with a 140kHz clock the MAX 170 A/D converter can produce 10,000 conversions/s (to keep data synchronisation at the output of circuit, Start Convert pulses must repeat eveiy 14 clock cycles, see figure 3 in Max90). Hence, for 12 channels ECG system and 1000 sample rate per channel the converter will produce 12,000 conversion/s (the converter's speed limit is more than 100,000 conversions/s).Considering the high clock pulse (168kHz for 12,000 conversions/s) and the high data rate of serial output (144kHz for 12-bit resolution A/D converter), faster optocouplers are required to pass the clock pulses and output data across the isolation barrier. The 6N136 optocoupler [Hew91-1] is a high speed optocoupler (IMb/s) and capable of withstanding test voltages of 5000V ac for 1 minute (option 020) [Hew91-2]. So, the optocoupler 6N136 satisfies the isolation circuit requirements. The configuration of the isolation circuit shown in figure 3.1 is a simple and cheap way in design of the multi-channel ECG measuring device to protect the patient from the electric shock if the isolation power supply is adequately rated. The main problem of isolating data signals with optocouplers in the multi channel ECG recording system is high isolated power consumption. The isolated power must provide power for the input buffer amplifiers, the amplifiers of instrumentation amplifier configuration, Driven Right Leg amplifiers, Shield Drive amplifiers, lead selection multiplexers, optocouplers for the isolation of logic control signals, the amplifiers of anti-aliasing filter, multiplexer for analog to digital converter, analog to digital converter. These all complicate the design of the isolated power circuitry. -85- 3-ISOLATION CONSIDERATIONS Isolated power Start Convert Analoc input Clock Input GND Data 10uF _Z 47uF S7 Common Figure 3.1. A digital isolated system using high speed optocouplers and serial data transmission A/D converter. 3.1.2 Linear Optical Isolation Methods To solve the isolated power consumption problem, it is possible to use optocouplers for signal isolation in analogue form. For precision analogue applications, however, the non-linear light output and time-temperature instability of optocouplers present a significant problem. A conventional optocoupler is shown in figure 3.2 and consists of a light emitting diode (LED) and a photodiode to receive the emitted light. There are several error sources contributing to a typical nonlinearity. The main source of error results from the non-linear light output of the LED with forward current. It also presents poor temperature coefficients due to the -86- 3-ISOLATION CONSIDERATIONS negative temperature coefficient of LED. The non-linear light output is mainly caused by reduced efficiency with time leading to a fall off in light output. i ^.Ve Figure 3.2. A conventional optocoupler circuit To overcome these problems mentioned in the conventional optocoupler circuit compensation of the major optocoupler errors can be achieved by using a servo controlled opto-coupling amplifier shown in figure 3.3 which is a photoconductive isolation amplifier. The optical configuration shown in Figure 3.3 contains a single LED and two photo-diodes D] and D2 which are arranged to receive the light for a given LED current. The diode Dx captures the LED's light output and generates a control signal that can be used to servo the drive current of the LED, that is, the diode Dx provides negative feedback. The diode D2 receives light output from the LED to supply the output signal that is linearly related to the served optical flux created by the LED. In this way, the nonlinearity in LED's light output and instability of time-temperature associated with LED's drive current can be compensated. -87- 3-ISOLATION CONSIDERATIONS ISOLATIVE BARRIER +Viso_ Figure 3.3. The linear optocoupler with a couple of operational amplifiers builds a highly linear isolation amplifier. The circuit works as follows: A current flowing out of the op-amp Ax inverting input drives the LED. The LED and diode D] form a closed feedback loop around the op-amp Av The current IPl through D} flows the resistor Rx connected to the inverting input of op-amp A] and is forced by negative feedback to a value that satisfies the relationship: -IPX - V1N /R} (3.1) where the current IPX equals the feedback transfer gain Kx multiplied by the LED drive current IF, that is, IPX — KXIF. So, the equation (3.1) can be rewritten as: IF = m /R\K\ (3.2) -88- 3-ISOLATION CONSIDERATIONS In fact, the negative feedback loop forces the op-amp A1 to supply enough output current IF in order to increase photo-current IPX until the voltage Va is equal to the input voltage VIN. The loop is now stable. The output diode D2 is connected to the non-inverting voltage follower amplifier A2. The diode's load resistor 7^ performs the current to voltage conversion. Thus, the output voltage of op amp A2 can be expressed as: V0 = -IpK.R, (3.3) where K2 is the output forward gain. Substituting Equation (3.2) into (3.3), the relationship between input and output is V0IVin=K2R2IKxRx (3.4) The equation (3.4) shows that the overall transfer gain VJV1N becomes completely independent of the main source of error from the non-linear light output of the LED with forward current The analysis above demonstrates that a photoconductive isolation amplifier circuit (Fig 3.3) with optical servo technique can eliminate the non-linear light output and time/temperature instability presented in the conventional opto-coupler circuit (Fig 3.2). However, the analysis of results obtained is to assume that the operational amplifier Ax and A2 are ideal op-amps in which the differential open loop gain is infinite. An important question is this the influence of the op-amps on -89- 3-ISOLATION CONSIDERATIONS the linearity of the photoconductive isolation amplifier. To answer this question the first step is to analyse the optical servo feedback amplifier circuit shown in Fig 3.4. (The photoconductive isolation amplifier circuit (Fig 3.3) can be separated into an optical servo feedback amplifier circuit (Fig 3.4) and an output transfer amplifier circuit shown in Fig 3.5.) R3 Giso +Viso Figure 3.4 Optical servo feedback amplifier circuit in Fig 3.3 From the point of view of differential amplifier analysis the output voltage Vb of the amplifier Ax is K = Ad\(VJN -Va) + Acl(V1N +Va)/2 = (^l + a„)vm+(~l-a„)K (3-5) where Ad] and Acl is the differential open loop gain and the common mode gain of the op amp Ax, respectively. The output voltage Vb can also be expressed as Vb = IF-R3+VLED (3.6) -90- 3-ISOLATION CONSIDERATIONS where VLED is the LED forward voltage. From the optical servo feedback amplifier circuit (Fig 3.4) the feedback voltage Va at the inverting input of op amp Ax is Va = Rx-IP\- R\ IF- K] (3.7) In equation (3.7) the photocurrent IPX equals the LED drive current IF times the feedback transfer gain Kx (IPX = IF-KX). Substituting equations (3.6) and (3.7) into the equation (3.5), the following equation will be obtained h ■«, + vm = (^f-+ Adi )Vm + (^ - An From the above equation, the LED drive current IF will be = (Adx+AJ2)V1N-VLED R3+Rl Kl (Adx - Acl / 2) If the differential open loop gain Ad] is much greater than the common mode gain Ac] and RxKxAdx » R3 (Rx =\0kQ., Kx =0.007, R3 = 100Q are quoted from the IL300 optocoupler data sheets [Sie91]) the equation (3.8) can be simplified as A •V -V /V1 ¥ IN y LED (3.9) If = R, ■K, Atn -91- 3-ISOLATION CONSIDERATIONS Figure 3.5 Output transfer amplifier circuit in Fig 3.3 The next step is to analyse the output transfer amplifier circuit shown in Fig 3.5. In this circuit the differential input voltage Vd2 - VQ-Vt and the common mode input voltage Vc2 =(V0+Vt)/2. The output V0 of the circuit can be expressed as K=4d2(K-Vt) + Ac2(V0+Vt)/2 = (^Y+^2)K+(^-aiI2)K (3.10) In Fig 3.5 the transfer voltage Vt at the non-inverting input of the op amp A2 is Vt=IP2-R2=IF-K2-R2 (3.11) where the output photocurrent IP2 equals the LED drive current IF times the forward gain K2 (IP2 =IF-K2) Substituting equation (3.11) into the equation (3.10) the following equation can be obtained. -92- 3-ISOLATION CONSIDERATIONS From above equation the output V0 will be (Ad2~Ac2/2)^-1^ J (3.12) (Ad2 + Ac2 /2) — 1 F When Ad2 » Acl, and Ad2 » 1, the equation (3.12) can be simplified as Vq=K2-R2-If (3.13) Equation (3.13) shows that the output voltage Vo is related to the LED drive current IF and the output operational amplifier A2 does not affect the output linearity. Substituting the equation (3.9) into the equation (3.13) the relationship between the input and output in the photoconductive isolation amplifier (Fig 3.3) is obtained. (3.14) If AdlV1N » the above equation will be The above equation is the same as equation (3.4). The output voltage VQ is dependent on the input voltage VIN -93- 3-ISOLATION CONSIDERATIONS Equation (3.14) also shows that if the input signal is very small (the LED forward voltage cannot be neglected) the output voltage Vo is related both to the differential gain Adl and the input voltage VIN. A changing Ad] causes a non-linearity of the LED drive current IF, see equation (3.9). (Ad] has a first-order low pass frequency dependence and usually starts to decrease at low frequencies. For the AD OP-27G, for example, Ad] starts to decrease at 10Hz shown in Fig 3.6) 130 110 « *° < 70 0 o. § so 1z ° 30 10 \ -10 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY - Hi Open Loop Frequency Response Figure 3.6 AD OP-27G open loop frequency response The above discussed a photoconductive isolation amplifier circuit which uses the optical servo technique to compensate for the non-linear characteristics of the conventional optocouplers (Fig 3.2). But In the photoconductive isolation circuit the photodiode will generate photocurrent in reversed biased mode and produce a small reverse leakage current [Sie91]. This reverse leakage current will result in a non linearity in photoconductive isolation circuit. In addition, the circuit (Fig 3.3) only can process unipolar input voltage. However, in ECG recording system the isolated preamplifier is required to have as high linearity as possible and the input voltage range can be bipolar. To solve these problems a prebiased bipolar input photovoltaic isolation amplifier may be considered. -94- 3-ISOLATION CONSIDERATIONS 3.1.3 Bipolar Input Photovoltaic Isolation Amplifier In photovoltaic mode the photodiode will produce photocurrent in forward bias. The current output is linear with increase in incident flux [Sie91], Compared with the photoconductive mode the photovoltaic mode can achieve low offset drift and greater than 12bit linearity. Fig 3.7 is shown a typical bipolar photovoltaic isolation amplifier circuit which uses two current sources. The first current source prebiases the input amplifier At and the second current source is connected to the inverting input of output amplifier A2 to match the input prebias. By introducing the prebias current the input amplifier will force the LED to provide photocurrent 7/J to servo the input back to a zero volt equilibrium, that is, the inverting input equals the non- inverting input of the amplifier. +v LM334 IL300 +Visol LM334 +Visol Figure 3.7. Prebiased bipolar input photovoltaic isolation amplifier -95- 3-ISOLATION CONSIDERATIONS In Fig 3.7, when the amplifier input is equilibrium (Va = Vb) at the inverting input of op amp^,, the following equation is established V„ IP} = +/i (3.15) The above equation shows when input voltage V1N = 0 the quiescent operating current IPq is equal to the current /, from the current source. The quiescent operating point is determined by the dynamic range of the input signal (see Fig 3.8). ipi Figure 3.8 Transfer characteristic prebiased bipolar amplifier The prebias current source can be as simple as a series resistor connected to power supply. However, in order to achieve best stability and minimise offset drift of the desired quiescent operating point, a good quality current source is introduced (see figure 3.9). -96- 3-ISOLATION CONSIDERATIONS Figure 3.9. A zero temperature coefficient current source with 3- terminal adjustable regulator LM334 The configuration in figure 3.9 is a special zero temperature coefficient current source using a convenient 3-terminal adjustable regulator LM334 IC optimised for use as a low power current source. The current can be adjusted down to luA. This feature is very useful in multi-channel recording system when the available isolated power is limited. The following analysis will demonstrate that under appropriate conditions the bipolar photovoltaic isolation circuit can have a high linearity and op amps characteristics will not affect the circuit. In order to analyse the circuit (Fig 3.7) it can be divided into two parts, the optical servo amplifier circuit (Fig 3.10) and the output transfer amplifier circuit (Fig 3.11). -97- 3-ISOLATION CONSIDERATIONS +Visol +Visol Figure 3.10 Optical servo amplifier circuit in the bipolar input photovoltaic isolation amplifier (Fig 3.7). From the point of view of differential amplifier analysis, the output voltage Vc of op amp A] in Fig 3.10 will be K = (Vb ~Va) + Acl(Vb +Va)/2 (3.16) When the non-inverting input of op-amp A] is connected to the isolated ground the non-inverting input voltage Va equals to zero and the equation (3.16) is Vc={Adl+AcJ2)Vb (3.17) From the Fig 3.10 the output of the op amp A, can also be expressed as K=yM-IP-R*-VUD (3.18) where VLED is the LED forward voltage and VlS0l is the positive isolated power supply. -98- 3-ISOLATION CONSIDERATIONS At the inverting input of the op amp Ax the input voltage Vb is and Vb = Vl ~(IPX ~i\)R\ ~V\ ~(If'Kx -ix)Rx (3.19) where the photocurrent IPX is the LED drive current IF times the feedback transfer gain Kx (IPX = IF-KX). Substituting the equations (3.18) and (3.19) into the equation (3.17), the following equation will be obtained Visol -If R4 - VLED = (Adx + AcX / 2)[VX - (JF • - h )*, ] From the above equation the LED drive current IF will be _(Adl+AJ2)(Vm+irR,)+Visol+V1 LED (3.20) (Adl + AJ2)Kt-R.-RA When Adl » Ac,, Ad,(Vm +il R1)» (Vml + ) and AdrKrR, » R4 (/, = lOOuA, Rx = 10AQ, R4 = 100Q and Kx =0.007 are quoted from the IL300 optocoupler data sheets [Sie91]) the equation (3.20) can be simplified as V1N +il-Rl (3.21) F KA -99- 3-ISOLATION CONSIDERATIONS +V Figure 3.11 Output transfer amplifier circuit in the bipolar input photovoltaic isolation amplifier (Fig 3.7) From Fig 3.11 the output voltage Va can be written as K = Ad2(Vk -Vj) + Ac2(Vk +Vj)/2 (3.22) When the non-inverting input of the op amp A2 is connected to the non-isolated ground the non-inverting input voltage is equal to zero and the equation (3.22) can be expressed as K=(Ad2+Ac2/ 2)Vk (3.23) In Fig 3.11 the inverting input voltage Vk of the op amp A2 is K-vk + 70 — IP~, *2 and = V0-{IFK,-i2)R, (3.24) -1 00- 3-ISOLATION CONSIDERATIONS where IP2 = IF-K2 Substituting equation (3.24) into the equation (3.23) the output voltage V0 will be y _ (4/2 +^c2 ! 2)(/f K2 -/2)^2 (Ad2+Ac2/ 2)-l When (Ad2 + Acl / 2)» 1 the above equation can be written as Va={IF-K2-i2)R2 (3.25) Substituting the equation (3.21) into the equation (3.25) the relationship between the input and output in the prebiased bipolar input photovoltaic isolation amplifier (Fig 3.7) is A, -K (3.26) KrR, m K, 1 2 ^ From the equation (3.26) it can be seen that the differential gain and the common mode gain of two op amps will not affect the relationship between the input and output, and when two current sources are trimmed to obtain z2 / /, -K2! Kx the tr ansfer function of the circuit can be simplified as -101- 3-ISOLATION CONSIDERATIONS K_=K^ (3.27) VIN Kx Rx 3.2 An Isolated Front End Amplifier Recording ECG signals requires them to be isolated before entering the processing circuit which connected with main power to protect the patient from potential electrical shock. Using optocouplers to provide the isolation barrier may be a less expensive method compared with commercial monolithic IC isolation amplifiers based on magnetic coupling techniques, especially in the multi-channel recording system. Figure 3.12 presents a composite isolation instrumentation amplifier, that combines two bipolar input photovoltaic isolation amplifiers (See figure 3.7) with a simple differential amplifier or a monolithic IC instrumentation amplifier. Because of the differential configuration the bias current source at the output shown in figure 3.7 is no longer needed. This isolation amplifier design seemed very attractive because of its very high CMRR (140dB) [Sie91] and lower system isolation power supply consumption than currently available low noise isolation methods. -102- 3-ISOLATION CONSIDERATIONS IL300 +V -AAA R5 Current Source IL300 Current Source FIRST STAGE SECOND STAGE pre.h‘iased Figure 3.12 Differential prebiased photovoltaic isolation amplifier In Fig 3.12 the first stage is a pair of noncoupled isolation buffers with gain and the second stage is a differential amplifier based on a single op amp with an adjustable resistor. A high gain and high CMRR commercial IC instrumentation amplifier can be used instead of the differential amplifier. In order to obtain high CMRR the IC instrumentation amplifier must have high gain. Thus, in the first stage the photovoltaic isolation buffer can be designed as unity gain buffer. According to the equation (3.26) if the transfer gain R of optocoupler is K21 Kx and the values of R / R and i2 //, can be trimmed to equal R the unity gain buffer is obtained. Hence, in theory the circuit shown in Fig 3.12 could achieve a very high CMRR depending on the IC instrumentation amplifier. In practice it may be difficult to obtain well matched photovoltaic isolation unity gain buffers by trimming the resistor R (R = R'+R") and current sources /, or i2 for high CMRR. -103- 3-ISOLATION CONSIDERATIONS In order to avoid these difficulties the bipolar input photovoltaic isolation amplifier shown in Fig 3.7 is connected directly to the output of the preamplifier circuit in Fig 2.4. The total isolation preamplifier circuit is shown in Fig 3.13. The advantages of the circuit are: (a) very high common mode input impedance and differential input impedance for both inputs. This is an important property as differences in electrode/skin impedance and common mode input impedances convert common mode voltage into a differential voltage; this phenomenon is known as the 'potential divider effect'. (b) AC coupling to block any DC offset before high gain differential amplifier stage, which can prevent amplifier saturation from DC offset voltage arising from electrode/skin interface. (c) very high differential gain (G^ = 1000) in the instrumentation amplifier stage. This feature makes it possible to handle common mode voltages, such as 50Hz interface voltage, nearly as high as the supply voltage and to achieve a high common mode rejection ratio (97dB) (d) a linear prebiased photovoltaic isolation amplifier to establish an isolation barrier for protecting the patient from potential electrical shock. This isolation method is a less expensive method and low isolated power consumption and also not affect the CMRR of the circuit. -104- 3-ISOLATION CONSIDERATIONS Tu/< u 5 c c 0 -u o V? t~~-A *) L 2 53 LL -1 05- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE CHAPTER 4 - Design Details and Validation of Performance 4.1 Design Details A major aim of this design is to consider a novel 8 channel# ECG preamplifier system which can be used as a base module for a multichannel (256 channels) ECG body mapping system. A schematic for the preamplifier system developed appears in Appendix. It includes: • input protection circuit • Wilson Central Terminal circuit • Driven Right Leg circuit and shield drive circuit • input unity gain buffer, AC coupling circuit and high CMRR instrumentation amplifier of AD624CQ with high gain • bipolar input photovoltaic isolation amplifier circuit • isolation power supply In this preamplifier system all of the circuitry will be powered by an isolated power supply module except for the output circuit of the bipolar input photovoltaic isolation circuit. With the limited available isolation power, selecting low power devices and carefully evaluating the parameters of bipolar input photovoltaic isolation circuit are very important for proper design. 4.1.1 Devices Selection The main devices which are provided with isolation power supply are the isolation optocouplers, operational amplifiers and instrumentation amplifiers. In the -1 06- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE circuit the isolated optocoupler is a monolithic linear optocoupler IL300 [Sie90] which consists of a light emitting diode (LED) and two photodiodes to receive the emitted light. It is capable of withstanding 7500V ac peak for 1 second, or 6250V ac peak for 1 minute. The IL300 also has a 0.01% servo linearity. In high fidelity ECG measurement, the high CMRR and linearity are crucial for a successful design. The operational amplifier is a dual package AD648CQ which is a low power device drawing less than 400uA from each supply for both amplifiers and low noise of 2uV p-p in the bandwidth 0.1-10Hz near to the maximum energy frequencies of the QRS complex. The instrumentation amplifier is AD624CQ which is a high CMRR with high gain. It draws less than 5mA. 4.1.2 Design of The Bipolar Photovoltaic Isolation Circuit An overview of the bipolar photovoltaic isolation circuit using IL300 optocoupler has already been provided in section 3.1.3. In order to establish the quiescent operation point Ipq to achieve the maximum desired dynamic range of the input signal and obtain the parameters of interest in the bipolar input photovoltaic isolation circuit, the prebias current and the maximum LED current supplied by isolated power must be evaluated carefully due to the limited available isolated power. Without considering the prebias current sources and the LED drive current in the isolation configuration the currents drawn from each isolated power supply for 8 channels on the isolated side of the barrier is 8 AD624CQ instrumentation amplifiers (8 x 5mA ) 40mA -1 07- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE 8 AD648C amplifiers for 16 input buffer amplifiers (8 x OAmA) 3.2mA 5 AD648C amplifiers for driven right leg and shield amplifiers (5 x OAmA) 2.0mA 4 AD648C amplifiers for isolated amplifiers (4 x OAmA) 1.6mA The isolated power device PWR1316A can provide a maximum of 63mA at +/- 12V for the isolated part and the total currents drawn from the above chips are 46.8mA. Hence, in 8-channel system the maximum available current for the current sources (/',) and the LED drive currents (ILED) is 63mA-46.8mA=16.2 mA, that is, for each channel the current source and the LED drive current can only have 16.2mA/8=2.025mA, or: ILED + IPX =2.025mA. +v IL300 K1\K2 +Visol Figure 4.1 Bipolar input photovoltaic isolation amplifier According to the equation (3.15), in the quiescent operation stage (V1N =0) the photocurrent IPX is equal to the current source ix. Hence, the following equation is obtained. -1 08- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE I led + IP\ - 2.025mA (3.28) In figure 3.7, it can been seen that the magnitude of the current IPX is directly proportional to the servo gain (Kx), multiplied by the LED drive current ILED, that is, IPX = KJ^. Hence, equation (3.28) can be rewritten as (1 + Kx )ILED = 2.025mA (3.29) The typical value of the servo gain Kx of IL300 is 0.007 [Sie90], Substituting Kx =0.007 into the equation (3.29), the LED drive current ILED will be 2.011mA. With the relationship IPX = KXILED the maximum photocurrent IPX will be 0.007 x 2.01lmA = \4uA. According to the transfer characteristic of prebiased photovoltaic bipolar amplifier (see figure 3.8), the quiescent operation current Ipq is set at the middle point of the maximum photocurrent IPX, that is 7uA. As a result, in the quiescent operation state the isolated current source will supply 7uA prebias currents Ibias. In figure 3.7, with the maximum desired input signal swing, VJNMAX = ±5V, the value of resistor Rx can be derived from Kirchhoffs current law as follows: ------= 7147:D (3.30) 14 uA - In A For unity gain of the isolated amplifier, that is Vo /V1N = 1, from equation (3.27) the resistor 7^ can be expressed as -1 09- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE (3.31) Typically the ratio K2/ Kx of IL300 within bin E is 0.93. Hence, the value of the resistor R1 is 161.1KQ. When the quiescent operation current I pq is 7uA and the servo gain Kx of IL300 is 0.007, using the relationship IPX = KXILED the LED current in the quiescent state can be obtained to be 1mA. For 1mA LED quiescent current IFq, the LED forward voltage VF is approximately equal to 1.15V (see figure 3. LED forward current vs.forward voltage in Sie90 ). With the positive isolation supply VISOL =+12F, the output of the operational amplifier Ax is targeted to be 50% of VJSOL, or 6 V. Thus, in figure 3.7, given the LED forward voltage VF and the output voltage Vopanipof the operational amplifier Ax, the LED current limiting resistor R4 can be calculated as follows _ ’v 1SOL -V' opamp -VF 12F-6F- 1.15F = 4.85 KQ (3.32) 1 mA In practical circuit, the transfer gain K3 (K3 = K2 / Kx) of the optocoupler IL300 has a range of 0.950-1.056 within code WF. So, in order to obtain a unity gain of resistor -1 1 0- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE 4.2 Testing Results A prototype system was designed and constructed comprising 3 ECG channels, lead I and lead II and a single chest lead. The measurements of 3 channels were carried out to test the function and the performance of the system. The output of this isolation preamplifier system was also connected to the Laboratoiy Workstation which can be conveniently used to record and display these ECG signals. The following are the results of performance tests. 4.2.1 Common Mode Rejection Ratio of Isolation Preamplifier The common mode rejection test was performed under the conditions required by the AAMI standard in which the impedance of 5 IK in parallel with a 47nF capacitor should be introduced. The test circuit is shown in figure 4.2 and test results were obtained by measuring the input voltage without the DRL and then measuring the output voltage with the DRL. The obtained CMRR of three channels are shown in TABLE 4.1. -111- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE 300mV 6.2Vrm: 50Hz Figure 4.2 Common mode rejection testing circuit TABLE 4.1 shows that the prototype system has a CMRR of approximately 115dB for all three channels with the driven right leg circuit (DRL). The AAMI requirement is that a 20Vrms signal (50Hz) applied to the common node through a lOOpF capacitor shall not produce an output signal exceeding lmVp-p referred to input over a 60 sec period. Under this requirement the CMRR of the amplifier should not be lower than 95.05dB. The measured values of CMRR in the present circuit are much higher than required. -11 2- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE Channel CH1 CH2 CH3 Vin (RMS) 3.23mV 3.22mV 3.23mV Vout (RMS) 3.301V 3.304V 3.298V Ad (V/V) 1022 1026 1021 Vin without DRL (RMS) 3.09V 3.09V 3.10V Vout without DRL (MRS) 38.79mV 42.31mV 50.12mV Ac (VA/) without DRL 0.012553 0.013692 0.016167 CMRR (dB) without DRL 98.21 97.49 96.0 Vout with DRL (MRS) 4.61 mV 3.80mV 6.53mV Ac (VA/) with DRL 0.001491 0.001229 0.002113 CMRR (dB) with DRL 116.71 118.42 113.68 TABLE 4.1. CMRR measurements and results 4.2.2 Preamplifier Frequency Response The frequency of the preamplifier is mainly characterised by the RC high pass filter which is used to block the DC offset. The response was obtained with frequencies in the range 0.01Hz to 1kHz. The magnitude and phase curve are plotted in figure 4.3 and 4.4 respectively. -113- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE MAGNITUDE (dB) FREQUENCY (Hz) Figure 4.3 Magnitude response for isolated preamplifier The magnitude response indicate that the low frequencies are roll off at 6dB per octave near the -3dB point and the -3dB point of the low frequency is at approximately 0.05Hz which agrees with the AHA recommendations (see chapter PHASE (Degrees)) FREQUENCY (Hz) Figure 4.4 Phase response for isolated preamplifier The phase response of the preamplifier shown in Fig 4.4 illustrates that the phase delay is only 18 degrees at 0.05Hz. -1 1 4- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE 4.2.3 50Hz Interference The test from the patient through measuring cables was performed by connecting the output of the prototype system to the Laboratory Workstation. Fig 4.5 and 4.6 show the ECG signal by setting the anti-aliasing filter of the Laboratory Workstation at 100Hz and 40Hz respectively. In Fig 4.5 because of high common mode rejection ratio of the isolation preamplifier (115dB at 50Hz) there is only a slight amount of noise in the signal. Comparing Fig 4.5 and Fig 4.6 the removal of the remaining 50Hz interference is achieved by the anti-aliasing filter at 40Hz. VOLTS ECG CH1 - LEAD II AT 100Hz 2mV r~ -1mV SECS Figure 4.5 Low pass anti-aliasing filter at 100Hz applied to prototype the system VOLTS ECG CH1 - LEAD II AT 40Hz -1mV SECS Figure 4.6 Low pass anti-aliasing filter at 40Hz applied to the prototype system -11 5- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE 4.2.4 Driven Right Leg In ECG measurements the common mode noise introduced from the environment can heavily distort the ECG signal. Normally some rejection of this noise can occur with the implementation of instrumentation amplifier. But the amplifier itself has a limited common mode rejection ratio. The use of the driven right leg is the most effective means of removing common mode noise at the source itself. The prototype system was measured both with and without the driven right leg connected. Fig 4.7 shows a ECG signal measured without driven right leg circuit (DRL) and Fig 4.8 shows a ECG signal with DRL. VOLTS ECG CH1 - LEAD II AT 100Hz WITHOUT DRL -1mV Figure 4.7 Interference noise without the DRL VOLTS ECG CH1 - LEAD II AT 100Hz WITH DRL -1mV SECS Figure 4.8 Interference noise reduced with the DRL -11 6- 4-DESIGN DETAILS AND VALIDATION OF PERFORMANCE Comparing Fig 4.7 with Fig 4.8 the common mode noise is significantly minimised by the Driven Right Leg circuit. -1 1 7- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM CHAPTER 5 - Interface Requirements for Body Potential System A multichannel opto-isolated instrumentation amplifier, developed to permit us to put 8 channels on one reasonably sized card, is described. In present ECG research, recording systems with a large number of measuring channels are often required. The primary purpose of this project is to consider a large body surface mapping system: ECG measurements with 256 channels. The system would consist of 32 cards, each having 8 channels. To be able to communicate with 32 cards the data acquisition part and computer interface of this recording system with respect to the processing of the large amount of data gathered must be considered as well. 5.1 Data Acquisition Before any data processing is performed by computer all data must be first converted into digital form. In multi-channel system the data acquisition architecture mainly includes channel-selecting multiplexer, programmable gain amplifier, anti aliasing filter, analogue to digital converter, programmable I/O device and computer interface. In each 8-channel card one of 8 analogue channels can be selected by 8-to-l analogue multiplexer. The multiplexer address needs to be decoded to enable the selected analogue channel to be programmed. After the output of the analogue multiplexer the ECG signal is required to be amplified by programmable gain amplifier to obtain the best resolution in the dynamic range of the analogue to digital converter. The software must be able to control the multiplexer and the -118- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM programmable gain amplifier to obtain a desired signal before the signal is converted into digital form (Fig 5.1). —fih [>> — 8-Channle Analogue — Input [>> —Kh programmable Gain —8b Amplifier --- — TT 1 2 3 4 5 6 7 8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LOGIC DATA CONTROL BUS 37 \z I/O Interface bus Figure 5.1 An 8-channel data acquisition block diagram Before the acquired ECG analogue signals may be sampled, higher frequencies that are not of interest must be rejected from the input signals. According to Nyquist criteria, sampling must occur at least at twice the frequency of the highest frequency signal to be captured, to avoid aliasing and noise. Aliasing is a condition produced with too slow a sampling rate. To avoid this problem an anti-aliasing filter is always present prior to analogue to digital conversion to filter higher frequencies above the ECG signal. Ideally the anti-aliasing filter must have a sharp roll off. But since practical filters will not fully attenuate signals in the cut-off-frequency range -11 9- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM without attenuating a signal in the passband, the sampling frequency is veiy often three or more times the cut-off-frequency of the anti-aliasing filter. In ECG signal processing if the cut-off-frequency of the anti-aliasing filter is at 250Hz, a 1000Hz sampling rate for each channel is adequate. In data acquisition, the A/D converter performs the key function of translating analogue measurements into digital information which can be processed by host -the computer bust. Usually the output of programmable gain amplifier is fed to a unity gain Sample and Hold Amplifier (S/H) which provides a stable voltage over the conversion period of the Analogue to Digital Converter. In this conversion period, the converter is operating on the sample from one channel but the multiplexer and programmable gain amplifier are already switching and settling out the next channel to be sampled. According to the AAMI performance standard that recommends 500Hz sampling with lOuV resolution, a 12bit A/D converter with a dynamic range of +/- 10V can achieve this standard. At unity gain this 12bit A/D converter will give a resolution of 4.88mV (20V/4096=4.88mV). However, at a typical gain of 1000 the resolution will increase to 4.88uV which exceeds the AAMI performance standard. Once converted, the data needs to be transferred from the output buffer of the A/D converter into the memory space of the host computer. Being capable of communicating with 32 cards of the body surface mapping system, the system needs a standard compatible connector and standard bus structure for transfering a large amount of data. The connector compatibility means that designers will be able to mix buses in a system (in this case the STEbus and PCbus). The bus is used for communicating between boards to transfer data efficiently. -1 20- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM 5.2 Standard Bus Considerations An interface is a shared boundary between systems. It is quite clear that there are many advantages, both to the systems user and their producer, in using well defined, accepted standards for these boundaries. As far as standardization of connections in general is concerned, the communication with the connection of one device to another is much easier. The most successful interfaces are those which are most ofter used. Over the years, since the Eurocard mechanical standards began to become popular throughout Europe and also to be adopted by US engineers, almost all the more recent buses have used the Eurocard as standard connector. Because Eurocard allows designers to maximise the use of enclosure space by including such as prototyping boards, power supplies and a variety of other functions, whether related or not, all within the same box. Moreover, the associated DIN 41612 connector offers far higher reliability for industrial applications than many other connector types, such as the edge-connectors used on other system. Manufacturers have developed a large number of Eurocard-compatible products that have ensured these DIN standards a foundation for building computer systems capable of operating in flexible environments. Being based on the DIN connector and Eurocard, STE bus suits all kinds of applications from data-acquisition and control to information-processing in low to medium complexity designs. Compared with older bus standards, such as STD and S100 with outdated signal schemes originally designed for a single 8-bit processor family, STE bus can be used with the latest generation of 8/16-bit processors and -121 - 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM also can be used with other buses to form relatively low cost multiple-bus system. The STE signal scheme may be summarized as follows [Win89] • an 8-bit bus embracing the Eurocard standard and designed for low cost • independence of processor manufacturers, giving the widest choice of processor on any 8-bit bus • provision for future requirements through asynchronous, non-multiplexed data transfers at over 5Mbyte/s • a full 1Mbyte addressing range • up to 4Kbyte I/O space • a position-independent, non-daisy-chained bus • multiprocessor capability • high-speed burst transfer mode • eight attention-request lines • vectored or non-vectored interrupts • interrupt-acknowledge cycle • read-modify-write cycle • fully buffered signals and terminated backplane for data integrity STEbus is a standard backplane bus. So it can be used to mix boards from any sources. Although designed for 8-bit data bus STEbus can also be used with the last generation of 8/16-bit processors. Another point worth noting is that due to a large number of established standards, most ascii data interchanged between systems and peripherals is almost universally byte organised. Consequently interfaces implemented for industrial computer systems are byte organized, such as IEEE488 General Purpose Interface Bus and asynchronous RS232C communication. Furthermore data is almost always transferred to and from storage media in byte -1 22- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM format, and data moving between the CPUs and the various I/O devices is necessarily transferred a byte at a time. This is wasteful of a wider path bus bandwidth. The most obvious way to understand this situation is to look at a 32-bit VME system, for example, 75% of the bus bandwidth is wasted each time an I/O byte is transferred over the bus. The ability to easily expand an active memory range is also a desirable attribute. The upper limit on the number of devices which communicate with the CPU in the system is determined by the total addressing space including I/O locations and memory addressing space of the bus. Many systems are limited by the restricted addressing ranges of earlier buses. Comparing with STDbus which has 64K-byte memoiy addressing space and 256-byte I/O space, the STEbus provides a lM-byte memory addressing region and 4K-byte I/O locations. Obviously the STEbus I/O capability is more larger than the STDbus. For most low to medium complexity system the STEbus I/O capability is enough. A major advantage of STEbus over the others is asynchronous operation which increases a system's useful lifetime by allowing of devices of different generations and operations speeds. However, this is a significant problem for most buses using synchronous operation to work with boards designed later in the standard's life. Figure 5.2 is the 64-signal STEbus pin-out defined on rows a and c of a DIN41612 connector. Address lines A0_l9 provide lM-byte of main memoiy addressing. Depending on the cycle, A0_n are used to address the 4K-byte of I/O space and Aq_2 provided a three-bit acknowledge address. Lines Z)0_7 are the eight bit data bus. -1 23- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM Signals ADRSTB and DATSTB are address and data strobes. Lines CM0_2 define the type of bus cycle in progress, i.e whether it is memory or I/O read or write, or an acknowledge. Request lines BUSQR0] are for use by temporary masters, BUSRQ0 being higher priority. The bus is asynchronous and DATACK is asserted when a master accepts data (on a read cycle) or when its data is valid (during a write). Signal TRFERR is used if data from a slave is wrong. Signals ATNRQ 0_7 are attention request lines and SYSCLK and SYSRST are for 16M system clock and reset functions. Remaining lines are for power with fully distributed grounds. -1 24- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM PIN Row a Row c 1 OV ov C ) r ) +5V 2 ( +5V ) c ) D1 3 ( DO ) c ) 4 ( D2 ) c D3 ) D5 5 C 04 ) c ) 6 ( 06 ) ( D7 ) 7 ( A0 ) c OV ) A1 8 C « ) c ) 9 C A4 ) c A3 ) A5 10 C A6 ) c ) 11 C AS ) c A7 ) A9 12 ( A10 ) ( ) 13 C A12 ) ( A11 ) A13 14 ( A14 ) c ) 15 C A16 ) ( A15 ) 16 ( A18 ) (_ A17 ) 17 ( CMO ) c A19 ) CM1 18 ( CM2 ) ( ) 19 ( ADRSTB* ) ( OV ) DATSTB* 20 ( DATACK* ) c ) ( TRFERR* ) OV 21 c ) SYSRST* 22 ( ATNRQO* ) c ) ATNRQ1* 23 ( ATNRQ2* ) ( ) 24 ( ATNRQ4* ) c ATNRQ3* J 25 ( ATNRQ6* ) ( ATNRQ5* ) 26 C ov ) ( ATNRQ7* ) 27 C BUSRQO* J ( BUSRQ1* ) 28 c BUSAKO* J ( BUSAK1* ) 29 c SYSCLK* J ( +VSTBY ) 30 c -AUXV J C +AUXV J 31 c +5V J r +5V 32 c OV 3 c_ OV j Figure 5.2 STEbus backplane signal assignment -1 25- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM 5.3 The host computer in the system A flexible measurement system should be such that its functionality can be selected for each individual user allowing the most efficient use without necessarily increasing the cost of the system. A suitable host computer as the system signal processing platform is desired to achieve the requirements. An IBM Personal Computer (PC) is a popular choice to fulfil the host computer role for the system because of its relative low cost and the large number of software packages availabe for it. Without any hardware design effort the PC provided a display system, keyboard, data storage mechanisms and power supply. Because of the added software available from word processing to engineering packages the PC has made a tremendous difference and become more popular for multi-use. You can switch off your test system and start using the PC for word processing for example. The PC also defined a standard bus which can interface to a lot of other useful commercial hardware. Because of the standard bus interface accommodated in the PC the instrument devices simply plug in the back of a PC and communicate with each other. The availability of the hardware and software provided by the PC can increase the flexibility and reduced the development time of the system. 5.4 The Bridge As previously stated the PC has several advantages as the system host computer. Within the PC there is an original 8-bit PC-XT bus implemented in a 62-pin edge connector. Many of the bus signals are used direct memory access and interrupt handling. The communication by the PCbus with the external transducer interface circuitry needs to have a bidirectional link both for data transmission and reprogramming use. -126- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM STEbus The PCLINK is a PC to SET bus- interface, which simplifies real time control system development by providing a software transparent link between PC compatible computers and the standardized STEbus. It is a two boards package. One called PPCLINK is installed in the PC expansion slot and the other called SPCLINK resides in each STEbus system. These two boards are connected by 50 way ribbon cable which can be up to 15 metres. Consequently the PC is used for program development, and the STEbus is used for low cost I/O. In this way the PC will become a master of the STEbus. Therefore, using PCLINK has several advantages: • Extending PCbus I/O to access STEbus peripherals • Monitoring STEbus processor activity • Simulating a STEbus target processor to develop software Accessing data from specific memory locations is central to the task of interfacing, no matter what kind of link is used. Normally memoiy is considered as data storage in which once a data is set it will keep that value until the processor write a new value to the same location. With the PCLINK functions the STEbus memory can be shared with PC and also the PC memory can be shared with STEbus. This means that the STEbus memory locations can be mapped into PCs memory area. With respect to the PC the procedure can be viewed as follows. An unprocessed data stream is fed into STEbus memory locations. The PC obtains the data stream which is mapped into PC memoiy area from the STEbus memory locations, then calculates new data values. After a period of time the values of STEbus memory location are altered to be a processed data stream which is available to be used as output. The PCLINK can open a 256 or 128-byte I/O window and 8K memory window into an STEbus system, then map these windows into unused areas of the PC addressing range. -1 27- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM The PPCLINK board which is installed in the PC expansion slot only uses the signals from the original 8-bit PCbus implemented in a 62-pin edge connector. It is noteworth that the PCbus address lines A0-A19 can address up to 1Mbyte of address space and PC processor can use all 16 lines A0-A15 to access up to 64Kbyte of I/O space. But only 10 lines A0-A9 are actually decoded restricting the number of available I/O space to 1024 bytes. Futhermore, many of the available I/O locations have been adopted by IBM for their own purposes, these assigned locations shown in Table 5.1. Despite the crowded nature of the I/O space there are several ports available, particularly in the region 300H-31FH which is reserved for prototype card address specified by the IBM Technical Reference Manual [IBM85]. However, certain peripheral board manufacturers have monopolized some of these addresses for their own products, which means to avoid conflicts with other interface cards it must be sure that no other interface cards using these addresses for I/O space. -1 28- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM Hex address range [000-01F] DMA controller. (MASTER) [020-021] INTERRUPT controller. (MASTER) [022-023] CHIPSET control registers I/O ports. [040-05F] TIMER control registers [060-06F] KEYBOARD interface controller. [070-07F] RTC ports & CMOS I/O ports. [080-09F] DMA register. [0A0-0BF] INTERRUPT controller. (SLAVE] [0C0-0DF] DMA controller. (SLAVE) [0F0-0FF] MATH COPROCESSOR [1F0-1F8] HARD DISK controller. [278-27F] PARALLEL port-2 [2B0-2DF] GRAPHICS adapter controller. [2F8-2FF] SERIAL port-2. [360-36F] NETWORK ports. [378-37F] PARALLEL port-1. [3B0-3BF] MONOCHROME & PRINTER adapter. [3C0-3CF] EGA adapter. [3D0-3DF] CGA adapter. [3F0-3F7] FLOPPY DISK controller [3F8-3FF] SERIAL port-1 TABLE 5 1 Address space for PC I/O devices The communication between PC and STEbus can be performed by software controlling a memory to memory transfer between PCbus memoiy and STEbus memory locations. The PC addresses of memoiy window occupied 8Kbyte and 256 or 128byte I/O window can be switch-programmed, and the STEbus addresses both of memory and I/O space are register-programmed, shown in Figure 5.3. -129- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM STEbus memory space Switch- Memory defined Window (8K) PCLINK RAM (32K) LinK defined PCbus STEbus I/O space I/O space Switch^. Control registers defined I/O window Switch^. (128 or 256 bytes) defined I/O window (128 or 256 bytes) Figure 5.3 Memory window and I/O window in PC and STEbus space There are three Dual Inline Package (DIP) switches on the PPCLINK board used to select three base addresses of the PC: control register base address, 8K memory window base address and EO window base address. A switch 'on' will select a low bit pattern and 'off will select a high bit pattern for the base address bits. It must be ensured that all these base addresses are unoccupied by other PC device to avoid conflicts. The PCLINK control registers occupy an 8 bytes block in the PC EO space. The base address of control register can be selected to be 21 OH which is unoccupied assigned I/O location (see TABLE 5.1). The base address of 210H will result in the DIP switch pattern shown in TABLE 5.2. -1 30- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM A9 A8 A7 A6 A5 A4 A3 SWA OFF ON ON ON ON OFF ON Bit 1 0 0 0 0 1 0 HEX 2 1 0 TABLE 5.2 PCbus control register base address switch settings The 128-byte I/O window forms the main I/O communication pathway between the PCbus and the STEbus. The PCLINK allows many of the STEbus devices to use this 128-byte I/O window for transfering their I/O memoiy locations to the PCbus I/O memory space. This means that if each STEbus device has a certain I/O base address the PC can read out the value from the control register in which the value represents the I/O base address of the device, then map the STEbus memory window located at the base address of the device into the 128-byte I/O window of the PC. In the same manner when the PC needs to communicate with the STEbus device the value which is previously defined as the I/O base addresss of the device will be loaded into the control register then the data appears in the PCbus I/O space will be automatically transfered to the STEbus memory location at the base address of the device. For this reason the STEbus devices need to have different base addresses which allow the PC to be easily accessed by programming the control register. The control register located at address 215H (base +5) can be programmed to define which 128-byte window of STEbus I/O space presents on the PC I/O space. This control register format is shown in TABLE 5.3 D7 D6 D5 D4 D3 D2 D1 DO NA NA NA NA A11 A10 A9 A8 TABLE 5.3 Control register: Start of I/O window in STEbus memoiy space As previously stated the PCLINK uses a DIP switch to choose the EO base address and open a 128-byte EO window on the PC I/O map. Looking for a suitable -131- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM unoccupied I/O space for this 128-byte I/O window in the PC I/O map, the region 100H-1EFH is available for this window, see TABLE 5.1. When the base address is considered to be located at 100H the DIP switch pattern will be shown in TABLE 5.4. A11 A10 A9 A8 swc ON ON ON OFF Bit 0 0 0 1 HEX 1 TABLE 5.4 Set PCbus I/O window base address Linked with a current signal processing device which has a I/O base address 400H for example, the PC sets the I/O window by writing 04H to the STEbus I/O base-address register shown in TABLE 5.3. At this time the signal processing device can communicate with the PC through the I/O window. 5.5 Programmable Input and Output Device Communication between the real world and the PC is through the ports of the peripheral interface adapter. These relatively complex and specialized peripheral interface adapter can be programmed to behave as input and output devices and effectively buffer the data stream from the peripheral, thereby protecting the system. Using I/O memory window opened into PC I/O space to map the input and output between the PC and I/O device ensures that the PC "sees" the ports simply as a collection of addresses. Consequently the operation of these devices are simply performed by placing the required bit patterns in the appropriate control registers Due largely to the established particular programmable input and output device is suitable to STEbus system with PCLINK, the SPINC as input and output peripheral interface is chosen to fulfil the role for this system. The SPINC mainly -1 32- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM uses two Zilog Z8536 CIO (Counter/time and Parallel I/O) chips to provide 6 I/O ports and also consists of ten 8-bit registers to control the available I/O ports where the outside devices are located. The 10-register map is shown in figure 5.4. Address Bit Function Base Port C / 3-1 Input only 0 Output only CI01 Base+1 7-0 Port B Base+2 7-0 Port A Base+3 7-0 Control \ Base+4 Port C / 3-1 Input only 0 Output only CI02 Base+5 7-0 Port B Base+6 7-0 port A Base+7 7-0 Control \/ Base+8 7-0 Reading this location generates an INTACK cycle to acknowledge the interrupt being serviced Base+12 7-0 Buffer control. Direction T [__ Enable (PB of CI02) (PA of CI01) Enable ______Direction (PB of CI02) (PB of CI01) Direction___ __ Enable (PA of CI02) (PB of CI01) Enable ___ Enable (PA of CI02) (PC of both CIO chips) Figure 5.4 SPINC registers map To explain the adopted interfacing I/O device SPINC with clarity it is necessaiy to describe the chip functions. The Zilog Z8536 CIO Counter/Timer and Parallel I/O chip is a general purpose programmable peripheral interface. This device contains three I/O ports and three counter/timers. The software configurable offers the flexibility of design in which the value placed in the control register determine which groups of lines are inputs and outputs to specific applications. Communication between the microprocessor and the real would is through the 20 input-output lines. These are divided into two groups of eight lines, 8-bit double- -133- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM buffered bidirectional I/O ports A and B, together with a group of four lines which is a 4-bit special purpose I/O port C. The operation of the I/O ports can be controlled by the format of the 8-bit word written to the control registers. Making the ports become programmable polarity and programmable direction. INTERRUPT PORT ------N CONTROL/1 INTERRUF^- L0GIC ^ PORT I/O DATA BU CPU r PORT INTERFACEV PORT A COUNTER^ I/O V TIMER 3 V CONTROL1 INPUTS INTERNAL CONTROLA COUNTERS LOGIC V TIMER 2 - PORT PORT B COUNTERS I/O TIMER 1 - Figure 5.5 Zilog Z8536 CIO programmable port block diagram The programmable Z8536 consists of 48 internal registers including 8 main control registers, 8 most often accessed registers, 16 counter/timer related registers, 8 port A specification registers and 8 port B specification registers. Due to the internal register configuration which differs from the venerable programmable peripheral interface Intel 8255 the Z8536 requires two steps of I/O operation to access any of these registers. The first step is to send the internal register address represented the expected I/O function into a certain register and the second is the control word. For example, simple port A input-output operations, with interlocked handshaking, require firstly the port A handshake specification register address 20H to be sent and then the format of the 8-bit control word in which zeroes are written. -1 34- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM Thus the port A is specified as a bit port. The handshake specification register is shown in figure 5.6. During bit port operations, if the port A is further required to be a input or output port two I/O operations will be such that the first data byte sent is the address of the port A data direction register 23 H, and the second byte sent is the value of the register. The port A data direction register as shown in figure 5.7 specifies the direction of data flow for each bit. A 1 specifies an input bit, and a 0 specifies an output bit. Port A Address 10000 (20H) D7| D6 D5j D4 D3 D2 Dl[ DO HANDSHAKE TYPE SPECIFICATtO DESKEW TIME SPECIFICAFION HST1 HST2 BITS (HST) BITS SPECIFIES THE MSB's OF DESKEW TIMER TIME CONSTANT 0 0 INTERLOCKED HANDSHAKE LSB IS FORCED 1 0 1 STROBED HANDSHAKE 1 0 PULSED HANDSHAKE 1 1 REQUEST/WAIT SPECIFICATION------BITS (RWS) RWS2 RWS1 RW3HUNCTION 0 0 0 REQUEST/WATOISABLED 0 0 1 0 1 1 INPUT WAIT 1 0 0 SPECIAL REQUEST 1 0 1 OUTPUT REQUEST 1 1 1 INPUT REQUEST Figure 5.6 Port handshake specification register PORT A ADDRESS: 100011 (23H) D7 D6 D5 D4 D3 D2 D1 DO ------DATA DIRECTION 0=OUTPUT BIT 1=INPUT BIT Figure 5.7 Data direction register As previously stated the SPINC as a programmable peripheral interface of the STEbus system communicates with the PC by the PCLINK. When the base address of the SPINC is selected for example 3C0H, (on the SPINC board the base address -1 35- 5-INTERFACE REQUIREMENTS FOR BODY POTENTIAL SYSTEM is selected by jumpers in the link area 1) the PCLINK can open a 128-byte I/O window on the PC I/O map for the communication between the PC and the SPINC by the base address of the SPINC (3C0H) written to the PCLINK control register located at address 215H (base + 5). Thus, the input or output data stream of the SPINC can be processed by the PC through the PCLINK and the PC becomes the master of the SPINC. -136- CONCLUSIONS CONCLUSIONS In this thesis a new design of an isolated biopotential preamplifier is presented which achieves high gain, high differential and common mode input impedances, high CMRR, ac coupling and satisfies all international standards for safety and performance. The report also illustrates how to calculate and analyse the CMRR of cascaded differential amplifier stages for either differential output or single ended output. In a cascaded differential system with single ended output the analysis of the CMRR include the CMRR of the single ended output stage. This is because the mismatch of the resistor ratio and the limited CMRR of the op amplifier itself to be considered in the single ended output stage. Using a potentiometer in the second RC stage to compensate for the unmatched operational amplifiers in the first stage can improve the CMRR of the system. But the compensation is limited because the condition, CMRRf = -CMRRS, is difficult to meet. A new method of providing patient isolation using linear optocouplers with optical servo technique is analysed in this report. It shows that the method of prebiased bipolar input photovoltaic isolation amplifier connected directly to the differential amplifier output will not affect the system CMRR. It also proves that the differential prebiased photovoltaic isolation amplifier which combines two bipolar input photovoltaic isolation amplifiers with a simple differential amplifier may make it difficult to meet high CMRR requirements. A novel way to communicate between a multiple ECG body potential system and a host PC is introduced. In this method emphasis is placed on accessing data from specific memory locations and mapping STEbus memoiy locations into PC memory area. As a research based analysis tool the system flexibility is -137- CONCLUSIONS implemented more and more towards software development. Hence, the software development will be desirable to complete the system. The design presented in this thesis includes input protection circuitry, cable shielding, driven right leg circuitry, instrumentation amplifiers and analogue isolation barrier. However, from the point of view of a complete ECG measuring system the ECG analogue data needs to be digitised and then passed to the host PC. The PCLINK can be used as bridge to access data between the PC and the external I/O device. The proposed development plan for the system will still require • completing the anti-aliasing filter before the acquired analogue signal to be sampled. The anti-aliasing filter must always be present prior to analogue to digital conversion to avoid aliasing problems. • providing a programmable gain stage to extend the dynamic range of the analogue to digital converter. This will allow a greater resolution of the analogue to digital converter. • arrange a selected analogue multiplexer to enable the selected analogue channel to be sampled in the multi-channel system. • using a high resolution (12-Mbit) analogue to digital converter to digitise the analogue signal. • write PCLINK and SPINC code to drive the programmable gain stage, analogue multiplexer and analogue to digital converter. -138- CONCLUSIONS • write the PC software to display real time ECG data on the screen. -139- REFERENCES REFERENCES AD624 "Linear Products Databook", Analog Device Inc. 1990-91, pp4-49,60. AD708 "Linear Products Databook", Analog Device Inc. 1990-91, pp2-159,166. AD648 "Linear Products Databook", Analog Device Inc. 1990-91, pp2-159,166. Alm70 Almasi, J.J.and Schmitt,O.H. Systemic and random variations of ECG electrode impedance. Ann. NY Acad. Sci., 170,509-519 1970. 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Spatial features and effects of myocardial infarction. J.Electrocardio. 18,185-193.1985. Pal88 Pallas-Areny, R. Interference-Rejection Characteristics of biopo- tential Amplifier: A Comparative Analysis. IEEE Transactions on Biomedical Enginerring, Vol 35, No 11, November 1988. pp953-959. Pal90 Pallas-Areny, R. and Webster, J.G. Composite instrumentation amplifier for biopotentials. Annals of Biomedical Engineering, Vol 18, pp.251- 262,1990. -1 43- REFERENCES Pal91-1 Pallas-Areny, R. and Webster, J.G. Common mode rejection ratio in differential amplifiers. IEEE Trans. Instrum.Meas., vol.40,669-676.1991. Pal91-2 Pallas-Areny, R. and Webster, J.G. Common mode rejection ratio for cascaded differential amplifier stages. IEEE Trans.Instrum. Meas., vol. 40,677-681.1991. Phi77 Small signal diode handbook, Philips Corporation, 1977. Rig79 Riggs, T. Isenstein, B. Thomas, C. Spectral analysis of the normal electrocardiogram in children and adults. J. Electrocardiol. 12, 377- 379.1979. Ros88 Rosell, J., Colominas, J., Riu,P., Pallas-Areny, R. and Webster, J.G. Skin impedance from 1Hz to IMHz.IEEE Trans., BME-35,649-651.1988. Sch78 Schick, T.D. and Powers, S.R. Jr. Spcetral analysis of the high frequency electrocardiogram in contusive myocardial injury. Ann. Biomed. Eng. 6,154-160.1978. Sch71 Schoenfeld, R.L. Common-mode rejection ratio-two definitions. IEEE trans. Biomed. Eng.BME-17,73-74,1970. Further comments in BME- 18,251,1971. Scl86 Sclarovsky, S., Davidson, E., Lewin, R., Strasberg, B., Arditti, A., Agmon, J. Unstable angina pectoris evolving to acute myocardial infarction: -1 44- REFERENCES Significance of ECG changes during chest pain.Am Heart J. 112:459- 462.1986. Sie88 Transient supression devices data sheet, Siemens, 1988. Sie90 Designing linear amplifiers using the IL300 optocoupler, Siemens, 1990. Sie91 Designing linear amplifiers using the IL300 optocoupler, appnote 50, Siemens, 1991. Sil83 Silverman, M.E. Electrocardiography. MaGraw-Hill, Inc. Chapter 1, PP5- 12.1983. Smi77 Smither, M.A., et al. CMRR analysis of the 3-op-amp instrumenta- tion amplifier. Electronics Letters, 13, P. 594,1977. Swa74 Swanson,D.K.and Webster J.G. A model for skin-electrode impedance. In: Miller, A.H., Harrison, D.C. eds. Biomedical Electrode Technology. New Youk: Academic Press, 117-28.1974. Szy83 Szynowski J. CMRR analysis of instrumentation amplifiers. Electronics letters, Vol.19, No. 14, pp547-549. 1983. Tay83 Tayler D., Vincent R. "Signal distortion in the Electrocardiogram due to inadequate Phase response. IEEE Transactions on Biomedical Engineering, 1983; 30:6; pp 352-356. -145- REFERENCES Wil34 Wilson, F.N., Johnston, F.D., MacLeod, A.G., Barker, P.S. Electrocar diograms that represent the potential variations of a single electrode. Am. Heart J.9:447-458.1934. Wil47 Wilson, F.N., Johnston, F.D., Kossmann C.E. The substitution of a tetrahedron for the Einthoven triangle. Am Heart J. 33:594-603. 1947. Win83 Winter, B. and Webster, J.G. Driven-Right-Leg Circuit Design IEEE Transactions on Biomedical Enginerring, Vol BME-30, No 1., Januray, 1983. pp62-66. Win89 Winter, A. Dual buses for industrial I/O J.Electronics & Wireless World pp517-519 May 1989. Won76 Wong, Y.G. and Ott, W.E. Functional circuits: design and applications. McGraw-Hill, New York, 42-45.1976. Zyw89 Zywietz, C. Electrode-Skin Impedance and Offset Voltage. In: Macfarlane, P.W. and Veitch Lawrie, T.D. eds. Comprehensive Elec trocardiology, 365-68.1989. -1 46- APPENDIX ECG Isolation Preamplifier Circuit Diagrams !■■■ ■■ >> Q GODO i >> COCO ZZ (J (J + + Q.inoLincLin Q.inQ.inQ.in Q.inQ_ino.in _j in o q^gngm o ^ o in o in 1/1 in in in in r>AAr>r»Ar»AAAAA iiHHUuyuaari in \s\sww\sww\s in in in _j _j sr ininvavQ HH1" HHf —Iff HH'" HBP HB1" HBP HBP HBP > UJ H ct <£- z H % >- O' IP ro K Id Id O Id _J h- z . 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