(12) United States Patent Retre 3O4
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USOO8964818B2 (12) United States Patent (10) Patent No.: US 8,964,818 B2 Longo et al. (45) Date of Patent: Feb. 24, 2015 (54) USE OF MULTI-LEVEL MODULATION 375/300; 375/316; 375/320; 375/346 SIGNALING FOR SHORT REACH DATA (58) Field of Classification Search COMMUNICATIONS USPC ......... 375/219, 233, 340, 232, 242, 268, 286, 375/288, 295,300, 316, 320, 346 (71) Applicants: Lorenzo Longo, Laguna Beach, CA See application file for complete search history. (US); Vivek Telang, Austin, TX (US) (56) References Cited (72) Inventors: Lorenzo Longo, Laguna Beach, CA (US); Vivek Telang, Austin, TX (US) U.S. PATENT DOCUMENTS 7,376,199 B1* 5/2008 Nix ............................... 375,295 (73) Assignee: Broadcom Corporation, Irvine, CA 2003/01940 16 A1* 10, 2003 Gorecki et al. ... 375,268 (US) 2008, OO69570 A1* 3, 2008 DalleSasse ..... ... 398,139 2008/0101510 A1* 5/2008 Agazzi ....... 375,346 (*) Notice: Subject to any disclaimer, the term of this 2013/0027088 A1 1/2013 Francese ......................... 327/74 2013/0077669 A1* 3/2013 Malipatilet al. ... ... 375,233 patent is extended or adjusted under 35 2013/0114665 A1 5/2013 Aziz et al. .......... ... 375,233 U.S.C. 154(b) by 0 days. 2013/0163126 A1* 6/2013 Dong .............................. 361.56 2013/0287088 A1* 10/2013 Mobin et al. .................. 375,233 (21) Appl. No.: 13/739,782 * cited by examiner (22) Filed: Jan. 11, 2013 Primary Examiner — Siu Lee (65) Prior Publication Data (74) Attorney, Agent, or Firm — Garlick & Markison; Randy W. Lacasse US 2014/O15362O A1 Jun. 5, 2014 (57) ABSTRACT Related U.S. Application Data A short reach communication system includes a plurality of communication SERDES that communicate data over a short (60) Provisional application No. 61/732,077, filed on Nov. reach channel medium such as a backplane connection (e.g., 30, 2012. PCB trace) between, for example, chips located on a common (51) Int. C. PCB. A multi-level modulated data signal is generated to H04B I/38 (2006.01) transmit/receive data over the short reach channel medium. H04L 25/219 (2006.01) Multi-level modulated data signals, such as four-level PAM, (52) U.S. C. reduce the data signal rate therefore reducing insertion loss, CPC .................................. H04L 25/4917 (2013.01) power, complexity of the circuits and required chip real USPC ........... 375/219; 375/233; 375/340; 375/232; estate. 375/242; 375/268; 3.75/286; 375/288; 3.75/295; 18 Claims, 9 Drawing Sheets 31 RANSTER Tx 303 We 3OO retre 3O4. 1 RECEIVER U.S. Patent Feb. 24, 2015 Sheet 1 of 9 US 8,964,818 B2 1 O. G. pc RACE SR Claire U.S. Patent Feb. 24, 2015 Sheet 2 of 9 US 8,964,818 B2 SEREES 201 (CB RACE SR Care U.S. Patent Feb. 24, 2015 Sheet 3 of 9 US 8,964,818 B2 301 TRANSMITTER 3OO RECEIVER VING RECOVERY Clock CDR Out 308 GDI-SLICER reFEC 9t 3O7 31 O DFE 309 U.S. Patent Feb. 24, 2015 Sheet 4 of 9 US 8,964,818 B2 U.S. Patent Feb. 24, 2015 Sheet 5 Of 9 US 8,964,818 B2 2in FR4, connector 14.8 dBg4GHz INSERTION LOSS SEEN BY CONVENTIONA 2-LEVE. : NR2 SERIES : F. 3 U.S. Patent Feb. 24, 2015 Sheet 6 of 9 US 8,964,818 B2 80 RANSER SOO Data 603 Pre-Emph - Driver 804. Channe K 805 RECEIVER 8. RECOWERY N sLICER 67 U.S. Patent Feb. 24, 2015 Sheet 7 Of 9 US 8,964,818 B2 FG. U.S. Patent Feb. 24, 2015 Sheet 8 of 9 US 8,964,818 B2 2in FR4, connector 3:::::::::::::::::: ................::::::::::::8:::::::::::::::::::::::::::::::::::::...: 8.4 dB(3.7GHz insertion loss Seen by : 4- level PAM-4 SERDES FG, 8 U.S. Patent Feb. 24, 2015 Sheet 9 Of 9 US 8,964,818 B2 power (typ.) | power (max) | Area US 8,964,818 B2 1. 2 USE OF MULTI-LEVEL MODULATION 3. IEEE Std 802.3baTM, “IEEE Standard for Information SIGNALING FOR SHORT REACH DATA technology IEEE 802.3ba defines a 40 Gbit/s and 100 COMMUNICATIONS Gbit/s Ethernet. 40 Gbit/s over 1 m backplane, 10 m Cu cable assembly (4x25 Gbit or 10x10 Gbit lanes) and 100m of MMF CROSS REFERENCE TO RELATED and 100 Gbit/s up to 10 m of Cu cable assembly, 100 m of APPLICATIONS MMF or 40 km of SMF respectively. 4. IEEE Std 802.3bmTM, “IEEE Standard for Information The present U.S. Utility Patent Application claims priority technology—IEEE Standard for Information technology— pursuant to 35 U.S.C. S 119(e) to the following U.S. Provi Telecommunications and information exchange between sys sional Patent Application which is hereby incorporated herein 10 tems—Local and metropolitan area networks—Specific by reference in its entirety and made part of the present U.S. requirements Part 3: Carrier Sense Multiple Access with Col lision Detection (CSMA/CD) Access Method and Physical Utility Patent Application for all purposes: Layer Specifications Amendment: Physical Layer Specifica 1. U.S. Provisional Application Ser. No. 61/732,077 tions and Management Parameters for 40 Gb/s and 100 Gb/s entitled “Use of Multi-Level Modulation Signaling for Short 15 Operation Over Fiber Optic Cables. Reach Data Communications, filed Nov.30, 2012. Currently, wireline and wireless communications occur within licensed or unlicensed frequency spectrums. For BACKGROUND OF THE INVENTION example, wireline systems, such as those using fiber optics as a transfer medium, operate in the GHZ frequency spectrum 1.Technical Field of the Invention (e.g., 25 GHz-100 GHz). This invention relates generally to communications and Channel loss at high data speeds (e.g., Gigabit/sec (Gb/sec) more particularly to circuits used to Support short reach com range, plus) may be influenced by decisions made around munications. power and chip area costs. One area for consideration, input/ 2. Description of Related Art output (I/O), uses high speed SERDES circuitry. A serializer/ Communication systems are known to Support wireline 25 deserializer (SERDES) converts data between serial data and and wireless communications between various devices. Such parallel interfaces in each direction. The term “SERDES' communication systems include, for example, backplane, generically refers to interfaces used in various technologies chip-to-chip, copper wire (e.g., trace), fiber optic communi and applications. The basic SERDES function is made up of cations, national and/or international cellular telephone sys two functional blocks: a Parallel In, Serial Out (PISO) block tems, satellite, cable television, the Internet, point-to-point 30 (aka Parallel-to-Serial converter) and a Serial In, Parallel Out in-home wireless networks and radio frequency identification (SIPO) block (aka Serial-to-Parallel converter). (RFID) systems. Each type of communication system is con The PISO (Parallel Input, Serial Output) block typically structed, and hence operates, in accordance with one or more has a parallel clock input, a set of data input lines, and input communication standards. For instance, short reach commu data latches. It may use an internal or external Phase-locked nication systems may operate in accordance with one or more 35 loop (PLL) to multiply the incoming parallel clock up to the standards including, but not limited to, IEEE 802.3 iii. Wire serial frequency. The simplest form of the PISO has a single less communication systems may operate in accordance with shift register that receives the parallel data once per parallel one or more standards including, but not limited to, 3GPP. clock, and shifts it out at the higher serial clock rate. Imple LTE, LTE Advanced, RFID, IEEE 802.11, Bluetooth, mentations may also have a double-buffered register. advanced mobile phone services (AMPS), digital AMPS, 40 The SIPO (Serial Input, Parallel Output) block typically global system for mobile communications (GSM), code divi has a receive clock output, a set of data outputlines and output sion multiple access (CDMA), local multi-point distribution data latches. The receive clock may have been recovered from systems (LMDS), multi-channel-multi-point distribution the data by the serial clock recovery technique. However, systems (MMDS), and/or variations thereof. SERDES which do not transmit a clock use reference clock to The following IEEE standards/draft standards are hereby 45 lock the PLL to the correct TX frequency, avoiding low har incorporated herein by reference in their entirety and are monic frequencies present in the data stream. The SIPO block made part of the present U.S. Utility Patent Application for all then divides the incoming clock down to the parallel rate. purposes: Implementations typically have two registers connected as a 1. IEEE Stds 802.3#TM (generically), “IEEE Standard for double buffer. One register is used to clock in the serial Information Technology—IEEE 802.3 is a working group 50 stream, and the other is used to hold the data for the slower, and a collection of IEEE standards produced by the working parallel side. Such serializer encoder and deserializer decoder group defining the physical layer and data link layer's media blocks are generally defined in the Gigabit Ethernet specifi access control (MAC) of wired Ethernet. This is generally a cation. local area network technology with some wide area network Conventional high-speed SERDES I/O use 2-level non applications. Physical connections are made between nodes 55 return-to-Zero (NRZ) signaling. As data rates increase to 25 and/or infrastructure devices (hubs, switches, routers) by Gb/sec and beyond, the power and area costs of these SER various types of copper or fiber cable. 802.3 is a technology DES increase hyper-linearly with the rate.