Cache Timing Side-Channel Vulnerability Checking With
Cache Timing Side-Channel Vulnerability Checking with Computation Tree Logic Shuwen Deng, Wenjie Xiong and Jakub Szefer Yale University New Haven, Connecticut {shuwen.deng,wenjie.xiong,jakub.szefer}@yale.edu ABSTRACT can then be used to leak secrets of a victim program, and this has Caches are one of the key features of modern processors as they been exploited by the various cache timing side-channel attacks, help to improve memory access timing through caching recently e.g., [1, 5, 7, 21, 30]. used data. However, due to the timing dierences between cache To address the security issues of cache timing side-channel at- hits and misses, numerous timing side-channels have been discov- tacks, numerous secure processor caches have been designed and ered and exploited in the past. In this paper, Computation Tree analyzed through simulation and probability analysis in attempt Logic is used to model execution paths of the processor cache logic, to prove that the proposed caches indeed prevent attacks [12, 13, and to derive formulas for paths that can lead to timing side-channel 26, 27, 33–36, 39, 40]. Furthermore, to reason about the dierent vulnerabilities. In total, 28 types of cache attacks are presented: 20 attacks, researchers have classied cache timing side-channels on types of which map to attacks previously categorized or discussed basis whether the attacks leverage cache hits or misses and whether in literature, and 8 types are new. Furthermore, to enable practical they are access-based or reuse-based, and whether the attacks lever- vulnerability checking, we present a new approach that limits the age internal or external interference [22, 41].
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