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Hdlplanner: Design Development Environment for HDL-Based FPGA Designs

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Hdlplanner: Design Development Environment for HDL-Based FPGA Designs HDLPlanner®: Design Development Environment for HDL-based FPGA Designs Design Abstract design cycle involving simulation, syn- thesis and testing. Development Rapid prototyping of designs using From a synthesis perspective, the most FPGAs requires HDL-based design appealing benefits of using HDLs are the for HDL-based entry which leverages upon highly ability to parameterize modules and the parameterized components in conjunc- technology independent manner in FPGA Designs tion with an ability to translate these which designs can be created. Module components to layouts. Designs that are parameterization encourages reusing developed with layout related consider- existing design effort and offers a conve- ations more often tend to become Application nient and powerful method for technology specific. This has a direct customizing modules in the environment consequence in migrating designs to Note in which they are used. Another impor- ASICs and may require a design to go tant advantage of using anHDL centric through an additional design cycle. approach is to leverage upon the design HDLPlanner solves this problem by pro- optimization support that is built into all viding an environment for creating HDL tools. This optimization support technology independent HDL designs, allows rapid searching for a design solu- which when translated to Atmel FPGAs, tion that meets user’s constraints in an are guaranteed to produce performance automated, correct by construction fash- delivering layouts. The primary contribu- ion. All these benefits make HDLs a tion of the HDLPlanner is its ability to preferred choice for designers involved address layout considerations up front in in rapidly prototyping digital systems the design process without compromis- using FPGAs. ing the technology independence of the design. In doing so, the planner parti- HDL centric approach, on the other tions the design creation process hand, can result in severe penalty if the between itself and the synthesis soft- synthesis and optimization support that ware in the following way. It manages is built into it is used without giving a due layout related considerations by itself consideration to underlying technology. and delegates the task of random logic This is particularly true in the case of optimization to synthesis software. The FPGAs because synthesis tools cannot planner is tightly integrated with MGL incorporate FPGA technology specific Parameterized Layout Synthesis Soft- issues such as logic cell, RAMs, tri-state ware [1] which produces highly efficient resources, clock and reset scheme etc. layouts of the components. during synthesis, to produce good qual- ity designs (these issues are dealt in the later part of this section) . The outcome Motivation can be a large netlist which may not be Hardware description languages (HDL) placed and routed in an optimum are increasingly replacing schematic ori- fashion. ented design entry methods because Some recent improvements in synthesis they offer a very short and efficient technology have partially overcome Rev. 1444A–10/99 these shortcomings. A notable improve- 1 ment called operator inferencing, identifies operator gate level representations. In many cases, however, opera- functions from HDL expressions and links them to their pre- tor inferencing does not guarantee optimal results, a case ferred layout implementation instead of constructing their for which is given in Figure 1. Figure 1. (a) VHDL template of registered adder. (b) Optimized implementation and (c) preferred implementation. PROCESS (CLOCK, RESET) BEGIN A B A B IF (RESET = 'B0) THEN SUM <= "00000000"; ELSE IF (CLOCK = '1' AND CLOCK EVENT) SUM <= A + B; END IF; REGISTER BANK REGISTER BANK END PROCESS; (A) (B) (C) The operator inferencing has one more limitation- only and a search for an optimal solution often requires manual operators that are supported in the language can be intervention in the design process. inferred. Simple building blocks such as counters and decoders cannot be inferenced and must be explicitly used Limitations in Languages and Software Tools in the design. Explicit references to cells can cause design portability problem. Some limitations in HDLs, as described below can have a significant bearing on the quality of the synthesis results. In addition to the shortcomings in synthesis technology as An example of these limitations is the inability to parame- discussed above, issues that are specific to FPGA technol- terize design modules with respect to clock, set and reset ogy and limitations that are inherent to HDL languages and schemes (i.e., according to active edges and polarities, synthesis systems are discussed below. respectively). In the absence of this capability, re-using modules can be a difficulty to achieve. In some cases, lack FPGA Technology Specific of the provision is also likely to create designs which may indiscriminately use limited numbers of clock and reset Considerations resources available on FPGAs. Synthesis tools perform an architecture specific optimiza- Besides the problem outlined above, CAE vendors do not tion, without giving due consideration to the technology seem to have a consistent method for supporting parame- contents of the FPGA device (1). terization in Verilog. For example Synopsys recommends Note: 1. The term FGPA architecture is broadly used to iden- using the parameter construct and Exemplar recommends tify architecture of the basic logic cell in it. using the defparam construct to define the parameters. What is really desired from the performance standpoint is This difference can cause design migration problems to accommodate technology specific resources in the between synthesis platforms. design synthesis. Examples of such resources are clock and reset resources, tri-state resources, wired logic Proposed Solution resources, I/O buffers, on-chip configurable memory Atmel Corporation has developed a design planning envi- resources and their address decoding circuitry etc. A cost ronment called HDLPlanner that encourages users to driven optimization of these resources is important to follow meet-in-the-middle methodology for creating HDL uncover optimum performance from an underlying technol- designs. HDLPlanner can be considered as a design man- ogy. We are not aware of any synthesis system which can ager tool which enforces design partitioning and generates fully understand and utilize technology specific information instructions to synthesis and placement software towards to perform constraint driven synthesis. an objective of creating highly regular and efficient imple- The limiting factors described above leave designers very mentations. It does so by encouraging designers to limited options for maintaining technology independence partition the system into a set of basic building blocks. It 2 FPGAs FPGAs then provides highly parameterized behavioral HDL The remainder of this paper is organized as follows. Sec- descriptions for them and a seamless link to generating lay- tion II describes the Graphical User Interfaces of out descriptions via MGL Parameterized Layout Synthesis HDLPlanner. Section III describes the central ideas in plan- software. MGL generates layouts that are highly optimized ning HDL designs using the planner. Section IV presents to architecture and technology. In this fashion, layout-spe- the features and benefits of using HDLPlanner. Section V cific issues can be addressed much earlier in the design discuss future work and presents the conclusion. process in a technology independent fashion, resulting in a simplified and shortened design cycle. HDLPlanner: An Environment for HDLPlanner has special code generation support with which modules can be parameterized with respect to clock Design Planning and reset pins. It is also tightly integrated with the target The HDLPlanner Graphical User Interface is described synthesis tool and knows the inner workings of each tool briefly. such as the parameterization and elaboration mechanisms. Figure 2. HDLPlanner Graphical User Interface DESIGN EDITOR: The built-in editor contains buttons for parameterized behavioral description of the module can be project creation, saving and supports basic text editing inserted into text view by pressing the Define button. The operations such as cut, copy, paste, search, find etc. These Instantiate button can be used to instantiate a component. buttons are located on the tool bar. The instantiation statement conforms to the parameteriza- MODULE DEFINITION AND INSTANTIATION PANES: tion mechanism recommended by the synthesis software Special list panes and buttons are provided to select, being used. define and instantiate modules (Refer to Figure 2). A fully 3 Figure 3. Options window for parameterizing designs for clock and reset polarities. OPTIONS: The Options user interface (UI) in Figure 3 can • Top level design: Specify the name of the top level be invoked by selecting the Tools > Options sub menu. design. It is used in the synthesis script to set the top The important options are listed below. level design name. • Clock trigger: Specify clock trigger for the component • VHDL package name: Specify the name of the package being defined/instantiated. in which all defined components will be declared. This • Clock signal: Specify global signals to be used in buffer package is saved in the specified file name. This option insertion. is specific to VHDL only. • Set or reset polarity: Specify polarity of the set or reset LAYOUT SYNTHESIS: A menu button Tools > Invoke pin for the component
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