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Raspberry Pi to Backplane Through SGMII Petter Lundström Josef Toma

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Raspberry Pi to Backplane Through SGMII Petter Lundström Josef Toma LiU-ITN-TEK-A--18/019--SE Raspberry pi to backplane through SGMII Petter Lundström Josef Toma 2018-06-01 Department of Science and Technology Institutionen för teknik och naturvetenskap Linköping University Linköpings universitet nedewS ,gnipökrroN 47 106-ES 47 ,gnipökrroN nedewS 106 47 gnipökrroN LiU-ITN-TEK-A--18/019--SE Raspberry pi to backplane through SGMII Examensarbete utfört i Elektroteknik vid Tekniska högskolan vid Linköpings universitet Petter Lundström Josef Toma Handledare Qin-Zhong Ye Examinator Amir Baranzahi Norrköping 2018-06-01 Upphovsrätt Detta dokument hålls tillgängligt på Internet – eller dess framtida ersättare – under en längre tid från publiceringsdatum under förutsättning att inga extra- ordinära omständigheter uppstår. Tillgång till dokumentet innebär tillstånd för var och en att läsa, ladda ner, skriva ut enstaka kopior för enskilt bruk och att använda det oförändrat för ickekommersiell forskning och för undervisning. Överföring av upphovsrätten vid en senare tidpunkt kan inte upphäva detta tillstånd. All annan användning av dokumentet kräver upphovsmannens medgivande. För att garantera äktheten, säkerheten och tillgängligheten finns det lösningar av teknisk och administrativ art. Upphovsmannens ideella rätt innefattar rätt att bli nämnd som upphovsman i den omfattning som god sed kräver vid användning av dokumentet på ovan beskrivna sätt samt skydd mot att dokumentet ändras eller presenteras i sådan form eller i sådant sammanhang som är kränkande för upphovsmannens litterära eller konstnärliga anseende eller egenart. För ytterligare information om Linköping University Electronic Press se förlagets hemsida http://www.ep.liu.se/ Copyright The publishers will keep this document online on the Internet - or its possible replacement - for a considerable time from the date of publication barring exceptional circumstances. The online availability of the document implies a permanent permission for anyone to read, to download, to print out single copies for your own use and to use it unchanged for any non-commercial research and educational purpose. Subsequent transfers of copyright cannot revoke this permission. All other uses of the document are conditional on the consent of the copyright owner. The publisher has taken technical and administrative measures to assure authenticity, security and accessibility. According to intellectual property law the author has the right to be mentioned when his/her work is accessed as described above and to be protected against infringement. For additional information about the Linköping University Electronic Press and its procedures for publication and for assurance of document integrity, please refer to its WWW home page: http://www.ep.liu.se/ © Petter Lundström, Josef Toma Communicating with a backplane through SGMII via a Raspberry Pi Compute Module 3 Petter Lundström and Josef Toma Examiner: Amir Baranzahi Campus Norrköping, ITN May 29, 2018 Abstract This thesis explores a method on how communication with a backplane through SGMII via a Raspberry Pi Compute Module 3 is achieved. The thesis focuses on the steps required to design a carrier board that can mount the module and incorporate a bridge between SGMII and USB. The different steps required to achieve this were to find the components, design a power solution, draw the schematics and eventually designing the PCB. ii Abbreviations AC Alternating Current MII Media-Independent CM3 Compute Module 3 Interface MOSFET Metal Oxide Semiconductor CM3L Compute Module 3 Lite Field Effect Transistor CMIO Compute Module MPSSE Multi-Protocol Input/Output board Synchronous Serial DC Direct Current Engine DDR2 Double Data Rate 2 OS Operating System DPDT Double Pole, Double Throw PC Personal Computer EEPROM Electrically Erasable PCB Printed Circuit Board Programmable Read-Only PHY Physical Layer Transceiver Memory RAM Random Access Memory eMMC embedded MultiMediaCard RGMII Reduced Gigabit Media- FIFO First In, First Out Independent Interface FPGA Field-Programmable Gate RMII Reduced Media- Array Independent Interface GB Gigabyte RX Receive GMII Gigabit Media-Independent SD Secure Digital Interface SGMII Serial Gigabit Media- GND Ground Independent Interface HDMI High-Definition Multimedia SMPS Switched Mode Power- Interface Supply Hz Hertz SODIMM Small Outline Dual In-line JTAG Joint Test Action Group Memory Module LDO Low-Dropout regulator SRAM Static Random-Access Memory LED Light Emitting Diode TX Transmitter MAC Media Access Control UART Universal Asynchronous Mb Megabit Receiver/Transmitter MB Megabyte USB Universal Serial Bus MDI Medium Dependent XGMII 10-Gigabit Media- Interface Independent Interface MDIO Management Data Input/Output iii Table of contents 1 Introduction ............................................................................................... 1 1.1 Background ...................................................................................................... 1 1.2 Purpose............................................................................................................. 1 1.3 Problem Description ......................................................................................... 2 1.3.1 Requirements and Limitations ................................................................................. 2 2 Theory ........................................................................................................ 3 2.1 Raspberry Pi ..................................................................................................... 3 2.2 Media-Independent Interface ............................................................................ 3 2.3 USB ................................................................................................................. 3 2.4 Ethernet over twisted pair ................................................................................. 4 2.5 Capacitors ........................................................................................................ 4 2.5.1 Filter Capacitor ....................................................................................................... 4 2.5.2 Decoupling capacitor .............................................................................................. 5 3 Method ....................................................................................................... 6 3.1 Block Diagram ................................................................................................. 6 3.2 Components ..................................................................................................... 7 3.2.1 Compute Module 3/3L ............................................................................................ 7 3.2.2 LAN9514 ................................................................................................................ 8 3.2.3 LAN7500 ................................................................................................................ 8 3.2.4 DP83867E .............................................................................................................. 9 3.2.5 FT4232H .............................................................................................................. 10 3.3 Additional Circuitry ........................................................................................ 11 3.3.1 FSUSB42UMX ..................................................................................................... 11 3.3.2 Switching .............................................................................................................. 11 3.3.3 Transformers......................................................................................................... 12 3.3.4 Supervisory Circuit ............................................................................................... 14 3.3.5 Attach/Detach Circuit............................................................................................ 14 3.3.6 Crystal oscillators ................................................................................................. 15 3.4 Power Supply ................................................................................................. 16 3.4.1 Switched-Mode Power Supply .............................................................................. 16 3.4.2 Low-Dropout Regulator ........................................................................................ 17 3.4.3 Calculations and Comparisons .............................................................................. 17 3.4.4 Power Sequencing ................................................................................................. 21 3.5 Schematic ....................................................................................................... 22 3.6 Layout Design ................................................................................................ 24 3.6.1 Stack-up................................................................................................................ 24 3.6.2 Design Constraints ................................................................................................ 25 3.6.3 Power Layer.......................................................................................................... 26 4 Results ...................................................................................................... 27 5 Discussion ................................................................................................ 29
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