82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR ✹ Performs Complete CSMA/CD Medium ✹ Optimized CPU Interface Access Control (MAC) Functions— — Optimized Bus Interface to Intel Independently of CPU i486TMDX, i486 TMSX, i487SX and — IEEE 802.3 (EOC) Frame Delimiting 80960CA Processors — 33 MHz, 25 MHz, 20 MHz and 16 MHz ✹ Supports Industry Standard LANs — IEEE TYPE 10BASE-T, Clock Frequencies IEEE TYPE 10BASE5 (Ethernet), — Supports Big Endian and Little IEEE TYPE 10BASE2, Endian Byte Ordering IEEE TYPE 1BASE5 (StarLAN*), ✹ 32-Bit Bus Master Interface and the Proposed Standard — 106 MB/s Bus Bandwidth 10BASE-F — Burst Bus Transfers — Proprietary CSMA/CD Networks Up — Bus Throttle Timers to 20 Mb/s — Transfers Data at 100% of Serial Bandwidth ✹ On-Chip Memory Management — Automatic Buffer Chaining — 128-Byte Receive FIFO, 64-Byte — Buffer Reclamation after Receipt of Transmit FIFO Bad Frames; Optional Save Bad ✹ Configurable Initialization Root for Data Frames Structures — 32-Bit Segmented or Linear (Flat) ✹ High-Speed, 5V, CHMOS IV Memory Addressing Formats Technology ✹ Network Management and Diagnostics ✹ 132-Pin Plastic Quad Flat Pack (PQFP) — Monitor Mode and PGA Package — 32-Bit Statistical Counters (See Packaging Spec Order No. 240800-001, ✹ 82586 Software Compatible Package Type KU and A) ✹ Self-Test Diagnostics 290218–1 Figure 1? 82596CA Block Diagram 82596CA Legal Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. 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Copyright © 2005, Intel Corporation. * Third-party brands and names are the property of their respective owners. i 82596CA 82596CA High-Performance 32-Bit Local Area Network Coprocessor CONTENTS PAGE CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 3 SYSTEM CONTROL BLOCK (SCB) ÀÀÀÀÀÀ 27 PIN DESCRIPTIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 SCB OFFSET ADDRESSES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 82596 AND HOST CPU CBL Offset (Address) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 INTERACTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11 RFA Offset (Address) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 82596 BUS INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11 SCB STATISTICAL COUNTERS ÀÀÀÀÀÀÀÀÀÀ 31 82596 MEMORY ADDRESSING ÀÀÀÀÀÀÀÀÀÀ 11 Statistical Counter Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31 82596 SYSTEM MEMORY ACTION COMMANDS AND STRUCTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13 OPERATING MODES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32 NOP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33 TRANSMIT AND RECEIVE MEMORY STRUCTURES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 Individual Address Setup ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33 Configure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34 TRANSMITTING FRAMES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17 Multicast-Setup ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 RECEIVING FRAMES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 Transmit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 82596 NETWORK MANAGEMENT AND Jamming Rules ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43 DIAGNOSTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 TDR ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44 NETWORK PLANNING AND Dump ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46 MAINTENANCE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 Diagnose ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49 STATION DIAGNOSTICS AND SELF- RECEIVE FRAME DESCRIPTOR ÀÀÀÀÀÀÀÀÀ 50 TEST ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 Simplified Memory Structure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50 82586 SOFTWARE COMPATIBILITY ÀÀÀÀÀ 21 Flexible Memory Structure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 51 INITIALIZING THE 82596 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 Receive Buffer Descriptor (RBD) ÀÀÀÀÀÀÀÀÀÀ 52 SYSTEM CONFIGURATION POINTER PGA PACKAGE THERMAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57 (SCP) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 Writing the Sysbus ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 ELECTRICAL AND TIMING CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57 INTERMEDIATE SYSTEM Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57 CONFIGURATION POINTER (ISCP) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 DC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 57 AC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 58 INITIALIZATION PROCESS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 82596CA C-Step Input/Output System CONTROLLING THE 82596CA ÀÀÀÀÀÀÀÀÀÀÀ 24 Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 58 82596 CPU ACCESS INTERFACE Transmit/Receive Clock Parameters ÀÀÀÀÀÀ 63 (PORT) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 82596CA BUS Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 66 System Interface AC Timing MEMORY ADDRESSING FORMATS ÀÀÀÀÀ 24 Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 67 LITTLE ENDIAN AND BIG ENDIAN Input Waveforms ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 68 BYTE ORDERING ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 Serial AC Timing Characteristics ÀÀÀÀÀÀÀÀÀÀÀ 70 COMMAND UNIT (CU) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 OUTLINE DIAGRAMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 72 RECEIVE UNIT (RU) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 76 2 82596CA INTRODUCTION tallies, channel activity indicators, optional capture of all frames regardless of destination address The 82596CA is an intelligent, high-performance (promiscuous mode), optional capture of errored or 32-bit Local Area Network coprocessor. The collided frames, and time domain reflectometry for 82596CA implements the CSMA/CD access method locating fault points on the network cable. The sta- and can be configured to support all existing IEEE tistical counters, in 32-bit segmented and linear 802.3 standardsÐTYPEs 10BASE-T, 10BASE5, modes, are 32-bits each and include CRC errors, 10BASE2, 1BASE5, and 10BROAD36. It can also be alignment errors, overrun errors, resource errors, used to implement the proposed standard TYPE short frames, and received collisions. The 82596CA 10BASE-F. The 82596CA performs high-level com- also features a monitor mode for network analysis. mands, command chaining, and interprocessor com- In this mode the 82596CA can capture status bytes, munications via shared memory, thus relieving the and update statistical counters, of frames monitored host CPU of many tasks associated with network on the link without transferring the contents of the control. All time-critical functions are performed in- frames to memory. This can be done concurrently dependently of the CPU, this increases network per- while transmitting and receiving frames destined for formance and efficiency. The 82596CA bus interface that station. is optimized for Intel's i486TMSX, i486TMDX, i487TMSX, 80960CA, and 80960KB processors. The 82596CA can be used in both baseband and broadband networks. It can be configured for maxi- The 82596CA implements all IEEE 802.3 Medium mum network efficiency (minimum contention over- Access Control and channel interface functions, head) with networks of any length. Its highly flexible these include framing, preamble generation and CSMA/CD unit supports address field lengths of stripping, source address generation, destination ad- zero through six bytes for IEEE 802.3/Ethernet dress checking, short-frame detection, and automat- frame delimitation. It also supports 16- or 32-bit cy- ic length-field handling. Data rates up to 20 Mb/s are clic redundancy checks. The CRC can be trans- supported. ferred directly to memory for receive operations, or dynamically inserted for transmit operations. The The 82596CA provides a powerful host system inter- CSMA/CD unit can also be configured for full duplex face. It manages memory structures automatically, operation for high throughput in point-to-point con- with command chaining and bidirectional data chain- nections. ing. An on-chip DMA controller manages four chan- nels, this allows autonomous transfer of data blocks The 82596 C-step incorporates several new features (buffers and frames) and relieves the CPU of byte not found in previous steppings. The following is a transfer overhead. Buffers containing errored or col- summary of the 82596 C-step's new features. lided frames can be automatically recovered without # The 82596 C-step fixes Errata found in the A1 CPU intervention. The 82596CA provides an up- and B steppings. grade path for existing 82586 software drivers by providing an 82586-software-compatible mode that # The 82596 C-step has improved AC timings over supports the current 82586 memory structure. The both the A and B steppings. 82586CA also has a Flexible memory structure and # The 82596 C-step has a New Enhanced Big Endi- a Simplified memory structure. The 82596CA can an Mode where in Linear Addressing Mode, true address