DOCSLIB.ORG

PCI Local Bus Specification

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
PCI Local Bus Specification PCI Local Bus Specification Revision 2.3 March 29, 2002 Revision 2.3 REVISION REVISION HISTORY DATE 1.0 Original issue 6/22/92 2.0 Incorporated connector and add-in card specification 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter 6/1/95 2.2 Incorporated ECNs and improved readability 12/18/98 2.3 Incorporated ECNs, errata, and deleted 5 volt only keyed 3/29/02 add-in cards The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein. Contact the PCI Special Interest Group office to obtain the latest revision of the specification. Questions regarding the PCI specification or membership in the PCI Special Interest Group may be forwarded to: PCI Special Interest Group 5440 SW Westgate Drive Suite 217 Portland, Oregon 97221 Phone: 800-433-5177 (Inside the U.S.) 503-291-2569 (Outside the U.S.) Fax: 503-297-1090 e-mail [email protected] http://www.pcisig.com DISCLAIMER This PCI Local Bus Specification is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. FireWire is a trademark of Apple Computer, Inc. Token Ring and VGA are trademarks and PS/2, IBM, Micro Channel, OS/2, and PC AT are registered trademarks of IBM Corporation. Windows, MS-DOS, and Microsoft are registered trademarks of Microsoft Corporation. Tristate is a registered trademark of National Semiconductor. NuBus is a trademark of Texas Instruments. Ethernet is a registered trademark of Xerox Corporation. All other product names are trademarks, registered trademarks, or service marks of their respective owners. Copyright © 1992, 1993, 1995, 1998, 2002 PCI Special Interest Group ii Revision 2.3 Contents Preface Specification Supersedes Earlier Documents .................................................................. xiii Incorporation of Engineering Change Notices (ECNs) ................................................... xiii Document Conventions.................................................................................................... xiv Chapter 1 Introduction 1.1. Specification Contents ................................................................................................1 1.2. Motivation...................................................................................................................1 1.3. PCI Local Bus Applications .......................................................................................2 1.4. PCI Local Bus Overview ............................................................................................3 1.5. PCI Local Bus Features and Benefits .........................................................................4 1.6. Administration ............................................................................................................6 Chapter 2 Signal Definition 2.1. Signal Type Definition................................................................................................8 2.2. Pin Functional Groups ................................................................................................8 2.2.1. System Pins...................................................................................................................... 8 2.2.2. Address and Data Pins ..................................................................................................... 9 2.2.3. Interface Control Pins .................................................................................................... 10 2.2.4. Arbitration Pins (Bus Masters Only) ............................................................................. 11 2.2.5. Error Reporting Pins ...................................................................................................... 12 2.2.6. Interrupt Pins (Optional) ................................................................................................ 13 2.2.7. Additional Signals.......................................................................................................... 15 2.2.8. 64-Bit Bus Extension Pins (Optional)............................................................................ 17 2.2.9. JTAG/Boundary Scan Pins (Optional)........................................................................... 18 2.2.10. System Management Bus Interface Pins (Optional) ................................................... 19 2.3. Sideband Signals.......................................................................................................19 2.4. Central Resource Functions ......................................................................................19 iii Revision 2.3 Chapter 3 Bus Operation 3.1. Bus Commands .........................................................................................................21 3.1.1. Command Definition...................................................................................................... 21 3.1.2. Command Usage Rules.................................................................................................. 23 3.2. PCI Protocol Fundamentals ......................................................................................26 3.2.1. Basic Transfer Control ................................................................................................... 26 3.2.2. Addressing ..................................................................................................................... 27 3.2.2.1. I/O Space Decoding ................................................................................................ 28 3.2.2.2. Memory Space Decoding........................................................................................ 28 3.2.2.3. Configuration Space Decoding ............................................................................... 30 3.2.3. Byte Lane and Byte Enable Usage................................................................................. 38 3.2.4. Bus Driving and Turnaround ......................................................................................... 39 3.2.5. Transaction Ordering and Posting.................................................................................. 40 3.2.5.1. Transaction Ordering and Posting for Simple Devices........................................... 41 3.2.5.2. Transaction Ordering and Posting for Bridges........................................................ 42 3.2.6. Combining, Merging, and Collapsing............................................................................ 44 3.3. Bus Transactions.......................................................................................................46 3.3.1. Read Transaction............................................................................................................ 47 3.3.2. Write Transaction........................................................................................................... 48 3.3.3. Transaction Termination ................................................................................................49 3.3.3.1. Master Initiated Termination .................................................................................. 49 3.3.3.2. Target Initiated Termination ................................................................................... 51 3.3.3.3. Delayed Transactions.............................................................................................. 61 3.4. Arbitration.................................................................................................................68 3.4.1. Arbitration Signaling Protocol ....................................................................................... 70 3.4.2. Fast Back-to-Back Transactions .................................................................................... 72 3.4.3. Arbitration Parking ........................................................................................................ 74 3.5. Latency......................................................................................................................75 3.5.1. Target Latency ............................................................................................................... 75 3.5.1.1. Target Initial Latency.............................................................................................. 75 3.5.1.2. Target Subsequent Latency..................................................................................... 77 3.5.2. Master Data Latency ...................................................................................................... 78 3.5.3. Memory Write Maximum Completion Time Limit ....................................................... 78 3.5.4. Arbitration Latency........................................................................................................ 79 3.5.4.1. Bandwidth and Latency Considerations.................................................................. 80 3.5.4.2. Determining Arbitration Latency...........................................................................
Load more

Recommended publications
  • Allgemeines Abkürzungsverzeichnis
    Allgemeines Abkürzungsverzeichnis L.
    [Show full text]
  • Dell EMC Poweredge T340 Technical Guide
    Dell EMC PowerEdge T340 Technical Guide Regulatory Model: E60S Regulatory Type: E60S001 Dec. 2020 Rev. A07 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2018 - 2020 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 1 Product Overview Topics: • Introduction • New technologies Introduction The Dell EMC PowerEdge T340 is the reliable, easy to manage, and scalable 1-socket tower server for growing businesses and remote offices/ branch offices. New technologies The PowerEdge T340 equipped with Intel® Xeon® E-2100 and E-2200 product family processors support to help run applications faster and support for full-feature remote management (iDRAC9). The T340 is versatile enough to address many customer segments and workloads. Target workloads include ● Small and medium businesses and organizations: Collaboration/sharing productivity applications, databases, web serving, backup/recovery, and mail and messaging. ● ROBO: Applications and workloads specific to the particular industry, e.g. Retail, Healthcare, Finance, Education, etc. The following table shows the list of new technologies offered by the PowerEdge T340: New Technologies Detailed Descriptions Intel® C246 series chipset Please refer to the chipset section for details. Intel® Xeon® processor E- 2100 and E-2200 Product The Intel® processor that works with Intel® C246 series Family chipset.
    [Show full text]
  • 3. System Management Bus
    Input/Output Systems and Peripheral Devices 1 3. SYSTEM MANAGEMENT BUS This laboratory work presents the System Management Bus (SMBus). After an over- view of SMBus, bit and data transfers are described, the bus arbitration procedure is present- ed, the differences between SMBus and the I2C bus are highlighted, and several command protocols are detailed. Next, the Intel SMBus controller is presented, including its registers and commands, as well as its use with I2C devices. The applications aim to detect the devices connected to the computer’s SMBus, read the contents of SPD memories present in the sys- tem, and decode the contents of these memories. 3.1. Overview of SMBus System Management Bus (SMBus) is a simple serial bus with only two signal lines. This bus can be used for communication between various system devices and between these devices and the rest of a system. The operating principles of SMBus are similar to those of the I2C bus. There are, however, several differences between the two buses, differences which will be presented later. SMBus represents a control bus for system management and power management op- erations. A system may use the SMBus to transfer messages to and from various devices in- stead of using individual control lines, which allows to reduce pin count and interconnection wires. A device may use the SMBus to provide manufacturer information, provide the device model number, report different types of errors, accept control parameters, and return the de- vice status. SMBus was initially proposed by Intel as a link between an intelligent battery, a charger for the battery and a microcontroller that communicates with the rest of the system.
    [Show full text]
  • EPC612D8A-TB EPC612D8A EPC612D8 User Manual
    EPC612D8A-TB EPC612D8A EPC612D8 User Manual Version 1.1 Published August 2016 Copyright©2016 ASRock Rack INC. All rights reserved. Version 1.1 Published October 2016 Copyright©2016 ASRock Rack Inc. All rights reserved. Copyright Notice: No part of this documentation may be reproduced, transcribed, transmitted, or translated in any language, in any form or by any means, except duplication of documentation by the purchaser for backup purpose, without written consent of ASRock Rack Inc. Products and corporate names appearing in this documentation may or may not be registered trademarks or copyrights of their respective companies, and are used only for identification or explanation and to the owners’ benefit, without intent to infringe. Disclaimer: Specifications and information contained in this documentation are furnished for informational use only and subject to change without notice, and should not be constructed as a commitment by ASRock Rack. ASRock Rack assumes no responsibility for any errors or omissions that may appear in this documentation. With respect to the contents of this documentation, ASRock Rack does not provide warranty of any kind, either expressed or implied, including but not limited to the implied warranties or conditions of merchantability or fitness for a particular purpose. In no event shall ASRock Rack, its directors, officers, employees, or agents be liable for any indirect, special, incidental, or consequential damages (including damages for loss of profits, loss of business, loss of data, interruption of business and the like), even if ASRock Rack has been advised of the possibility of such damages arising from any defect or error in the documentation or product.
    [Show full text]
  • SBIR Program Document
    Topic Index and Description A20-101 Continuous Flow Recrystallization of Energetic Nitramines A20-102 Deep Neural Network Learning Based Tools for Embedded Systems Under Side Channel Attacks A20-103 Beyond Li-Ion Batteries in Electric Vehicles (EV) A20-104 Wireless Power transfer A20-105 Direct Wall Shear Stress Measurement for Rotor Blades A20-106 Electronically-Tunable, Low Loss Microwave Thin-film Ferroelectric Phase-Shifter A20-107 Automated Imagery Annotation and Segmentation for Military Tactical Objects A20-108 Multi-Solution Precision Location Determination System to be Operational in a Global Positioning System (GPS) Denied Environment for Static, Dynamic and Autonomous Systems under Test A20-109 Environmentally Adaptive Free-Space Optical Communication A20-110 Localized High Bandwidth Wireless Secure Mesh Network A20-111 Non-Destructive Evaluation of Bonded Interface of Cold Spray Additive Repair A20-112 Compact, High Performance Engines for Air Launched Effects UAS A20-113 Optical Based Health Usage and Monitoring System (HUMS) A20-114 3-D Microfabrication for In-Plane Optical MEMS Inertial Sensors A20-115 Using Artificial Intelligence to Optimize Missile Sustainment Trade-offs A20-116 Distributed Beamforming for Non-Developmental Waveforms A20-117 Lens Antennas for Resilient Satellite Communications (SATCOM) on Ground Tactical Vehicles A20-118 Novel, Low SWaP-C Unattended Ground Sensors for Relevant SA in A2AD Environments A20-119 Efficient Near Field Charge Transfer Mediated Infrared Detectors A20-120 Very Small Pixel Uncooled
    [Show full text]
  • Dell EMC Poweredge C4140 Technical Guide
    Dell EMC PowerEdge C4140 Technical Guide Regulatory Model: E53S Series Regulatory Type: E53S001 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2017 - 2019 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 2019 - 09 Rev. A00 Contents 1 System overview ......................................................................................................................... 5 Introduction............................................................................................................................................................................ 5 New technologies.................................................................................................................................................................. 5 2 System features...........................................................................................................................7 Specifications......................................................................................................................................................................... 7 Product comparison.............................................................................................................................................................
    [Show full text]
  • Kontron Design Guide ®
    ® Kontron Design Guide ® ETX® Document Revision 2.4 This page intentionally left blank Table of Contents Table of Contents 1 User Information ........................................................................................................ 6 1.1 Objective ......................................................................................................... 6 1.2 Target Audience ................................................................................................ 6 1.3 Assumptions .................................................................................................... 6 1.4 Scope.............................................................................................................. 6 1.5 About This Document ......................................................................................... 6 1.6 Copyright Notice ............................................................................................... 7 1.7 Trademarks ...................................................................................................... 7 1.8 Standards ........................................................................................................ 7 1.9 Warranty ......................................................................................................... 7 1.10 Technical Support .............................................................................................. 8 2 Introduction .............................................................................................................
    [Show full text]
  • System Management Bus (Smbus) Specification Version 2.0
    System Management Bus (SMBus) Specification Version 2.0 System Management Bus (SMBus) Specification Version 2.0 August 3, 2000 SBS Implementers Forum Copyright 1994, 1995, 1998, 2000 Duracell, Inc., Energizer Power Systems, Inc., Fujitsu, Ltd., Intel Corporation, Linear Technology Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc., Toshiba Battery Co. Ltd., Unitrode Corporation, USAR Systems, Inc. All rights reserved. SBS Implementers Forum 1 System Management Bus (SMBus) Specification Version 2.0 THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. IN NO EVENT WILL ANY SPECIFICATION CO-OWNER BE LIABLE TO ANY OTHER PARTY FOR ANY LOSS OF PROFITS, LOSS OF USE, INCIDENTAL, CONSEQUENTIAL, INDIRECT OR SPECIAL DAMAGES ARISING OUT OF THIS SPECIFICATION, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. FURTHER, NO WARRANTY OR REPRESENTATION IS MADE OR IMPLIED RELATIVE TO FREEDOM FROM INFRINGEMENT OF ANY THIRD PARTY PATENTS WHEN PRACTICING THE SPECIFICATION. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owner’s benefit, without intent to infringe. Revision No. Date Notes 1.0 2/15/95 General Release 1.1 12/11/98 Version 1.1 Release 2.0 8/3/00 Version 2.0 Release Questions and comments regarding this For additional information on Smart specification may be forwarded to: Battery System Specifications, visit the [email protected] SBS Implementer’s Forum (SBS-IF) at: www.sbs-forum.org SBS Implementers Forum 2 System Management Bus (SMBus) Specification Version 2.0 Table of Contents 1.
    [Show full text]
  • Hello, and Welcome to This Presentation of the STM32 I²C Interface
    Hello, and welcome to this presentation of the STM32 I²C interface. It covers the main features of this communication interface, which is widely used to connect devices such as microcontrollers, sensors, and serial interface memories. 1 The I²C interface is compliant with the NXP I2C-bus specification and user manual, Revision 3; the SMBus System Management Bus Specification, Revision 2; and the PMBus Power System Management Protocol Specification, Revision 1.1. This peripheral provides an easy-to-use interface, with very simple software programming, and full timing flexibility. Additionally, the I²C peripheral is functional in low-power stop modes. 2 The I²C peripheral supports multi-master and slave modes. The I²C IO pins must be configured in open-drain mode. The logic high level is driven by an external pull-up. The I²C alternate functions are available on IO pins supplied by VDD, which can be from 1.71 to 3.6 volts, and on IO pins supplied by VDDIO2, which can be from 1.08 to 3.6 volts. This allows communication with external chips at voltages different from the STM32L4 main power supply. A typical use case is communication with an application processor in sensor hub applications. The IO pins support the 20 mA output drive required for Fast mode Plus. The peripheral controls all I²C bus-specific sequencing, protocol, arbitration and timing values. 7- and 10-bit addressing modes are supported, and multiple 7-bit addresses can be supported in the same 3 application. The peripheral supports slave clock stretching and clock stretching from slave can be disabled by software.
    [Show full text]
  • System Management Bus(Smbus)Specification
    System Management Bus (SMBus) Specification Version 3.1 19 Mar 2018 www.powerSIG.org © 2018 System Management Interface Forum, Inc. – All Rights Reserved Filename: SMBus 3_1_20180319.docx Last Saved: 19 March 2018 09:31 System Management Bus (SMBus) Specification Version 3.1 This specification is provided “as is” with no warranties whatsoever, whether express, implied or statutory, including but not limited to any warranty of merchantability, non-infringement or fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. In no event will any specification co-owner be liable to any other party for any loss of profits, loss of use, incidental, consequential, indirect or special damages arising out of this specification, whether or not such party had advance notice of the possibility of such damages. Further, no warranty or representation is made or implied relative to freedom from infringement of any third party patents when practicing the specification. Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owner’s benefit, without intent to infringe. Revision No. Date Notes Editor 1.0 15 Feb 1995 General Release Robert Dunstan 1.1 11 Dec 1998 Version 1.1 Release Robert Dunstan 2.0 3 Aug 2000 Version 2.0 Release Robert Dunstan 3.0 20 Dec 2014 Version 3.0 Release Robert V. White Embedded Power Labs 3.1 19 Mar 2018 Version 3.1 Release Robert V. White Embedded Power Labs Questions and comments regarding this For additional information on Smart Battery System specification may be forwarded to: Specifications, visit the SBS Implementer’s Forum [email protected] (SBS-IF) at: www.sbs-forum.org © 2018 System Management Interface Forum, Inc.
    [Show full text]
  • A4000/A3000 Hardware
    A4000/A3000 H ardware D eveloper N otes P art I: T he Z orro III Bus S pecification P art II: T he A miga Local B us Slot P art III: T he A miga V ideo S lot Document Revision 1.11 December 1992 by Dave Haynie with Scott Schaeffer, Scott Hood and Dan Baker Copyright © 1990,1991,1992 Commodore-Amiga, Inc. Important Information "A life spent maJäng mistakes is not onty more honorable but more usefuljhan a life spent doing nothing." -George Bernard Shaw This Pocument Contains Preliminarv Information The Information contained here is preliminary in nature and subject to possible errors and omissions. Few Zorro ID cards have yet been designed, so some features described here have not actually been tested in a System, or in some cases, actuaUy implemented as of this wridng. That, of course, is one major reason for having a specification in the first place. Commodore Technology reserves the right to correct any mistake, error, omission (or viscious lie). Corrections will be published as Updates to this document, which will be released as necessary. Revisions will be tracked via the revison number that appears on the front cover. New revisions will always list the conections up front, and developers will be kept up to date on released revisions via the normal CATS channels. All Information herein is Copyright © 1990,1991,1992 by Commodore-Amiga, Inc., and may not be reproduced in any form without permission. A cknowledgements "Art is I; Science is we." -Claude Bernard I’d like to acknowledge the following people and groups, without whom this new stuff would have been impossible: • The original Amiga designers, for designing the first microcomputer bus with support for multiple masters, Software board configuration, and room to grow.
    [Show full text]
  • PCI Local Bus Specification
    PCI Local Bus Specification Revision 2.2 December 18, 1998 Revision 2.2 REVISION REVISION HISTORY DATE 1.0 Original issue 6/22/92 2.0 Incorporated connector and expansion board specification 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter 6/1/95 2.2 Incorporated ECNs and improved readability 12/18/98 7KH3&,6SHFLDO,QWHUHVW*URXSGLVFODLPVDOOZDUUDQWLHVDQGOLDELOLW\IRUWKHXVHRIWKLVGRFXPHQW DQGWKHLQIRUPDWLRQFRQWDLQHGKHUHLQDQGDVVXPHVQRUHVSRQVLELOLW\IRUDQ\HUURUVWKDWPD\DSSHDU LQ WKLV GRFXPHQW QRU GRHV WKH 3&, 6SHFLDO ,QWHUHVW *URXS PDNH D FRPPLWPHQW WR XSGDWH WKH LQIRUPDWLRQFRQWDLQHGKHUHLQ &RQWDFWWKH3&,6SHFLDO,QWHUHVW*URXSRIILFHWRREWDLQWKHODWHVWUHYLVLRQRIWKHVSHFLILFDWLRQ 4XHVWLRQVUHJDUGLQJWKH3&,VSHFLILFDWLRQRUPHPEHUVKLSLQWKH3&,6SHFLDO,QWHUHVW*URXSPD\EH IRUZDUGHGWR 3&,6SHFLDO,QWHUHVW*URXS 1(.DWKU\Q +LOOVERUR2UHJRQ 3KRQH ,QVLGHWKH86 2XWVLGHWKH86 )D[ HPDLO SFLVLJ#SFLVLJFRP http://www.pcisig.com ',6&/$,0(5 7KLV3&,/RFDO%XV6SHFLILFDWLRQLVSURYLGHGDVLVZLWKQRZDUUDQWLHVZKDWVRHYHU LQFOXGLQJDQ\ZDUUDQW\RIPHUFKDQWDELOLW\QRQLQIULQJHPHQWILWQHVVIRUDQ\SDUWLFXODU SXUSRVHRUDQ\ZDUUDQW\RWKHUZLVHDULVLQJRXWRIDQ\SURSRVDOVSHFLILFDWLRQRUVDPSOH 7KH3&,6,*GLVFODLPVDOOOLDELOLW\IRULQIULQJHPHQWRISURSULHWDU\ULJKWVUHODWLQJWRXVH RILQIRUPDWLRQLQWKLVVSHFLILFDWLRQ1ROLFHQVHH[SUHVVRULPSOLHGE\HVWRSSHORU RWKHUZLVHWRDQ\LQWHOOHFWXDOSURSHUW\ULJKWVLVJUDQWHGKHUHLQ $/3+$LVDUHJLVWHUHGWUDGHPDUNRI'LJLWDO(TXLSPHQW&RUSRUDWLRQ )LUH:LUHLVDWUDGHPDUNRI$SSOH&RPSXWHU,QF 7RNHQ5LQJDQG9*$DUHWUDGHPDUNVDQG36,%00LFUR&KDQQHO26DQG3&$7DUHUHJLVWHUHG WUDGHPDUNVRI,%0&RUSRUDWLRQ :LQGRZV06'26DQG0LFURVRIWDUHUHJLVWHUHGWUDGHPDUNVRI0LFURVRIW&RUSRUDWLRQ
    [Show full text]