Low Power Gbit/Sec Low Voltage Differential Signaling I/O System
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Low Power Gbit/sec Low Voltage Differential Signaling I/O System Eddie Ng and Kenneth Oo [email protected], [email protected] Electrical Engineering and Computer Science University of California, Berkeley Abstract Therefore we call attention to the study of I/O interface with a low voltage The effects that I/O circuits have on the differential signaling (LVDS) I/O overall system performance are circuitry which allows clock frequency becoming more and more pronounced operate up to GHz range, despite lossy nowadays, as many digital processors transmission line and unintentional reached GHz frequency range while I/O improper transmission line termination. operates only up to MHz range. Extensive studies have been done on I/O In the Analysis and Results section, high signal processing and multi-clocking performance LVDS I/O system is first schemes to increase number of bits per considered, then followed by LVDS Hz of transmission. In this paper, a power analysis and finally additional circuit level approach to this problem is operations of LVDS system are presented, in particular a low voltage introduced. differential signaling (LVDS) interface circuitry is investigated. Simulations I/O Architectures have shown 3.0Gbit/sec transmission rate is achieved in a 0.18µm technology The most straightforward conventional while transmitter and receiver dissipate I/O driver is a chain of inverters driver less than 20mW and 25mW power and receiver configuration (Figure 1) respectively. which is simple, has wide noise margins, and does not dissipate static power. Introduction In today’s digital system, clock frequency of digital processor has Figure 1. Conventional I/O Inverters Chain reached multi-GHz range and up, while frequency of I/O circuits only operates However this approach cannot achieve up to MHz range due to circuits and the highest performance and lowest transmission line limitations. As a result, possible power because interconnection overall global performance is must be driven between Vdd (power) and significantly limited by I/O circuits Vss (ground). Besides, the receiving rather than circuits at the core level and inverter does not respond until its input silicon process technology. [1] As reaches the switching point which is CMOS technology continues to take approximately Vdd /2. In addition, ESD enormous progress, this issue will be (Electro Static Discharge) protection more noticeable in the near future. presents parasitic, making the signal differential signal into full rail-to-rail delay suffer more severely. digital output data. In addition, single-ended signaling would also result in uncontrolled high- speed return currents flowing in supply and/or ground plane in the system. Therefore, the conventional approach is quite unsuitable for high-speed low- power applications Figure 2. Typical LVDS link. [6] Differential Methods LVDS Operations The large voltage swing on the signal line is one of the speed and power limitation factors. For power Transmitter enchantment, a lower voltage swing level can be considered, but the noise The simplified version of the fully margin gets deteriorated immediately. differential LVDS transmitter is illustrated as switches in Figure 3. The To compensate the possible performance transmitter essentially acts as a current degradation, differential signaling steering switch that can source and sink methods have been exploited. current simultaneously to and from the Differential signals are immune to pair of interconnects. Four MOS common-mode noise and any issues of switches are constructed in a bridge shifting DC levels are furthermore configuration and each cross-opposite cancelled out when differential signals pair is connected to the full rail-to-rail are used. However, differential signal digital input signal and its amplitudes must be high enough to complementary signal respectively. secure noise margin since signal amplitude decreases with transmission distance. LVDS Link A typical LVDS link is shown in Figure 2. It consists of three main components as in many other I/O systems: (a) a source/transmitter to drive the signal differentially to propagate across the interconnects, (b) two transmission lines for the differential signal propagation, and c) a differential receiver that senses Figure 3. Simplified switching model of the the difference in the signals between the LVDS fully differential transmitter [17] two transmission lines and converts the Receiver Other Simulation Considerations The receiver is implemented as a high There are many other simulation gain differential pair amplifier, followed considerations taken with the most by buffers. The 100-Ω resistor shunting noticeable one is the fact that we have the two transmission lines at the input of simulated well-grounded substrates on the receiver acts as both the termination both receiver and transmitter ends. In a and load resistance, converting current typical communication system different sourced by transmitter into a small ground levels at both end could lead to differential voltage. The receiver then inferior overall performance. Due to the senses this small differential signal differential natural of LVDS, common voltage and amplified it into a rail-to-rail mode noise rejection is extremely high digital signal to the core circuit. so noise coupling in transmission is not accounted for. Input voltage offset in Transmitter Line Model receiver is not taken into consideration; however trimming can be done easily to minimize this non-ideality. Transmission line model used in simulations is the RGLC model as To appreciate the speed improvement, featured in fig. 4. In our simulation SPICE simulation is performed on both setup, wire length of 1cm, propagation I/O circuits (figs.1 and 2) driving a speed of 15cm/ns (SiO ), capacitance per 2 properly terminated transmission line, unit length 200pF/m and inductance per with characteristics impedance, Z of unit length 500nH/m are used. This o Ω setup gives characteristic line impedence 50 . Improved variations of the SA receiver are designed, compared and of about 50Ω. studied as well The LVDS voltage levels used in all simulations are specified by IEEE [12] Figure 4. Transmission line model [13] Analysis and Results However resistance plays an important High Speed Design role [13] in I/O performance, thus a lossy transmission line is used to The key to high performance LVDS simulate I2R and skin effect (–3dB at design is to realize a fast switching 1GHz) losses. network of the driver and a high gain, fast respond receiver sense amplifier. At this point we should emphasize the fact that even though simulations are To achieve the first criteria, transistors done for on chip silicon inter-module must be sized carefully to handle the communication, all results apply to PCB reference current Iref fig. 5 which flows and long distance AWG twisted pair through the transmission line. In addition communication since a “pessimistic” to that, driver transistors must handle the loss in link is accounted for a 1cm wire. reflection waves and current Ireflection if not line is not properly terminated. Parasitics effect and area set the upper However to account for velocity- size limit of transistors while lower limit saturated devices which suffer from is set by the line capacitance driven, transconductance gain degradation, a breakdown issue and the on resistance smaller overdrive Vdssat should be Rds(on) of transistors. Common mode chosen in order to minimize linear voltage must also be defined through the region, allowing fast conversion from use of feedback such that receiver small differential input voltage to rail-to- transistors are biased correctly. rail digital logic. With this in mind, a 100mV overdrive voltage is chosen for the receiver in our design and any further decrease will lead transistors to operate in weak inversion which gives inferior and less optimal performance. Logical effort/fanout-of-4 inverter sizing technique is used at the output of differential sense receiver to further restore level signal. Figure 5. Transmitter Schematics (common feedback circuit not shown in figure) At the receiver end, to ensure fast signal propagation, a high gain sense amplifier Digital Output is considered. Sense amplifier utilizes differential pair input network, biased with I . It can be shown that when tail := − Vid 2()VGS Vt (1) 200mV differential all of the tail current, Itail, flows to one side of the differential pair, allowing swing maximum current for slewing and thus minimum delay for given power dissipation. Figure 6. Simulations of LVDS I/O system, With this in mind, for an ideal long output rail-to-rail signal (top) and input channel device differential signal (bottom) Simulation shows differential line Vds = (VGS-Vt) (2) sat voltage of 200mV and receiver output is chosen for a given differential voltage gives rail-to-rail digital signal while at the receiver end Vid which equals to frequency of GHz range is easily Iref x R . From equations (1) and (2), T achievable. and based on ideal square law behave, Vd of 140mV should be used Vid of sat Additional results are generated in 200mV. SPICE simulation where the termination Delay vs Termination Resistance 1000 900 Buffer I/O Delay LVDS 800 700 600 500 400 Tdelay (ps) 300 200 Single-ended Characteristics impedence = 50ohm 100 0 Figure 8. Static and dynamic power 10 50 150 consumptions in a conventional buffer chain Termination Resistance (ohm) I/O and LVDS interface. Figure 7. Traditional I/O buffer chain and Furthermore, the dynamic power LVDS delays as a function of RT consumption scales with the supply ∝ 2 resistance is varied. The plot in fig. 7 voltage ( VDD ) for conventional single shows the result of the delays as ended I/O buffer chains because the termination resistance value derivates signal is driven rail-to-rail. (fig. 9) from the line characteristic impedence. Dynamic power in differential signaling As supposed to I/O buffer chains of fig. scheme in LVDS is independent of 1, LVDS system shows very little supply voltage as long as it can steer a variations as RT varies unintentionally constant current in and out of the possibly by means of ESD damage or impedance load.