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Solving Electromagnetic Coupling Problems by Spatial Component Placement

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Solving Electromagnetic Coupling Problems by Spatial Component Placement Guillaume Girard LCR Electronics Inc. 1 Solving Electromagnetic Coupling Problems by Spatial Component Placement. Guillaume Girard EMC Engineer LCR Electronics Inc. 9 Forest Avenue Norristown, PA, 19401 United States Telephone: (610) 278-0840 Fax: (610) 278-0935 E-Mail: [email protected] Web Address: www.lcr-inc.com Guillaume Girard LCR Electronics Inc. 2 ABSTRACT Many CAD software and design processes include Layout and More and more demand is being placed component placement rules to help on The Appliance Industry to meet achieve signal integrity and EMC. Global Electromagnetic Compatibility performance standards. The The Design review process is divided sophistication of these appliances with into 3 phases, which are considered the use of electronic controls and crucial in the development of an switching power supplies increases the electronic circuit. challenge of solving EMC problems. The most effective way of solving EMC They are; problems is to intervene at the interference sources, i.e. to tackle · Schematic review, them at the component placement level. · Component Placement review Several EMC phenomena take place in · Layout review. electronic circuits, which can be minimized by using simple placement Costly, Electromagnetic problems can rules. be avoided by using guidelines outlined in this article. In this article, guidance is given on component placement considerations SCHEMATIC REVIEW that affect the performance of shielding and filtering. These are in the form of Clock proximity rules that govern spacing between noisy integrated circuit devices Select the slowest clock rate and and ventilation screens, internal the slowest technology that the circuit connectors and filter devices. Special function allows. This will also minimize attention is given to Filter component the cost. If high clock speeds are placements (spatial orientation) to essential, give preference to clock minimize magnetic coupling. higher clock rate internal to the IC, which is locked to a lower external clock rate. It is preferable that the higher clock rate remains internal to the IC to INTRODUCTION contain most of the emission power. Clock frequencies should be selected to The sophistication of today’s minimize or eliminate harmonic overlap. home appliances with the use of By keeping harmonics > 120 kHz apart, electronic controls and switching power overlap “aliasing” should be eliminated. supplies increases the challenge of Slew resistors may be used on clocks to solving EMC problems. It is a known suppress rise times, which in turn will fact that the most effective way of lower higher frequency clock solving EMC problems is to intervene at harmonics.[1][2][3][7] the sources, on the printed circuit board (PCB). In order to prevent ringing, overshoot and undershoot, clock and signal traces Guillaume Girard LCR Electronics Inc. 3 should be properly terminate. The Attenuation curve in Figure 1 Unpopulated traces should be present results of decoupling capacitor terminated to ground to allow a return between a ground plane and a power path for surface current.[1][3][7] plane. Signal Lines All input and output power and signal lines that connect to system cables should be filtered with: common mode chokes, differential mode inductors, or capacitors. [1][3][7] There must be, at the very least, an LC filter at the power feed in order to aid in reducing conducted emissions. These filters should be placed as near as possible to the power entry. Power Figure 1. Ground plane radiation supplies or power converters will with/without decoupling capacitors. [5] probably require common-mode and differential-mode filtering. They are Bypass capacitors divert differential noisy devices, which can cause both mode currents from signal cables, thus conducted and radiated problems. allowing only the desired data to be present. They do this by removing the Capacitors alternating currents usually caused by ripple voltage. [9][1] Capacitors are used for various functions within a PCB, including Bulk capacitors keep the unit minimizing ground bounce, shunting RF functioning by insuring that sufficient energy, and removing common-mode [1][3][7] voltage is present for all circuits under and differential-mode RF currents. maximum power consumption usage. They also help prevent ground bounce Capacitors are used in one of three from occurring. [1][3][9] configurations: Surface mount decoupling capacitors · decoupling, provide the best attenuation. However, · bypassing, trace lengths between the components · bulk. and the power connections should be kept to a minimum. Decoupling Decoupling is provided at the capacitors need to have low loss and component level to prevent ground- high resonant frequencies in order to be noise voltage and high frequency efficient. Multiple decoupling capacitors voltage spikes from being injected into can lead to self-resonance. To prevent the power and ground plane structure. self-resonance, each capacitor should [1][3][7] be different by at least two orders of magnitude. Guillaume Girard LCR Electronics Inc. 4 ICs and Logic Families · Low levels of emissions; · High levels of immunity to ESD All unused ports on devices and on and other disturbing phenomena; modules should be terminated. · Low input capacitance; · Output drive capability no larger Surface mount components provide the than needed for the application; best EMI characteristics. If a heat sink · Low levels of power supply is used it should be isolated from the transient currents (sometimes ICs by thermal conductor and should be called "shoot-through currents"). RF bonded at multiple points to the ground plane. If no ground points are Connectors and Interconnect available it may be better in some instances, to leave the heat sink Use partitioning in the connector [1][3] floating. section. Separating reset lines from clock lines and noisy signals from quiet Figure 2 below show a simulation of a signals can significantly suppress noise heat sink emission patterns. The EMI emissions. Lower speed signals should from this can be suppress with good be placed on connector pins that have grounding. longer paths. Ground pins should surround all single ended 50 Mbps or higher frequency signals. Place at least one ground pin beside each noisy signal and ground pin should be placed next to sensitive lines like reset lines. Use more than one connector pin for power input and return, if necessary, to suppress the voltage drop across the Figure 2. Floating Heat sink radiation contacts. Any electrical connections with pattern. [5] external cabling must be properly filtered on the PCB. The purpose of the Integrated circuits should be chosen for filter is to remove any unnecessary high its advanced signal integrity and EMC frequency components from the features: transmitted signal, which could potentially cause severe, radiated and IC should feature: conducted emissions on the cable. Any cable exiting a shielded enclosure is a · Adjacent power and ground pins; potential EMI radiator. · Multiple power and ground pins; · Suppressed output voltage GUIDELINES FOR COMPONENT swing; PLACEMENT · Controlled slew rates; General · Transmission-line matching signals; A critical signal floor plan should · Differential signalling; be developed. Clock and high-speed · Low ground bounce; Guillaume Girard LCR Electronics Inc. 5 data signals should be identified. Trace All components, except those that carrying signals from the source to the interface with the outside world, should destination should be as short as not be placed in areas where they will possible. Components must be place to be susceptible to ESD discharges. minimize track length of critical signals. Components such as high-speed integrated circuits produce relatively Storage capacitors should be placed as strong magnetic and electric fields in close to the location where demand is their immediate vicinity at the the greatest. [1][3] frequencies ranging from the fundamental to frequencies over 1 GHz. Filtering for electrical connections with external cabling should be placed at the Shielding effectiveness of a ventilation point of entry on the PCB. If common screen or aperture varies with proximity mode chokes are employed, ground of a magnetic field source such as an planes should not be present IC. As a general rule, a 25 mm. or underneath the chokes. This is to help greater spacing between IC’s and reduce magnetic coupling. Decoupling ventilation screens and other apertures can be improved by placing Coil and should be maintained. transformer horizontally instead of vertically in some circuit layout. [1] Keep threat traces and the devices that produce them away from the edges of Clock generation components should be the PCB to minimize coupling to objects located near the signal section or centre near the PCB and to maintain a low of the PCB rather than along the return impedance. This should also help perimeter of the board. Using different with ESD discharges. Position all threat areas for low, medium, and high-speed traces and the devices that generate logic can help suppress aliasing and them away from signal devices and cross talk. [3] connectors. Table 1 and Figure 3 gives some proximity rules for IC placement. Component Proximity Effects [6][3] High-speed devices shall be located a minimum of 25 mm. from all connectors, to suppress direct coupling between the device and the connector pins. High frequency components, such as clocks or ICs, should not be placed close to any openings or interfaces where they may radiate easily through
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