Guillaume Girard LCR Electronics Inc. 1

Solving Electromagnetic Coupling Problems by Spatial Component Placement.

Guillaume Girard EMC Engineer LCR Electronics Inc. 9 Forest Avenue Norristown, PA, 19401 United States

Telephone: (610) 278-0840 Fax: (610) 278-0935 E-Mail: [email protected] Web Address: www.lcr-inc.com

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ABSTRACT Many CAD software and design processes include Layout and More and more demand is being placed component placement rules to help on The Appliance Industry to meet achieve signal integrity and EMC. Global Electromagnetic Compatibility performance standards. The The Design review process is divided sophistication of these appliances with into 3 phases, which are considered the use of electronic controls and crucial in the development of an switching power supplies increases the electronic circuit. challenge of solving EMC problems. The most effective way of solving EMC They are; problems is to intervene at the interference sources, i.e. to tackle · Schematic review, them at the component placement level. · Component Placement review Several EMC phenomena take place in · Layout review. electronic circuits, which can be minimized by using simple placement Costly, Electromagnetic problems can rules. be avoided by using guidelines outlined in this article. In this article, guidance is given on component placement considerations SCHEMATIC REVIEW that affect the performance of shielding and filtering. These are in the form of Clock proximity rules that govern spacing between noisy integrated circuit devices Select the slowest clock rate and and ventilation screens, internal the slowest technology that the circuit connectors and filter devices. Special function allows. This will also minimize attention is given to Filter component the cost. If high clock speeds are placements (spatial orientation) to essential, give preference to clock minimize magnetic coupling. higher clock rate internal to the IC, which is locked to a lower external clock rate. It is preferable that the higher clock rate remains internal to the IC to INTRODUCTION contain most of the emission power. Clock frequencies should be selected to The sophistication of today’s minimize or eliminate harmonic overlap. home appliances with the use of By keeping harmonics > 120 kHz apart, electronic controls and switching power overlap “aliasing” should be eliminated. supplies increases the challenge of Slew resistors may be used on clocks to solving EMC problems. It is a known suppress rise times, which in turn will fact that the most effective way of lower higher frequency clock solving EMC problems is to intervene at harmonics.[1][2][3][7] the sources, on the printed circuit board (PCB). In order to prevent ringing, overshoot and undershoot, clock and signal traces Guillaume Girard LCR Electronics Inc. 3 should be properly terminate. The Attenuation curve in Figure 1 Unpopulated traces should be present results of decoupling capacitor terminated to ground to allow a return between a ground plane and a power path for surface current.[1][3][7] plane.

Signal Lines

All input and output power and signal lines that connect to system cables should be filtered with: common mode chokes, differential mode inductors, or capacitors. [1][3][7]

There must be, at the very least, an LC filter at the power feed in order to aid in reducing conducted emissions. These filters should be placed as near as possible to the power entry. Power Figure 1. Ground plane radiation supplies or power converters will with/without decoupling capacitors. [5] probably require common-mode and differential-mode filtering. They are Bypass capacitors divert differential noisy devices, which can cause both mode currents from signal cables, thus conducted and radiated problems. allowing only the desired data to be present. They do this by removing the Capacitors alternating currents usually caused by ripple voltage. [9][1] Capacitors are used for various functions within a PCB, including Bulk capacitors keep the unit minimizing ground bounce, shunting RF functioning by insuring that sufficient energy, and removing common-mode [1][3][7] voltage is present for all circuits under and differential-mode RF currents. maximum power consumption usage. They also help prevent ground bounce Capacitors are used in one of three from occurring. [1][3][9] configurations: Surface mount decoupling capacitors · decoupling, provide the best attenuation. However, · bypassing, trace lengths between the components · bulk. and the power connections should be kept to a minimum. Decoupling Decoupling is provided at the capacitors need to have low loss and component level to prevent ground- high resonant frequencies in order to be noise voltage and high frequency efficient. Multiple decoupling capacitors voltage spikes from being injected into can lead to self-resonance. To prevent the power and ground plane structure. self-resonance, each capacitor should [1][3][7] be different by at least two orders of magnitude. Guillaume Girard LCR Electronics Inc. 4

ICs and Logic Families · Low levels of emissions; · High levels of immunity to ESD All unused ports on devices and on and other disturbing phenomena; modules should be terminated. · Low input capacitance; · Output drive capability no larger Surface mount components provide the than needed for the application; best EMI characteristics. If a heat sink · Low levels of power supply is used it should be isolated from the transient currents (sometimes ICs by thermal conductor and should be called "shoot-through currents"). RF bonded at multiple points to the ground plane. If no ground points are Connectors and Interconnect available it may be better in some instances, to leave the heat sink Use partitioning in the connector [1][3] floating. section. Separating reset lines from clock lines and noisy signals from quiet Figure 2 below show a simulation of a signals can significantly suppress noise heat sink emission patterns. The EMI emissions. Lower speed signals should from this can be suppress with good be placed on connector pins that have grounding. longer paths. Ground pins should surround all single ended 50 Mbps or higher frequency signals. Place at least one ground pin beside each noisy signal and ground pin should be placed next to sensitive lines like reset lines.

Use more than one connector pin for power input and return, if necessary, to suppress the voltage drop across the Figure 2. Floating Heat sink radiation contacts. Any electrical connections with pattern. [5] external cabling must be properly filtered on the PCB. The purpose of the Integrated circuits should be chosen for filter is to remove any unnecessary high its advanced signal integrity and EMC frequency components from the features: transmitted signal, which could potentially cause severe, radiated and IC should feature: conducted emissions on the cable. Any cable exiting a shielded enclosure is a · Adjacent power and ground pins; potential EMI radiator. · Multiple power and ground pins; · Suppressed output voltage GUIDELINES FOR COMPONENT swing; PLACEMENT · Controlled slew rates; General · Transmission-line matching

signals; A critical signal floor plan should · Differential signalling; be developed. Clock and high-speed · Low ground bounce; Guillaume Girard LCR Electronics Inc. 5 data signals should be identified. Trace All components, except those that carrying signals from the source to the interface with the outside world, should destination should be as short as not be placed in areas where they will possible. Components must be place to be susceptible to ESD discharges. minimize track length of critical signals. Components such as high-speed integrated circuits produce relatively Storage capacitors should be placed as strong magnetic and electric fields in close to the location where demand is their immediate vicinity at the the greatest. [1][3] frequencies ranging from the fundamental to frequencies over 1 GHz. Filtering for electrical connections with external cabling should be placed at the Shielding effectiveness of a ventilation point of entry on the PCB. If common screen or aperture varies with proximity mode chokes are employed, ground of a magnetic field source such as an planes should not be present IC. As a general rule, a 25 mm. or underneath the chokes. This is to help greater spacing between IC’s and reduce magnetic coupling. Decoupling ventilation screens and other apertures can be improved by placing Coil and should be maintained. transformer horizontally instead of vertically in some circuit layout. [1] Keep threat traces and the devices that produce them away from the edges of Clock generation components should be the PCB to minimize coupling to objects located near the signal section or centre near the PCB and to maintain a low of the PCB rather than along the return impedance. This should also help perimeter of the board. Using different with ESD discharges. Position all threat areas for low, medium, and high-speed traces and the devices that generate logic can help suppress aliasing and them away from signal devices and cross talk. [3] connectors. Table 1 and Figure 3 gives some proximity rules for IC placement. Component Proximity Effects [6][3]

High-speed devices shall be located a minimum of 25 mm. from all connectors, to suppress direct coupling between the device and the connector pins. High frequency components, such as clocks or ICs, should not be placed close to any openings or interfaces where they may radiate easily through nearby holes. High frequency components, as well, should generally be placed at least 25 mm from power converters and power filters. This should prevent high frequency noise from escaping onto ground or power traces.

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Table 1. Proximity Rules to Minimize Printed Circuit Board EMI Coupling. [3]

Description Figure Proximity Comments 3 IC Close to A >25 mm To suppress Vent Panel IC coupling through vent IC Close to B >15 mm To suppress PCB Edge PCB Edge currents PCB Edge to C >5 mm To suppress Vent Panel edge coupling to vent IC Close to D >35 mm To suppress signal noise load on Connector signal filters IC Close to E >25 mm For signal PCB Edge circuits Connectors IC Close to F >35 mm Important if Figure 3. Proximity Rules to Minimize [3] POWER POWER Coupling on Printed Circuit Board SUPPLIES SUPPLIES OR POWER OR POWER CONVERTER CONVERTER EMI Filter filter unshielded IC Close to G >25 mm Depends on Aperture aperture size Surface Clock H >25 mm To suppress Trace to Vent coupling through vent Surface Clock I >15 mm To suppress Trace to PCB PCB edge Edge currents Surface Clock J >35 mm To suppress Trace to noise load on signal signal filters Connector Guillaume Girard LCR Electronics Inc. 7

To optimize component placement, Clocks, Periodic and High Speed numerical simulation software can be Signals used. Such tools can be used to visualize field effect in an enclosure. Clock and periodic signal traces This can help the designer to avoid hot should always be manually routed first. spots. Figure 4 below show the EM field distribution over a populated circuit Route all clock lines with 25 - 50 mil board. separation from other signals. It is important to keep clock traces far from the edges of the board to eliminate EM jumping and coupling. When a jump is made from a horizontal to a vertical routing layer, the RF return current cannot make this jump due to the discontinuity occurring at the trace route from the via. The RF return current must find an alternate low impedance path to ground. A suitable alternate path usually does not exist when jumping a trace between layers.

Figure 4. E-Field Distribution on a To minimize creation of EMI and cross populated PCB. [5] talk, due to layer jumping, the following design techniques have been found to Guidelines for PCB Layout be effective: [1][3][7][9]

Multi-Layer boards - Route all clock and high- threat signal traces on only Selection of layer stack up is always one routing layer. This very dependent on the detailed means that both “x” and application. The following rules should “y” axis routes are on the be applied to multi-layer boards; same plane. - Verify that a solid 0V · Use embedded capacitance or reference, or ground buried capacitance technology if plane, is adjacent to the available. routing layer with no · Use adjacent power and 0V planes discontinuities in the route, to maximize capacitance and e.g., plane cuts or moats. suppress emissions. - If a via must be used for · Use a thin dielectric between routing a sensitive, high- adjacent power and 0V planes to threat, or clock signal trace improve their decoupling between horizontal and performance. vertical routing layers, incorporate corresponding ground vias at each and

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every via location where Power and Ground the axis jump occurs. Planes must not be floating or isolated on a Circuit board. For high- Inductance in a trace can cause both speed boards, use embedded signal integrity concerns (time domain) capacitance technology which and potential RF emissions (frequency sandwiches power and ground planes in domain). If a periodic signal, or clock very close proximity. If embedded trace, must traverse from one routing capacitance technology is not available, plane to another, this transition should place power and ground planes occur only at the component lead adjacent to each other in the stack up to ground reference. The reason for maximize capacitive coupling and making the transition adjacent to a suppress power supply noise. For high- component lead is to allow RF return speed boards, use extra ground planes current to easily make a layer transition and connect them with vias to allow jump. Try for a maximum of two vias return ground paths to follow signals as per route, one at the source, and one at closely as possible. Ground plane the load, if a strip line configuration is should be kept away from common provided. [1][3][7][9] mode chokes.

Rules to Minimize Cross talk: Differential Signals

Threat traces can couple capacitive All differential pairs must travel as or inductively to nearby traces. A close as possible to each other in order certain minimum spacing is required to reduce the loop area, and thus the between traces to keep cross talk to a emissions. All single-ended signals minimum. Here are some general rules should be routed as directly as possible of thumb:[7][9][10] in such a way that their total length is kept to a minimum. If differential noise is - Separate parallel traces by problematic and differential coils are 0.05 mm. for every inch of used, these coils should be parallel to common trace length. each other with a minimum distance - Separate threat traces between the two windings. Coils should from others by a spacing also be kept far from Transformer or equal to 3 times the power inductors to eliminate magnetic centre-to-centre distance coupling. [1][3][5][7] between the trace and its return. Reset & Interrupt Signals - Ensure physical spacing between traces. For clock Reset and interrupt lines should traces the trace edge-to- have more than 50-mil space from other edge separation distance, noisy signal tracks. Damping resistors S, shall be a minimum of 3 may be required for long reset/interrupt times the trace height, H, tracks to suppress any line effect. [7][3] hence S/H > 3. For data traces, S/H > 1. -

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[7] Howard W. Johnson and Martin CONCLUSION Graham, “High-speed digital design”, PTR Prentice Hall, 1993. There are numerous rules to follow for a good PCB review. These rules can help [8] MIL-HDBK-241B, 1983: Design increase the integrity of the product. Guide for Electromagnetic However only the EMC test can confirm Interference (EMI) Reduction in the compliance. By applying the above Power Supplies rules most EMC problem should be eliminated or reduced. [9] Henry W. Ott,”Noise reduction techniques in electronic The Appliance industry tends to use systems”, John Wiley & Sons, single layer boards due to cost. 1988 However, with the increase use of microprocessors, the Appliance industry may find it more economical to use multi-layer boards since it can reduce costly shielding and filtering.

[1] Isidor Straus, entitled “18 Rules to Follow for Better Digital EMC Design,” Conformity magazine, Vol. 3, No. 1, January 1998, ISSN 1094-2459.

[2] Patrick Mannion, “Minimize The Effects Of EMI And Let Your Design Do Its Job”, ELECTRONIC DESIGN - April 19 1999 Volume.

[3] Mark I. Montrose, “EMC and the Printed Circuit Board: Design, Theory, and Layout Made Simple”, Series Affiliation : IEEE Press Series on Electronics Technology. ISBN 0-7803-4703- X.

[5] http://www.flomerics.com

[6] Warren Boxleitner, Electrostatic discharge and electronic equipment, IEEE Press, 1989