Substrate Crosstalk Suppression Using Wafer-Level Packaging: Metalized Through-Substrate Trench Approach

Saoer Maniur SINAGA

Substrate Crosstalk Suppression Using Wafer-Level Packaging Technique: Metalized Through-Substrate Trench Approach

PROEFSCHRIFT

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magniﬁcus Prof. ir. K. Ch. A. M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op woensdag 6 oktober 2010 om 10.00 uur door

Saoer Maniur SINAGA

Master of Science in Communication Engineering, Universit¨atKassel, geboren te Medan, Indonesi¨e. Dit proefschrift is goedgekeurd door de promotor:

Prof. dr. J. N. Burghartz

Samenstelling promotiecommissie:

Rector Magniﬁcus, voorzitter Prof. dr. J. N. Burghartz, Technische Universiteit Delft, promotor Dr. M. Bartek, Technische Universiteit Delft, co-promotor Prof. dr. P. M. Sarro, Technische Universiteit Delft Prof. dr. P. J. French, Technische Universiteit Delft Prof. dr. E. Charbon, Technische Universiteit Delft Prof. dr. ir. M. K. Smit, Technische Universiteit Eindhoven Dr. S. Wane, NXP Semiconductors Prof. dr. K. A. A. Makinwa, Technische Universiteit Delft, reservelid

All rights reserved. No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without the prior permission of the author.

ISBN 978-90-8570-600-7

Author email: [email protected] Surely goodness and mercy shall follow me all the days of my life; and I will dwell in the house of the Lord forever (Psalm 23:6).

To my parents

Summary

The demand for miniaturization technology has been increasing over the last decades. Consumer electronics end-users often, if not always, go for more functionality and practicality. This is translated into systems that are more complex and yet smaller in size such as smart cellular phones and portable audio/video systems. System on Chip (SoC) is still a solution preferred by many. The SoC comprises of many different circuit blocks that fall into two categories namely analog/RF and digital. The integration of the analog/RF circuitry and digital circuitry on the same silicon substrate has yet another challenge to cope with. The noise generated from the switching activity of the digital circuitry is injected into the silicon substrate, which then can propagate to the sensitive analog/RF circuitry. Such substrate noise can significantly degrade the functionality of the analog/RF circuitry, thus deteriorating the performance of the entire electronic system. In this thesis, a method to isolate the noise generating circuit block from the noise sensitive circuit block is proposed and demonstrated. The proposed method is based on through-substrate trench isolation scheme to suppress the substrate noise. The idea behind this isolation scheme is to create a full through-substrate trench that physically separates the noise agressor from the victim. This idea is very simple and effective. The through-substrate trench is achieved by means of wafer-level packaging (WLP) technology and consists of only a few additional fabrication steps that can readily be incorporated in the WLP processing flow. In a few words, it can be described as follows: the silicon substrate is first bonded to a spacer substrate, e.g. AF-45 glass or High-Resistivity Polycrystalline Silicon (HRPS). Then, the bonded wafer stack is turned upside down before being thinned down. The next step is to create the through-substrate trench by means of KOH etching. At this stage, we now have an air-filled through- substrate trench. This isolation scheme can be further improved by metalizing

i ii SUMMARY the trench resulting in a backside metal plane. The backside metal can then be connected to ground to drain the substrate noise. This is called grounded- metalized through-substrate trench. In this work, we have successfully fabricated and measured several devices, i.e. control device (without isolation), air-filled trench device, and metalized trench device. At 50 MHz air-filed trench provides around 55 dB isolation with respect to control device, whereas the metalized-trench provides additional isolation of 7 dB. At 10 GHz air-filled trench provides around 10 dB isolation with respect to control device, whereas the metalized-trench provides additional isolation of 23 dB. At 40 GHz air-filled trench provides around 2 dB isolation with respect to control device, whereas the metalized-trench provides additional isolation of 20 dB. Samenvatting

De vraag naar miniaturisatie technologie is over de laatste decaden continu blijven groeien. Gebruikers van consumenten elektronica gaan vaak, bijna altijd, voor hogere functionaliteit en praktisch gebruik. Dit vertaalt zich in complexere systemen die toch steeds weer kleiner van afmetingen zijn, zoals intelligente mobieltjes, and draagbare audio/video systemen. System on Chip (SoC) is de voorkeurstech- nologie van de Chip fabrikanten om deze miniaturisatie te realiseren. De System on Chip bestaat uit vele verschillende bouwstenen van meer of minder complexe schakelingen die in twee categorien kunnen worden onderverdeeld: analoge/rf en digitale schakelingen. De integratie van analoge/rf schakelingen en digitale schakelingen op het zelfde silicium substraat is een speciale uitdaging. De stoorsignalen, die worden gegenereerd door de schakelactiviteiten in de digitale schakelingen, komen in het silicium substraat terecht en kunnen via deze weg doorgegeven worden aan de gevoelige analoge/rf schakelingen. Deze substraatstoring kan op een signiﬁcante wijze de functionaliteit van de analoge/rf circuits negatief benvloe- den, waardoor de prestaties, op elektronisch systeemniveau, onbevredigend kunnen zijn. In deze thesis wordt een methode om demping aan te brengen tussen de storende schakeling en de storingsgevoelige schakeling, voorgesteld en het de werking aangetoond. De voorgestelde methode om de substraatstoring te reduceren, is gebaseerd op een het toevoegen van isolatie op basis van een kanaal dat over de volledige dikte van het silicium substraat wordt gemaakt through-substrate trench isolation in het vervolg in deze samenvatting kanaal genoemd. Het concept achter deze isolatie aanpak is om een volledig kanaal te maken, die een fysieke barrire opwerpt tussen de bron en het mogelijk gestoorde schakeling. Deze aanpak is erg een- voudig en zeer eﬀectief. Het kanaal wordt gemaakt met Wafer Level Packaging technologie en bestaat uit slechts een paar extra productie stappen, die direct in

iii iv SAMENVATTING bestaande Wafer Level Packaging productie processen kan worden toegepast. Op hoofdlijnen kan het proces als volgt worden beschreven: Het silicium substraat wordt eerst verbonden met het spacer substraat. bijvoorbeeld op basis van AF-45 glas of High-Resistivity Polycrystalline Silicon (HRPS). Vervolgens wordt de ge- realiseerde wafer stack omgedraaid en op de juiste dikte gebracht thinned down. De volgende stap is om een kanaal te maken via een ets proces op KOH basis. In deze fase hebben we een op lucht gebaseerde through-substrate trench. De isolatie kan vervolgens worden verbeterd door het metalliseren van het kanaal en zijn omgeving in het silicium substraat. Dit leidt tot een gemetalliseerde backplane. Deze gemetalliseerde backplane kan vervolgens aan de aarde verbonden worden om de substraat storing af te voeren. Dit wordt een grounded-metalized through-substrate trench genoemd. In deze studie hebben we, met succes, meerdere test devices geproduceerd en gemeten. Het zijn een controle device (zonder isolatie), een lucht gesoleerd through-substrate trench device en een grounded-metalized through-substrate trench device. De resultaten van de metingen leverden de volgende isolatie verbeteringen op. Op 50 MHz gaf lucht isolatie een extra isolatie van 55 dB ten opzichte van het controle device. De metallisering leverde een extra winst van 7 dB. Op 10 GHz gaf lucht isolatie een extra isolatie van 10 dB ten opzichte van een controle device. De metallisering leverde een extra winst van 23 dB. Op 40 GHz gaf lucht isolatie een extra isolatie van 2 dB ten opzichte van het controle device. De metallisering leverde een extra winst van 20 dB op. Acknowledgements

After many years of working and typing on the train, this adventure has finally come to an end. The journey was definitely not without ups and downs, nor could I cross the finish line without the support and help from many people. I wish to express my gratitude to my promotor Prof. Dr.-Ing. Joachim N Burghartz for his guidance and encouragement during the course of my doctoral study, particularly for the time he spent to carefully review this thesis. I am forever grateful to my co-promotor Dr. Marian Bartek for his full support during my PhD study and after. I am also indebted to Dr. Behzad Rejaei and Gabriel Macias for many valuable discussions. Special thanks go to my project partner Alexander Polyakov for his excellent work in the clean room. Without him, I would not have had the device to measure. I would also like to thank scientific members of DIMES Lab. for their help and support in the clean room. My first two years in Delft were cherished by my fellow PhD students Andrey Sachko and Harish Pillai. Italian pizza, gyros and beer colored our days in Delft. Dude, wherever you are, it was great time we had. My skill in playing pool seemed to improve a little thanks to Jason Tian, Huang Cong, Han Yan and Sebastian Sosin. I would also like to mention Marco Spirito, Koen Buisman, Edmund Neo, Huseyin Sagkol, Theodoros Zoumpoulidis and Hsien Chang Wu for the corridor and lunch discussions. I would also like to acknowledge Hok Yap of Philips Applied Technologies for his support in providing the dutch translation of the summary and propositions.

v vi ACKNOWLEDGEMENTS

I am grateful to my siblings for their support and encouragement. I am indebted to my parents for their prayers and immeasurable love. Last but not least, I am grateful to my wife, Patricia Astrid, for her loving kindness and endless support. Without her, this thesis would not have come to a completion. This work was supported by Philips (PACD B1 project) and by EC (Blue Whale project IST-2000-10036).

Delft, Saoer Maniur Sinaga September 2010 Contents

Summary i

Samenvatting iii

Acknowledgements v

1 Introduction 1 1.1 Trends in Microelectronics ...... 1

1.2 Crosstalk in Integrated Circuits ...... 2

1.3 Solutions by Wafer-Level Packaging Technology ...... 4

1.3.1 Packaging roadmap ...... 4

1.3.2 Background and history of wafer-level packaging ...... 4

1.3.3 Crosstalk suppression by wafer-level packaging ...... 6

1.4 Work Objective ...... 8

1.5 Thesis Organization ...... 8

2 Substrate Crosstalk in Integrated Circuits: Mechanisms and Suppression Techniques 11 2.1 Crosstalk Mechanisms ...... 11

vii viii CONTENTS

2.1.1 Radiative coupling ...... 12 2.1.2 Circuit coupling ...... 15 2.1.3 Substrate coupling ...... 17

2.2 Substrate Noise and Its Coupling Mechanisms ...... 18 2.2.1 Substrate noise injection ...... 18 2.2.2 Substrate noise transmission ...... 21 2.2.3 Substrate noise reception ...... 25

2.3 Impact of Substrate Noise on Circuits’ Performance: Some Examples 26

2.4 State-of-the-art Substrate Noise Suppression Techniques ...... 27

2.5 Summary ...... 30

3 Substrate Crosstalk Modeling in Wafer-Level Packaged Integrated Circuits 35 3.1 Problem Description ...... 36

3.2 Substrate Crosstalk Between Two Ohmic Contacts ...... 36 3.2.1 Substrate thickness impact on isolation ...... 36 3.2.2 Distance impact on isolation ...... 38 3.2.3 Substrate resistivity impact on isolation ...... 38 3.2.4 Interconnect parasitic impact on isolation ...... 41

3.3 Through-Substrate Trench as Substrate Noise Suppression Technique 41

3.4 Synthesis of Equivalent Circuit Model ...... 45

3.5 Summary ...... 49

4 High-Frequency Substrate Characterization 51 4.1 Substrate Parameters ...... 52 4.1.1 Dielectric permittivity ...... 52 4.1.2 Substrate loss ...... 53

4.2 Coplanar Waveguide (CPW) ...... 54

4.3 Test Structures Design and Measurement Results ...... 57 4.3.1 Design of ﬁnite-ground CPWs ...... 57 CONTENTS ix

4.3.2 CPW utilization for substrate characterization ...... 59 4.3.3 Measurement and results ...... 60

4.4 Summary ...... 60

5 Metalized Through-Substrate Trench Approach 67 5.1 Design Objective and Considerations ...... 67

5.2 Test Structures Design and Simulations ...... 70 5.2.1 Control device ...... 71 5.2.2 Backside-plane isolation ...... 74 5.2.3 Air-ﬁlled through-substrate trench isolation ...... 74 5.2.4 Metalized through-substrate trench isolation ...... 74

5.3 Fabrication Flow ...... 79

5.4 Measurement Setup and Procedures ...... 83 5.4.1 Measurement setup and calibration techniques ...... 83 5.4.2 De-embedding techniques ...... 83

5.5 Experimental Veriﬁcation ...... 91

5.6 Lumped Model Development and Analysis ...... 96 5.6.1 Control device ...... 101 5.6.2 Backside-plane isolation ...... 110 5.6.3 Air-ﬁlled through-substrate trench isolation ...... 117 5.6.4 Metalized through-substrate trench isolation ...... 120

5.7 Summary ...... 127

6 Conclusions, Recommendations and Future Works 129 6.1 Conclusions ...... 129

6.2 Recommendations and Future Works ...... 132

A Boundary Conditions in HFSS 133 A.1 Symmetry Boundaries ...... 133 x CONTENTS

A.2 Radiation Boundaries ...... 133

A.3 Finite Conductivity Boundaries ...... 134

A.4 Perfect Electric Boundaries ...... 135

A.5 Inﬁnite Ground Planes Boundaries ...... 135

B Boundary Conditions Implementation 137 B.1 Device #1 ...... 138

B.2 Device #2 ...... 139

B.3 Device #3 ...... 140

B.4 Device #4 ...... 141

B.5 Device #5 ...... 142

B.6 Device #6 ...... 143

B.7 Device #7 ...... 144

B.8 Device #8 ...... 145

List of Publications 147

Bibliography 151

Curriculum Vitae 159 Chapter 1 Introduction

1.1 Trends in Microelectronics

In 1965, Intel co-founder Gordon Moore predicted the future of microelectronics. His prediction, now known as Moore’s law, states that the number of transistors on a chip doubles about every two years. Processing power, measured in millions of

transistors 10.000.000.000 Dual-Core Intel* Itanium* 2 Processor 1.000.000.000 MOORE´S LAW Intel* Itanium* 2 Processor Intel* Itanium* Processor Intel* Pentium* 4 Processor 100.000.000 Intel* Pentium* III Processor Intel* Pentium* II Processor 10.000.000 Intel* Pentium* Processor Intel486 TM Processor 1.000.000 Intel386 TM Processor 286 100.000 8086 8080 10.000 8008 4004 1.000 1970 1975 1980 1985 1990 1995 2000 2005 2010

Figure 1.1: Evolution of Intel’s processor following the Moore’s law [Cor08]. instructions per second (MIPS), has steadily risen because of both, increased oper-

1 2 INTRODUCTION 1.2 ating frequencies and increased transistor counts. This continuous miniaturization technology characterized by an ever-increasing level of integration complexity is driven primarily by cost-constrained applications such as cellular phones, home computing, and consumer multimedia devices [Gie03]. In the past, complete system occupied one or more circuit boards. Today, they are integrated on a few chips or even on one single chip known as System-on-Chip (SoC). SoCs can be found in many applications such as single-chip cameras and new generations of integrated telecommunication systems that include digital, analog, and eventually radio-frequency (RF) blocks. As the technical demands continuously grow, modern SoC designs are, therefore, becoming more and more mixed-signal. This is even becoming more prevalent when we move towards intelligent applications such as cars interacting with their environment or smart homes where variety of home electronics and appliances are able to communicate with each other performing synchronized tasks and to adapt their behavior to their inhabitants. Unfortunately, the higher functionality and lower cost offered with the integration of both analog/RF and digital circuits onto one single die do not come without any drawback, particularly in deep-submicron CMOS technologies. The analog circuits do not only remain difficult to design, but when integrated with the digital circuits on the same chip, they require costly fabrication processes, and are very prone to noise or crosstalk signals generated by, e.g. digital circuits. The higher levels of integration with ever increasing clock frequencies make the mixed-signal chip suffer from signal integrity problem even more. This is why crosstalk is becoming a serious delimiter in Integrated Circuit (IC) design.

1.2 Crosstalk in Integrated Circuits

Crosstalk is often deﬁned as the penetration of an unwanted signal from one circuit to another. One may also describe this unwanted signal as noise. This noise can propagate by various coupling mechanisms, i.e. radiative coupling, circuit coupling, and substrate coupling. The radiative coupling usually takes place in the form of a propagating electromagnetic ﬁeld, whereas circuit coupling propagates via a conductive path, which is commonly shared, e.g. signal interconnects and power lines. The substrate coupling uses the commonly shared substrate, such as a silicon substrate, as the propagation medium. Considering any of these mechanisms, noise generated by noisy circuitry propagates to sensitive analog circuitry. Already a small amount of noise, particularly, if reaching a high-gain circuitry, can cause failure of a circuit block, hence, a total failure of the whole system-on-chip. Substrate noise, in particular, has been receiving a lot of attention from the design and technology communities. Substrate noise is generally caused by coupling of switching or noise signals to the substrate. In digital CMOS circuits this noise is caused by three mechanisms: (1) coupling from the digital power supply, (2) coupling from switching source-drain nodes, and (3) impact ionization 1.2 CROSSTALK IN INTEGRATED CIRCUITS 3

LNA_in Vcc_dig Vcc_analog dig_out dig_in LNA_out Vgnd_dig Asub_gnd Dsub_gnd Vgnd_analog

Figure 1.2: A schematic illustration of a silicon-based SoC. Substrate noise injected into the substrate by the aggressive digital circuit disturbs the sensitive analog/RF circuit [Zei03].

in the MOSFET channel [Don03]. Noise in the power supply domain is generally caused by the parasitic inductance introduced by the interconnection to and from the chip, e.g. bondwires. The parasitic inductance and fast switching time cause the potential to fluctuate according to the following formula: di V = Ri + L (1.1) drop dt where R and L are the interconnect parasitics. The voltage fluctuation gets worse when the switching becomes faster. Additionally, the resonance between power and ground will also cause ringing of the power supply voltage. These effects are also called ground bounce or simultaneous switching noise [Sam00], [Gab88], [Sen91]. The second source of the substrate noise is capacitive coupling from switching source and drain nodes of the MOSFETs. Voltage fluctuation at the source or drain can couple to the bulk silicon through the source/bulk and drain/bulk junction capacitances [Bri00]. The third source of the substrate noise is an impact- ionization current. For an NMOS transistor, the holes created by impact ionization are injected into the substrate, such that the transistor has current flowing out of its bulk node and entering the substrate [Bri99]. Figure 1.2 gives an illustration where the silicon substrate of a SoC is commonly shared by the analog/RF circuitry and the digital circuitry. Having briefly described the increasing importance of crosstalk in modern ICs, it becomes clear that a proper design strategy needs to be adopted in the IC design process to manage the crosstalk issues. Such strategy would include: (1) simulations based on accurate crosstalk models, and (2) application of crosstalk- suppression techniques. The latter can include variety of measures that are rather straightforward such as modifications in layout or circuit scheme, but also more 4 INTRODUCTION 1.3 radical requiring modifications in the fabrication process or electronic packaging scheme used.

1.3 Solutions by Wafer-Level Packaging Technology

1.3.1 Packaging roadmap

ICs tend to be very sensitive to environmental hazards, which include electrical, mechanical and thermal effects. Although an IC may be directly attached to a PCB (Printed Circuit Board) and then glob-topped with epoxy for protection, the IC is usually supplied in a package. The IC package ensures the protection to the IC die from external influences. Additionally, the package provides mechanical interfacing for testing, burn-in, and electrical interconnection to the next level of packaging [Coh05]. The package, hence, must meet all device performance requirements, such as electrical (inductance, capacitance, and crosstalk), thermal (power dissipation, junction temperature), quality, reliability, and cost objectives [Coh05]. Similar to ICs, the electronic packages have also been evolving through the years. In the early days, packages like DIL (Dual in-Line) package, QFP (Quad Flat Pack) package, PLCC (Plastic Leaded Chip Carrier) package depicted in Figure 1.3a, were able to support many applications; even today they are still widely used. However, those packages are also known to introduce 1-20 nH lead inductances, which are considerably high particularly for high-speed and high- frequency ICs. That is why such packages are no longer suitable for present days’ applications. There is, thus, demand for more complex and higher integration level SoCs, at acceptable cost levels. The wafer-level package as shown in Figure 1.3b can be considered as one of the solutions. WLP offers many advantages over the conventional packages and will be explained later in the following sections.

1.3.2 Background and history of wafer-level packaging

Wafer-Level Packaging (WLP) is a term used to describe packaging technology of an integrated circuit at wafer level, instead of traditional process assembly after wafer dicing. The history of WLP technology started with bumping technologies used for tape automated bonding (TAB) and ﬂip chip solder bumping, where IBM was the ﬁrst to use them for its mainframe system in 1964 and later Delco for automotive electronics [Bal05]. The need for more input/output pins (I/O) as a result of the demand for higher densities on chip, and also the demand for product miniaturization for handheld and portable application were the driving 1.3 SOLUTIONS BY WAFER-LEVEL PACKAGING TECHNOLOGY 5

DIL (Dual In Line) package

QFP (Quater Flat Pack) package

PLCC (Plastic Leaded Chip Carrier) package (a) Traditional packages

(b) Wafer-level package

Figure 1.3: IC package evolution: (a) traditional packages add extra dimension to die size that increases the component size; (b) wafer-level packaging technology yields component with the same size as the die. 6 INTRODUCTION 1.3 forces behind the research and development of wafer-level packaging technology. WLP has emerged as a packaging technology of high interest within the electronics manufacturing community. WLP provides a 1:1 area ratio of package to die providing chip-size packages (CSP). As mentioned earlier, WLPs are fabricated prior to the dicing step, resulting in a package footprint that is the same as that of the IC chip. This also means that the device electrical interconnects as well as device physical protection processes are also done at wafer level. Addition- ally, the WLP approach also includes wafer-level test and burn-in, which provides potentially cost savings when compared to the traditional test and burn-in for each individual package [Bal05]. On the other side, WLP also brings new challenges and potential disadvan- tages. The intrinsicly chip-size package requires fine-pitch solder bump arrays when high I/O count ICs are packaged. These fine-pitch solder arrays require high-density PCBs that tend to be higher in cost [Bal05]. Additionally, since all ICs are packaged jointly on the wafer, fault ICs are packaged together with the good ICs. Yet another potential disadvantage is that the dicing and singula- tion of the packages from the wafer can damage the package interconnect, i.e. a redistribution layer. Nevertheless, WLP is today the fastest-growing packaging technology and is widely used for components like flash memories, DRAMs, microcontrollers, integrated passive components, and linear devices [And09].

1.3.3 Crosstalk suppression by wafer-level packaging

In the recent years many different approaches towards realization of WLPs have been investigated and implemented into practice. Because majority of the package processing steps takes place at a wafer level using advanced processing equipment, a rather limited modification of the packaging process flow can allow implementation of additional, high-accuracy structures, e.g. embedded passive components, in a highly effective way. Similarly, WLP technology offers new opportunities for packaging of Micro-Electro-Mechanical Systems (MEMS). This can be seen as the main added value of WLP technology and is also utilized in this thesis for substrate crosstalk supression. Figure 1.4 depicts some examples of WLP as well as the WLP concept proposed in this thesis. The WLP concept is quite similar to the ShellOP package (developed by ShellCase). It utilizes a low-loss substrate, i.e. glass as a spacer substrate, to ensure mechanical strength of the overall package. In this concept, passive devices that often consume the largest area on the SoC die are placed onto the low-loss substrate. Having the passive devices located on the spacer substrate will reduce lateral area consumed by the SoC. Moreover, high-Q factor passive devices can be achieved when these are realized on a low-loss substrate. 1.3 SOLUTIONS BY WAFER-LEVEL PACKAGING TECHNOLOGY 7

Metal traces Solder ball

Compliant layer

Silicon die Passivation layer Contact pad (a) Tessera WLP

(b) Fraunhofer IZM WLP (c) China WLCSP ShellOP

SpacerSpacer substrate substrate IntegratedIntegrated patch patch antenna antenna LargeLarge inductor inductor

Adhesive layer layer IsolationIsolation trench trench Through-waferThrough-wafer via via Wafer-to-wafer bonding (d) Proposed WLP concept

Figure 1.4: WLP examples: (a) Tessera WLP utilizes compliant layer; (b) Fraunhofer IZM WLP wth integrate inductor and capacitor; (c) ShellOP utilizes glass-silicon-glass sandwich; (d) Proposed WLP concept utilizes through-substrate trench for crosstalk isolation. 8 INTRODUCTION 1.5

Another very important feature oﬀered by the proposed WLP concept is the possibility to form through-substrate trenches to suppress the substrate crosstalk without jeopardizing the substrate mechanical integrity. The through-substrate trench is instrumental in blocking the substrate crosstalk and drain it when low impedance path to ground is provided. This is discussed later in this thesis.

1.4 Work Objective

As mentioned in the above sections, substrate noise in a mixed-signal IC can deteriorate its performance, and can eventually lead to overall system failure. The objective of this work is an investigation of novel opportunities oﬀered by WLP technology for substrate crosstalk supression in high-frequency applications. This thesis proposes a novel, WLP-based substrate noise suppressing technique to create a grounded metalized through-substrate trench in the lossy substrate, i.e. silicon, to block the noise propagating in it. The through-substrate trench divides the silicon substrate into silicon islands, thus insulating the sensitive circuitry from the noisy circuitry. To maintain the mechanical reliability due to the through- substrate trench, a spacer substrate is employed. The WLP concept employed in this thesis not only utilizes the low-loss substrate to suppress potential noise propagation through the spacer substrate itself, but also to realize high-Q passive devices. As shown in Figure 1.4d, the passive components are integrated onto the low-loss spacer substrate above the silicon islands thus reducing the required die area. The low-loss spacer substrate is an important part of the proposed WLP concept. Therefore, this thesis also discusses high-frequency substrate characterization. Comparison between high-resistivity polycrystalline silicon (HRPS) substrate and AF-45 glass is presented. Since the grounded metalized through-substrate trench relies on draining the substrate noise to the ground, its eﬀectiveness strongly depends on the ground interconnect’s impedance. Therefore, interconnect characterization is also investigated in this thesis.

1.5 Thesis Organization

Chapter 1 (this chapter) gives a short motivation for the work presented in this thesis. It explains why substrate crosstalk is becoming a serious challenge in IC design. Furthermore, the thesis objective and outline are described.

Chapter 2 focuses on the crosstalk mechanisms. More speciﬁcally, substrate 1.5 THESIS ORGANIZATION 9 crosstalk in System-on-Chip (SoC) ICs is described. The three main sources of substrate crosstalk, i.e. injection mechanisms, transmission mechanisms, and reception mechanisms, are discussed. State-of-the-art substrate crosstalk suppression techniques are systematically described. A novel substrate-crosstalk suppression technique based on a through-substrate trench with or without metalization realized using wafer-level packaging technology is proposed.

Chapter 3 presents various substrate crosstalk modeling techniques applied to wafer-level packaged ICs. The modeling work employs 2D and 3D device simulators, as well as 3D electromagnetic simulator, i.e. Medici, Taurus, and Ansoft HFSS, respectively. In this chapter, inﬂuence of parameters, such as distance, contact sizes, substrate thickness, and substrate resistivity on crosstalk isolation level are evaluated.

Chapter 4 describes characterization of selected high-frequency substrates that are or can potentially be used in WLP technology. The characterization algorithm utilized is based on the quasi-TEM mode and zero thickness metal assumption, applied to coplanar waveguide (CPW). A CPW was chosen as the prefered structure because it supports quasi-TEM mode and is easy to fabricate. As a result, electrical properties, i.e. dielectric constant and loss tangent of HRPS and AF-45 glass are presented.

Chapter 5 presents the design, fabrication and characterization of the test structures intended to demonstrate efficiency of the WLP techniques for substrate crosstalk suppression. Test structures were designed to verify the substrate crosstalk theory and to demonstrate that sufficient level of isolation can be achieved by implementing the proposed metalized through-substrate trench method. In the fabrication section, the fabrication flow is described in detail. The measurement results are used to verify the three-dimensional EM simulation data. Furthermore, based on the measured data, lumped models were developed for each of the isolation structures tested.

Finally, in Chapter 6 the main conclusions resulting from this thesis work are reviewed and the recommendations for future work are given. Appendix A brieﬂy describes the boundary conditions available in HFSS and the underlying theory, while Appendix B shows how those boundary conditions are implemented in the simulation work.

Chapter 2 Substrate Crosstalk in Integrated Circuits: Mechanisms and Suppression Techniques

Today, a single-chip transceiver realised in CMOS technology wherein radio- frequency (RF) analog circuits are integrated with baseband digital circuit, known as System-on-Chip (SoC), can be found on the market. Nevertheless, the design of an SoC itself remains challenging. One particular challenge is to minimize the noise (unwanted signal) coupling between circuit blocks on the same chip. The noise generated by noisy circuit blocks can propagate and couple to sensitive circuit blocks through several mechanisms, i.e. radiative coupling, circuit coupling, and substrate coupling. In this chapter, these mechanisms are discussed in detail. In particular, substrate noise coupling mechanisms and state-of-the-art substrate noise suppression techniques are described. Several examples on how substrate noise aﬀects the circuit performance, as well as how the circuit performance improves by suppressing the substrate noise, are also presented.

2.1 Crosstalk Mechanisms

While radiative and circuit coupling commonly exists at both the package and chip levels, the substrate coupling occurs at chip-level only. Circuit coupling usually occurs via mutual capacitances and inductances. It generally scales inversely with the distance between the conductors and, to a lesser degree, it depends on

11 12 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.1 their geometry. Radiative coupling arises due to unbalanced conductor currents and it is carried by propagating electromagnetic (EM) waves, especially at high frequencies.

2.1.1 Radiative coupling

Radiative coupling usually takes place in the form of propagating electromagnetic ﬁelds. In contrast to the free-space propagation, EM wave propagation within IC package occurs under complex near-ﬁeld conditions, where free-space distance scaling does not apply [Woo]. By means of its transmission, radiative coupling itself is divided into three categories:

• Capacitive coupling; • Inductive coupling; • Electromagnetic coupling.

Capacitive coupling

Capacitive coupling mechanism is illustrated in Figure 2.1, where the load ZL is connected to the ampliﬁer output by a metal trace, which passes close to another trace that is connected to the input of ampliﬁer A1. The coupling capacitance between these two traces is distributed (Figure 2.1a); however, for simplicity it is represented in Figure 2.1b as a capacitor denoted Cp.

The ﬂow of current IL through ZL charges the left circuit of Cp and as a consequence, the same amount of electric charge (but of opposite sign) will be induced in the right circuit. This is equivalent to a parasitic voltage Vp appearing at the input of ampliﬁer A2, such that: dV V = C L (2.1) p p dt where Zin represents the input impedance of A2 and Rg is the resistance of the signal generator Vg. Of course, reducing Cp (by increasing the separation between traces) can help to reduce Vp, but the unexpected conclusion from Eq. 2.1 is that a low input impedance of the victim circuit increases immunity to perturbations transmitted via capacitive coupling.

If either of the grounds M1 or M2 is ﬂoating, the only diﬀerence is that the stray capacitance between the point in question and ground will be seen in series with Cp. Finally, the best solutions to reduce this type of interference are:

• Decrease the coupling capacitance Cp by increasing the separation of traces or by shielding, i.e. introduce a ground trace between coupled traces; 2.1 CROSSTALK MECHANISMS 13

A1 A2 Zin

VL Z R Vg L g ∼∼∼ M1 M2

(a) Capacitive coupling between two traces.

V V p L Zin ||R g

(b) Equivalent circuit.

Figure 2.1: Schematic representation of capacitive coupling (adapted from [Vas05]): (a) capacitive coupling between two traces or more; (b) the aggressor circuit is modeled as a voltage source, while the victim circuit is modeled as a resistive load. The aggressor and the victim is connected through capacitor, which models the capacitive coupling between traces.

• Reduce the input impedance of the victim circuit (when possible).

Inductive coupling

Inductive coupling, also called magnetic coupling, is illustrated in Figure 2.2, where the current flowing through the output loop of amplifier A1 produces a magnetic field whose lines intersect the input loop of amplifier A2.

Consequently, an induced parasitic voltage Vp appears in the input loop which can be evaluated as [Vas05]: dI V = −M L (2.2) p dt

M being the mutual inductance between the loops (which depends on both loops areas, their orientation, and their separation). In the equivalent circuit, the 14 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.1

A1 A2 Zin IL

VL Vg ZL Rg ∼∼∼ M1 M2

(a) Inductive coupling

Rg Zin ∼∼∼ Vg

(b) Equivalent circuit

Figure 2.2: Schematic representation of inductive coupling (adapted from [Vas05]): (a) magnetic ﬁeld generated by the loop areas of the two circuits couple to each other; (b) the inductive coupling is modeled by a voltage source, which is proportional to mutual inductance.

perturbing voltage Vp is in series with the signal generator Vg, hence the noise added to the useful signal. Note, that Vp is unaﬀected by whether or not M1 and M2 are ﬂoating or connected to ground. To decrease the noise induced by inductive/magnetic coupling, three solutions may be considered [Vas05]:

• Limiting the area of the victim loop by properly designing the layout; • Reducing the magnetic ﬁeld by shielding or by decreasing the output current in the aggressor circuit; • When possible, modify the loop orientations so that their planes become 2.1 CROSSTALK MECHANISMS 15

perpendicular.

Electromagnetic coupling

Traditionally, this term refers to coupling between an electromagnetic plane wave and a transmission line (recall that a plane wave has both ﬁelds perpendicular to the direction of propagation and perpendicular to each other). In the present case, the electromagnetic coupling appears between intentionally emitted waves (i.e. antenna, radar, etc.) and each trace of the circuit, which acts like a receiving antenna [Vas05].

2.1.2 Circuit coupling

The circuit coupling often also called conducted coupling happens due to interfering signals that propagate from noise source to victim via a conductive path that is commonly shared. Perhaps the most obvious way to couple noise into or out of an integrated circuit is via the package leads or pins [Dhi06]. As described further in detail, there are two common conductive paths where the circuit coupling can take place [Vas05]: AC power lines and Common ground impedance.

AC power lines

Figure 2.3a illustrates a typical situation in which two different circuitries share one common AC power supply line. In this figure, let us define circuit 2 be the source of the noise and circuit 1 the victim. The equivalent circuit of the common AC power line problem is shown in Figure 2.3b, where Zi1 and Zi2 are the impedances of the AC power line sections. Zt is the impedance seen in the sec- ondary winding of the transformer and Vp2 represents the perturbation (noise) generated by the noise source, i.e. circuit 2. By applying a simple voltage divider formula, the perturbing voltage that reaches the victim, i.e. circuit 1, is:

2Zi1 + Zt Vp1 = Vp2 (2.3) 2 (Zi1 + Zi2) + Zt

From Eq. 2.3, one can also see that Vp1 increases when Zi2 is reduced which is the case when the distance between the two circuitries decreases. However, when ∼ Zi2 ¿ Zi1 then Vp1 = Vp2 and there is no attenuation of perturbation reaching the victim [Vas05]. To ﬁx this, one might insert ﬁlters at the AC terminals of circuit 1 [Vas05], or use separate AC power supply for each circuit. 16 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.1

Zi1 Zi2

220 V 50 Hz Circuitry 1 Circuitry 2

Zi1 Zi2

(a) Common AC power line

Circuitry 2

Zi1 Zi2

Zt Circuitry 1 Vp2

Zi1 Zi2

(b) Equivalent circuit

Figure 2.3: Circuit coupling via common AC power supply (adapted from [Vas05]): (a) noise occurs in circuit 1 is also seen by circuit 2 due to common AC power line; (b) the noise generator, circuit 2, is represented by Vp2

A1 A2

L Cp1 Cp2 R

Figure 2.4: Circuit coupling via common ground impedance(adapted from [Vas05]). Ground reference of one circuit is no longer ideal due to ground bounce caused by another circuit. The ground bounce eﬀect becomes signiﬁcant as the frequency goes higher. 2.2 CROSSTALK MECHANISMS 17

Common ground impedance

One path that is commonly shared in an electronic system is the ground path. Figure 2.4 illustrates two amplifiers that share one common ground return path. Considering the short length of the interconnect to the ground, at low frequency, it acts like a short circuit. At higher frequencies, however, the impedance becomes larger, and is no longer negligible. Hence, a voltage drop between M1 and M2 appears on the series combination of L and R, which is also known as ground bounce, and is given by: di V = Ri + L (2.4) drop dt The first terms denotes the resistive voltage drop that is proportional to the switching current. The second term denotes the inductive voltage drop that is proportional to the first derivative of the switching current, and it is also known as inductive noise, delta-I noise, and L(di/dt) noise. As far as A1 is concerned, its ground potential is modulated by ground current of A2 flowing in the common ground impedance. Despite the low value of L, the second term of Eq. 2.4 becomes dominant, especially when fast switching currents are flowing. This voltage transient is picked up by A1 through the stray capacitance Cp1 and vice versa to A2. The ground bounce can also propagate into the substrate through ohmic contacts and parasitic junction capacitances. These ways of noise propagation are called substrate noise; and will be described in the next section.

2.1.3 Substrate coupling

Substrate coupling in integrated circuits (ICs) is the process whereby a parasitic current flow in the substrate electrically couples devices in different parts of the circuit, or circuits in different parts of the system due to the presence of conductive and capacitive path in the silicon substrate [Gha95]. This is illustrated in Figure 2.5. In mixed-signal ICs, the main noise generator are the digital circuits due to their fast switching events. This digital switching noise is injected directly into the substrate through ohmic contacts and/or junction capacitances and then couples to sensitive analog/RF circuits through commonly shared substrate. It has been reported in [Kia98] that the substrate acts as a feedback path where it affects the amplifier small-signal gain, bandwidth, and stability. Not only can the substrate noise degrade the performance of analog/RF circuits, but the digital circuits can be affected as well. It was reported in [Cha99] that the propagation delay of sensitive digital blocks also increases. The ever increasing complexity of the ICs and the decreasing feature size of CMOS technology, which enables devices to operate at a very high speed, makes the effects of substrate coupling becoming even more severe. 18 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.2

In G

Gnd S VDD D

Cwell Out Subs Dig. V DD Dig.Gnd Ana.Gnd Subs Subs

In G S Out D

N-Well

Digital circuitry Analog/RF circuitry P-substrate

Figure 2.5: Substrate coupling via commonly shared substrate [Ver98]). A fast switching digital circuit injects noise into the substrate. This substrate noise can travel, which is then picked up by the sensitive analog/RF circuit.

2.2 Substrate Noise and Its Coupling Mechanisms

As described earlier, noise is generally defined as unwanted signal that degrades the performance of a system. In mixed-signal ICs, the noise itself is divided into two major categories: random noise and deterministic noise. Random noise is originated from active as well as passive devices. Random noise includes thermal noise, flicker noise, and shot noise. These random noises are quantified using the noise figure (NF) and signal-to-noise ratio (SNR) parameters [AK06]. De- terministic noise includes digital switching noise, and RF circuit noise. These deterministic noises can be quantified both in frequency domain and time domain. The digital switching noise is often the dominant source of deterministic noise in mixed-signal ICs [Ver98]. The mechanisms for substrate noise injection, transmission, and reception are discussed in the following sections.

2.2.1 Substrate noise injection

A mixed-signal integrated circuit typically consists of active and passive devices. Active devices include bipolar junction transistors, MOS transistors, and diodes. Passive devices typically include resistors, inductors, capacitors, and interconnects. This section describes diﬀerent substrate noise injection mechanisms. 2.2 SUBSTRATE NOISE AND ITS COUPLING MECHANISMS 19

Resistive injection into the substrate

Impact ionization current Figure 2.6 illustrates the cross-section of PMOS and NMOS devices. When a MOS transistor is biased in the saturation regime, a high electric field develops in the depletion region of the channel near the drain. Due to this high electric field, some fraction of the carriers in this region will gain enough energy to become ”hot”. When these hot carriers scatter, they can dissipate excess energy by generating electron-hole pairs [Bri99]. This process is known as impact ionization. Thus, some of the resulting holes (for NMOS case) flow into the substrate resistively creating a substrate current [Gra01]. The contribution of impact ionization is included in the noise current models employed by SPICE [AK06]. One example of these models expresses the hot-electron-induced substrate current in semi-analytical form as [Hu81]:

Ã 1/3 1/2 ! C2tox · xj Isub = C1(Vds − Vdsat)Id exp (2.5) Vds − Vdsat

where C1 and C2 are process-related empirically determined parameters, tox is the oxide thickness, xj is the junction depth, Vds is the drain-to-source voltage, and Vdsat is the saturation voltage. The empirical coeﬃcients, C1 and C2, can be determined by means of device simulation or measurement and then be incorporated for circuit simulation. Experimental result in [Mer] suggests that hot-electron induced substrate current is the dominant cause of substrate noise in NMOSFETs up to at least 100 MHz. Hot-electron induced current in PMOS devices were also observed [Bri99]. However, in PMOS devices with locally grounded well (with comparable size of NMOS devices) the amount of the hot-electron induced current is considerably smaller due to a lower hole ionization coeﬃcient. Thus, PMOS devices cause lower substrate bounce than comparably sized NMOS devices [Gha95]. It has also been reported in [Bri00] that the relative impact ionization current in their PMOS is about an order of magnitude less than in the NMOS. This makes the contribution of PMOS to hot-electron induced current in the common substrate negligible.

Ohmic guarding In a p-type silicon substrate, p-type diffusions are often used as substrate taps or guard rings for circuit protection. The p-type diffusions are connected to a certain potential to ensure that the substrate is at a desired potential. If this is not designed properly, however, these diffusion regions can inject a very high level of noise into the substrate. Any voltage bounce on these p-type regions will be distributed throughout the substrate [Gha95]. The p-type diffusion taps on a p-type silicon substrate are illustrated in Figure 2.7. 20 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.2

S D G

p-substrate Hole injection

(a) NMOS transistor

S G D

p+ p+

n-well

p-substrate

(b) PMOS transistor

Figure 2.6: MOS transistors (adapted from [Gha95]). The noise is injected into the substrate through the junction capacitance: (a) NMOS transistor; (b) PMOS transistor.

Capacitive injection into the substrate

Another mechanism, by which parasitic currents can be injected into the substrate, is the capacitive coupling. Figure 2.8a illustrates the cross-section of a bipolar NPN transistor. A bipolar NPN transistor interacts with the substrate through the collector-to-bulk pn-junction capacitance (Cjs). This capacitance 2.2 SUBSTRATE NOISE AND ITS COUPLING MECHANISMS 21

p-diffusion (guard ring)

p-type substrate

Figure 2.7: P-type diﬀusion used as guard ring on a p-type silicon substrate [Gha95]. gives a path for the current to propagate into the substrate capacitively. The value of (Cjs) depends on the substrate and collector doping levels, as well as the bias level of the collector with respect to the substrate [Gha95]. The capacitance formula for abrupt pn junction can be expressed as: s µ ¶ qε NCNS Cjs = (2.6) 2 (ψbi + Vcs) NC + NS where NC and NS are the collector and the substrate doping levels, respectively; ψbi is the built-in potential of the junction; and Vcs is the collector-to-substrate bias voltage [Gha95]. Lateral pnp transistors injects the noise through the base- to-substrate capacitance (Figure 2.8b) [Gha95]. The capacitive injections can also be caused by MOS transistors as illustrated in Figure 2.6. Voltage ﬂuctuations on the source or drain can couple to the substrate through the source-to-substrate and drain-to-substrate junction capacitances. The gate also contributes in injecting the noise into the substrate through gate oxide and channel capacitances [Bri00].

2.2.2 Substrate noise transmission

After having discussed the mechanisms of noise injection into the substrate, it is essential to know how the noise propagates from one device to another or from one circuit to another. Therefore, it is important to understand the physics of the substrate in order to be able to model the substrate. The distributed form of Ohm’s law shown below holds for a lossy dielectric, i.e. silicon [Gha95]: J~ = (σ + jωε)E~ (2.7) 22 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.2

C(n) B(p) E(n +)

+ Cjs n -type

p-substrate

(a) NPN transistor

B(n) C(p +) E(p +)

Cbs

p-substrate

(b) Lateral PNP transistor

Figure 2.8: Bipolar transistor capacitive coupling to the substrate (adapted from [Gha95]): (a) in NPN transistor the noise is injected through the pn junction; (b) in lateral PNP transistor the noise in injected through the base-to-substrate capacitance.

where J is the current density in the substrate (A/cm2), E~ is the electric ﬁeld strength (V/cm), σ is the conductivity and ε is the dielectric permittivity of the silicon. The Ohm’s law consists of real part and imaginary part, namely conductive behavior and capacitive behavior, respectively. 2.2 SUBSTRATE NOISE AND ITS COUPLING MECHANISMS 23

Resistive effect

The conductivity σ inside a doped semiconductor depends on the carrier concentration and the mobility as given by:

σ = q(pµp + nµn) (2.8) where q is the electron charge, µp and µn represent the mobility of the n-carriers and p-carriers, and p and n stand for the respective carrier densities. The µp and µn are functions of total semiconductor doping and temperature [Dut93], [Ver95].

Capacitive effect

Imaginary part of Eq. 2.7 expresses the capacitive behavior of the silicon. Silicon has a relative dielectric constant εrSi = 11.7 which gives the absolute dielectric constant: · ¸ pF ε = ε ε = 1.035 (2.9) Si rSi 0 cm

Silicon substrate can be modeled as an RC network, which behaves conductively and capacitively as depicted in Figure 2.9. However, for homogeneous silicon substrate, the capacitive behavior starts to occurs at relatively high frequencies. The admittance Ys of the RC network shown in Figure 2.9a can be expressed in frequency domain by:

1 + sRsCs 1 + jωTs Ys = = (2.10) Rs Rs

Therefore, Eq. 2.8 and Eq. 2.9 lead to a substrate time constant, Ts given by the expression below:

ρsdl εsdA εrSi ε0 Ts = RsCs = · = (2.11) dA dl q(pµp + nµn) which is now independent of the piece dimensions. Figure 2.9b suggests that for low frequencies the substrate resistance Rs is more dominant and, therefore, the associated capacitance Cs can be neglected. As the frequency increases (ω = 2πf), the capacitive effect rises to become equal to the resistive effect at the cut-off frequency, fT, defined by [Pfo]:

1 1 q(pµp + nµn) = ωTCs = 2πfTCs ⇒ fT = = (2.12) Rs 2πTs 2πεrSi ε0

The minimum fT is achieved for a lightly-doped p-type substrate, because mobility is lower for holes than for electrons [Ce03]. 24 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.2

dA ≡ RS = CS

(a) RC model of silicon

10 ) (dB) s |R s

10log(|Y 5

+3 dB

0 6 8 10 12 10 10 10 10 Frequency (GHz) (b) Conductive and capacitive behavior of a 3.5 Ω-cm silicon

Figure 2.9: Model and behavior of a piece of homogeneous silicon: (a) silicon is modeled by an RC network; (b) at low frequencies, the silicon substrate behaves conductively, thus modeled by resistance. At high frequencies, the silicon substrate behaves capacitively, thus modeled by capacitance. 2.3 SUBSTRATE NOISE AND ITS COUPLING MECHANISMS 25

2.2.3 Substrate noise reception

The noise reception of many devices such as bipolar transistors, capacitors, resistors, and interconnect lines, is mainly by means of capacitive sensing. The junction with the substrate in lateral PNP devices is formed by n-type base region. That is why, if the PNP device is used in a gain stage, the base of the device must be carefully shielded or connected to a low impedance node. Otherwise the substrate noise will be ampliﬁed by the gain of the circuit [Gha95].

G V G V G m gs mb bs D Gmb Vbs D Vbody Zsub Vb R C d Rd gs Csb S S

Body-to-Drain Gain ~ G mb Vbs ~cG mVbs Vb

Figure 2.10: Body eﬀect in MOSFETs [Ver98].

In addition to capacitive reception, there is another noise reception mechanism in MOS devices due to the body effect. The threshold voltage of an MOS transistor is a function with strong dependency on the substrate potential, which for a uniform surface impurity concentration NA is given by [Gra01]: √ ³ ´ 2qεNA p p Vt = Vt0 + 2φf + VSB − 2φf (2.13) Cox where Vt is the threshold voltage, ε is the silicon dielectric permittivity, Cox is the oxide capacitance per unit area, 2φf is the surface inversion potential and VSB is the source-to-body potential. It is explained in [Gra01] that the body effect can be represented by a linearized model parameter gmb in the small-signal device model. By shorting the gate and the source of the MOS transistors (see Figure 2.10), a gain stage is created between the substrate S and the drain D [Gha95]. A suitable approximation in [Gra01] shows that: √ g 2qεN mb = √ A (2.14) gm 2Cox 2φf + Vsb where gm is the small-signal transconductance of the device. The parameter gm relates the drain current to the gate-to-source voltage. While capacitive reception of the noise is significant at high frequencies, the body effect can be an issue at low frequencies [Gha95]. 26 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.3

2.3 Impact of Substrate Noise on Circuits’ Performance: Some Examples

Analog/RF circuits are known to be prone to substrate noise. However, it is worth mentioning that digital circuits are not immune from substrate noise either. The noise is often generated from logic gates switching activities and glitch transients. This noise is then injected into the substrate through capacitive coupling and impact ionization. Further, this noise propagates through the substrate and is subsequently received by active devices through capacitive coupling and the body effect. This creates delay effect which can be seen in an increasing datapath, thus possibly exceeding the pre-defined clock period [Cha99]. Measured results on the effects caused by logical control pulses on the behavior of OPAMPs are reported in [Cat95]. Heavy distortion was observed at the output of an on-chip OPAMP caused by a differentiation of the interfering substrate noise. Another important effect observed was the phase shift of the analog signal. Phase-locked loops (PLLs) are essential circuit blocks in RF and mixed-signal integrated circuits. Not only are they used as on-chip clock generators to synthe- size and de-skew a higher internal frequency from the external lower frequency, but also as clock recovery systems [Raz03]. The presence of partially-correlated substrate noise poses a new challenge to predicting PLL jitter [Cha04]. Sub- strate noise mostly arises due to impulsive charge injection during gate switching [Cha04]. Much research work has been conducted and results produced on how to reduce substrate noise or how to protect sensitive circuits. However, without detailed coupling information, a designer tends to over-design the safety-measures resulting in an extensive use of guard rings that consume a lot of space. Therefore, a cyclostationary noise model that describes the substrate noise-to-jitter transfer characteristic for CMOS ring oscillator-based PLLs on epitaxial substrate was proposed in [Cha04]. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for different power supply schemes in [Lar01], where the PLLs were built in a standard low- resistivity substrate process. The first scheme is to have the digital circuit and the analog PLL to share both Vdd and Vss. The result shows that the main jitter source is the supply coupling into the VCO. The second scheme is to have separate Vdd and Vss for the digital circuit and the analog PLL. This configuration causes substrate noise to couple into the loop filter node due to the parasitic resistances in the epi layer below the MOS transistor used as a filter capacitor. The third scheme is to have a separate Vdd for the analog PLL but still shares the same Vss with the digital circuit. This configuration exhibits far less jitter than the other two configurations. The main cause of jitter in this case are delay variations in the feedback divider that mix the PLL reference frequency into a low-frequency 2.4 STATE-OF-THE-ART SUBSTRATE NOISE SUPPRESSION TECHNIQUES 27 beat note. If this beat note frequency is lower than the PLL bandwidth, the PLL tracks the beat note. This occurs only when a harmonic of the clock of the noise generating digital circuit is close to the reference clock driving the PLL. The influence of substrate noise coupling on the performance of a low-noise amplifier (LNA) for a CMOS GPS receiver was investigated analytically and ex- perimentally in [Xu01]. In this work, substrate noise caused by a single digital transition and received capacitively by a sensor is first studied. The experimental results suggest that the substrate noise is linear function of the coupling capacitance when the trise/fall is constant. With knowledge of the substrate noise caused by a single digital transition, the total substrate noise induced by a digital circuit emulator can be calculated as the sum of noise components resulting from each of the digital transitions. When the digital circuit emulator is inactive, the LNA output spectrum has a single -44 dBm tone at 1.575 GHz. However, when the digital circuit emulator is turned on, the LNA output spectrum shows -60 dBm at 1.575 GHz.

2.4 State-of-the-art Substrate Noise Suppression Techniques

It was described earlier that substrate noise can really degrade the overall system- on-chip performance. Therefore, the substrate noise generated by the noisy circuit has to be suppressed or blocked so that it does not disturb the sensitive circuit. Many substrate noise suppression techniques exist at research level as well as industrial level. In this section, state-of-the-art substrate noise suppression techniques are thoroughly discussed.

Guard ring In [Wel98], an industrial frequency multiplier PLL for clock generation is used as test circuit. A large noise generator consisting of 5 output buffers in series was placed next to the PLL. It was built in a 0.72 micron epitaxial process with approximately 1800 transistors. In this work, simplifications were made to investigate the effect of substrate noise from the noise generator onto the VCO jitter. The sensitive analog circuits are protected by both ohmic and well guard rings. Six different guarding structures were chosen to evaluate guarding techniques which include: no guard, no guard with backplane contact, p+ guard ring, p+ guard ring with a backplane contact, ohmic guarding in the VCO, and both ohmic guarding and p+ guard ring in the VCO. The p+ guard ring and ohmic guarding are both ohmic guard structures but the p+ guard ring is a single ring placed around the entire section of the analog devices while the ohmic guarding is formed by many ohmic guard bands placed as close as possible to all sensitive devices not in well regions. When no pin parasitics are considered, protection with backplane only provides the best jitter performance followed by p+ guard ring with a backplane contact, both ohmic guarding and p+ guard ring in the 28 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.4

VCO, ohmic guarding in the VCO, and lastly the p+ guard ring. However, when the pin parasitics, especially inductance, are considered, the power supply value deteriorates due to the switching current flowing through the pin. Not only did the pin parasitics increase the amount of jitter for each guarding structure, but the effectiveness of each configuration also changed. In this case, configuration that includes both ohmic guarding and p+ guard ring shows the worst jitter, even worse than without applying any protection. The reason for this is that the p+ guard ring was biased through the analog ground line. Although the bulk fluctuation remained low, the substrate current is captured by the low-ohmic guard ring and flows through the analog ground node causing ground bounce to the sensitive devices. Biasing the p+ guard ring to the digital ground node causes less analog ground bounce but increases the fluctuation on the bulk substrate since the ground bounce on the digital ground line is greater due to the switching current activities. A solution to this problem is to hook the p+ guard ring to separate power supply.

Silicon-on-Insulator (SOI) technology was used by many for substrate crosstalk suppression as described in [Ank05], [Ham00], [Kum01], [Mae01], [Ras97], [Ste04], [Hir01], and [Viv95]. In [Ank05], it has been proven that the use of very-low- resistivity (LR) silicon (6 -10 mΩ-cm) forming an LR-SOI structure can lower the crosstalk significantly for all frequencies when compared to both medium- resistivity (9 -15 Ω-cm) and high-resistivity silicon (800 -1400 Ω-cm). The fabrication scheme used field oxide isolation followed by standard RCA cleaning and growth of a thinner oxide, which represents the isolating layer in SOI. The low crosstalk for the LR-SOI is the result of effective shunting of the signal to ground through the low-resistive substrate. Draining the signal to the backside ground is also proven effective as explained in the previous example [Wel98]. An additional advantage of the low-resistivity substrate is that the crosstalk is insensitive to re- laxation capacitive effects, due to the high doping level as confirmed by Eq. 2.12. This experiment also shows that an effective substrate ground is crucial. The measurement on dedicated test structures show an improvement in the range of 20-40 dB for low resistivity SOI substrate compared to high resistivity SOI substrate.

Buried layer and deep trench isolation are used for isolation in a BiCMOS technology [Bla]. Figure 2.11a shows isolation scheme that includes buried layer, sinkers, and deep trench in a BiCMOS technology. Firstly, the channel stop region which is three orders of magnitude less resistive than the substrate will increase the isolation. Secondly, the buried layers and the sinker are roughly four orders of magnitude more conductive than the bulk substrate. The buried layers and the sinker will guide and drain out carriers when connected to a low impedance AC ground. However, buried layers may also provide a low impedance path for sub- 2.4 STATE-OF-THE-ART SUBSTRATE NOISE SUPPRESSION TECHNIQUES 29 strate noise to travel into a sensitive area. In this case, the buried layer must be broken to increase the isolation. It has been proven in [Tak] that the break in buried layer combined with the addition of a double guard ring provided a 20x improvement in the isolation.

p+ r p e p contact k (~ 0.2 ΩΩΩ- in cm) h n-well s c (~10 ΩΩΩ-cm) + n p re t p e + e + p buried layer (~ 0.005 ΩΩΩ-cm) d n

p- silicon (~12 ΩΩΩ-cm)

(a) Deep trench in addition to buried-layer and sinker isolations.

N+ N+ p epitaxial layer sinker sinker ΩΩΩ + + + + (~1 -cm) n n

n+ buried layer (~0.005 ΩΩΩ-cm)

p+ buried layer (~0.005 ΩΩΩ-cm)

p- silicon (~12 ΩΩΩ-cm)

(b) NMOS with triple-well isolation.

Figure 2.11: BiCMOS cross-section with relative resistivities [Bla]: (a) deep trench provides physical noise blockage in addition to buried layer and sinker isolations; (b) triple-well isolation.

Triple-well isolation shown in Figure 2.11b is now commonly used in most CMOS processes at 0.18 nm and below [Bla]. The triple-well provides a means to isolation of n-type devices that normally exist in the p-type substrate. Redmond in [Red] 30 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.5 presented a result of using triple-well isolation. It provided ∼20 dB better isolation when compared to p+ guard ring at 100 MHz. But no improvement at 10 GHz. Therefore, the eﬀectiveness of triple-well isolation strongly depends on the signal frequency and many other aspects such as doping levels, grounding scheme, and package parasitics.

Faraday cage is one of the most common isolation structures used at radio frequencies. Some works on faraday cage can be found in [Wu01], [Ste04], and [Cho05]. In [Wu01], the faraday cage scheme for crosstalk suppression was formed by means of through-wafer via technology. The faraday cage structure consists of a ring of grounded vias encircling sensitive or noise portions of a chip. The via technology features aspect ratio as high as 14 [Wu00], through-wafer holes ﬁlled with electroplated Cu and lined with a silicon nitride barrier layer as illustrated in Figure 2.12a. As shown in Figure 2.12b, when a 77-µm substrate and 10-µm diameter vias with an aspect ratio close to 8 were used, and the noise transmitter and the noise receiver are separated by 100 µm, the faraday cage reduced the crosstalk by 40 dB at 1 GHz and 36 dB at 5 GHz.

Porous Si trench has been used to provide radio frequency isolation in Si because of its semi-insulating property [Kim02]. Heavily doped p-type Si substrates with resistivity less than 0.01 Ω-cm. Localized porous silicon (PS) trench was formed between the noise generator and the noise sensor. Afterwards, wafer lapping by mechanical polishing was performed to remove the conductive silicon below PS trench, enabling a through-wafer PS trench (see Figure 2.13). The standard thickness of the Si chip is approximately 250 µm. Reduction of crosstalk by 70 dB at 2 GHz and 45 dB at 8 GHz was demonstrated between Al pads with 800 µm separation on p+ Si.

2.5 Summary

Crosstalk may take place through several coupling mechanisms, i.e. radiative coupling, circuit coupling, and substrate coupling. Radiative coupling itself is divided into three subcategories: capacitive coupling, which usually refers to coupling within one system due to electric field; magnetic coupling, which also usually refers to coupling within one system due to magnetic field; and electromagnetic coupling, which usually refers to coupling between different system due to electric field, magnetic field, or both.

Circuit coupling takes place through the interconnects such as power supply and ground connections which are shared by diﬀerent circuit blocks, e.g. digital 2.5 SUMMARY 31 block and analog block.

Substrate coupling occurs in integrated circuits due to the conductive and capacitive path which exists in the silicon substrate. Conductive path of silicon substrate is predominant at low frequencies, while the capacitive path becomes signiﬁcant at high frequencies. Noise is injected into the substrate through resistive injection (e.g. impact ionization current and ohmic guarding) and capacitive injection (e.g. junction capacitance). Substrate noise reception mainly takes place through capacitive sensing (i.e. junction capacitances). Substrate noise, usually generated by noisy circuit block (i.e. digital block), received by sensitive analog/RF blocks can severely degrade its performance, thus the performance of the overall system. There are quite a few substrate crosstalk suppression techniques that have been widely implemented on industrial level. Guard ring is one of the most common techniques used, where p+ silicon substrate ring provides low impedance return path for the substrate noise towards the ground. Similarly, buried layer and triple-well isolation are used in BiCMOS and CMOS processes, respectively. Instead of using low resistivity substrate, Faraday cage uses through-substrate metal-ﬁlled vias to capture substrate noise. Faraday cage is known to provide isolation up to several GHz. Porous silicon trench has also been used to provide radio frequency isolation. 32 SUBSTRATE CROSSTALK IN INTEGRATED CIRCUITS: MECHANISMS AND SUPPRESSION TECHNIQUES 2.5

Si substrate

Silicon nitride Ta-Ti-Cu seed

Electroplated Cu

(a) High aspect-ratio through-substrate via ﬁlled with Cu and lined with an Al pad.

Test structure with Faraday Cage Reference

Receivers

Transmitters

Faraday Cage

(b) Top-view of the Faraday cage test structure.

Figure 2.12: Conceptual view of the Faraday cage scheme for substrate crosstalk suppression by means of high-aspect ratio through-wafer via technology [Wu00], [Wu01]: (a) cross-sectional view depicts the high aspect-ratio through-substrate via; (b) top view depicts Faraday cage that surrounds the noise transmitter. 2.5 SUMMARY 33

(a) Without porous silicon trench.

Porous Si

(b) With porous silicon trench.

Figure 2.13: Porous silicon trench isolation structure with one agressor and one victim [Kim02]: (a) test structures without porous silicon trench; (b) test structure with porous silicon trench that isolates the substrate noise to pass through conductively.

Chapter 3 Substrate Crosstalk Modeling in Wafer-Level Packaged Integrated Circuits

In general, it is possible to model the detailed transport and coupling processes in the substrate. However, even with state-of-the-art device simulation tools, a single simulation may take hours. Therefore, it is desirable to derive a compact model representation of all the critical interactions between circuit elements that are caused by the coupling through the silicon substrate. One of the most common approaches is to build a simple equivalent circuit or analytical model, whose parameters are determined by means of curve-fitting to either measured or simulated high-frequency substrate conduction behavior. Experiments are usually performed with many simplifications, i.e. using only a simplified geometries and considering only a small number of substrate contacts, typically two or three. These contacts usually represent the agressor, victim, and ground nodes. Several experiments can be repeated for different geometries and the results are empirically fitted to a model consisting of a small number of components. The approach mentioned above is also employed in this chapter to model substrate crosstalk. The impact of geometrical variations, i.e. substrate thickness, distance between the nodes, substrate resistivity, and interconnect parasitics, on the isolation is investigated. The same approach is also used to demonstrate the effectiveness of our proposed substrate crosstalk suppression techniques.

35 36 SUBSTRATE CROSSTALK MODELING IN WAFER-LEVEL PACKAGED INTEGRATED CIRCUITS 3.2

3.1 Problem Description

One of the features offered by the proposed WLP concept is the possibility to form a through-substrate trench to suppress substrate crosstalk as depicted in Figure 3.1a. In order to better understand the substrate crosstalk mechanisms, a simplified two-port model was built. Figure 3.1b depicts the model used in the 2D device simulator MEDICI. The upper side of the model consists of glass (²r=6.2), and silicon (²r=11.9) forms the lower side of it. The thickness of the glass substrate is set at 450 µm, while the thickness of the silicon substrate varies (as discussed later). For computational simplification, boundary conditions as depicted in Figure 3.1b were applied. The edges on the left, right, and top are modeled with Neumann boundary conditions so that current only flows out of the device through the contacts. The boundary condition defined on the bottom edge is based on the case study described in the following sub-section. The contacts as shown in Figure 3.1b are modeled with Dirichlet boundary condition, which guarantees equipotential along the surface. The bulk silicon substrate has doping 15 −3 concentration Na = 3 × 10 cm , while the contacts are formed with 100 µm + 20 −3 wide p silicon with the doping concentration Na = 10 cm .

3.2 Substrate Crosstalk Between Two Ohmic Contacts

In this section impact of various aspects on the isolation are thoroughly discussed. For simplicity reasons in the processing as well as the understanding, ohmic contact structures were chosen for this investigation. Figure 3.1b shows the silicon-glass sandwich structure as the model used in MEDICI. The model consists of four ohmic contacts, where two contacts are signal ports and the other two are perfectly grounded. The two ports act as the agressor (noise generator) and the victim (noise receptor). This arrangement will give us a two-port model which is easy to understand. Furthermore, the position of the ground contacts is the same for all simulations (Figure 3.1b), while the positions of the noise generator and receptor ports is variable. This conﬁguration will allow us to investigate the impact of various parameters, i.e. the physical distance between the nodes, substrate thickness and resistivity, etc., on the crosstalk isolation.

3.2.1 Substrate thickness impact on isolation

The grounding scheme is a very important factor in achieving suﬃcient isolation. Draining the substrate noise to ground is one way to reduce the substrate crosstalk, while trying to reduce the substrate noise injected into the substrate is the other. The ground node itself can be put either on the frontside of the silicon die or on the backside. Figures 3.2a and 3.2b present simulation results of 3.2 SUBSTRATE CROSSTALK BETWEEN TWO OHMIC CONTACTS 37

SpacerSpacer substrate substrate IntegratedIntegrated patch patch antenna antenna LargeLarge inductor inductor

Adhesive layer layer IsolationIsolation trench trench Through-waferThrough-wafer via via Wafer-to-wafer bonding (a) Illustrative ﬁgure of the proposed WLP concept.

Neumann boundary condition Neumann boundary conditionNeumann

Glass substrate

Port distance Glass thikcness Glass

GND Port 1 Port 2 GND

fixed

50µm 50µm Silicon substrate Neumann Neumann condition boundary Silicon thikcness Silicon 1100µm (b) Simulated model with applied boundary conditions.

Figure 3.1: Through-substrate trench isolation in wafer-level package: (a) illustrative figure of the proposed WLP concept that employs through-substrate trench; (b) simplified test structure to model substrate crosstalk in WLP. Aggressor and victim circuits are modeled by ohmic contacts. Certain boundary conditions are applied to enhance the simulation speed. 38 SUBSTRATE CROSSTALK MODELING IN WAFER-LEVEL PACKAGED INTEGRATED CIRCUITS 3.2 the impact of silicon substrate thickness on the isolation for different grounding schemes. Figure 3.2a shows the substrate crosstalk isolation for varying substrate thicknesses with the ground nodes located at the frontside. In this case, the bottom of the silicon substrate has the Neumann boundary condition applied. The results show that substrate thickness has little impact on the isolation when ground nodes are located at the frontside. This is because the current does not flow deep into the silicon substrate. On the other hand, isolation is strongly affected by the silicon substrate thickness as depicted in Figure 3.2b when the backside of the silicon substrate is grounded. The substrate current injected by the agressor port flows preferably towards the bottom of the silicon substrate due to lower potential instead of flowing to the victim port. Since in this case the re- 15 −3 sistivity of bulk silicon is considerably small (Na = 3 × 10 cm ), the substrate current will effectively be drawn down to the ground.

3.2.2 Distance impact on isolation

When noise is injected into the substrate by the agressor (i.e. port 1), some portion of the noise travels to the victim (i.e. port 2), while the remaining portion reaches the ground. The amount of the noise captured by port 2 depends on the physical distance between the two ports. Figure 3.3 shows the dependency of the isolation on the physical distance between the agressor and victim ports. Figure 3.3a shows that the isolation improves as the distance between ports gets longer, while the 20 dB-slope is not affected. This means that the cut-off frequency of the substrate does not change either. Figure 3.3b, however, shows a non-linear dependency of the isolation on the distance. One can see that the impact of the port distance on the isolation decreases as the distance increases. This means that at a certain distance, eventually, the dependency of the isolation on the distance becomes negligible. That is why increasing the distance to achieve higher isolation is effective only up to a certain limit, not mentioning the additional chip area required.

3.2.3 Substrate resistivity impact on isolation

Figure 2.9 in Chapter 2 shows that a piece of silicon substrate can be modeled by an RC network, where the R and C depend on the substrate resistivity and dielectric constant, respectively. While the capacitance takes effect at relatively high frequencies, the resistance is dominant at low frequencies. Simulation results depicted in Figure 3.4a show that the isolation becomes better when substrate resistivity becomes higher. It shows a similar phenomena where the isolation curve shifts down as the substrate resistivity becomes higher, because having larger resistivity has the same effect as having longer physical port distance. However, un- like in the previous case where the distance does not change the cut-off frequency, 3.2 SUBSTRATE CROSSTALK BETWEEN TWO OHMIC CONTACTS 39

−10

−20

| (dB) −30 21 |S −40

µ −50 50 m 100 µm 200 µm −60 −3 −2 −1 0 1 2 10 10 10 10 10 10 Frequency (GHz) (a) Isolation for varying silicon thicknesses with frontside grounding.

−10

−20

| (dB) −30 21 |S −40

µ −50 50 m 100 µm 200 µm −60 −3 −2 −1 0 1 2 10 10 10 10 10 10 Frequency (GHz) (b) Isolation for varying silicon thicknesses with backside grounding.

Figure 3.2: Simulated isolations for varying substrate thickness and ground locations. Silicon substrate thickness, resistivity, and port distance are 50 µm, 5 Ω-cm, and 100 µm, respectively, if not mentioned otherwise: (a) ground ports are located on top; (b) bottom side of the silicon substrate is grounded and no ground ports on top. 40 SUBSTRATE CROSSTALK MODELING IN WAFER-LEVEL PACKAGED INTEGRATED CIRCUITS 3.2

−10

−20

| (dB) −30 21 |S −40

µ −50 10 m 100 µm 300 µm −60 −3 −2 −1 0 1 2 10 10 10 10 10 10 Frequency (GHz) (a) Isolation when distance between ports is varied.

−10

−20

| (dB) −30 21 |S −40

−50 1 MHz 10 GHz 100 GHz −60 0 50 100 150 200 250 300 Distance (µm) (b) Isolation when distance between ports is varied.

Figure 3.3: Simulated isolations for different distances. Silicon substrate thickness, resistivity, and port distance are 50 µm, 5 Ω-cm, and 100 µm, respectively, if not mentioned otherwise: (a) frequency-dependent isolation for different distances; (b) distance- dependent isolation for different frequencies. THROUGH-SUBSTRATE TRENCH AS SUBSTRATE NOISE SUPPRESSION 3.3 TECHNIQUE 41 substrate resistivity does affect the cut-off frequency. According to Eq. 2.12, the cut-off frequency becomes lower as the substrate resistivity becomes larger. This is confirmed by the simulation results depicted in Figure 3.4a. This can be considered as one of the drawbacks in using the high-resistivity substrate to achieve high isolation. The high-resistivity substrate can improve the isolation below the cut-off frequency 1/2πρ² but starts to lose its isolation effectiveness at earlier stage which makes it less suitable for high-frequency1 application with respect to isolation, not to mention the higher cost of high-resistivity silicon substrates.

3.2.4 Interconnect parasitic impact on isolation

In general, a system-on-chip (SoC) after its packaging will have either bond- wire interconnections or flip-chip with redistribution layer (RDL) resulting in corresponding values of package equivalent model parasitics (i.e. resistances and inductances). One can clearly see in Figure 3.4b that the ground connection parasitics worsen the isolations. The ground connection parasitic, as expressed in Eq. 2.4, changes the potential level of the ground node according to the operating frequency, thus, affects the isolation achieved. The ground node potential becomes higher as the frequency increases. This makes the ground node no longer a lower potential node where the current should flow to. In other words, it will no longer be the node to drain the substrate current to ground. The isolation in Figure 3.4b is only plotted starting at 1 GHz due to the fact that at low frequencies the ground connection inductance has little effect on the isolation. Results achieved by Gharpurey in [Gha95] confirm the worsening of the isolation as the ground connection inductance gets larger.

3.3 Through-Substrate Trench as Substrate Noise Suppres- sion Technique

In the previous section, some design as well as processing-related strategies to suppress the substrate noise were discussed. It has been shown that those strategies can eventually suppress the substrate crosstalk to a certain extent. However, their drawbacks often prevent the designers from using them. In Chapter 2, nevertheless, some state-of-the-art substrate noise suppression techniques are discussed. In this section, the proposed through-substrate trench based on WLP technology as substrate noise suppression technique is thoroughly discussed. The reference structure is shown in Figure 3.1b, where the two signal ports are separated by 100 µm distance and the silicon substrate thickness is 50 µm.

1At frequency higher than the cut-oﬀ freqeency. 42 SUBSTRATE CROSSTALK MODELING IN WAFER-LEVEL PACKAGED INTEGRATED CIRCUITS 3.3

−10

−20

−30

| (dB) −40 21 |S −50

−60 5 Ω−cm −70 100 Ω−cm 1000 Ω−cm −80 −3 −2 −1 0 1 2 10 10 10 10 10 10 Frequency (GHz) (a) Isolation when silicon substrate resistivity is varied.

−5

−10

−15

| (dB) −20 21 |S −25

−30 L = 0 nH −35 gnd L = 0.1 nH gnd −40 0 1 2 10 10 10 Frequency (GHz) (b) Isolation when ground inductance is varied.

Figure 3.4: Simulated isolations for different substrate resistivities and ground inductances. Silicon substrate thickness, resistivity, and port distance are 50 µm, 5 Ω-cm, and 100 µm, respectively, if not indicated otherwise: (a) isolations for different resistivities; (b) isolations with different ground inductances. THROUGH-SUBSTRATE TRENCH AS SUBSTRATE NOISE SUPPRESSION 3.3 TECHNIQUE 43

(a) Test structure with air-ﬁlled through-substrate trench.

(b) Test structure with metalized through-substrate trench.

Figure 3.5: Test structures modeled in MEDICI for different isolation schemes. The isolation level becomes significantly higher when isolation structure is introduced. Grounded metalized trench proves to be superior over the air-filled trench: (a) test structure with air-filled through-substrate trench; (b) test structure with metalized through- substrate trench. 44 SUBSTRATE CROSSTALK MODELING IN WAFER-LEVEL PACKAGED INTEGRATED CIRCUITS 3.3

(a) Test structure with metalized through-substrate trench extended into glass substrate.

-20

-40 no trench air-filled trench | (dB) | grounded metalized trench 21 -60 extended grounded metalized trench |S

-80

-100 -2 0 2 10 10 10 Frequency (GHz) (b) Isolations with diﬀerent isolation schemes.

Figure 3.6: Test structures modeled in MEDICI for different isolation schemes. The isolation level becomes significantly higher when isolation structure is introduced. Grounded metalized trench proves to be superior over the air-filled trench: (a) test structure with metalized through-substrate trench extended into glass substrate; (b) isolations with different isolation schemes. 3.4 SYNTHESIS OF EQUIVALENT CIRCUIT MODEL 45

The first isolation scheme introduced here is the through-substrate trench depicted in Figure 3.5a. The through-substrate trench creates silicon islands that are completely separated. The formation of an open (air-filled) trench that divides the silicon island between the signal ports (Figure 3.5a) yielded a significant improvement in isolation at low frequencies (Figure 3.6b). At frequencies above 10 GHz, however, level of isolation approaches that of the reference structure due to the capacitive coupling across the air-filled trench. The residual improvement in isolation is related only to the lower dielectric constant of air as compared to silicon within the trench (²r,air = 1 vs. ²r,Si = 11.7), leading to a higher electrical separation of the ports compared to the reference structure. With a grounded metal formed within the trench (Figure 3.5b), however, the isolation is greatly improved both at low and high frequencies. This is due to the fact that the substrate noise is drained to ground through the metalized through-substrate trench. To improve the isolation even further, the metalized trench can be extended into the glass substrate (Figure 3.6a). The results of all the aforementioned schemes are plotted in Figure 3.6b.

3.4 Synthesis of Equivalent Circuit Model

The numerical modeling using the device solver requires considerable computational time. Therefore, it is desirable to build an equivalent circuit model com- prised of ideal lumped elements [Lan]. The equivalent circuit can be solved using common circuit simulators (e.g. SPICE, ADS). In this section, topology for the equivalent circuit for all cases, i.e. no trench, air-ﬁlled trench, and metalized trench, are proposed. The equivalent circuit consists of two major parts: a circuit model for the glass, and a circuit model for the silicon. The silicon can be represented by RC network [Don03], while the glass can be represented by a simple capacitor [Koo91] since it can be modeled as an insulator as mentioned earlier. The synthesis of equivalent circuit is based on the y-parameters obtained from the device simulation. The two-port Y-parameters for the equivalent circuit shown in Figure 3.8a are given by:

Y = Y + Y (3.1) ·Silicon Glass ¸ Y1(ω) + Y2(ω) −Y2 YSilicon = (3.2) −Y2 Y3(ω) + Y2(ω) · ¸ Y (ω) Y (ω) = 11 12 (3.3) Y21(ω) Y22(ω)

YGlass = Y4(ω) (3.4)

where Yij(ω) = Gij(ω) + jωCij(ω). The values of Yij(ω) are obtained from the 46 SUBSTRATE CROSSTALK MODELING IN WAFER-LEVEL PACKAGED INTEGRATED CIRCUITS 3.4

ωωω Y4( ) glass C 1st order 2 glass polynomial R4 ωωω Y2( ) R 3 C R1 3 R5 silicon silicon ωωω ωωω Y1( ) Y3( )

C1 R2 C4 R6 2nd order polynomial (a) PI-structure for a two-port network. (b) Equivalent circuit topology for no- trench reference structure: namely case a.

C2 glass C2 glass

C R 3 R1 3 R1 R3 silicon silicon C C 2 R2 3 R4 C2 R2C4 R4

(c) Equivalent circuit topology for air- (d) Equivalent circuit topology for metalized ﬁlled trench structure: namely case b. trench structure: namely case c.

Figure 3.7: Equivalent circuit topology for a silicon-glass sandwich structure. The silicon substrate is modeled by R and C, while the glass substrate is modeled by C: (a) PI- structure for a two-port network; (b) equivalent circuit topology for no-trench reference structure: namely case a; (c) equivalent circuit topology for air-ﬁlled trench structure: namely case b; (d) Equivalent circuit topology for metalized trench structure: namely case c. 3.5 SYNTHESIS OF EQUIVALENT CIRCUIT MODEL 47

Table 3.1: Extracted parameters table. Parameter case a case b case c case d

R1 1.21 Ω 0.54 Ω 0.20 Ω 0.20 Ω R2 2841.40 Ω 2862.70 Ω 165.61 Ω 165.61 Ω R3 3.51 Ω 0.54 Ω 0.20 Ω 0.20 Ω R4 14503 Ω 2862.70 Ω 165.61 Ω 165.61 Ω R5 1.21 Ω - - - R6 2841.40 Ω - - - C1 4.58 fF 4.57 fF 39.36 fF 39.36 fF C2 1.39 fF 1.39 fF 1.39 fF 0.22 fF C3 5.47 fF 4.03 fF 39.36 fF 39.36 fF C4 4.58 fF 4.57 fF - -

device simulation which are then extracted to yield the components of Yn(ω) by means of curve ﬁtting [Lev]. The curve ﬁtting procedure is done based on the rational polynomial (see Eq. 3.5). The equivalent circuit is then constructed based on the transfer function given by the rational polynomial. The transfer function of the circuit for the silicon area can be modeled accurate enough by 2nd order rational polynomial. However, to extract the value for individual components (Y1(ω), Y2(ω), Y3(ω)), only the 1st order rational polynomials are required.

2 m A0 + A1(jω) + A2(jω) + ··· + Am(jω) F (jω) = 2 n (3.5) 1 + B1(jω) + B2(jω) + ··· + Bn(jω)

The equivalent circuit topologies proposed are depicted in Figure 3.7, where case c and case d use the same topology. The procedure to extract all the parameters for all cases is as follows:

1. Extract the parameters for case c.

2. Extract the parameters for case b by using the same value of C2 obtained in case c.

3. Extract the parameter for case a by using the same value of C2 obtained in case c.

The extracted component values are listed in Table 3.1 and are now ready to be included in the equivalent circuit to model the substrate coupling problem. The isolation behavior resulting from the equivalent circuit modeling is shown in Figure 3.8 and compared to the results obtained from device simulation. 48 SUBSTRATE CROSSTALK MODELING IN WAFER-LEVEL PACKAGED INTEGRATED CIRCUITS 3.5

0 0

−20 −20

−40 −40 | (dB) | (dB) 21 21

|S −60 |S −60

−80 −80 device simulation device simulation circuit simulation circuit simulation

−100 −2 0 2 −100 −2 0 2 10 10 10 10 10 10 Frequency (GHz) Frequency (GHz) (a) case a: reference structure with no isolation (b) case b: air-ﬁlled trench structure

0 0 device simulation device simulation circuit simulation circuit simulation −20 −20

−40 −40 | (dB) | (dB) 21 21

|S −60 |S −60

−80 −80

−100 −2 0 2 −100 −2 0 2 10 10 10 10 10 10 Frequency (GHz) Frequency (GHz) (c) case c: metalized trench structure (d) case d: extended metalized trench structure

Figure 3.8: Curve-fitting results for all test cases. Equivalent circuits are built based on the extracted values from curve-fitting. Circuit simulation results are then compared with device simulation results: (a) reference structure; (b) air-filled trench structure; (c) metalized trench structure; (d) extended metalized trench structure. 3.5 SUMMARY 49

3.5 Summary

It has been shown that the substrate thickness impact on the isolation is largely dependent on the grounding scheme, i.e. position of the ground either on the frontside or backside of the silicon substrate. As current always goes through the path defined by the lowest impedance value, a larger part of the substrate noise reaches the backside ground when the substrate gets thinner. This is confirmed by the simulation results depicted in previous sections. Simulation results also show that the isolation between the aggressor and the victim nodes depends on the physical distance between them. The farther the aggressor and the victim are separated, the higher isolation will be reached. Relying on the distance to achieve higher isolation, however, is only effective to a certain extent since a saturation level can be observed. In other words, at a certain distance the separation increase no longer shows any significant effect on isolation, and the chip-size increase required will only increase cost but would not improve performance. Higher degree of isolation can also be achieved by using higher resistivity substrate as demonstrated by simulations. The isolation is shifted down to higher degree at low frequencies where the resistive behavior of the silicon substrate is in effect. At high frequencies, however, the isolation degrades 20 dB/dec. At a certain frequency, higher resistivy no longer brings any improvement with respect to isolation. As mentioned earlier the largest portion of current flows through the path with the least impedance. That is why ground connection parasitics (e.g. inductance) impacts the isolation level. The isolation degrades as the ground connection inductance gets larger. The substrate with or without isolation structure has to be modeled correctly. Lumped element circuit model is preferable with respect to computational time. The frequency-dependent behavior of the substrate is shown from the S-parameter which later can be converted into Y-parameter. From the Y-parameter, a rational polynomial equation can be built to fit the Y-parameter response. Then, RC network can be synthesized to model the rational polynomial equation. Lastly, the RC network can then be hooked up with the circuit design in order to model the substrate effects properly.

Chapter 4 High-Frequency Substrate Characterization

On-chip integrated passive devices such as spiral inductors, antennas, and transmission lines form the limiting factor of silicon radio-frequency integrated-circuits (RFICs) in terms of the performance and the required chip area. Therefore, any advances in the technology of their implemetation can potentially lead to a significant cost reduction. A major reason behind these limitations is the considerable substrate loss due to the electrical conductivity of the silicon substrate. The relatively high substrate conductivity is not only causing the low quality factor (Q-factor) of on-chip passive devices, but also enables the parasitic current to be injected into the substrate, thus coupling devices at diﬀerent parts of the circuits, which eventually deteriorates the overall performance. One way to improve the Q-factor of the passive devices is to use high-resistivity silicon [Bur03]. Moreover, higher substrate resistivity can also suppress the substrate crosstalk [Sin04]. As mentioned in Chapter 1, one of the typical features of the emerging wafer- level packaging technology is the utilization of spacer substrate that has preferably low RF loss, high permittivity, and good thermal conductivity. While the low RF loss property is required to obtain high Q factor, the high permittivity is mainly for the reason of size reduction. The length of transmission lines in passive circuits such as matching networks, couplers, and dividers are given as fraction of a guided wavelength, λg. For transverse-electromagnetic (TEM) and quasi-TEM structures, the free-space wavelength (λ0) and guided wavelength (λg) are related directly through eﬀective dielectric constant of the material Eq. 4.1:

λ0 λg = (4.1) ²eﬀ

51 52 HIGH-FREQUENCY SUBSTRATE CHARACTERIZATION 4.1

The same device realized on two different substrate materials having different dielectric constant will occupy a smaller area on the higher dielectric constant material. This saving in circuit area usually translates into reduced cost, lower weight, and higher density circuits, all of which are attractive properties to the commercial circuit designer. Lastly, the spacer substrate has to be thermally conductive in order to effectively transfer the heat generated by the devices to the package, especially when high DC current is used [Sag05]. In this chapter, several possible spacer substrate materials such as AF-45 glass and high-resistivity polycrystalline silicon (HRPS) are characterized up to 40 GHz. The high-frequency substrate characterization was done using a coplanar waveguide (CPW) test structure [Hin95], [Hin01].

4.1 Substrate Parameters

4.1.1 Dielectric permittivity

Michael Faraday discovered that when a slab of insulator was inserted between two parallel metal plates kept at a constant electrical potential (i.e. a parallel- plate capacitor, to which a constant voltage was applied by means of a battery), the charge on the plates increased, hence, the capacitance of such capacitor is increased [Ble76]. If the insulator entirely fills the intervening space between the parallel plates, the capacitance is increased by a factor ²r, where ²r is called the relative permittivity or dielectric constant of the insulating material, which depends on the nature of the material. The relative dielectric constant of vacuum is, of course, unity. Since the insulators are insulating materials and do not conduct electricity, so why is there any electrical effect, given the fact that the capacitance is increased. Let us now consider an air-filled parallel-plate capacitor with negative charges on the top plate and positive charges on the bottom plate. Suppose that the spacing between plates is d and the area of each plate is A, then the capacitance of such capacitor according to [Fey63a] is: ² A C = 0 (4.2) d and the charge and voltage on the capacitor are related as: Q = CV (4.3) Now according to the experiment by Michael Faraday, the capacitance becomes larger when a piece of insulating material is inserted between the parallel plates. That means for the same amount of charges, the voltage becomes lower. Know- ing that the voltage is the integral of the electric field across the capacitor, it 4.1 SUBSTRATE PARAMETERS 53 can be concluded that the electric field inside the capacitor is reduced, although the amount of charges on the plates remains unchanged [Fey63b]. According to

conductor

______

+ + + + + + + s

E dielectric d

______

+ + + + + + + + + + + + + conductor

Figure 4.1: A parallel-plate capacitor with a dielectric. The lines of E˜ ﬁeld are shown (adapted from [Fey63b]). Capacitance value depends on the dielectric constant of the material in between the parallel plate, area of the plate and the distance between the two plates.

Gauss’s law, the flux of electric field is directly related to the enclosed charge (consider the Gaussian surface S in Figure 4.1). Since the electric field is reduced with the dielectric present, it is concluded that the net charge inside the surface must be lower than it would be the case without the dielectric material. There is only one possible conclusion, that is that there must be positive charges on the surface of the dielectric material. Since the field is reduced but is not zero, it is expected that this positive charge to be smaller than the negative charge on the conductor. In other words, when a dielectric material is placed in an electric field there is positive charge induces on one surface and negative charge induced on the other (see Figure 4.1).

4.1.2 Substrate loss

When electric ﬁeld E~ is applied inside a dielectric material, it causes the polarization of the atoms or molecules of the material creating electric dipole moments that augment the total displacement ﬂux, P~e. This additional polarization vector is called P~e, the electric polarization, where [Poz98]

D~ = ²0E~ + P~e (4.4) In a linear medium, the electric polarization is linearly related to the applied electric ﬁeld as P~e = ²0χeE,~ (4.5) 54 HIGH-FREQUENCY SUBSTRATE CHARACTERIZATION 4.2

where χe, which may be complex, is called the electric susceptibility. Then,

D~ = ²0E~ + P~e = ²0(1 + χe)E~ = ²E,~ (4.6) where 0 00 ² = ² − j² = ²0(1 + χe) (4.7) is the complex permittivity of the medium, where the imaginary part accounts for the loss in the medium (heat) due to the damping of the vibrating dipole moments and is negative (²00 positive) due to the energy conservation [Poz98]. The loss in a dielectric material may also be considered as an equivalent conductor loss. In a material with conductivity σ, a conduction current density will exist [Poz98]:

J~ = σE~ (4.8) which is Ohm’s law from an electromagnetic ﬁeld’s point of view. Thus, we can rewrite the Ampere-Maxwell law [Poz98]:

∇ × H~ = jωD~ + J~ (4.9) = jω²E~ + σE~ (4.10) = jω²0E~ + (ω²00 + σ)E~ (4.11) ³ σ ´ = jω ²0 − j²00 − j E~ (4.12) ω where it is seen that loss due to dielectric damping (ω²00) is indistinguishable from conductivity loss (σ). The term ω²00 + σ can then be considered as the total eﬀective conductivity. A related quantity of interest is the loss tangent, deﬁned as: ω²00 + σ tan δ = (4.13) ω²0 which is seen to be the ratio of the real to the imaginary part of the total displacement current. For microwave application, materials are usually characterized 0 by specifying the real permittivity, ² = ²r²0, and the loss tangent at a certain frequency.

4.2 Coplanar Waveguide (CPW)

Coplanar Waveguide (CPW) was ﬁrst proposed by C. P. Wen in 1969. It consisted of a dielectric substrate with conductors on the top surface [Wen69]. The CPW has the center strip as a signal line separated by a narrow spacing from two ground planes on either side. CPW has rapidly gained widespread use for RF and microwave ICs due to its many attractive features, such as elimination of via holes connecting circuit elements to ground, easy integration with solid-state devices, 4.2 COPLANAR WAVEGUIDE (CPW) 55

2b h4 t = 0 2a εεε r1 h1 εεε r2 h2

Figure 4.2: Cross-sectional view of a CPW with top and bottom metal layer. A CPW consists of signal line in the middle and ground lines on the sides. Top and bottom conductors are optional. ease realization of compact balanced circuits, and reduction of crosstalk between lines. The dimensions of signal line, spacing, the thickness and permittivity of the dielectric substrate determine the effective dielectric constant ²eff , characteristic impedance (Z0) and the attenuation of the line (α) [Sim01]. In this section a variant of the cross-sectional view of a coplanar waveguide (CPW) with top and bottom metal layer on a multi-layer dielectric substrate is illustrated in Figure 4.2. Closed-form expressions for the effective dielectric constant Eq. 4.14 and characteristic impedance Eq. 4.15 of these transmission lines with zero strip thickness were derived using conformal-mapping methods [Ghi84]. For the conventional CPW where h2 = 0 and h3 = h4 =∝, they are given below: 0 ²r − 1 K(k0) K(k1) ²eff = 1 + 0 (4.14) 2 K(k0) K(k1) and 0 30π K(k0) Z0 = √ (4.15) ²eff K(k0) where a k3 = k4 = k0 = (4.16) qb 0 2 k0 = 1 − k0 (4.17) sinh(πa/2h ) k = 1 (4.18) 1 sinh(πb/2h ) q 1 0 2 k1 = 1 − k1 (4.19)

K represents the complete integral of the ﬁrst kind, whose values can be determined from an integral or tabulated tables. The K(k)/K(k0) ratio can also be 56 HIGH-FREQUENCY SUBSTRATE CHARACTERIZATION 4.2 obtained approximately by [Hil69]:

 π  Ã ! , 0 ≤ k ≤ 0.707  √  1 + k0  ln 2 √ K(k)  1 − k0 = (4.20) K(k0)  Ã !  √  1 1 + k  ln 2 √ , 0.707 ≤ k ≤ 1 π 1 − k

For the conductor-backed CPW where h2 = h3 = 0 and h4 =∝, the eﬀective dielectric constant and characteristic impedance can be evaluated from [Ghi83]:

0 K(k0) K(k1) 1 + ²r 0 K(k0) K(k1) ²eﬀ = 0 (4.21) K(k0) K(k1) 1 + 0 K(k0) K(k1) and 60 π 1 Z0 = √ (4.22) ²eﬀ K(k0) K(k1) 0 + 0 K(k0) K(k1) where a k0 = (4.23) pb 0 2 k0 = 1 − k (4.24) tanh(πa/2h ) k = 1 (4.25) 1 tanh(πb/2h ) q 1 0 2 k1 = 1 − k1 (4.26)

Analytical formula for conductor attenuation constant for the conventional CPW is given as [Gup81]:

4.88 × 104 b + a α = R ² Z × c π s eﬀ 0 (b − a)2    1.25t 8πa 1.25t   ln + 1 +  π t 2πa · µ ¶¸2 (4.27)  2a 1.25t 8πa   2 + − 1 + ln  b − a π(b − a) t 4.3 TEST STRUCTURES DESIGN AND MEASUREMENT RESULTS 57 where  · ¸2  k K(k)  , 0 ≤ k ≤ 0.707 0 0 3/2 K(k0) P = (1 − k )(k ) (4.28)  1  √ , 0.707 ≤ k ≤ 1 (1 − k) k p Rs = ωµ0/2σ is the surface resistivity of the conductor. (4.29)

The expression for the dielectric attenuation constant is given as [Ngu00]

27.3 ²r (²eﬀ − 1) tan δ αd = √ (dB/m) (4.30) ²eﬀ (²r − 1) λ0 where tan δ is the loss tangent of the dielectric and λ0 is the free-space wavelength.

4.3 Test Structures Design and Measurement Results

Electrical properties such as complex permittivity, permeability, and loss tangent for a large variety of thin planar materials in the broad microwave frequency range are required for numerous applications. Therefore, it is very important that these properties are accurately determined. In this work, AF-45 glass and high-resistivity polycrystalline silicon (HRPS) substrate are characterized from 50 MHz to 40 GHz. HRPS wafers were obtained from an undoped polycrystalline silicon rod that is normally used as the starting material for a ﬂoat-zone process of high-resistivity single-crystalline silicon wafers.

4.3.1 Design of ﬁnite-ground CPWs

There are many types of planar transmission line structures that support quasi- TEM modes, where the most common ones are microstrip, stripline, and coplanar waveguide (CPW). Out of these three transmission lines, only CPW offers the possibility of single-sided metalization, thus, easy design, fabrication, and measurement. The finite-ground CPW (FGCPW) is a variant of CPW, in which the width of the ground planes are limited to Wg as shown in Figure 4.2. The ground- signal-ground configuration gives the advantages of balanced wave propagation, while the finite width ground planes allows control of the cut-off frequencies for higher order modes, increasing the upper operating frequency bound. Moreover, since CPWs structure where 2b < h (see Figure 4.2) supports quasi-TEM mode, it is possible to compute the substrate properties from analytical equations determined from conformal mapping techniques instead of any numerical methods, which decreases the computational time significantly [Hin02]. The transverse E~ field and H~ field in a CPW structure are depicted in Figure 4.3. 58 HIGH-FREQUENCY SUBSTRATE CHARACTERIZATION 4.3

(a) Fundamental mode of E~ ﬁeld in CPW

(b) Fundamental mode of H~ ﬁeld in CPW

Figure 4.3: The field pattern in CPW structure: (a) Fundamental mode of E~ field in CPW; (b) Fundamental mode of H~ field in CPW. 4.3 TEST STRUCTURES DESIGN AND MEASUREMENT RESULTS 59

Higher order modes will occur when the total width of the line geometry is equal to a half wavelength [Her00]:

λ 2b + 2W ≤ g (4.31) g 2 The parallel plate modes will cause a drastic increase in the line parasitics and thus undesired loss. Therefore, it is important to design a structure with cut-oﬀ frequency above the maximum frequency of the measurement, i.e. 40 GHz, to assure a single-mode propagation throughout the measurement band. Since the materials to be characterized are expected to be low loss, the primary source of attenuation is then the conductor loss. In FGCPW lines, if the ground planes are made too narrow, the ground plane conductors as the signal return paths can add signiﬁcant loss. It is explained in [Her00] that, in order to have FGCPW attenuation within 2% of CPW attenuation, the ground plane width must be equal to or greater than the spacing between the two ground planes:

Wg ≥ 2b (4.32)

Both of the ground plane width criteria prescribed in Eq. 4.31 and Eq. 4.32 must be met through careful choice of Wg.

4.3.2 CPW utilization for substrate characterization

In this section, an extraction method found in [Hin01] and [Hin02] is used to characterize the materials, i.e. high-resistivity polycrystalline silicon and AF-45 glass. The method used to characterize material properties incorporates the S- parameter obtained from the measurement. The method requires the propagation to be quasi-TEM as the fundamental mode as discussed earlier. From the S- parameters, the transmission coefficient (T) can be obtained using the following equation: S + S21 − Γ T = 11 (4.33) 1 − (S11 + S21)Γ where p Γ = K ± K2 − 1 (4.34) and S2 − S2 + 1 K = 11 21 (4.35) 2S11 With the transmission coefficient (T ) and the physical length of the coplanar, we are now able to define the complex effective permittivity using the following equations: µ ¶ − ln T 2 ²eff = − √ (4.36) ωd ²0µ0 60 HIGH-FREQUENCY SUBSTRATE CHARACTERIZATION 4.4 and the relative permittivity which is the real part of the complex relative permittivity is obtained from analytical equations [Ghi83], [Hof87]:

0 0 0 2(²eﬀ − 1)K(k1)K(k0) ²r = 0 + 1 (4.37) K(k1)K(k0)

4.3.3 Measurement and results

A vector network analyzer and a probe station were used to perform the on-wafer measurement to obtain S-parameters of the two-port network device. The measurement setup was calibrated by means of LRM method in the frequency range from 50 MHz up to 40 GHz. The accuracy of the obtained values strongly depends on the accuracy of the measured S-parameters [Eis92]. Therefore, the measured S-parameters had to be checked for accuracy and reliability. Thus, measurement for a single device was conducted more than once and only repeatable measurement results were taken for further analysis. Also, devices having different lengths (i.e. 0.5 mm, 1 mm, 3 mm, and 5 mm) were fabricated and measured. The measured S-parameters of the test device are depicted in Figure 4.5. Based on these parameters, material properties of AF-45 glass and high-resistivity polycrystalline silicon (HRPS) were extracted using the algorithm described above. The dielectric constant of the characterized materials is depicted in Figure 4.6 while the losses are shown in Figure 4.7. The loss figure obtained for HRPS proves, that it is a low-loss material. Given this result, HRPS offers several advantages in comparison to AF-45 glass, such as higher and nearly frequency independent dielectric constant (∼11.7 compared to ∼5.2; Figure 4.6) allowing for a more compact component integration, the >10-times higher thermal conductivity, the perfect matching of the thermal expansion coefficient to that of integrated circuit (IC) wafer, and the full compatibility to silicon processing.

4.4 Summary

From the design and processing technology perspective, CPW is an easy to implement structure. That makes it the preferred device for substrate characterization used in this work. Both characterized substrates, i.e. HRPS and AF-45 glass, show very low loss even at high frequency (up to 40 GHz). That makes both substrates suitable for use as a spacer material, particularly, when the spacer substrate is used to integrate passive devices at low dc, such as inductors. The dielectric constants of the substrates, however, are quite diﬀerent. AF-45 glass substrate shows more or less half of the dielectric constant of HRPS. Dielectric constant impacts the guided wavelength, hence, the guided velocity. Also, the higher the dielectric constant 4.4 SUMMARY 61 the more capacitive the substrate is. Designs such as multi transmission line may suﬀer from capacitive coupling due to high dielectric constant. Therefore, a proper analysis has to be done before substrate is chosen for particular application. 62 HIGH-FREQUENCY SUBSTRATE CHARACTERIZATION 4.4

Figure 4.4: Top view of fabricated FGC with signal width 50 µm, spacing 35 µm, and Wg 475 µm with various length from 0.5 mm to 5 mm. 4.4 SUMMARY 63

−10

−20

| (dB) −30 11 |S

−40

−50 HRPS Glass −60 0 5 10 15 20 25 30 35 40 Frequency (GHz)

(a) Measured S11

−0.2

−0.4

−0.6

−0.8

| (dB) −1 21

|S −1.2

−1.4

−1.6

−1.8 HRPS Glass −2 0 5 10 15 20 25 30 35 40 Frequency (GHz)

(b) Measured S21

Figure 4.5: Measured S-parameter of CPW shown in Figure 4.4: (a) S11 in dB; (b) S21 in dB 64 HIGH-FREQUENCY SUBSTRATE CHARACTERIZATION 4.4

ε r HRPS

ε eff HRPS Permittivity

5 ε r Glass

ε eff Glass

0 0 5 10 15 20 25 30 35 40 Frequency (GHz)

Figure 4.6: Extracted dielectric constant of AF-45 glass and HRPS. 4.4 SUMMARY 65

0.4 HRPS Glass 0.35

0.3

0.25

0.2 LossTan 0.15

0.1

0.05

0 0 5 10 15 20 25 30 35 40 Frequency (GHz) (a) Extracted loss tangent of AF-45 glass and HRPS

0.1 HRPS 0.09 Glass

0.08

0.07

0.06

0.05

0.04

Total Loss (dB/mm) 0.03

0.02

0.01

0 0 5 10 15 20 25 30 35 40 Frequency (GHz) (b) Total loss of the CPW in dB/mm

Figure 4.7: Extracted total loss of AF-45 glass and HRPS. The total loss consists of conductor loss and substrate loss: (a) Extracted loss tangent of AF-45 glass and HRPS; (b) Total loss of the CPW in dB/mm.

Chapter 5 Metalized Through-Substrate Trench Approach

In this chapter first the objective of the test structure design is presented. Then the related considerations for boundary conditions used in simulations and their matching with technology and measurement limitations are discussed. It is important to know if certain assumptions are made and if they still hold in order to achieve the design objective. Next, step-by-step fabrication flow of the wafer- level packaging technique is presented in detail. This include all the parameters applied in the process. The measurement setup used as well as the calibration and de-embedding method applied to guarantee accurate and valid measurement results are described. Finally, the simulation results are verified by measurements and any observed discrepancies are discussed.

5.1 Design Objective and Considerations

In Chapter 2, theoretical studies on substrate noise are thoroughly discussed. Substrate noise injection, transmission, and reception mechanisms are described. It also describes the state-of-the-art substrate noise suppression techniques. In Chapter 3, various simulations to study the substrate noise behavior were done and results are presented. In that chapter, several factors that have impact on the substrate noise are studied. Based on these results, equivalent circuit models were synthesized. As mentioned earlier, the objective of this thesis is to propose a new scheme of substrate noise isolation. This chapter, in particular, deals with the designs of the test structures. The test structures are designed in order to

67 68 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.1 verify all the theoretical studies and simulation results presented earlier. Pfost in [Pfo98] and Szmyd in [Szm] used concentric ring shape substrate tap as test structures. This shape of structure was used to minimize the inﬂuence of the remote groundline substrate taps. This was not the case when simple rectangular test structures were used. Interestingly, a ground shield made of polysilicon is present under the signal pads in Figure 5.1a in order to prevent direct coupling to the substrate. Top views of these two shapes are illustrated in Figure 5.1.

G2 S2 G2 G2 S2 G2

Port 2

Portv 1

Port 1

Ground shield G1 S1 G1 G1 S1 G1 (a) A concentric shape test structure (b) A rectangular shape test structure

Figure 5.1: Top views of test structures for substrate coupling investigation with ground- signal-ground conﬁguration. Port 1 and port 2 model the aggressor and the victim, respectively: (a) a concentric shape test structure; (b) a rectangular shape test structure.

Looking at the test structure illustrated in Figure 5.1, all parasitics, i.e. resistive, inductive, and capacitive, of the interconnects need to be removed in order to properly model the substrate coupling. In addition to that, a major problem of on-wafer measurement is the crosstalk between the RF probes as illustrated in Figure 5.2a. This crosstalk can lead to measurement errors, particularly when measuring a weak substrate coupling. Therefore, the coupling between the RF probes also needs to be de-embedded. Such de-embedding procedure was performed in [Ste02]. This work explores the potential of wafer-level packaging technique where the silicon substrate is bonded to a spacer substrate, i.e. AF-45 glass substrate at the frontside. Therefore, the frontside of the silicon substrate will no longer be accessible. Alternatively, backside of the silicon (see Figure 5.2b) can host the measurement probes. Details of the process ﬂow is described in the fabrication ﬂow section. Other measurement detail like the minimum size of the pads, i.e. 50 µm, which allows the probes to skid has also to be considered. Multiple structures are to be designed in arrays to enable convenient measurement. Technological aspects also need to be taken into account. In wafer-level pack- 5.1 DESIGN OBJECTIVE AND CONSIDERATIONS 69

G1 S1 G1 Silicon G2 G1 G2 S2 S1 DUT S2 G2 G1 G2

Glass

(a) Coupling between RF probes (b) Backside measurement access

Figure 5.2: Measurement consideration in designing test structures. GSG (Ground- Signal-Ground)probes are used. Depending the position of the probes, they may couple to each other, therefore, need to be de-embedded: (a) coupling between RF probes; (b) backside measurement access. aging, etching is frequently used. In this particular work, KOH etching was employed to create the isolation trenches. KOH etching is known to produce imperfect corners as depicted in Figure 5.3, and therefore this phenomena needs to be anticipated in the designs1. All test structures in this work were processed on a single wafer to maintain consistent results. The wafer-level packaging technique implemented in this work uses a spacer substrate. Not only is the spacer substrate used as supporting substrate, but also to provide low-loss material to achieve high Q-factor for the passive devices. Chap- ter 4 discusses high-frequency material characterization where a coplanar waveguide was used as the test device. Two materials were characterized, i.e. high- resistivity polycrystalline silicon (HRPS) and AF-45 glass. Measurement results show that AF-45 glass introduces smaller substrate loss compared to HRPS. Thus, AF-45 was chosen to be the spacer substrate in this work. Lastly, a proper tool to run the simulation is required. The materials used in the test structures include p-type silicon, BCB, AF-45 glass and metal. Later in the next section, it is described that ohmic contacts are used as the sensors. This means that we are dealing only with a single type of semiconductor material, i.e. p-type silicon. Therefore, an electromagnetic solver would be an appropriate tool to simulate the eﬀect of substrate noise. Due to the nature of wafer-level packaging technology that explores three-dimensional integration, it is required that the employed tool has the 3D simulation capability. EM tools that are available on the market can largely be divided into two groups, namely full-wave and quasi-static. A full-wave EM tool solves both Electric Field (E~ ) and Magnetic Field (H~ ), namely Maxwell’s Equations, simultaneously in a rigorous way. Eq. 5.1

1This can be done by adding a corner-compensating mask structures. 70 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.2

(a) Ideal KOH etching result (b) Imperfect corner from KOH etching

Figure 5.3: Comparison between ideal and realized KOH etching results: (a) ideal KOH etching result; (b) imperfect corner from KOH etching. and Eq. 5.2 show that E~ ﬁeld and H~ ﬁeld are coupled to each other, therefore, cannot be solved independently.

∂H~ ∇ × E~ = −µ (5.1) " ∂t# ∂E~ ∇ × H~ = ² + J~ (5.2) ∂t

However, under the assumption that the device-under-test (DUT) is electrically small, the time derivatives (∂H/∂t~ and ∂E/∂t~ ) in Maxwell’s Equations can be neglected as shown by Eq. 5.3 and Eq. 5.4.

∇ × E~ = 0 (5.3) ∇ × H~ = J~ (5.4)

The solutions represented by Eq. 5.3 and Eq. 5.4 is called Quasi-Static approximation. There is no precise threshold when to use the Full-Wave solution, and when the Quasi-Static solution. One rule of thumb is to use the Full-Wave solution when the DUT is larger than λg/10. For all these reasons, Ansoft HFSS was selected to do all the simulations. Ansoft HFSS is a Frequency-Domain 3D Full-Wave EM solver based on Finite Element Method (FEM).

5.2 Test Structures Design and Simulations

As described in the early section, a concentric structure is preferred over the rectangular one. This is because the latter one has a dependency on the ground substrate tap positions. However, the polysilicon ground shield mentioned earlier requires an additional mask and is, thus, more expensive. For this reason, the 5.2 TEST STRUCTURES DESIGN AND SIMULATIONS 71 rectangular structure was chosen. The positions of the ground substrate taps remain the same to maintain consistent results. In this section, all test devices designed are thoroughly described. In the actual design flow, all devices were simulated to ensure that they would give results as expected. When everything was according to expectation, the masks were designed and taped-out. As mentioned earlier, Ansoft HFSS is the selected tool for the EM simulation. Ansoft HFSS recognizes several boundary conditions. These boundary conditions are used for physical conditions enforcement as well as design simplification. The latter brings benefits for computational time saving. These boundary conditions are discussed in Appendix A. Appendix B describes how the boundary conditions are implemented onto the models in the simulation.

5.2.1 Control device

The first device designed was the control device which we use as a reference, denoted as Device #1. Device #1 is a two-port device with ground-signal-ground configuration and is depicted in Figure 5.4. The device was processed on a low- resistivity p-type silicon substrate (²r = 11.7, ρ = 2 − 5 Ω-cm) bonded to a spacer substrate which is AF-45 glass (²r=5.2) using BCB (²r = 2.7). Figure 5.4b shows that Device #1 consists of 10 substrate taps. Two substrate taps with size 100 µm × 100 µm are each connected to the signal line. The other eight substrate taps with size 50 µm × 50 µm are connected to the ground lines to provide low-impedance return path for the signal. Contact pads for landing the probes’ tips are 80 µm × 80 µm. From Figure 5.4a and Figure 5.4b, one can clearly see that only small fractions of the signal lines reach underneath the silicon substrate. The silicon area where the major part of the signal lines go through is etched away. This means that the capacitive coupling into the silicon substrate caused by these small fractions of the signal lines is very small and therefore can be neglected. This implies that an additional ground shield discussed earlier is no longer required. The simulation results depicted in Figure 5.5 show the resistive behavior of the silicon at low frequencies where the responses stay flat. At frequencies higher than the cut-off frequency, one can see the capacitive behavior of the silicon substrate. The 20 dB curve cannot be shown since the simulation data was not yet de-embedded. 72 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.2

Silicon‘s backside

p+ Silicon - Oxide - BCB

Glass AF5 Silicon‘s frontside

(a) Perspective-view

50µm x 50µm 100µm x 100µm substrate taps substrate taps connected to connected to ground line signal lines G1 G2

S1 S2 100µm G1 G2

50µm x 50µm substrate taps connected to ground line

(b) Top-view

Figure 5.4: Device #1 design. Two-port reference structure processed on a low- resistivity p-type silicon (ρ = 2−5 Ω-cm) substrate, bonded to AF-45 glass (²r = 5.2 S/m) using BCB. The substrate taps of the signal lines are 100 µm × 100 µm, while the substrate tap connected to ground lines are 50 µm × 50 µm each: (a) perspective view; (b) top-view. 5.2 TEST STRUCTURES DESIGN AND SIMULATIONS 73

−5

−10

−15

| (dB) −20 11 |S −25

−30

−35

−40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100

−120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.5: Device #1 simulated results. Two-port reference structure processed on low- resistivity p-type silicon (ρ = 2 − 5 Ω-cm), bonded to AF-45 glass (²r = 5.2 S/m) using BCB. The substrate taps of the signal lines are 100 µm × 100 µm, while the substrate tap connected to ground lines are 50 µm × 50 µm each: (a) |S11| in dB; (b) |S21| in dB. 74 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.2

5.2.2 Backside-plane isolation

The first isolation scheme implemented in this section is the backside metalization. This isolation concept is demonstrated by Device #2, Device #3, and Device #4. Figure 5.6 illustrates this particular concept with various width of ground connection. When noise is injected into the substrate, some fraction of the noise travels along the surface, while some will propagate deep into the substrate. This of course depends on several factors with one of them being operating frequency. Since the silicon thickness is considerably small, i.e. 50 µm, it is worth trying to drain the substrate noise through the backside of the silicon to the ground. However, before the substrate noise reaches the backside ground plane, it has to go through the oxide layer capacitively. The oxide layer adds impedance to the return path. Furthermore, effectiveness of the isolation provided by this scheme also depends on the impedance of the ground plane. Figure 5.7 shows simulated results of devices with different width of the connection lines to the ground plane. One can clearly see that the wider the ground connection, the better the isolation. This occurs because the backside plane impedance decreases as the width increases.

5.2.3 Air-ﬁlled through-substrate trench isolation

The second isolation scheme implemented in this section is the air-filled trench isolation scheme illustrated in Figure 5.8. In this concept, the silicon is completely removed creating silicon islands to provide complete physical isolation. This is not possible in a standard silicon technology due to mechanical integrity issue. This is, however, possible to achieve in WLP technology because spacer substrate is used as a mechanical support. The through-substrate trench, which provides DC disconnection, should give excellent isolation at low frequencies as far as substrate noise is concerned. At high frequencies, however, the signal can still propagate in a capacitive manner through the air-filled trench. Nevertheless, the capacitive propagation should be reduced proportionally to ²Air/²Si. The coupling also depends on the width of the trench. The wider the trench, the smaller the capacitance, meaning increased isolation. The simulation results depicted in Figure 5.9 show a tremendous increase in isolation at low frequencies. The effectiveness of this isolation scheme, however, decreases as the frequency becomes higher.

5.2.4 Metalized through-substrate trench isolation

The third isolation scheme implemented in this section is the metalized trench isolation scheme illustrated in Figure 5.10. In this concept, the air-ﬁlled trench described in the previous section is fully metalized and connected to ground. Figure 5.11 shows signiﬁcant improvement of the isolation at higher frequencies 5.2 TEST STRUCTURES DESIGN AND SIMULATIONS 75

Backside plane 10 µm 320 µm 320 320 µm

(a) Perspective-view (b) Top-view

50 µm 320 µm 320 320 µm 320 µm

Figure 5.6: Design of backside-plane isolation scheme with diﬀerent width of the ground connections: (a) perspective view; (a) ground connection width 10 µm for Device #2; (b) ground connection width 50 µm for Device #3; (c) ground connection width 320 µm for Device #4. 76 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.2

−5

−10

−15

| (dB) −20 11 |S −25

−30

device #2 −35 device #3 device #4 −40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100 device #2 device #3 device #4 −120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.7: Simulated results of backside-plane isolation scheme with diﬀerent width of ground connections. Ground connection width 10 µm, 50 µm and 320 µm for Device #2, Device #3 and Device #4, respectively: (a) |S11| in dB; (b) |S21| in dB. 5.2 TEST STRUCTURES DESIGN AND SIMULATIONS 77

9 0 µ m

2 0 µ m

(a) Perspective-view

Air-filled trench

(b) Top-view

Figure 5.8: Design of air-ﬁlled through-substrate trench isolation scheme implemented in Device #5. The trench creates physical separation that block the conductive path for substrate noise to travel: (a) perspective-view; (b) top-view. 78 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.2

−5

−10

−15

| (dB) −20 11 |S −25

−30

−35

−40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100

−120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.9: Simulated results of air-ﬁlled through-substrate trench isolation scheme implemented in Device #5. The trench creates physical separation that block the conductive path for substrate noise to travel. At high frequency, however, the noise can pass through the trench capacitively: (a) |S11| in dB; (b) |S21| in dB. 5.4 FABRICATION FLOW 79 as the capacitive coupling through the trench is completely suppressed. A residual capacitive coupling, however, still occurs through the space below and above the grounded metalized trench, i.e. through the glass spacer substrate and the free air, respectively. This residual coupling can further be minimized by extending the metalization (and the trench) further into the glass substrate and by controlling the width of the ground connections (i.e. ground metalization overlap of the silicon substrate slabs).

5.3 Fabrication Flow

The fabrication sequence is schematically shown in Figure 5.12. Test samples were fabricated on a low-resistivity (2–5 Ω-cm) 4-inch p-type silicon wafers. The substrate taps (ohmic contacts) were defined by ion implantation (B+ 40 keV) through a photo-resist mask. A 300 nm thermally grown SiO2 layer, a pho- tolithographic mask step to define via contacts, and a 600 nm 99% Al / 1% Si metal layer were used to complete the front-side processing (Figure 5.12a). After the completion of the front-side processing, one wafer was selected as the measurement reference, and the remaining wafers were bonded to AF-45 glass carriers 4 (εr = 6.2, tan δ = 9 x 10 ). The bonding was done using ∼10 µm-thick Benzocy- 4 clobutene (BCB: εr = 2.7, tan δ = 8 x 10 ) layer that was spun on the processed silicon wafers (Figure 5.12b). Silicon and glass wafers were brought into contact under vacuum condition and then bonded at an elevated pressure of 2 Bar. Fi- nally, BCB polymerization was carried out at 300 ◦C for 3 hours (Figure 5.12c). Afterwards, the bonded glass-silicon wafers were turned up-side down and then thinned down to ∼ 50 µm by using 33% TMAOH solution at 80 ◦C (Figure 5.12d). A 500 µm thick PECVD SixNy layer was deposited onto the exposed (back-side) silicon surface. A trench and contact pattern were then defined in that SixNy layer (Figure 5.12e). The exposed silicon was selectively removed by anisotropic wet etching in 33% TMAOH solution. The silicon separation was therefore reduced to 20 µm instead of the 90 µm mask dimension. Next, the remaining SixNy layer was removed by means of plasma etching and a 500 µm PECVD SiO2 isolation layer was deposited. Photoresist spray coating was applied in order to provide a controlled resist application over the resulting excessive wafer topography and to form well-defined contact windows to the front side metalization (Figure 5.12f) [Pha04]. Due to considerably large size of contact windows, there was no DOF (Depth of Focus) problem found. The backside metalization was formed by using 10/40 nm Ti/TiN barrier and 1.5 µm thick sputtered copper layers, an electrode- posited photoresist mask, and wet etching (Figure 5.12g). 80 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.4

Metalized trench

100 µµµm

(a) Perspective-view of Device #6: width of (b) Top-view of Device #6: width of ground ground connection is 100 µm connection is 100 µm

(c) Perspective-view of Device #7: 320 µm (d) Top-view of Device #7: 320 µm x x 320 µm plane is connected to the ground 320 µm plane is connected to the ground line line

(e) Perspective-view of Device #8: the (f) Top-view of Device #8: the backside is backside is fully metalized fully metalized

Figure 5.10: Design of metalized through-substrate trench with diﬀerent width of ground connection. The trench is now metalized and grounded. It no longer suﬀers from capacitive coupling through the trench. The noise is now drained to ground: (a) Device #6 with ground width of 100 µm (perspective-view); (b) Device #6 with ground width of 100 µm (top-view); (c) Device #7 with 320 µm x 320 µm ground plane (perspective-view); (d) Device #7 with 320 µm x 320 µm ground plane (top-view); (e) Device #8 where the backside is fully metalized (perspective-view); (f) Device #8 where the backside is fully metalized (top-view). 5.4 FABRICATION FLOW 81

−5

−10

−15

| (dB) −20 11 |S −25

−30

device #6 −35 device #7 device #8 −40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100 device #6 device #7 device #8 −120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.11: Simulated results of metalized through-substrate trench with diﬀerent width of ground connection: Device #6, Device #7, and Device #8. The trench is now metalized and grounded. It no longer suﬀers from capacitive coupling through the trench. The noise is now drained to ground: (a) |S11| in dB; (b) |S11| in dB. 82 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.4

(a) step 1: Front-side processed (b) step 2: BCB applied

(e) step 5: Silicon etched (f) step 6: Oxide removed

(g) step 7: Back-side metalization

Figure 5.12: Test structures fabrication ﬂow. Silicon substrate is thinned and bonded to glass substrate for mechanical reliability: (a) step 1: Front-side processed; (b) step 2: BCB applied; (c) step 3: Glass bonded; (d) step 4: Silicon thinned down to 50 µm; (e) step 5: Silicon etched; (f) step 6: Oxide removed; (g) step 7: Back-side metalization. 5.4 MEASUREMENT SETUP AND PROCEDURES 83

5.4 Measurement Setup and Procedures

In this section, the measurement setup used for electrical veriﬁcation is discussed. Procedures to ensure the accuracy of the measurement are also described. This is very important in order to avoid misinterpretation later on. Only when accurate data are obtained, a proper model can be built.

5.4.1 Measurement setup and calibration techniques

Figure 5.13 depicts the on-wafer measurement setup and the reference planes for calibration purposes. The measurement setup includes Vector Network Analyzer (VNA), coaxial cables, probes, and a probe station. To get the proper measurement result of the device under test (DUT)2, all possible errors should be removed. Coaxial cable calibration normally will remove all the errors to the end of coaxial cable. For on-wafer measurement, however, errors up to the probe tips need to be removed. Thus, standard calibration structures are required and standard calibration procedure needs to be followed. There are several full two-port calibration techniques available:

• Thru-Reflect-Match (LRM) • Thru-Reflect-Reflect-Match (LRRM) • Thru-Reflect-Line (TRL or LRL) • Short-Open-Load-Thru (SOLT) • Short-Open-Load-Reciprocal (SOLR)

In this work, we applied LRRM calibration technique. This LRRM calibration technique requires three standard structures, i.e. Line, Reﬂect, and Match structures. The Reﬂect structure is obtained by lifting the probes up.

5.4.2 De-embedding techniques

Figure 5.14 depicts the control device (Device #1), which is a two-port device, with four reference planes. The measurement planes are the planes where the probes landed on the contact pads. The actual DUT lies between the two reference planes. Thus, the area between measurement plane 1 and reference plane 1, as well as the area between the measurement plane 2 and reference plane 2 are considered to be errors. Figure 5.15 illustrates the block diagram of the DUT cascaded between two Error Boxes. Therefore, the errors need to be removed in order to get the actual characteristic of the DUT. 2The DUT here should be interpreted as the whole device before de-embedding. 84 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.4

(a) VNA and probe station

On-wafer On-wafer reference reference plane plane

VNA & Cabling Probe Probe VNA & Cabling DUT Errors Errors Errors Errors

Coaxial Coaxial reference reference plane plane (b) Reference planes for calibration purpose

Figure 5.13: On-wafer measurement setup and reference planes for calibration. Every- thing that is not part of the DUT must be de-embedded: (a) VNA and probe station; (b) reference planes for calibration purpose. 5.4 MEASUREMENT SETUP AND PROCEDURES 85

Measurement Measurement Plane 1 Plane 2

Device under test

Reference Reference Plane 1 Plane 2

Figure 5.14: Device #1 with error correction planes to extract DUT.

Am Bm    C m Dm 

Device Error Error a under b 1 box 1 box 2 2 [ ] 1 test 2 S1 [S ] [S ' ] 2 A B  1 1 A B  b1    ' '   2 2  a2 C1 D1  A B   C2 D2  C ' D' 

Measurement Reference Reference Measurement plane for plane for plane for plane for port 1 device port 1 device port 2 port 2

Figure 5.15: Block diagram of measurement of two-port network. Error boxes must be de-embedded. 86 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.4

For this purpose, we need to apply a de-embedding technique. In principle, de- embedding is the same as calibration where the initial measurement needs to be corrected by removing the errors. Similar to calibration procedure, de-embedding also uses some standard structure. Here, we applied Thru-Reflect-Line (TRL) de- embedding technique [Eng79]. TRL uses three different standard, namely Thru, Reflect, and Line. We can use signal flow graphs from three standards available and derive a set of equations to find the S-parameters of the Error Boxes by applying the TRL de-embedding procedure. Here, we need to make several valid assumptions for simplicity reason. The first assumption is that port 1 and port 2 have the same characteristic impedance. The second assumption is that the Error Boxes are reciprocal and identical for both ports. The Error Boxes are characterized by S-matrix [S], and alternatively by the ABCD matrix. Since the error boxes are reciprocal, S21 = S12 applies to both Error Boxes. Also, since both ports are identical, S11 of Error Box 1 [S1] is the same as S22 of Error Box 2 [S2], and vice versa. These conditions can be better described by the following matrix equations:

· ¸ · ¸ S11 S12 S11 S12 S1 = = (5.5) S21 S22 S12 S22

thus, S-parameters of Error Box 2 can be deﬁned as:

· ¸ S22 S12 S2 = (5.6) S12 S11

Alternatively, the Error Box 1 can be represented by ABCD matrix such as: · ¸ · ¸ A B AB 1 1 = (5.7) C1 D1 CD

hence, the Error Box 2 is represented by ABCD matrix such as:

· ¸ · ¸ A B DB 2 2 = (5.8) C2 D2 CA

Therefore, the ABCD matrix of the complete device shown in Figure 5.15 can be formed by cascading the ABCD matrices of the Error Box 1 and 2 with DUT in the middle as described by the following matrix equation:

· ¸ · ¸ · 0 0 ¸ · ¸ Am Bm AB A B DB = 0 0 (5.9) Cm Dm CB C D CA 5.4 MEASUREMENT SETUP AND PROCEDURES 87

To avoid confusions in notations, the S-parameters of Thru, Reﬂect, and Line are denoted as [T], [R], and [L], respectively. Thru structure is formed by physically removing the DUT from the complete system illustrated in Figure 5.15 and connecting Error Box 1 and Error Box 2. Figure 5.16 depicts the block diagram and signal ﬂow graph of the network built up by the Thru structure.

[T ]

a Error Error b 1 box 1 box 2 2 [ ] 1 2 S1 [ ] S2 A B  1 1 A B  b1    2 2  a2 C1 D1  C2 D2 

Reference planes for DUT

S12 1 S12 a1 b2

S11 S22 S22 S11 b1 a2 S12 1 S12

Figure 5.16: Block diagram and signal ﬂow graph of Thru network.

From signal ﬂow graph in Figure 5.16, we can derive Eq. 5.10 and Eq. 5.11.

¯ ¯ 2 b1 ¯ S22 S12 T11 = ¯ = S11 + 2 (5.10) a1 1 − S ¯a2=0 22 b ¯ S2 T = 1 ¯ = 12 (5.11) 12 a ¯ 1 − S2 2 a1=0 22

Reflection structure is formed by creating an Open structure. This can be realized by simply removing the DUT from the whole system illustrated in Fig- ure 5.15 and keep the Error Boxes separated at the same distance. Figure 5.17 depicts the Reflect structure block diagram and shows the signal flow graph. From 88 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.4

[R]

a Error Error b 1 box 1 box 2 2 [ ] S1 R R [ ] S2 A B  1 1 A B  b1    2 2  a2 C1 D1  C2 D2 

1 2 Reference planes for DUT

S12 S12 a1 b2

S11 S22 R R S22 S11 b1 a2 S12 S12

Figure 5.17: Block diagram and signal ﬂow graph of Reﬂect network.

Figure 5.17, it is clear that a perfect isolation between Error Box 1 and Error Box 2 is taken as an assumption. From Reﬂect signal ﬂow graph, we can derive Eq. 5.12:

¯ b ¯ S2 Γ R = 1 ¯ = S + 12 L (5.12) 11 a ¯ 11 1 − S Γ 1 a2=0 22 L

Lastly, Line structure can be formed by replacing the DUT from the whole system illustrated in Figure 5.15 with a length of matched transmission line. It is not necessary to know the length of the transmission line and it does not to be lossless. All these parameters will be defined in the TRL procedure. Figure 5.18 depicts the block diagram and signal flow graph of Line structure. From the signal flow graph depicted in Figure 5.18, we can derive Eq. 5.13 and Eq. 5.14. 5.4 MEASUREMENT SETUP AND PROCEDURES 89

[L]

a Error Error b 1 box 1 box 2 2 [ ] 1 -γl 2 S1 Z , e [ ] 0 S2 A B  1 1 A B  b1    2 2  a2 C1 D1  C2 D2 

Reference planes for DUT

-γl S12 e S12 a1 b2

S11 S22 S22 S11 b1 a2 -γl S12 e S12

Figure 5.18: Block diagram and signal ﬂow graph of Line network.

¯ ¯ 2 −2γl b1 ¯ S22 S12 e L11 = ¯ = S11 + 2 −2γl (5.13) a1 1 − S22 e ¯a2=0 b ¯ S2 e−γl L = 1 ¯ = 12 (5.14) 12 a ¯ 1 − S2 e−2γl 2 a1=0 22

Eq. 5.10 -5.14 shows that we have ﬁve equations with ﬁve unknowns S11, S12, −γl S22,ΓL, and e . We will begin by eliminating S12 in Eq. 5.10 and Eq. 5.13 using Eq. 5.11. Re-arranging Eq. 5.11 we have:

2 2 S12 = T12(1 − S22)

S12 can then be substituted into Eq. 5.10, Eq. 5.13, Eq. 5.14 and which gives us:

T11 = S11 + S22T12 (5.15)

and 90 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.4

2 −2γl S22T12(1 − S22)e L11 = S11 + 2 −2γl (5.16) 1 − S22e 2 −γl T12(1 − S22)e L12 = 2 −2γl (5.17) 1 − S22e

S11 can then be eliminated from Eq. 5.15 and Eq. 5.16, which gives us:

−2γl ¡ 2 2 ¢ e −L11S22 + T11S22 − S22T12 = T11 − L11 − S22T12 (5.18) Eq. 5.17 can be re-arranged as follows:

−2γl ¡ 2 ¢ −γl ¡ 2 ¢ e L12S22 − e T12 − T12S22 = L12 (5.19)

Eq. 5.19 can now be solved for S22 and substituted into Eq. 5.18 and form a quadratic equation for e−γl. The quadratic equation can then be solved in terms of the measured TRL S-parameters: r ³ ´2 2 2 2 2 2 2 2 2 L12 + T12 − (T11 − L11) ± L12 + T12 − (T11 − L11) − 4L12T12 e−γl = 2L12T12 (5.20)

The root that has to be taken from Eq. 5.20 is the one that gives positive real ◦ part and imaginary part of γ, or by knowing the the phase Γl to within 180 . Next,¡ we can extract¢ the S-parameters of the Error box by multiplying Eq. 5.17 2 −2γl by 1 − S22e and substrate from Eq. 5.16 to get:

−γl L11 = S11 + S22L12e (5.21)

−γl Combining Eq. 5.21 and Eq. 5.15 to eliminate S11 gives us S22 in terms of e as:

T11 − L11 S22 = −2γl (5.22) T12 − L12e

Substituting the S22 into Eq. 5.15 gives:

S11 = T11 − S22T12 (5.23) and similarly solving Eq. 5.11 gives:

2 ¡ 2 ¢ S12 = T12 1 − S22 (5.24) 5.5 EXPERIMENTAL VERIFICATION 91

Finally, Eq. 5.12 can be solved for ΓL as follows:

R11 − S11 ΓL = 2 (5.25) S12 + S22 (R11 − S11) The S-parameters of the Error box 1 and Error box 2 can then be arranged according to Eq. 5.5 and Eq. 5.6, respectively. Finally, the ABCD matrix of the DUT can be derived from the matrix equation in Eq. 5.9:

· 0 0 ¸ · ¸−1 · ¸ · ¸−1 A B AB Am Bm DB 0 0 = (5.26) C D CB Cm Dm CA

5.5 Experimental Veriﬁcation

The S-parameter measurements were carried out using HP8510c network analyzer within the frequency range from 50 MHz to 40 GHz. G-S-G picoprobes with 200 µm pitch were used. LRRM calibration procedure was applied to characterize the devices. In this section, the simulation results of fabricated structures are compared to raw measurement results (before de-embedding). Figure 5.19 depicts the processed control device and compares the measured and simulated S-parameters of the control device (Device #1). The simulated data fits quite well to the measurement. In Chapter 2, it is described that silicon substrate behaves conductively at low frequencies and capacitively at high frequencies. The response depicted in Figure 5.20 resembles these two kinds of behavior. Both in the simulated as well as measured curves, one can clearly see the resistive behavior of the silicon substrate at low frequencies and capacitive behavior at high frequencies. In logarithmic scale, the |S21| response is continuously flat, i.e. resistive behavior until it approaches the cut-off frequency and goes up at high frequencies, i.e. capacitive behavior. The DC isolation (∼ 20 dB) is provided by the silicon substrate resistivity which is 2-5 Ω-cm, while the RF 3 isolation depends on the silicon substrate dielectric constant (εr). The impact of different resistivity on the isolation can be found in Chapter 3. The first isolation scheme implemented in this section is backside-plane isolation, which is shown in Figure 5.21. The isolation structure as well as simulated and measured S-parameters are depicted in Figure 5.22. One can see that the measured result clearly deviates from the simulation. The measured response, however, qualitatively behaves the same way. This deviation occurs due to the difference between process technology outcome and the simulated model. For example, the backside plane is considerable very large, covering almost the whole backside. This backside-plane introduces large capacitance to

3The interconnect parasitics also impacts the isolation. 92 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.5

(a) Front view

(b) Back view

Figure 5.19: Processed control device as the reference without any isolation scheme implemented with the comparison between simulated vs. measured S-parameters in dB: (a) front-view; (b) back-view. 5.5 EXPERIMENTAL VERIFICATION 93

−5

−10

−15

| (dB) −20 11 |S −25

−30

−35 simulated measured −40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100 simulated measured −120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.20: Comparison between simulated vs. measured S-parameters of processed control device as the reference without any isolation scheme implemented: (a) |S11| in dB; (b) |S21| in dB. 94 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.5

(a) Front view

(b) Back view

Figure 5.21: Backside-plane isolation scheme with 50 µm-wide ground connections: (a) top-view; (b) back-view. 5.5 EXPERIMENTAL VERIFICATION 95

−5

−10

−15

| (dB) −20 11 |S −25

−30

−35 simulated measured −40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100 simulated measured −120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.22: Simulated vs. measured of device with backside-plane isolation: (a) |S11| in dB; (b) |S21| in dB. 96 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6 the substrate. As it is very difficult, though possible, to measure the exact oxide thickness underneath the backside plane, it is also cumbersome to model a very thin substrate in the 3D EM simulation, which would increase complexity. The second isolation scheme implemented, which we propose, is the air-filled through-substrate trench isolation. Figure 5.23 depicts the processed structure and the comparison between the measured and simulated S-parameters. The silicon substrate is completely removed creating two silicon islands, which provides excellent physical substrate isolation. Figure 5.24 depicts the simulated and measured result of the air-filled through-substrate trench isolation. Again, Figure 5.24 shows small deviations between the simulated and measured results. However, both the simulated and measured results qualitatively show the same response. At low frequencies, extremely high isolation is achieved due the physical substrate separation explained earlier. This, however, does not stay long as the frequency increases. The capacitive coupling through the trench becomes more apparent at high frequencies, which reduces the isolation. It can be noted as a weakness of this approach. The aforementioned isolation scheme, i.e. air-filled through substrate trench, loses its effectiveness as the frequency goes higher due to the capacitive coupling through the air-filled trench. As a solution to this drawback, we propose to combine the backside-plane isolation together with the air-filled through substrate trench isolation. As a result, we came up with metalized through-substrate trench. This particular isolation structure is depicted in Figure 5.25. The idea behind this technique is to drain the substrate noise that couples capacitively to the ground. Figure 5.26 depicts the simulated and measured results of the metalized through-substrate trench isolation structure. When compared to Device #1 (control device), the metalized through-substrate trench isolation provides ∼60 dB suppression at 50 MHz and ∼20 dB suppression at 40 GHz. Although ∼20 dB suppression at 40 GHz is quite an achievement, one would question why the isolation level degrades at high frequencies. This is due to imperfect return path impedance which in this case is the backside metalization as explained in the early section. In other words, when the impedance of the backside metal can be reduced, the suppression achieved will be higher. As the backside metal can only be widened to a certain extent, one can increase the thickness of the backside metal to reduce the impedance.

5.6 Lumped Model Development and Analysis

In the early sections, it was shown that substrate noise can really deteriorate the circuit performance. While computing the substrate noise using device simulator would generally require excessive computing times, it is practically possible to model the substrate with lumped element network that can easily be embedded 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 97

(a) Front-view

(b) Back-view

Figure 5.23: Air-ﬁlled through-substrate trench isolation scheme implemented in Device #5. The trench creates silicon islands that provides physical separation between two ports. Thus, conductive path through the substrate is no longer available: (a) front-view; (b) back-view. 98 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

−5

−10

−15

| (dB) −20 11 |S −25

−30

−35 simulated measured −40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100 simulated measured −120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.24: Simulated vs. measured of device with air-ﬁlled through-substrate trench isolation: (a) |S11| in dB; (b) |S21| in dB. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 99

(a) Front-view

(b) Back-view device

Figure 5.25: Metalized through-substrate trench with diﬀerent width of ground connection. The trench is now metalized and grounded. Thus, the device no longer suﬀers from capacitive coupling through the trench: (a) front-view; (b) back-view. 100 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

−5

−10

−15

| (dB) −20 11 |S −25

−30

−35 simulated measured −40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100 simulated measured −120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.26: Simulated vs. measured of device with metalized through-substrate trench with diﬀerent width of ground connection: (a) |S11| in dB; |S21| in dB. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 101 into the circuit simulation. In this work, all the devices that have been designed, simulated and fabricated are two-port devices. In this section, therefore, two-port lumped element PI network is used to model the devices as shown in Figure 5.27. Y1 and Y2 can be obtained

Y1 Port 2Port

Y2 Y2 Port 1

Figure 5.27: PI topology of two-port network. from the measured Y-parameters based on the following formulas

Y1 = −Y12 (5.27)

Y2 = Y11 + Y12 (5.28) where Y12 = Y 21 and Y 11 = Y22 since it is a symmetric two-port device. Y1 and Y2 can then be fed into the curve-fitting procedure developed by Levy [Lev]. This curve-fitting technique is based on rational polynomial equation. Furthermore, the values obtained from this procedure can then be fed into Advanced Design System (ADS) optimization tool to get the best fit. In this section, different topologies are explored for each device in order to get the best fit. All topologies follows the general two-port PI-network topology, though.

5.6.1 Control device

In this section, circuit topologies for the control device (Device #1) are discussed. Figures 5.28, 5.30, and 5.32 depict the circuit topologies that model the control device, in which there is no isolation structure implemented. Figure 5.29 depicts S-parameter responses modeled by two-port PI network following circuit topology #1. One can see clearly that the simulated lumped model ﬁts reasonably well to the measured S-parameters. There are, however, very small discrepancies found between the simulated and measured S-parameters. When we refer to Fig- ure 5.14, the DUT still includes some portions of the ground line. This ground line, however, was not de-embedded from the measurement of the overal device. 102 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

Yet, Figure 5.28 only models the silicon substrate that is connected to the ground without ground impedance. We believe that this is responsible for the discrepancies between the simulated and measured S-parameter as shown in Figure 5.29a and 5.29b. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 103

Port 2 Ω Ω Ω ΩΩ Ω ΩΩ 415.48 415.48 226.54 226.54 111.92 fF 111.92 Ω Ω ΩΩ 26.86 fF 26.86 814.58 814.58 Ω Ω ΩΩ Control device: topology #1. 65.3 65.3 Ω Ω ΩΩ Figure 5.28: 415.48 415.48 Ω Ω ΩΩ

226.54 226.54 111.92 fF 111.92 Port 1 Port 104 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

−5

−10

−15

| (dB) −20 11 |S −25

−30

−35 simulated measured −40 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(a) |S11| (dB) response

−20

−40

| (dB) −60 21 |S

−80

−100 simulated measured −120 −2 −1 0 1 2 10 10 10 10 10 Frequency (GHz)

(b) |S21| (dB) response

Figure 5.29: Control device: curve-ﬁtted S-parameters based on circuit topology #1: (a) |S11| in dB; (b) |S21| in dB.

Figure 5.30 depicts the second circuit topology to model the control device. One can clearly see that in Figure 5.30 the ground impedance is introduced. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 105

Here, the ground interconnect is modeled with a symmetric RL network with a capacitance in the middle connected to ground. This capacitance models the distributed capacitance of the ground interconnect to the ultimate grounding point. The simulated S-parameters depicted in Figure 5.31 fit really well to the measured S-parameters. In other words, the discrepancies shown by circuit topology #1 (see Figure 5.28) no longer exists. Let us, again, look at the control device in Figure 5.14. Port 1 and Port 2 are actually not only coupled through the silicon substrate, but also through the glass substrate. As it is very difficult to separate the coupling originated from two different paths, nevertheless, we tried to accommodate this by adding a capacitor to model the capacitive coupling through the glass substrate. Figure 5.32 depicts circuit topology #3 where a capacitor is introduced in the model. Figure 5.33 shows the comparison between the simulated and measured results. Except for the glass substrate capacitance, topology #2 and #3 show the same value of all the parameters while the glass substrate capacitance value obtained is negligibly small, which is around 3 × 10−8 fF. 106 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

Port 2 Ω Ω ΩΩ Ω Ω ΩΩ Ω Ω Ω ΩΩ Ω ΩΩ 324.12 32.02 0.16 nH 0.16 nH 79.55 79.55 Ω Ω ΩΩ 3 2x10 57.75 fF 53.28 fF 2.09 pF Ω Ω ΩΩ Ω Ω ΩΩ 566.21 Ω Ω ΩΩ 324.12 2.09 pF 32.02 Control device: curve-ﬁtted S-parameters based on circuit topology #2. Ω Ω Ω ΩΩ Ω ΩΩ 0.16 nH 0.16 nH 79.55 79.55 Figure 5.30:

57.75 fF Port 1 Port 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 107

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Figure 5.31: Control device: curve-ﬁtted S-parameters based on circuit topology #2: (a) |S11| in dB; (b) |S21| in dB. 108 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

Port 2 Ω Ω ΩΩ Ω Ω Ω ΩΩ Ω ΩΩ Ω Ω ΩΩ 324.12 0.16 nH 0.16 nH 79.55 79.55 32.02 Ω Ω ΩΩ 3 fF 2x10 57.75 fF 53.28 fF -8 2.09 pF Ω Ω ΩΩ 3.15x10 Ω Ω ΩΩ 566.21 Ω Ω ΩΩ 324.12 2.09 pF 32.02 Control device: curve-ﬁtted S-parameters based on circuit topology #3. Ω Ω Ω ΩΩ Ω ΩΩ 0.16 nH 79.55 0.16 nH 79.55

57.75 fF Figure 5.32: Port 1 Port 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 109

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Figure 5.33: Control device: curve-ﬁtted S-parameters based on circuit topology #3: (a) |S11| in dB; (b) |S21| in dB. 110 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

5.6.2 Backside-plane isolation

As discussed earlier, the first isolation scheme we implemented is the backside- plane isolation. This was done by metalizing the backside of the silicon substrate, as depicted in Figure 5.21. It was mentioned in the early section that the idea behind this isolation scheme was to drain the substrate current through the silicon substrate to the grounded backside metal. Figure 5.34 depicts the first topology implemented for this isolation scheme, which is the same is topology #2 for the control device. The simulated S- parameters shown in Figures 5.35a and 5.35b suggest that this topology is not suitable as the |S21| shows a resonating behavior. This is due to the thin layer of silicon oxide between the silicon substrate and the backside metal. Therefore, topology that can introduce resonance should be considered instead. In other words, a capacitor has to be placed in between the substrate circuit model and the backside metal return path. Figure 5.36 depicts the second topology proposed for this isolation scheme as well as the comparison between the simulated and measured S-parameters. In topology #2, a capacitor as big as 0.12 pF is placed to model the silicon oxide layer between the silicon substrate and the backside metal. One can see clearly that the S-parameters obtained from topology #2 fits better to the measurement than the ones obtained from topology #1. Figure 5.37b already shows resonance similar to the one shown in the measurement. When we analyze Figure 5.37b carefully, however, the simulated results fits better to the measurement at high frequencies than at low frequency. As current always goes through the shortest path4, this indication suggests that current mainly goes through the ohmic contacts underneath the side ground metal rather than through the backside metal. In other words, the substrate current is drained out to the ground through two possible paths5. The substrate current may take the path directly to the side ground metal through the ohmic contact, but may also take the path through the silicon oxide and then to the backside metal. Therefore, a circuit topology that offers these two possible path should be considered in order to improve the fitting. This brings us to circuit topology #3, which is depicted in Figure 5.38. Topol- ogy #3 provides two paths for the current to reach the ground. One can clearly see that the simulated S-parameters fits better to the measurement when compared to the two previous topologies.

4Shortest path is the path with the least impedance. 5From the lumped element perspective, the current itself , however, ﬂows in a distributed way. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 111

Port 2 Ω Ω ΩΩ Ω Ω ΩΩ 158.33 14.32 Ω Ω Ω ΩΩ Ω ΩΩ Ω Ω ΩΩ 2.67 0.26 pH 0.26 pH 2.67 3 0.27 pF 1.24 pF 4.83x10 1.51 pF Ω Ω ΩΩ Ω Ω ΩΩ 3 Ω Ω ΩΩ 158.33 2.62x10 1.51 pF 14.32 Ω Ω Ω ΩΩ Ω ΩΩ Backside-plane isolation: curve-ﬁtted S-parameters based on circuit topology #1. 2.67 0.26 pH 0.26 pH 2.67

0.27 pF

Figure 5.34: Port 1 Port 112 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

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Figure 5.35: Backside-plane isolation: curve-ﬁtted S-parameters based on circuit topology #1: (a) |S11| in dB; (b) |S21| in dB. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 113

Port 2 Ω Ω ΩΩ 2.29 pF 128.47 0.16 pF Ω Ω ΩΩ Ω Ω ΩΩ Ω Ω ΩΩ 3 93.81 0.12 pF 0.27 46.62 pH 1.16 pF Ω Ω ΩΩ 2.87x10 Ω Ω ΩΩ 0.27 6 Ω Ω ΩΩ 2.29 pF 46.62 pH 10x10 128.47 Ω Ω ΩΩ Backside-plane isolation: curve-ﬁtted S-parameters based on circuit topology #2.

93.81 Port 1 Port Figure 5.36: 114 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

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Figure 5.37: Backside-plane isolation: curve-ﬁtted S-parameters based on circuit topology #2: (a) |S11| in dB; (b) |S21| in dB. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 115

Port 2 Ω Ω ΩΩ 0.93 pF 124.46 0.18 pF Ω Ω ΩΩ Ω Ω ΩΩ 50 pH Ω Ω ΩΩ 46.09 924 Ω Ω ΩΩ 3.87 pF -8 94.05 Ω Ω ΩΩ 6 0.93 pF Ω Ω ΩΩ 5.02x10 10x10 0.67 11.05 pF 45.81 pH Ω Ω ΩΩ Ω Ω ΩΩ 124.46 46.09

Backside-plane isolation: curve-ﬁtted S-parameters based on circuit topology #3. Port 1 Port Figure 5.38: 116 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

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Figure 5.38: Backside-plane isolation: curve-ﬁtted S-parameters based on circuit topology #3: (a) |S11| in dB; (b) |S21| in dB. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 117

5.6.3 Air-ﬁlled through-substrate trench isolation

The second isolation scheme, which is the first one we propose in this work, is the air-filled through substrate trench isolation. As mentioned earlier, the through- substrate trench creates silicon islands that are physically disconnected from each other (see Figures 5.23a and 5.23b). Thus, the only possible coupling is the capacitive coupling through the air and the glass substrate. In the processed device, however, the two silicon islands are still connected through the side ground lines. Figure 5.39 depicts the circuit topology proposed this isolation scheme, while Fig- ure 5.40 shows the comparison between simulated and measured S-parameters. One can see clearly that the ports are connected by a 9.27 fF capacitor that models the capacitive coupling through the air. The two ports, however, take the same connection to the ground reference. From the S-parameters shown in Fig- ure 5.40, one can see that there is still significant amount of capacitive coupling between the two ports. The isolation eventually deteriorates at higher frequencies. This makes the air-filled substrate-trough trench isolation not suitable for high-frequency application. 118 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

Port 2 Ω Ω ΩΩ 55.83 Ω Ω ΩΩ 0.31 pF 225.62 0.03 fF Ω Ω ΩΩ Ω Ω Ω ΩΩ Ω ΩΩ 9.27 fF -9 -9 55.83 41.44 pH 41.44 pH 1.96x10 1.96x10 Ω Ω ΩΩ

225.62

0.03 fF Port 1 Port Air-ﬁlled through-substrate trench isolation: curve-ﬁtted S-parameters based on circuit topology #1. Figure 5.39: 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 119

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Figure 5.40: Air-ﬁlled through-substrate trench isolation: curve-ﬁtted S-parameters based on circuit topology #1: (a) |S11| in dB; (b) |S21| in dB. 120 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

5.6.4 Metalized through-substrate trench isolation

In the second isolation scheme (air-filled through-substrate isolation), it was described that the coupling is originated from the capacitive coupling through the air, which eventually deteriorated the isolation at higher frequencies. While the first isolation scheme (backside-plane isolation) offers a technique that drains the substrate current to ground, it can also be combined with the second isolation scheme. That brings us to the last isolation scheme proposed in this work. The substrate current can be drained to the ground to avoid capacitive coupling. This isolation scheme is called metalized through-substrate trench isolation which is illustrated in Figure 5.10, while the processed device is depicted in Figure 5.25. Figure 5.41 depicts the first circuit topology to model the metalized through- substrate trench isolation. It is clearly depicted in Figure 5.41 that there is no longer direct connection between Port1 and Port2. Instead, they are connected through the trench metalization. From Figure 5.42a and Figure 5.42b, one can see that the simulated S-parameters fit better to the measured S-parameters at high frequencies rather than at low frequencies. This discrepancy originates from the ground connection model. The resistance plays a major role at low frequencies, while the inductance plays a major role at high frequencies. As depicted by topology #1, the ground connection is modeled by one segment T-network. The current injected by Port 1 into the substrate reaches the ground connection through various paths, which is currently not modeled in topology #1. Topology #2 for the metalized substrate-through trench isolation is depicted in Figure 5.43. Topology #2 models the metalized area of the trench and ground connection separately. In other words, topology #2 models the overall ground connection with several segments of lumped circuits. Figure 5.44a and Figure 5.44b show that the simulated S-parameters fit better to the measured S-parameters when compared to topology #1 at low and high frequencies. Topology #3 models the ground connection with even higher number of segments as depicted in Figure 5.45. The results shown in Figure 5.45 is visually just as good as the one provided by topology #2. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 121

Port 2 Ω Ω ΩΩ 24.20 0.77 pF Ω Ω ΩΩ 127.36 Ω Ω Ω ΩΩ Ω ΩΩ -12 -12 12.10 pH 12.10 pH 0.001 fF 0.001 fF 11.50x10 11.50x10 Ω Ω ΩΩ Ω Ω ΩΩ 24.20

127.36

Metalized through-substrate trench isolation: curve-ﬁtted S-parameters based on circuit topology #1. Port 1 Port Figure 5.41: 122 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

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Figure 5.42: Metalized through-substrate trench isolation: curve-ﬁtted S-parameters based on circuit topology #1: (a) |S11| in dB; (b) |S21| in dB. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 123 Ω Ω ΩΩ 0.21 fF 0.21 16.84 16.84 Ω Ω ΩΩ -9 Ω Ω ΩΩ 8.72x10 Ω Ω ΩΩ 0.09 0.09 -9 5.89 pF 5.89 4.06x10 8.10 pF 8.10 Ω Ω ΩΩ H Ω Ω ΩΩ -9 -6 -9 5.03 nH 5.03 5.73x10 Ω Ω Ω ΩΩ Ω ΩΩ 8.77x10 4.39x10 -9 -9 Ω Ω ΩΩ 1.22 pH 1.22 pH 1.22 -9 2.73x10 2.73x10 5.03 nH 5.03 5.89 pF 5.89 0.21 fF 0.21 4.06x10 Ω Ω ΩΩ -9 Ω Ω ΩΩ Metalized through-substrate trench isolation: curve-ﬁtted S-parameters based on circuit topology #2. 8.72x10 Ω Ω ΩΩ 16.84 16.84 0.09 0.09 Figure 5.43: 124 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.6

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Figure 5.44: Metalized through-substrate trench isolation: curve-ﬁtted S-parameters based on circuit topology #2: (a) |S11| in dB; (b) |S21| in dB. 5.6 LUMPED MODEL DEVELOPMENT AND ANALYSIS 125 Ω Ω ΩΩ 0.18 fF 0.18 16.92 16.92 Ω Ω ΩΩ -9 Ω Ω ΩΩ -9 Ω Ω ΩΩ 9.11x10 H Ω Ω ΩΩ -9 0.006 0.006 -9 91.14x10 8.85 pF 8.85 0.4x10 8.10 pF 8.10 H -6 Ω Ω ΩΩ H -9 -9 Ω Ω ΩΩ -9 8.77x10 H H Ω Ω Ω ΩΩ Ω ΩΩ 0.29x10 -9 -9 -12 -12 110.30x10 H 4.75x10 2.95x10 -9 0.67x10 0.67x10 Ω Ω ΩΩ 1.22x10 1.22x10 Ω Ω ΩΩ -9 -9 4.75x10 8.85 pF 8.85 0.18 fF 0.18 Ω Ω ΩΩ -9 0.4x10 91.14x10 Ω Ω ΩΩ 9.11x10 Metalized through-substrate trench isolation: curve-ﬁtted S-parameters based on circuit topology #3. Ω Ω ΩΩ 16.92 16.92 0.006 0.006 Figure 5.45: 126 METALIZED THROUGH-SUBSTRATE TRENCH APPROACH 5.7

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Figure 5.46: Metalized through-substrate trench isolation: curve-ﬁtted S-parameters based on circuit topology #3: (a) |S11| in dB; (b) |S21| in dB. 5.7 SUMMARY 127

5.7 Summary

The experiments described in this chapter proved that through-substrate trench isolation structures can be realized using wafer-level packaging technology. The procedure used is based on a thick low-loss spacer substrate, such as HRPS and glass, and guarantees high degree of mechanical reliability. Backside-plane isolation scheme has been successfully implemented in simulation and experiment. Both simulation and measurement results show that the backside-plane can introduce resonance, which makes it less suitable for practical applications.

Air-filled through-substrate trench creates silicon islands that provide physical separation between the aggressor and the victim. Thus, there is no electrical connection through the substrate at low frequencies. Simulation and measurement results confirm that the isolation achieved is very high at low frequencies. This isolation scheme, however, suffers from the capacitive coupling at high frequencies.

To suppress the substrate crosstalk at high frequencies, we introduced the backside-metalization resulting in the metalized through-substrate trench isolation scheme. The backside-metalization draws the substrate current to ground and limits the capacitive coupling observed for the air-filled trench isolation scheme. The simulation and measurement results show that the isolation levels are greatly improved. The substrate with or without isolation structures described above are modeled by lumped element equivalent circuit. The synthesis of the equivalent circuit was based on the PI-network defined by Y-parameters. The value of the components in the Y-parameter were obtained through curve-fitting procedure. Different topologies for different cases were investigated.

The initial aim of this work was actually to develop scalable equivalent circuit, where the component values can be scaled based on parameters like size, distance, and etc. Unfortunately, there were not enough samples to proceed with the initial plan. Nevertheless, the results thoroughly discussed above give very good insight on how to develop such circuit.

Chapter 6 Conclusions, Recommendations and Future Works

6.1 Conclusions

The integration of noisy digital circuits and sensitive analog/RF circuit on a single silicon chip does not come without any drawbacks. Substrate noise has been proven to be a major cause to the deterioration of the entire system-on- chip (SoC). Not only is the substrate noise captured directly by the devices, e.g. diodes, transistors and resistors, but also through the on-chip interconnects and bondwires. In this thesis, various kinds of isolation scheme were described. Some isolation schemes are part of the CMOS technology, some are implemented by means of post-processing. With the emerging demand for wafer-level packaging technology, where cost can be reduced and end-product, i.e. packaged die whose scale is just as big as the die itself can be achieved, new substrate noise suppression techniques have been introduced and demonstrated in this thesis. In order to get accurate simulation results, thus, the substrate eﬀect as well as the isolation structure to be employed have to be then taken into account by means of a lumped element equivalent circuit. Lumped element equivalent circuits can easily be attached to the circuit schematic in the circuit simulator. The simulation results in Chapter 3 conﬁrm that silicon substrate can be modeled by RC network due to its conductive behavior and capacitive behavior at low frequencies and high frequencies, respectively. On the other hand, spacer substrate like glass can be modeled with a capacitor only since it barely introduces any resistive loss.

129 130 CONCLUSIONS, RECOMMENDATIONS AND FUTURE WORKS 6.1

Spacer substrate plays major role in WLP technology, therefore, it has to be properly characterized. Chapter 4 describes high-frequency characterization thoroughly. High-resistivity polysilicon and glass substrates have been characterized to obtained the dielectric permittivity and substrate loss. From the substrate loss introduced by the two substrates, glass substrate is proven to be superior over the high-resistivity silicon. This is an important factor, particularly to achieved high-Q factor passive devices. As for the dielectric permittivity, higher dielectric permittivity means higher capacitive coupling, thus stronger capacitive coupling. However, higher dielectric permittivity also means reduced physical size of the structure. Thus, higher density of the circuit can be achieved. Therefore, proper choice has to be made prior to the substrate selection.

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Figure 6.1: Isolations achieved by diﬀerent devices.

Figure 6.1 depicts the isolations (|S21|) achieved by the control and different isolation schemes. The measured |S21| of the control device showed flat response in logarithmic scale at low frequencies, which suggests the conductive behavior of the silicon substrate. At high frequencies, the silicon substrate behaves capacitively which, was shown by the 20 dB/dec slope. Through-substrate trench isolation technique has been successfully implemented by means of wafer-level packaging technology. The measurement data showed that air-filled through-substrate isolation technique increased the isolation by ∼ 55 dB, ∼ 10 dB, and ∼ 2 dB at 50 MHz, 10 GHz, and 40 GHz, respectively. The isolation significantly deteriorates at high frequencies due to the capacitive coupling through the air-filled trench. Depending on the operating frequency, one might 6.2 CONCLUSIONS 131

find the air-filled through-substrate trench isolation technique sufficiently effective. For high-frequency and high-speed application, however, this may not be sufficient to suppress the substrate noise. The crosstalk through the air-filled through-substrate trench can be suppressed by metallizing the trench and eventually grounding it. The measurement data showed that grounded metalized through-substrate trench increases the isolation ∼ 62 dB, ∼ 33 dB, and ∼ 22 dB at 50 MHz, 10 GHz, and 40 GHz, respectively, with respect to the control device. The grounded metalized through-substrate trench improves the isolation by ∼ 23 dB, and ∼ 22 dB at 10 GHz and 40 GHz, respectively, with respect to the air-filled through-substrate trench. This is a significant improvement. The substrate as well as the isolation structure have to be modeled in order to take the effect into account. Lumped element equivalent circuit model is very suitable in terms of integration in the circuit simulation tools. In principle, the model used should be scalable models. We were unable to develop scalable model due to an insufficient number of samples. The equivalent circuit models that have been developed in this work, however, give us excellent insight on choosing the right topologies. The simulation results show that control device which basically consists of a uniform silicon substrate only can be modeled using resistors and capacitors to build RC network. The ground metal connection, hence, can be modeled by resistors and inductors. The glass substrate can then be modeled by capacitor only. The capacitive coupling through the glass substrate is negligible, thus, can be omitted. The backside metalization isolation structure can be modeled by RC and RLC networks, for the silicon and backside metal, respectively. The capacitor in latter part is to model the oxide between the silicon substrate and the backside metal. The simulation result obtained from topology #3 (Figure 5.38) shows very good fit. Air-filled through-substrate trench structure requires RC network to model the silicon substrate and a capacitor to model the capacitive coupling through the air. The simulation result depicted in Figure 5.39 show a very good fit to the measured data. The grounded metalized through-substrate trench can be best modeled by dividing it into multiple sections such as the silicon substrate, the metal trench on top, vertical section of the trench that is located between the two ports, and the trench on the backside of the silicon substrate. This topology is shown by the topology #3 depicted in Figure 5.45. This simulated result show very good fit to the measured data. 132 CONCLUSIONS, RECOMMENDATIONS AND FUTURE WORKS 6.2

6.2 Recommendations and Future Works

It is absolutely interesting to implement the grounded metalized through-substrate trench in a real circuit. The circuit consists of the agressor, e.g. inverter, and the victim, e.g. LNA. The isolation provided by grounded metalized through-substrate trench can still be improved. In the current design, there is a thin-layer of oxide between the backside metal and the silicon substrate. The oxide provides capacitive path for the substrate noise to ﬂow to the ground. An extra mask and step to create ohmic contacts will provide resistive path for the substrate noise to be drained to ground. Also, development of scalable model is a very interesting topic to investigate. Using scalable model, optimum parameters, i.e. distance, thickness and width can be ﬁgured out in order to achieve higher isolation level. Other future work we propose is to further explore the wafer-level packaging technology for higher level of integration such as to integrate passive devices on the glass substrate as depicted in Figure 6.2. High-Q passive devices can be

SpacerSpacer substrate substrate IntegratedIntegrated patch patch antenna antenna LargeLarge inductor inductor

Adhesive layer layer IsolationIsolation trench trench Through-waferThrough-wafer via via Wafer-to-wafer bonding

Figure 6.2: Proposed WLP concept. realized on the low-loss substrate as we did in this work. In addition to achieving high Q-factor, silicon area is also reduced. However, care has to be taken due to additional parasitics i.e. resistance, inductance, and capacitance introduced by the through-substrate vias. The thickness of the spacer substrate has to be properly defined to ensure the magnetic field generated by the passive device, i.e. inductor, does not couple to active devices on silicon substrate. Also illustrated in Figure 6.2, it is a possibility to have an antenna on the spacer substrate. Similarly, care has to be taken with respect to the near-field generated by the antenna. Appendix A Boundary Conditions in HFSS

A.1 Symmetry Boundaries

HFSS recognizes symmetry boundary condition for a structure whose field is sym- metrically distributed. Figure A.1 shows a rectangular waveguide having TE10 Mode as the dominant mode of the E~ field. The rectangular waveguide has two planes of symmetry, one vertically through the center and one horizontally. The horizontal plane of symmetry is called perfect E where the E~ field is normal to the surface and the H~ field is tangential to the surface. The vertical plane of symmetry is a perfect H where the E~ field is tangential to the surface and the H~ field is normal to the surface. Symmetry boundary condition reduces the size or complexity of the model, thereby shortening the computational time.

A.2 Radiation Boundaries

HFSS recognizes radiation boundaries to model an inﬁnitely radiating wave far into space. Such boundary condition is very important radiating structure like antenna. At the surfaces where this boundary condition are applied, the second- order radiation boundary condition is used:

³ ´ j ³ ´ ∇ × E~ = jk0E~tan − ∇tan × ∇tan × E~tan tan k0 j ³ ´ + ∇tan ∇tan • E~tan (A.1) k0

133 134 APPENDIX A

Electric Field of TE 10 Mode

Perfect H symmetry plane Perfect E symmetry plane

Figure A.1: Perfect E and perfect H applied onto Symmetry boundary condition.

where

• E~tan is the tangential component of E-ﬁeld.

• k0 is the free space phase constant. √ • ω µ0²0. √ • j is −1.

The second-order radiation boundary condition is an approximation of free space.

A.3 Finite Conductivity Boundaries

HFSS recognizes Finite Conductivity Boundaries to model imperfect conductors, where the following condition holds: ³ ´ E~tan = ZS nˆ × H~ tan (A.2) where

• E~tan is the tangential component of E-ﬁeld.

• H~ tan is the tangential component of H-ﬁeld.

• ZS is the surface impedance of the boundary, (1 + j)/(δσ), where PERFECT ELECTRIC BOUNDARIES 135

p – δ is the skin depth, 2/(ωσµ), of the conductor being modeled. – ω is the frequency of the excitation wave. – σ is the conductivity of the conductor. – µ is the permeability of the conductor.

A.4 Perfect Electric Boundaries

In the HFSS, the space or background is by default assigned as perfectly conduct- ing material. Therefore all surfaces exposed to the background are assumed to have perfect E boundary if not assigned otherwise. On the perfect E boundary, the E-field is assumed to be normal to the surface. Therefore, the final solution must give the zero value to the tangential component of the E field at perfect E boundaries.

A.5 Inﬁnite Ground Planes Boundaries

The inﬁnite ground plane boundary models the situation where the device under test (DUT) is largely smaller than the measurement chuck. This boundary, con- ceptually, divides the whole spatial domain into half above it and half below it. The radiated ﬁelds in the half below area are set to zero.

Appendix B Boundary Conditions Implementation

137 138 APPENDIX B

B.1 Device #1

50µm x 50µm Silicon‘s 100µm x 100µm backside substrate taps substrate taps connected to connected to ground line signal lines p+ Silicon G1 G2 - Oxide - BCB S1 S2 100µm G1 G2

Glass AF5 Silicon‘s 50µm x 50µm frontside substrate taps connected to ground line

(a) Perspective-view of the reference (b) Top-view of the reference struc- structure ture’s backside

Symmetric Perfect H Boundary condition Lumped ports

(c) Half of the reference structure for (d) Perfect H boundary condition ap- computational time saving plied onto the symmetric face of the whole structure

Radiation Boundary condition

Infinite Ground Plane with Finite Conductivity

(e) Radiation boundary condition ap- (f) Inﬁnite ground plane with ﬁnite plied onto other three side walls and top conductivity (σ = 5.8 × 107 S/m) surface of the air box

Figure B.1: Reference structure with no isolation scheme applied. The silicon substrate is 50µm thick bonded to 450µm thick AF-45 Glass substrate: (a) Perspective-view of the reference structure; (b) Top-view of the reference structure’s backside; (c) Half of the reference structure for computational time saving; (d) Perfect H boundary condition applied onto the symmetric face of the whole structure; (e) Radiation boundary condition applied onto other three side walls and top surface of the air box; (f) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m). DEVICE #2 139

B.2 Device #2

Backside plane 10 µm 320 µm 320 320 µm

(a) Perspective-view of device (b) Top-view

50-ohm port

Perfect E 2D sheet

50-ohm port

(c) Excitation settings (d) Radiation boundary condition applied onto other four side walls and top surface of the air box

(e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m)

Figure B.2: Backside-plane metalization isolation scheme. The size of the backside- plane is 320 µm × 320 µm with 90 µm × 20 µm connections to the ground-plane: (a) Perspective-view of device; (b) Top-view; (c) Excitation settings; (d) Radiation boundary condition applied onto other four side walls and top surface of the air box; (e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m). 140 APPENDIX B

B.3 Device #3

Backside plane 50 µm 320 µm 320 320 µm

(a) Perspective-view of device (b) Top-view

50-ohm port

Perfect E 2D sheet

50-ohm port

(c) Excitation settings (d) Radiation boundary condition applied onto other four side walls and top surface of the air box

(e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m)

Figure B.3: Backside-plane metallization isolation scheme. The size of the backside- plane is 320 µm × 320 µm with 90 µm × 50 µm connections to the ground-plane: (a) Perspective-view of device; (b) Top-view; (c) Excitation settings; (d) Radiation boundary condition applied onto other four side walls and top surface of the air box; (e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m). DEVICE #4 141

B.4 Device #4

Backside plane

320 µm

(a) Perspective-view of device (b) Top-view

50-ohm port

Perfect E 2D sheet

50-ohm port

(c) Excitation settings (d) Radiation boundary condition applied onto other four side walls and top surface of the air box

(e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m)

Figure B.4: Backside-plane metallization isolation scheme. The size of the backside- plane is 320 µm × 320 µm with 90 µm × 320 µm connections to the ground-plane: (a) Perspective-view of device; (b) Top-view; (c) Excitation settings; (d) Radiation boundary condition applied onto other four side walls and top surface of the air box; (e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m). 142 APPENDIX B

B.5 Device #5

Air-filled trench

9 0 µ m

2 0 µ m

(a) Perspective-view (b) Top-view

(d) Perfect H boundary condition ap- (c) Half of the reference structure for plied onto the symmetric face of the computational time saving whole structure

(e) Radiation boundary condition ap- (f) Inﬁnite ground plane with ﬁnite plied onto other three side walls and top conductivity (σ = 5.8 × 107 S/m) surface of the air box

Figure B.5: Air-filled isolation scheme. The trench is 20 µm-wide at the frontside and 90 µm-wide at the backside: : (a) Perspective-view of the reference structure; (b) Top-view of the reference structure’s backside; (c) Half of the reference structure for computational time saving; (d) Perfect H boundary condition applied onto the symmetric face of the whole structure; (e) Radiation boundary condition applied onto other three side walls and top surface of the air box; (f) Infinite ground plane with finite conductivity (σ = 5.8 × 107 S/m). DEVICE #6 143

B.6 Device #6

Metalized trench

100 µµµm

(a) Perspective-view of the reference (b) Top-view of the reference structure structure

(c) Half of the reference structure for (d) Perfect H boundary condition ap- computational time saving plied onto the symmetric face of the whole structure

(e) Radiation boundary condition ap- (f) Inﬁnite ground plane with ﬁnite plied onto other three side walls and top conductivity (σ = 5.8 × 107 S/m) surface of the air box

Figure B.6: Grounded metalized trench isolation. The trench is 20 µm-wide at the frontside and 90 µm-wide at the backside. The trench is metalized and connected the ground-plane. The lateral size of the metallization is 500 µm × 100 µm: (a) Perspective- view of the reference structure; (b) Top-view of the reference structure’s backside; (c) Half of the reference structure for computational time saving; (d) Perfect H boundary condition applied onto the symmetric face of the whole structure; (e) Radiation boundary condition applied onto other three side walls and top surface of the air box; (f) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m). 144 APPENDIX B

B.7 Device #7

(a) Perspective-view of device (b) Top-view

(c) Excitation settings (d) Radiation boundary condition applied onto other four side walls and top surface of the air box

(e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m)

Figure B.7: Grounded metalized trench isolation. The trench is 20 µm-wide at the frontside and 90 µm-wide at the backside. The trench is metalized with a 320 µm×320 µm backside-plane and connected the ground-plane through a 100 µm × 90 µm plane: (a) Perspective-view of device; (b) Top-view; (c) Excitation settings; (d) Radiation boundary condition applied onto other four side walls and top surface of the air box; (e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m). DEVICE #8 145

B.8 Device #8

(a) Perspective-view of device (b) Top-view

(c) Excitation settings (d) Radiation boundary condition applied onto other four side walls and top surface of the air box

(e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m)

Figure B.8: Grounded metallization trench. The trench is 20 µm-wide at the frontside and 90 µm-wide at the backside. The trench is metalized with a 500 µm×320 µm backside- plane connected to the ground-plane: (a) Perspective-view of device; (b) Top-view; (c) Excitation settings; (d) Radiation boundary condition applied onto other four side walls and top surface of the air box; (e) Inﬁnite ground plane with ﬁnite conductivity (σ = 5.8 × 107 S/m).

List of Publications

1. S.M. Sinaga, M. Bartek, and J.N. Burghartz (2002). Modeling and analysis of substrate coupling in silicon integrated circuits. Proceedings of 5th Semi- conductor Advances for Future Electronics Workshop (SAFE 2002), Nov. 2002, Veldhoven, the Netherlands, pp. 704-707.

2. A. Polyakov, P.M. Mendes, S.M. Sinaga, M. Bartek, B. Rejaei, J.H. Correia, and J.N. Burghartz. Processability and Electrical Characteristics of Glass Substrates for RF Wafer-Level Chip-Scale Packages, Proc. 53rd Electronic Components and Technology Conference (ECTC 2003), May 27-30, 2003, New Orleans, Louisiana, USA, ISBN 0-7803-7430-4, pp. 875-880.

3. S.M. Sinaga, A. Polyakov, M. Bartek, and J.N. Burghartz. On-Chip Isola- tion in Wafer-Level Chip-Scale Packages: Substrate Thinning and Circuit Partitioning by Trenches, IMAPS 2003, 16-20 November 2003, Boston, USA, publ. IMAPS, ISBN 0-930815-71-8, pp. 768-773.

4. S.M. Sinaga, M. Bartek, and J.N. Burghartz. Analysis and Optimization of Via-Connected Spiral Inductors in RF Silicon Technology, Proc. SAFE 2003, November 25-26, 2003, Veldhoven, the Netherlands, ISBN 90-73461- 39-1, pp. 757-760.

5. S.M. Sinaga, A. Polyakov, M. Bartek, and J.N. Burghartz. Circuit Parti- tioning and RF Isolation by Through-Substrate Trenches, 54th ECTC conference, June 1-4, 2004, ISBN 0-7803-8365-6, pp. 1519-1523.

6. P.M. Mendes, S.M. Sinaga, A. Polyakov, M. Bartek, J.N. Burghartz, and J.H. Correia. Wafer-Level Integration of On-Chip Antennas and RF Pas-

147 148 LIST OF PUBLICATIONS

sives Using High-Resistivity Polysilicon Substrate Technology, 54th ECTC conference, June 1-4, 2004, ISBN 0-7803-8365-6, pp. 1879-1884.

7. S.M. Sinaga, A.Polyakov, M.Bartek, J.N. and Burghartz. Substrate Thin- ning and Trenching as Crosstalk Suppression Techniques, Proc. 3rd Euro- pean Microelectronic and Packaging Symposium, June 16-18, 2004, Prague, Czech Republic, ISBN 80-239-2835-X, pp. 131-136.

8. M. Bartek, G. Zilber, D. Teomin, A. Polyakov, S.M. Sinaga, P.M. Mendes, and J.N. Burghartz. Wafer-Level Chip-Scale Packaging for Low-End RF Products, Digest of papers 2004 Topical Meeting on Silicon Monolithic In- tegrated Circuits in RF Systems, 8-10 September 2004, Atlanta, USA, eds. J.D. Cressler, J. Papapolymerou, ISBN 0-7803-8703-1, pp. 41-44.

9. M. Bartek, G. Zilber, D. Teomin, S.M. Sinaga, A. Polyakov, and J.N. Burghartz. Shellcase-type Wafer-Level Packaging Solutions: RF Charac- terization and Modeling, CD-ROM proc. 1st International Wafer-Level Packaging Congress (IWLPC 2004), October 10-12, 2004, San Jose, CA, USA, paper 5.1, 6 p.

10. M. Bartek, A. Polyakov, S.M. Sinaga, P.M. Mendes, J.H. Correia, and J.N. Burghartz. Characterization of High-Resistivity Polycrystalline Silicon Sub- strates for Wafer-Level Packaging and Integration of RF Passives, Proc. AS- DAM 2004, 17-21 October 2004, Smolenice Castle, Slovakia, eds. J. Osvald, S. Hascik, publ. IEEE, ISBN 0-7803-8535-7, pp. 227-230.

11. A. Polyakov, S.M. Sinaga, M. Bartek, and J.N. Burghartz. Wafer-Level Packaging for RF Applications Using High-Resistivity Polycrystalline Sili- con Substrate Technology, CD-ROM Proc. IMAPS 2004, 14-18 November 2004, Long Beach, CA, USA, publ. IMAPS, ISBN 0-930815-74-2, paper WP1-7, 8 p.

12. S.M. Sinaga, A. Polyakov, M. Bartek, and J.N. Burghartz. Through-Substrate Trenches for RF Isolation in Wafer-Level Chip-Scale Package, Proc. 6th Electronics Packaging Technology Conference (EPTC 2004), 8-10 Decem- ber 2004, Pan Paciﬁc Hotel, Singapore, publ. IEEE, ISBN 0-7803-8821-6, pp. 13-17.

13. A. Polyakov, S. Sinaga, P.M. Mendes, M. Bartek, J.H. Correia, and J.N. Burghartz. High-Resistivity Polycrystalline Silicon as RF Substrate in Wafer- Level Packaging, Electronic Letters, Vol. 41, No. 2, 20 January 2005, ISSN 0013-5194, pp. 100-101.

14. M. Bartek, S.M. Sinaga, J.N. Burghartz; Inﬂuence of Via-Connections on Electrical Performance of Vertically-Spaced RF Passives, Proc. The 55th LIST OF PUBLICATIONS 149

Electronic Components and Technology Conference (ECTC 2005), May 31- June 3, 2005, Lake Buena Vista, FL, USA, publ. IEEE, ISBN 0-7803-8906-9, pp. 1584-1589. 15. M. Bartek, S.M. Sinaga, and J.N. Burghartz. Vertical Integration of RF Passive Components in Stacked Wafer-Level Packages, Proc. 15th European Microelectronics and Packaging Conference & Exhibition, June 12-15, 2005, Brugge, Belgium, publ. IMAPS, pp. 190-194. 16. S.M. Sinaga, M. Bartek, and J.N. Burghartz. On-Chip RF Isolation in Stacked Wafer-Level Packages, Proc. 15th European Microelectronics and Packaging Conference & Exhibition (EMPC 2005), June 12-15, 2005, Brugge, Belgium, publ. IMAPS, pp. 303-307.

17. H. Sagkol, S. Sinaga, J.N. Burghartz, B. Rejaei, and A. Akhnoukh. Thermal eﬀects in suspended RF spiral inductors, IEEE Electron Device Letters, Vol. 26, No. 8, August 2005, pp. 541-543. 18. S.M. Sinaga, A. Polyakov, and M. Bartek. Wafer-Level Packaging for RF Applications Using Low-Loss Spacer Substrate for Integration of Passives, 1st International Workshop on 3S (SoP, SiP, SoC) Electronic Technologies, September 22-23, 2005, Atlanta, USA.

19. J. Iannacci, J. Tian, S.M. Sinaga, R. Gaddi, A. Gnudi, and M. Bartek. Electromagnetic Optimization of a Wafer-Level Package for RF-MEMS Ap- plications, Proc. 4th European Microelectronic and Packaging Symposium with Table-Top Exhibition (EMPS 2006), May 22-24, 2006, Terme Catez, Slovenia, publ. MIDEM (Ljubljana), eds. D. Belavic, M. Kosec, I. Sorli, ISBN 961-91023-5-5, pp. 79-84. 20. J. Iannacci, J. Tian, S.M. Sinaga, R. Gaddi, A. Gnudi, and M. Bartek. Parasitic Eﬀects Reduction for Wafer-Level Packaging of RF-MEMS, Proc. DTIP 2006 (Symposium on Design, Test, Integration and Packaging of MEMS / MOEMS), 26-28 April 2006, Stresa, Lago Maggiore, Italy. 21. S.M. Sinaga, A. Polyakov, M. Bartek, and J.N. Burghartz. RF crosstalk suppression based on wafer-level packaging concept. Proc. 3rd Annual International Wafer-Level Packaging Conference (IWLPC 2006), pp. 5-9.

22. J. Tian, S.M. Sinaga, and M. Bartek. Study of thermal behaviour in a multi-chip-composed optoelectronic package, Proc. 16th European Micro- electronics and Packaging Conference & Exhibition (EMPC 2007), June 17-20, 2007, Oulu, Finland, publ. IMAPS, ISBN 978-952-99751-1-2, pp. 262-267.

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Curriculum Vitae

Saoer Maniur Sinaga was born in Medan, North Sumatera, Indonesia on the 2nd of March 1976. He grew up and finished all his schools in Medan before he left for university. In 1994 he went to study Electrical Engineering at Institut Teknologi Bandung, West Java. Four years later, he finished his undergraduate study and received his BSc degree in Electrical Engineering. In spring 1999, he received a scholarship from Siemens AG to pursue a Mas- ter’s study in Communication Engineering at the University of Kassel, Germany. He worked part-time as a research student (studentische hilfskraft) at Theoret- ical Electromagnetic Laboratory at the same university. From October 2000 to February 2001, he did an internship at Corporate Technology, Siemens AG in Mu- nich. In October 2001, he received his MSc degree with a thesis entitled “Inverse Electromagnetic Scattering using Linear Sampling Method”. In April 2002, he joined Delft Institute of Microelectronics and Submicron Technology (DIMES) at Delft University of Technology (TU Delft) as a PhD student. His research was supported by Philips (PACD B1 project) and by EC (Blue Whale project IST-2000-10036). In April 2006, he joined NXP Semiconductors (former Philips Semiconductor) as a design-flow engineer, where he developed the use model for power and signal integrity analysis in a System-in-Package (SiP). In November 2008, he left NXP and joined Philips Applied Technologies to take a role as an EMC consultant. Until now, he has been involved in various modeling and simulation works such as power and signal integrity analysis in high-speed interface and far-field emission from electronic equipments.

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