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Digital and Analogue Circuit Design 288 EMC for Product Designers Chapter 12 Digital and analogue circuit design Circuit design is an essential contributor to EMC. In this area we can distinguish the techniques used to control radio frequency emissions from an operating circuit, and those used to control radio frequency and transient immunity of an operating circuit. There are some common points between these two, but there are also some differences which mean that to completely address the compatibility of a product you need to deal with both. Low frequency (mains supply) EMC is also a function of circuit design, principally of the power supply, but does not suffer from the mystery surrounding RF effects and is not considered in this chapter. 12.1 Design for emissions control Digital circuits are prolific generators of electromagnetic interference. High frequency square waves, rich in harmonics, are distributed throughout the system. The harmonic frequency components reach into the part of the spectrum where cable and enclosure resonance effects are important. Analogue circuits are in general much quieter because high frequency square waves are not normally a feature. A major exception is wide bandwidth video circuits, which transmit broadband signals up to several tens of MHz, or over a hundred MHz for high resolution video. Any analogue design which includes a high frequency oscillator or other high di/dt circuits must follow HF design principles, especially with regard to ground layout. Some low frequency amplifier circuits can oscillate in the MHz range, especially when driving a capacitive load, and this can cause unexpected emissions. The switching power supply is a serious cause of interference at low to medium frequencies since it is essentially a high-power square wave oscillator. 12.1.1 The Fourier spectrum 12.1.1.1 The time domain and the frequency domain Basic to an understanding of why switching circuits cause interference is the concept of the time domain/frequency domain transform. Most circuit designers are used to working with waveforms in the time domain, as viewed on an oscilloscope, but any repeating waveform can also be represented in the frequency domain, for which the basic measuring and display instrument is the spectrum analyser (section 6.1.2). Whereas the oscilloscope shows a segment of the waveform displayed against time, the spectrum analyser will show the same signal displayed against frequency. Thus the relative amplitudes of different frequency components of the signal are instantly seen. The mathematical tool which allows you to analyse a known time domain waveform in the frequency domain is called the Fourier transform. The necessary Digital and analogue circuit design 289 equations for the Fourier transform are covered in Appendix D, section D.7. Figure 12.2 shows the spectral amplitude compositions of various types of waveform (phase relationships are rarely of any interest for EMC purposes). The sinewave has only a single component at its fundamental frequency. A square wave with infinitely fast rise and fall times has a series of odd harmonics (3, 5, 7, etc. multiples of the fundamental frequency) extending to infinity. A sawtooth contains both even and odd harmonics. Frequency MHz 15 Duty cycle % 50 tr, t f µs 0.007 trace 1 0.001 trace 2 dB 0 -10 -20dB/decade -20 1/ πtr 1/ πtr -30 -40 -50 Harmonic amplitudes 7ns -60 Envelope 7ns -40dB/decade Harmonic amplitudes 1ns -70 Envelope 1ns -80 10 100 MHz 1000 Figure 12.1 Harmonic envelope of a 50% duty cycle trapezoid Switching waveforms can be represented as trapezoidal; a digital clock waveform is normally a square wave with finite rise and fall times. The harmonic amplitude content of a trapezoid decreases from the fundamental at a rate of 20dB per decade until a breakpoint is reached at 1/ πtr, after which it decreases at 40dB/decade (Figure 12.1). Of related interest is the differentiated trapezoid, which is an impulse with finite rise and fall times. This has the same spectrum as the trapezoid at higher frequencies, but the amplitude of the fundamental and lower order harmonics is reduced and flat with frequency. (This property is intuitively obvious as a differentiator has a rising frequency response of +20dB/decade.) Reducing the trapezoid’s duty cycle from 50% has the same effect of decreasing the fundamental and low frequency harmonic content. Asymmetrical slew rates and duty cycles other than 50% generate even (multiples of 2, 4, 6, etc.) as well as odd harmonics. This feature is important, since differences between high- and low-level output drive and load currents mean that most logic circuits exhibit different rise and fall times, and it explains the presence and often preponderance of even harmonics at the higher frequencies. Changing the duty cycle even slightly away from 50% will dramatically increase the amplitude of even harmonics with little change to the odd components; conversely a duty cycle of 33.3% causes a null in the odd harmonics. 12.1.1.2 Choice of logic family The damage as far as emissions are concerned is done by switching edges which have a fast rise or fall time (note that this is not the same as propagation delay and is rarely specified in data sheets; where it is, it is usually a maximum figure). Using the slowest 290 Figure 12.2 Frequencyspectra forvarious waveforms sine wave square wave sawtooth wave trapezoid differentiated asymmetrical trapezoid trapezoid EMCfor ProductDesigners Digital and analogue circuit design 291 risetime compatible with reliable operation will minimize the amplitude of the higher- order harmonics where radiation is more efficient. Figure 12.1 shows the calculated harmonic amplitudes for a 15MHz clock with risetimes of 1ns and 7ns. An improvement approaching 20dB is possible at frequencies around 400MHz by slowing the risetime. The advice based on this premise must be, use the slowest logic family that will do the job; don’t use fast logic when it is unnecessary. Treat with caution any proposal to substitute devices from a faster logic family, such as replacing 74HC parts with 74AC. Where parts of the circuit must operate at high speed, use fast logic only for those parts and keep the clock signals local. This preference for slow logic is unfortunately in direct opposition to the demands of software engineers for ever-greater processing speeds. The graph in Figure 12.3 shows the measured harmonic envelope of a 10MHz 50% duty cycle waveform for three devices of different logic families in the same circuit. Note the emphasis in the harmonics above 200MHz for the 74AC and 74F types. From the point of view of immunity, a slow logic family will respond less readily to fast transient interference (see section 12.2.2.1). 74HC244 74AC244 74F244 10dB/div 10MHz 100MHz 1GHz Figure 12.3 Comparison of harmonic envelopes of different logic families Some IC manufacturers are addressing the problem of RF emissions at the chip level. By careful attention to the internal switching regime of VLSI devices, noise currents appearing at the pins can be minimized. The transition times can be optimized rather than minimized for a given application [73]. Alternatively, the shape of the transition can be “softened” to reduce higher order harmonic content without substantially reducing the logic switching speed. Revised package design and smaller packages can allow the decoupling capacitor (section 12.1.3) to be placed as close as possible to the chip, without the internal leadframe’s inductance negating its effect; also, the reduction in operating silicon area gained from shrinking silicon design rules can be used to put a respectable-sized decoupling capacitor (say 1nF) actually on the silicon. 12.1.1.3 ICC at switching The Fourier components of the output waveform are not the only reason for emissions of logic circuits. The current taken from the V CC pin or pins related to driving the outputs has two components (Figure 12.4): 292 EMC for Product Designers • the current fed through the output pin(s) and used for charging or discharging the capacitance of each output node; • the current taken through the totem-pole output stage transistors as they switch, which is not passed through the output pin(s). Both of these components appear at the V CC pin and have to be decoupled, as discussed shortly in section 12.1.3. The second component does not involve the signal tracks and is not affected by the quality of their routing or layout, but it is significantly affected by the nature of the decoupling regime and of the use of ground and power planes. Logic families which control this unwanted current (sometimes known as “delta-I” noise) are widely touted as helping to reduce emissions overall. As well as the current associated with output drivers, there are similar supply currents associated with switching each of the internal nodes of the device. Individually, these are orders of magnitude less than the output drive currents. But in a typical VLSI device there are many more of them: thousands at least, and if as is usual the device is synchronously clocked then all of the current transitions occur simultaneously, at the clock edge. Therefore the supply current of any VLSI device tends to be dominated by short but potentially high amplitude current spikes at each transition of the internal clock. lower levels of current pass I = I + I through each logic buffer CC OS OP at clock transitions ICC IOS flows through both output transistors when they switch IOP flows through the output pin to switch the node Figure 12.4 Current through the supply pin Since these current transients are almost entirely a function of the internal design of the chip, it is for this reason as much as any other that different manufacturers’ implementations of a particular device may be noisier or quieter in EMC terms.
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