Modeling of the Substrate Path for Direct Power Injection in Integrated Circuits

Ali Alaeldine∗†, Richard Perdriau∗, Mohamed Ramdani∗, Etienne Sicard‡, M’hamed Drissi† and Ali M. Haidar§ ∗ESEO-LATTIS - 4, rue Merlet-de-la-Boulaye - BP 30926 - 49009 Angers Cedex 01 - France (e-mail : [email protected]) †IETR - INSA de Rennes - 20, avenue des Buttes de Coësmes - 35043 Rennes Cedex - France ‡LATTIS - INSA de Toulouse - 135, avenue de Rangueil - 31077 Toulouse Cedex 04 - France §Dept. of Computer Eng. and Informatics - Faculty of Engineering - Beirut Arab University - PO Box 11-5020 - Lebanon

Abstract—This paper presents a substrate coupling path model Therefore, this paper aims at introducing suitable simulation for the direct power injection (DPI) of EMI disturbances into models for different EMI protection strategies in ICs, with the substrate of an (IC). This modeling is comparisons between simulations and measurements. For that achieved on a 0.18 µm test chip composed of several functionally identical cores, differing only by their EMI protection strategies purpose, a special test chip (CESAME) [8] will be used. (RC protection, isolated substrate), and takes into account these The paper is organized as follows. First of all, the internal different strategies. The comparison between simulation results structure of the CESAME test chip is introduced in Sect. and related measurements demonstrates that, once combined II. Then, Sect. III presents the DPI measurement set-up used with the complete model of the injection set-up itself, these in this study, along with its simulation model. The different models are helpful to choose the best protection strategy against electromagnetic disturbances. substrate models for the internal cores of the IC are described in Sect. IV. Finally, Sect. V provides a comparison between I. INTRODUCTION measurements and simulations, along with comparisons among For many years, integrated circuits (ICs), and digital blocks the efficiencies of different EMI protection strategies. in particular, have been the source of ever increasing electro- magnetic interference (EMI), due to higher clock frequencies II. TEST CHIP and data rates as well as decreased node capacitances. In A. Structure parallel, their immunity to EMI has decreased at the same pace, due to a steady reduction in power supply voltage and, The integrated circuit used in this study (CESAME) was consequently, noise margin. Therefore, the characterization designed and fabricated by ST-Microelectronics in 0.18 µm and modeling of their susceptibility is a topical demand. CMOS technology (1.8 V supply voltage), and was initially For that purpose, several measurement methods have been intended for the validation of low-emission design techniques developed and standardized by the IEC, including direct power [6] [8]. It consists of six logic cores which are identical from injection (DPI) [1] and bulk current injection (BCI) [2]. a functional point of view and are located on the same die, Both methods reproduce operating conditions, however, DPI but differ only by their protection strategies. All these cores is easier to set up and, therefore, was chosen for this study. are based on D flip-flops, a clock tree and standard gates, and In particular, substrate noise generated in an IC by either are intended to reflect the activity of a typical logic core [8]. internal logic or external sources can dramatically disturb the Each core includes 240 identical synchronous base cells, and operation of other analog and digital blocks, due to the low each base cell consists of 400 transistors (5 D-flip-flops, 25 resistivity of the substrate in modern ICs [3]. Various solutions NAND gates and 4 buffers). This IC is mounted on a custom [4] have been pointed out in order to enhance substrate printed circuit board (PCB), called ALI, which is displayed in shielding against electromagnetic interference. Moreover, pre- Fig. 1 (left). For the sake of simplicity, only 3 different cores vious authors [5] have already mentioned the use of substrate (NORM, ISO and RC) out of 6 are used, which are highlighted injection to characterize the behavior of an IC towards EMI. in dotted boxes in the right half of the same figure. 4 cores Later, this experiment was standardized using DPI test benches (NORM, RC, NOR and GRID) are built in the global substrate [6], and made it possible to identify the efficiency of substrate of the IC, while the other ones (ISO and ISV) are built in a shielding techniques through measurements. However, these local isolated substrate. "a posteriori" experiments require the fabrication of a test a) NORM core: The NORM core is built in the global chip. Conversely, the use of simulation for the prediction of substrate of the IC. The only EMI protection strategy used in immunity to substrate injection would avoid this fabrication. this core consists of two small 1.7 Ω series , one on Simulation models for DPI tests on ICs have already been each power supply rail. These resistors, along with the metal developed [7], but only for Vdd injection. In order to estab- and MOS capacitances of the logic core, build up a RC filter, lish accurate simulation models of substrate DPI, modeling with a high cutoff frequency (about 200 MHz). The structure substrate coupling paths in ICs is a required additional task. of this core is depicted in Fig.3 (left).

978-1-4244-1699-8/08/$25.00 ©2008 IEEE the data output overshooting 20 % of its nominal voltage, or its jitter overshooting 10 % of the period. The transmitted power PTrans dissipated into the substrate of the circuit under test can be expressed from the measured incident power PInc : 2 PTrans =(1−|S11| ) PInc (1)

where S11 is the reflection factor and PInc the incident power injected into the system under test. By replacing the reflection factor by its expression, Eq. 2 is obtained : Fig. 1. ALI test board and CESAME test chip with the 3 cores under      2 test (NORM, ISO and RC) in dotted boxes ZDUT − Z0  PTrans = 1 −   PInc (2) ZDUT + Z0

in which ZDUT is the impedance of the device under test and b) ISO core: The ISO core uses a different EMI protec- Z0 the characteristic impedance of the sine-wave generator (50 tion strategy. It is embedded in its own local substrate, isolated Ω). By separating the real and imaginary parts of ZDUT ,the from the rest of the chip thanks to a triple-well technique exact expression of the transmitted power can be obtained : (Fig.4, left). This strategy has already been pointed out as very interesting for EMI shielding [4]. 4 Z0 Re(ZDUT ) PTrans = 2 PInc (3) c) RC core: In the RC core, built in the global substrate |ZDUT + Z0| like the NORM core, an additional 1-nF integrated decou- The expression in Eq. 3 is well suited to the calculation pling is inserted between both supply rails (Fig.5, of PTrans from measurements, owing to the use of power right). This distributed on-chip capacitor is made from several meters in DPI experiments. However, it is unusable for DPI poly1/poly2 , and increases the area of the RC electrical modeling and simulation, since power generators core by 40 % compared with the NORM core. By lowering are not available in common circuit simulators. A convenient the cutoff frequency of the RC filter (about 40 MHz), this solution consists in using a RF voltage source, and expressing technique allows the reduction of the power distribution noise the transmitted power as a function of source voltage instead arising from multiple drivers switching simultaneously [9]. of injected power(Eq. 4):

B. Modeling and measurement conditions 4 Z0 2 PTrans = 2 VInc (4) The different cores of the CESAME chip can be activated |ZDUT + Z0| separately. In order to simplify modeling, only one core will be activated for each measurement and will be subject to power These expressions will be used in Sect. V in order to build up injection. Therefore, the DPI injection set-up used in this study immunity plots (in dBm) from electrical simulation results (in (and described in the following section) can be considered the V). only source of the noise dissipated into the substrate of the B. Modeling of the DPI set-up logic core under measurement. In order to predict the immunity of the cores, a compre- III. DPI SET-UP hensive model must now be developed for the injection set-up and the device under test (PCB and IC). A. DPI measurement method The model used for the injection set-up itself is a generic one The DPI injection method used in this paper has already suggested in [7], depending on the length of the directional been introduced in a previous paper [6] for the same set- coupler and its associated cables. The latter are represented up. Conducted-mode interference is injected through a probe by a transmission line adapted to 50 Ω, with a delay time Td V connected to the ss pin of each logic core under test through given by Eq.5: a 1 nF capacitor. This probe is fed by a 10 W power amplifier l 76.08 · 10−2 through a directional coupler, allowing the measurement of T = = = 2538 · 10−12 s d 8 (5) incident and reflected powers through a dual-channel power c 3 · 10 meter. However, only the incident power will be used in this in which l is the total length of the directional coupler and study for the representation of the measured and simulated its cables, and c the speed of light. immunity plots of each core. Likewise, the models of the PCB, the IC and the injection The data output of the circuit under test is connected to an probe have already been introduced in [8] and [7], respectively, oscilloscope (adapted to 1 MΩ) through a 1 MΩ passive probe, and are being re-used in this study. However, in this case, which makes possible to observe a malfunction of the circuit injection is performed on the Vss pins of the IC instead of during the experiment. This malfunction is characterized by the Vdd pins. Therefore, the 1.2 Ω , used for VDE the immunity criterion described in [6], namely, the ripple of conducted emission measurements [10] on the ALI board, is Fig. 2. Complete electrical model of the DPI experiment (without any substrate model)

modeled accurately with its parasitic inductance. Device Value Device Value Repi−NORM 30 Ω Cpcb 500 fF The global model of the DPI experiment is depicted in Fig. RGRID 30 Ω LGRID 3.57 nH 2. However, this model still does not take into account the RRC 30 Ω LRC 3.67 nH substrate injection path itself. RNOR 30 Ω LNOR 3.67 nH TABLE I DEVICE VALUES FOR THE SUBSTRATE MODEL OF THE NORM CORE IV. SUBSTRATE MODELING FOR THE 3 CORES UNDER TEST A. NORM core In the case of the NORM core, power is injected straight into its substrate (which is indeed the global substrate of the circuit) while the other ones are replaced by their equivalent parallel through the Vss pin. Fig. 3 (left) depicts the architecture of an RC model. inverter of the NORM core. As can be seen, the global epitaxial substrate is modeled in the vertical direction by a resistance, designated by Repi−NORM. B. ISO core Then, the substrate is coupled to the PCB ground through a capacitance (Cpcb) representing the spacing between the The ISO core bears a more complex model, with the addi- chip and the PCB itself. It can be noted that the model tion of the NISO isolation layer between the local substrate of the bonding and package of the Vss pin of the NORM of the core and the global substrate of the integrated circuit. core is not represented here, but in the global model already Indeed, two coupling capacitances must be taken into account: presented in Fig. 2. However, it is also necessary to take into the first one (Cpwell1) is located between the global P substrate account the coupling paths to the PCB ground through the and the NISO layer, while the second one (Cpwell2) is located Vss rails of the 3 other cores (NOR, RC and GRID) built in between the NISO layer and the local P substrate of the ISO the same substrate (the ISO and ISV cores, built in their own core, as can be seen in Fig. 4. Moreover, Rnwell models the substrate, were neglected in this first-order approximation). actual resistance of the N-well which allows the buried NISO Each rail is modeled by a series RL network representing layer to be connected to the Vdd rail. the substrate resistance (same as the one of the PCB core) Repi−ISO represents the equivalent resistance of the epitaxial and the inductance of the package and the bonding of the substrate (analogous to the NORM core) ; however, its value corresponding IC pin. Therefore, the complete model of the is lower than the one of the NORM core, due to the reduced substrate coupling path for the NORM core can be built (Fig. equivalent thickness of the substrate under the NISO layer. The 3, right) ; the corresponding values of the equivalent passive rest of the model is identical to the NORM core, namely, the devices of this model are shown in Tab. I. coupling path to the PCB ground through the Cpcb capacitance, In order to perform the immunity simulation, the model of the and the Vss pins of the other cores built in the global substrate NORM substrate is added to the model of the system under (NORM, RC, NOR and GRID). The complete model of the test already shown in Fig. 2. In order to speed up simulations, substrate of the ISO core is depicted in Fig. 4 (right), while the actual transistor netlist of one base cell of the core is used, the values of its equivalent devices are printed in Tab. II. Fig. 3. Structure of an inverter of the NORM core (left) and electrical model of the substrate of the NORM core (right)

Fig. 4. Structure of an inverter of the ISO core (left) and electrical model of the substrate of the ISO core (right)

Fig. 5. Structure of an inverter of the RC core (left) and electrical model of the substrate of the RC core (right)

Device Value Device Value strate resistance of the path starting from the Vdd input. Repi−ISO 22 Ω Rnwell 2 Ω Like in the NORM model, the coupling paths to the PCB Cpwell1 270 pF Cpwell2 348 pF ground through the Vss rails of the 3 other cores (NORM, TABLE II NOR and GRID) built in the same substrate are taken into DEVICE VALUES FOR THE SUBSTRATE MODEL OF THE ISO CORE account. The complete model of the substrate of the ISO core is depicted in Fig. 5 (right), while the values of its equivalent devices are printed in Tab. III.

C. RC core Device Value Device Value Repi−RC 30 Ω Rsub−RC 34 Ω The RC core is almost identical to the NORM core, apart Cdecoup 1nF Rdecoup 1 Ω from the inclusion of a 1 nF on-chip decoupling capacitor TABLE III located between both Vdd and Vss power supply rails. It is DEVICE VALUES FOR THE SUBSTRATE MODEL OF THE RC CORE modeled and represented by the series RC network Cdecoup and Rdecoup. Moreover, another resistance (Rsub−RC ) is added to the vertical resistance (Rsub−RC ), and represents the sub- V. R ESULTS 40 Measurement A. Comparison between simulations and measurements for Simulation each core 35 A first immunity simulation was performed from 10 MHz to 1 GHz for each core. This time-domain simulation is performed for each frequency step (10 MHz); as stated in 30 Sect. III, a failure in the IC is characterized by the ripple of the output signal reaching 20 % of the logic "1" voltage level, or by the jitter of this output signal reaching 10 % of 25 the period [11]. Injected power (dBm) Fig. 6, 7 and 8 depict the comparisons between experimental 20 measurements and simulation results for the susceptibility of DPI into the substrate of the RC core: the NORM, ISO and RC cores, respectively. −Output signal susceptibility

15 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) 40 Measurement Simulation Fig. 8. Susceptibility of the RC core : measurement (solid) and simulation 35 (dotted)

30 It can be noted that all cores are immune to a 10-watt incident 25 power below 60 MHz. Above this frequency, they are be- coming more and more susceptible. Low- and high-immunity Injected power (dBm) 20 frequencies are almost identical between measurement and simulation results. Moreover, the simulation is generally "pes- simistic", namely, the simulated immunity is lower than the 15 measured one ; this is the most favorable case for immunity DPI into the substrate of the NORM core: −Output signal susceptibility prediction. Conversely, in the 460-640 MHz frequency range, 10 0 100 200 300 400 500 600 700 800 900 1000 the difference is greater then 6 dBm with the simulation Frequency (MHz) being more "optimistic". These discrepancies may be due to power losses [12] which haven’t been included so far in the Fig. 6. Susceptibility of the NORM core : measurement (solid) and simulation model and remain to be studied. simulation (dotted) B. Discussion and comparison among simulation results Another interesting result consists in comparing simulation results for the 3 cores on the same diagram (Fig. 9), in order 40 to assess the relative efficiencies of the protection strategies Measurement Simulation and compare them with the ones obtained from measurements.

35 Previous studies [3] have pointed out the efficiency of reduc-

30 tion techniques for substrate noise. Moreover, measurements for the 3 cores under test have already been presented in [6] ; they demonstrated that the RC core is the most immune to 25 DPI, followed by the ISO core and, finally, the NORM core. As far as simulations are concerned, it is important to notice Injected power (dBm) 20 that the hierarchy among the 3 cores is exactly identical. This result thus confirms the previous studies conducted on this

15 topic. DPI into the substrate of the ISO core: −Output signal susceptibility VI. CONCLUSION 10 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) In this paper, coupling paths for direct power injection into the substrate of an IC were identified and modeled for 3 different cores of the IC (plain, isolated substrate, Fig. 7. Susceptibility of the ISO core : measurement (solid) and integrated decoupling capacitor). These models were added simulation (dotted) to a comprehensive simulation model of a DPI set-up, making REFERENCES 40 Simulation: NORM core Simulation: ISO core [1] IEC EMC Task Force. IEC62132-4 : Measurement of electromagnetic Simualtion: RC core immunity 150 KHz to 1 GHz - part 4: Direct RF power injection method. Draft technical report, IEC, September 2007. 35 [2] IEC EMC Task Force. IEC62132-3 : Measurement of electromagnetic immunity 150 KHz to 1 GHz - part 3: Bulk current injection (BCI) method. Draft technical report, IEC, December 2007. 30 [3] S. Ardalan and M. Sachdev. An overview of substrate noise reduction techniques. In International Symposium on Quality Electronic Design (ISQED04), USA, pages 291–296, 2004. [4] R. Rossi, G. Torelli, and V. Liberali. Model and verification of triple-well 25 shielding on substrate noise in mixed-signal CMOS ICs. In ESSDERC, Injected power (dBm) Portugal, September 2003. [5] T. Tsukagoshi, T. Kuriyama, H. Wabuka, and T. Watanabe. LSI immunity test by direct GND pin injection. In IEEE International 20 Symposium on Electromagnetic Compatibility (EMC2003), USA,pages

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