LTC3723-1/LTC3723-2 Synchronous Push-Pull PWM Controllers

FEATURES DESCRIPTIO U ■ High Efficiency Synchronous Push-Pull PWM The LTC®3723-1/LTC3723-2 synchronous push-pull PWM ■ 1.5A Sink, 1A Source Output Drivers controllers provide all of the control and protection func- ■ Supports Push-Pull, Full-Bridge, Half-Bridge, and tions necessary for compact and highly efficient, isolated Forward Topologies power converters. High integration minimizes external ■ Adjustable Push-Pull Dead-Time and Synchronous component count, while preserving design flexibility. Timing The robust push-pull output stages switch at half the ■ Adjustable System Undervoltage Lockout and Hysteresis oscillator frequency. Dead-time is independently pro- ■ Adjustable Leading Edge Blanking grammed with an external resistor. Synchronous rectifier ■ Low Start-Up and Quiescent Currents timing is adjustable to optimize efficiency. A UVLO pro- ■ Current Mode (LTC3723-1) or Voltage Mode gram input provides precise system turn-on and turn off (LTC3723-2) Operation voltages. The LTC3723-1 features peak current mode ■ Single Resistor Slope Compensation control with programmable slope compensation and lead- ■ ing edge blanking, while the LTC3723-2 employs voltage VCC UVLO and 25mA Shunt Regulator ■ Programmable Fixed Frequency Operation to 1MHz mode control with voltage feedforward capability. ■ 50mA Synchronous Output Drivers The LTC3723-1/LTC3723-2 feature extremely low operat- ■ Soft-Start, Cycle-by-Cycle Current Limiting and ing and start-up currents. Both devices provide reliable Hiccup Mode Short-Circuit Protection short-circuit and overtemperature protection. The ■ 5V, 15mA Low Dropout Regulator LTC3723-1/LTC3723-2 are offered in a 16-pin SSOP

■ Available in 16-Pin SSOP Package package. U , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S All other trademarks are the property of their respective owners. ■ Telecommunications, Infrastructure Power Systems ■ Distributed Power Architectures

TYPICAL APPLICATIO U Isolated Push-Pull Converter

VOUT

VIN

ME UVLO DRVA SYNC FROM • • AUXILIARY LTC3901 WINDING SPRG DRVB VCC CS MF

VREF DPRG

CT SDRA VREF VOUT RLEB SDRB V REF V+ LTC3723-1 COLL RREF VOUT LT1431 SS COMP FB GND GND-F GND-S

372312 TA01 372312f 1

LTC3723-1/LTC3723-2

WW U

ABSOLUTE AXI UW RATI GS (Note 1)

VCC to GND (Low Impedance Source) ...... –0.3V to 10V VREF Output Current ...... Self-Regulated (Chip Self-Regulates at 10.3V) Operating Temperature (Notes 5,6) UVLO to GND...... –0.3V to VCC LTC3723E ...... –40°C to 85°C All Other Pins to GND Storage Temperature Range ...... –65°C to 125°C (Low Impedance Source) ...... –0.3V to 5.5V Lead Temperature (Soldering, 10sec)...... 300°C

VCC (Current Fed) ...... 40mA W

PACKAGE/ORDER IUU FOR ATIO

TOP VIEW TOP VIEW

VREF 1 16 SPRG VREF 1 16 SPRG SDRB 2 15 UVLO SDRB 2 15 UVLO SDRA 3 14 SS SDRA 3 14 SS DRVB 4 13 FB DRVB 4 13 FB

VCC 5 12 RLEB VCC 5 12 DPRG DRVA 6 11 COMP DRVA 6 11 COMP GND 7 10 CS GND 7 10 CS

CT 8 9 DPRG CT 8 9 RAMP

GN PACKAGE GN PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 100°C/W TJMAX = 125°C, θJA = 100°C/W ORDER PART NUMBER GN PART MARKING ORDER PART NUMBER GN PART MARKING LTC3723EGN-1 37231 LTC3723EGN-2 37232

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supply

VCCUV VCC Undervoltage Lockout Measured on VCC 10.25 10.7 V VCCHY VCC UVLO Hysteresis Measured on VCC 3.8 4.2 V ICCST Start-Up Current VCC = VUVLO – 0.3V ● 145 230 µA ICCRN Operating Current No Load on Outputs 3 8 mA VSHUNT Shunt Regulator Voltage Current into VCC = 10mA 10.3 10.8 V RSHUNT Shunt Resistance Current into VCC = 10mA to 17mA 1.4 3.5 Ω SUVLO System UVLO Threshold Measured on UVLO Pin, 10mA into VCC 4.8 5.0 5.2 V SHYST System UVLO Hysteresis Current Current Flows Out of UVLO Pin, 10mA into VCC 8.5 10 11.5 µA Pulse Width Modulator ROS Ramp Offset Voltage Measured on COMP, RAMP = 0V 0.65 V

IRMP Ramp Discharge Current RAMP = 1V, COMP = 0V, CT = 4V, 3723-1 Only 50 mA

372312f 2 LTC3723-1/LTC3723-2

ISLP Slope Compensation Current Measured on CS, CT = 1V, 3723-1 Only 30 µA CT = 2.25V 68 µA DCMAX Maximum Duty Cycle COMP = 4.5V ● 47 48.2 50 % DCMIN Minimum Duty Cycle COMP = 0V ● 0% DTADJ Dead-Time 130 ns Oscillator

OSCI Initial Accuracy TA = 25°C, CT = 270pF 220 250 280 kHz OSCT VCC Variation VCC = 6.5V to 9.5V, Overtemperature ● –3 3 % OSCV CT Ramp Amplitude Measured on CT 2.35 V Error Amplifier

VFB FB Input Voltage COMP = 2.5V, (Note 3) 1.172 1.2 1.22 V FBI FB Input Range Measured on FB, (Note 4) –0.3 2.5 V AVOL Open-Loop Gain COMP = 1V to 3V, (Note 3) 70 90 dB

IIB Input Bias Current COMP = 2.5V, (Note 3) 5 50 nA VOH Output High Load on COMP = –100µA 4.7 4.92 V VOL Output Low Load on COMP = 100µA 0.27 0.5 V ISOURCE Output Source Current COMP = 2.5V 400 700 µA ISINK Output Sink Current COMP = 2.5V 2 5 mA Reference

VREF Initial Accuracy TA = 25°C, Measured on VREF 4.925 5.00 5.075 V REFLD Load Regulation Load on VREF = 100µA to 5mA 2 15 mV REFLN Line Regulation VCC = 6.5V to 9.5V 1 10 mV REFTV Total Variation Line, Load and Temperature ● 4.900 5.000 5.100 V

REFSC Short-Circuit Current VREF Shorted to GND 18 30 45 mA Push-Pull Outputs

DRVH(x) Output High Voltage IOUT(x) = –100mA 9.0 9.2 V DRVL(x) Output Low Voltage IOUT(x) = 100mA 0.17 0.6 V RDH(x) Pull-Up Resistance IOUT(x) = –10mA to –100mA 2.9 4 Ω RDL(x) Pull-Down Resistance IOUT(x) = –10mA to –100mA 1.7 2.5 Ω TDR(x) Rise-Time COUT(x) = 1nF 10 ns TDF(x) Fall-Time COUT(x) = 1nF 10 ns Synchronous Outputs

OUTH(x) Output High Voltage IOUT(x) = –30mA 9.0 9.2 V OUTL(x) Output Low Voltage IOUT(x) = 30mA 0.44 0.6 V RHI(x) Pull-Up Resistance IOUT(x) = –10mA to -30mA 11 15 Ω RLO(x) Pull-Down Resistance IOUT(x) = –10mA to -30mA 15 20 Ω TR(x) Rise-Time COUT(x) = 50pF 10 ns TF(x) Fall-Time COUT(x) = 50pF 10 ns Current Limit and Shutdown CLPP Pulse by Pulse Current Limit Threshold Measured on CS 280 300 320 mV CLSD Shutdown Current Limit Threshold Measured on CS 475 600 725 mV CLDEL Current Limit Delay to Output 100mV Overdrive on CS, (Note 2) 80 ns

372312f 3 LTC3723-1/LTC3723-2

ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SSI Soft-Start Current SS = 2.5V 10 13 16 µA SSR Soft-Start Reset Threshold Measured on SS 0.7 0.4 0.1 V FLT Fault Reset Threshold Measured on SS 4.5 4.2 3.5 V

Note 1: Absolute Maximum Ratings are those values beyond which the life performance specifications from 0°C to 70°C. Specifications over the of a device may be impaired. –40°C to 85°C operating temperature range are assured by design, Note 2: Includes leading edge blanking delay, RLEB = 20k, not tested in characterization and correlation with statistical process controls. production. Note 6: This IC includes overtemperature protection that is intended to Note 3: FB is driven by a servo loop amplifier to control VCOMP for these protect the device during momentary overload conditions. Junction tests. temperature will exceed 125°C when overtemperature protection is active. Note 4: Set FB to –0.3V, 2.5V and insure that COMP does not phase invert. Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: The LTC3723E–1/LTC3723E-2 are guaranteed to meet UW

TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C unless otherwise noted) Oscillator Frequency vs Start-Up ICC vs VCC VCC vs ISHUNT Temperature 200 10.50 260 CT = 270pF

150 10.25 250 A) µ (V)

( 100 10.00 240 CC CC V I FREQUENCY (kHz) 50 9.75 230

0 9.50 220 0 2 4 6 8 10 0 10 20 30 40 50 –60–40 –200 20 40 6080 100 VCC (V) ISHUNT (mA) TEMPERATURE (°C)

372312 G01 372312 G02 372312 G03

Leading Edge Blanking Time vs RLEB VREF vs IREF VREF vs Temperature 350 5.05 5.01

300 TJ = 25°C 5.00 5.00 250 TJ = 85°C

200 4.95 (V) (V) 4.99 REF REF V 150 V 4.90 BLANK TIME (ns) 100 TJ = –40°C 4.98 4.85 50

0 4.80 4.97 0 1020 3040 5060 70 80 90 100 0 5101520 2530 35 40 –60–40 –200 20 40 6080 100 RLEB (kΩ) IREF (mA) TEMPERATURE (°C)

372312 G04 372312 G05 372312 G06

372312f 4

LTC3723-1/LTC3723-2 UW

TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C unless otherwise noted)

LTC3723 Deadtime vs RDPRG With and Without 200k Prebias Error Amplifier Gain/Phase Start-Up ICC vs Temperature Compensation 190 275 100 180 250 80 60 170 225 200k PREBIAS 40 160 200 GAIN (dB) 20

0 A) 150 175 µ (

CC 140 150 I –180 DELAY (ns) NO 200k PREBIAS 130 125

–270 120 100

PHASE (DEG) –360 110 75

100 50 10100 1k 10k 100k1M 10M –55 –25 5 3565 95 125 0 50 100 150 200 250300 350 400 450 500 FREQUENCY (Hz) TEMPERATURE (°C) RDPRG (kΩ)

372312 G07 372312 G08 372312 G09

VCC Shunt Voltage vs Synchronous Driver Turn-Off Delay Slope Current vs Temperature Temperature vs RSPRG Referenced to CT Peak 90 10.5 900 ICC = 10mA 80 10.4 800 70 CT = 2.25V 700 10.3 60 600 A) µ 50 10.2 500

40 10.1 400 CT = 1V DELAY (ns) CURRENT ( 30 300

SHUNT VOLTAGE (V) 10.0 20 200 9.9 10 100

0 9.8 0 –55 –25 5 3565 95 125 –55 –25 5 3565 95 125 0 50 100 150 200 250 300 TEMPERATURE (°C) TEMPERATURE (°C) RSPRG (kΩ)

372312 G10 372312 G11 372312 G12

Synchronous Driver Turn-Off Delay vs RSPRG Referenced to FB Input Voltage vs Temperature Push-Pull Driver Outputs 1.205 350 RDPRG = 150k 1.204 300

1.203 250

1.202 200

1.201 150

1.200 DELAY (ns) 100 FB VOLTAGE (V) 1.199 50

1.198 0

1.197 –50 –55 –25 5 3565 95 125 0 50100 150 200 250 300 TEMPERATURE (°C) RSPRG (kΩ)

372312 G13 372312 G14 372312f 5

LTC3723-1/LTC3723-2

U U PI DESCRIPTIO S (LTC3723-1/LTC3723-2)

VREF (Pin 1/Pin 1): Output of the 5.0V Reference. VREF is mended. VIN and VREF bypass capacitors must be termi- capable of supplying up to 18mA to external circuitry. VREF nated with a star configuration as close to GND as practical should be decoupled to GND with a 0.47µF ceramic for best performance. capacitor. CT (Pin 8/Pin 8): Timing Capacitor for the Oscillator. Use SDRB (Pin 2/Pin 2): 50mA Driver for Synchronous Recti- a ±5% or better low ESR ceramic capacitor for best fier associated with DRVB. results. CT ramp amplitude is 2.35V peak-to-peak SDRA (Pin 3/Pin 3): 50mA Driver for Synchronous Recti- (typical). fier associated with DRVA. DPRG (Pin 9/Pin 12): Programming Input for Push-Pull DRVB (Pin 4/Pin 4): High Speed 1.5A Sink, 1A Source Dead-Time. Connect a resistor between DPRG and VREF Totem Pole MOSFET Driver. Connect to gate of external to program the dead-time. The nominal voltage on DPRG push-pull MOSFET with as short a PCB trace as practical is 2V. to preserve drive signal integrity. A low value resistor RAMP (N/A/Pin 9): Input to PWM Comparator for connected between DRVA and the MOSFET gate is op- LTC3723-2 Only (Voltage Mode Controller). The voltage tional and will improve the gate drive signal quality if the on RAMP is internally level shifted by 650mV. PCB trace from the driver to the MOSFET cannot be made CS (Pin 10/Pin 10): Input to Pulse-by-Pulse and Overload short. Current Limit Comparators, Output of Slope Compensa- VCC (Pin 5/Pin 5): Supply Voltage Input to the LTC3723-1/ tion Circuitry. The pulse-by-pulse comparator has a nomi- LTC3723-2 and 10.25V Shunt Regulator. The chip is nal 300mV threshold, while the overload comparator has enabled after VCC has risen high enough to allow the VCC a nominal 600mV threshold. An internal switch discharges shunt regulator to conduct current and the UVLO com- CS to GND after every timing period. Slope compensation parator threshold is exceeded. Once the VCC shunt regu- current flows out of CS during the PWM period. lator has turned on, VCC can drop to as low as 6V (typical) An external resistor connected from CS to the external and maintain operation. Bypass VCC to GND with a high current sense resistor programs the amount of slope quality 1µF or larger ceramic capacitor to supply the compensation. transient currents caused by the high speed switching and COMP (Pin 11/Pin 11): Error Amplifier Output, Inverting capacitive loads presented by the on chip totem pole Input to Phase Modulator. drivers. R (Pin 12/N/A): Timing Resistor for Leading Edge DRVA (Pin 6/Pin 6): High Speed 1.5A Sink, 1A Source LEB Blanking. Use a 10k to 100k resistor connected between Totem Pole MOSFET Driver. Connect to gate of external R and GND to program from 40ns to 310ns of leading push-pull MOSFET with as short a PCB trace as practical LEB edge blanking of the current sense signal on CS for the to preserve drive signal integrity. A low value resistor LTC3723-1. A ±1% tolerance resistor is recommended. connected between DRVA and the MOSFET gate is op- The LTC3723-2 has a fixed blanking time of approximately tional and will improve the gate drive signal quality if the 80ns. The nominal voltage on R is 2V. If leading edge PCB trace from the driver to the MOSFET cannot be made LEB blanking is not required, tie R to V to disable. short. LEB REF FB (Pin 13/Pin 13): Error Amplifier Inverting Input. This is GND (Pin 7/Pin 7): All circuits in the LTC3723 are refer- the voltage feedback input for the LTC3723. The nominal enced to GND. Use of a ground plane is highly recom- regulation voltage at FB is 1.2V.

372312f 6

LTC3723-1/LTC3723-2 U

PI DESCRIPTIO SU (LTC3723-1/LTC3723-2) SS (Pin 14/Pin 14): Soft-Start/Restart Delay Circuitry threshold is exceeded, the LTC3723-1/LTC3723-2 com- Timing Capacitor. A capacitor from SS to GND provides a mences a soft-start cycle and a 10µA (nominal) current is controlled ramp of the current command (LTC3723-1) or fed out of UVLO to program the desired amount of system duty cycle (LTC3723-2). During overload conditions, SS is hysteresis. The hysteresis level can be adjusted by chang- discharged to ground initiating a soft-start cycle. SS ing the resistance of the divider. UVLO can also be used to charging current is approximately 13µA. SS will charge up terminate all switching by pulling UVLO down to less than to approximately 5V in normal operation. During a con- 4V. An open drain or collector switch can perform this stant overload current fault, SS will oscillate at a low function without changing the system turn on or turn off frequency between approximately 0.5V and 4V. voltages. UVLO (Pin 15/Pin 15): Input to Program System Turn-On SPRG (Pin 16/Pin 16): A resistor is connected between and Turn-Off Voltages. The nominal threshold of the UVLO SPRG and GND to set the turn off delay for the synchro- comparator is 5.0V. UVLO is connected to the main DC nous rectifier driver outputs. The nominal voltage on

system feed through a resistor divider. When the UVLO SPRG is 2V.

U W

TI IW G DIAGRA

PROGRAMMABLE PROGRAMMABLE SYNCHRONOUS DEAD-TIME TURN-OFF DELAY DRVA

DRVB

SDRA

SDRB

CURRENT SENSE OR CT RAMP PWM COMPARATOR 372312 TD01 (–)

372312f 7 LTC3723-1/LTC3723-2

BLOCK DIAGRA SW

LTC3723-1 Block Diagram

VCC UVLO VREF CT DPRG SPRG 5 15 1 8 9 16

VCC UVLO 10µA REF, LDO 5V 1.2V 10.25V “ON” V 6V “OFF” CC REF GOOD

ERROR SYSTEM VCC AMPLIFIER UVLO GOOD FB 13 – +

3 SDRA 1.2V 5V + – SYNC RECTIFIER DRIVE PULSE WIDTH LOGIC 50k MODULATOR COMP 11 – 2 SDRB 14.9k

+ + OSCILLATOR 650mV – 1A SOURCE

Q R 6 DRVA Q T 1.5A SINK + S RQ Q

– VREF S

13µA 1A SOURCE

SS 14 4 DRVB SHUTDOWN CURRENT 1.5A SINK LIMIT + FAULT LOGIC

600mV –

SLOPE COMPENSATOR PULSE-BY-PULSE CURRENT LIMIT CS 10 BLANK +

RLEB 12 7 300mV – GND 372312 BD01

372312f 8 LTC3723-1/LTC3723-2

BLOCK DIAGRA SW

LTC3723-2 Block Diagram

VCC UVLO VREF CT SPRG 5 15 1 8 16

VCC UVLO 10µA REF, LDO 5V 1.2V 10.25V “ON” V 6V “OFF” CC REF GOOD

ERROR SYSTEM VCC AMPLIFIER UVLO GOOD FB 13 – +

3 SDRA 1.2V 5V + – SYNC RECTIFIER DRIVE PULSE WIDTH LOGIC 50k MODULATOR COMP 11 – 2 SDRB

+ + OSCILLATOR 650mV – RAMP 9 1A SOURCE

Q R 6 DRVA Q T 1.5A SINK S RQ + Q OUTPUT DRIVE S LOGIC – VREF 1A SOURCE

13µA 4 DRVB

SS 14 1.5A SINK SHUTDOWN CURRENT LIMIT + FAULT LOGIC

600mV –

PULSE-BY-PULSE CURRENT LIMIT CS 10 BLANK +

7 9 300mV – GND DPRG 372312 BD02

372312f 9 LTC3723-1/LTC3723-2

OPERATIOU Please refer to the detailed Block Diagrams for this discus- Programming Driver Dead-Time sion. The LTC3723-1 and LTC3723-2 are synchronous The LTC3723-1/LTC3723-2 controllers include a feature PWM push-pull controllers. The LTC3723-1 operates with to program the minimum time between the output signals peak pulse-by-pulse current mode control while the on DRVA and DRVB commonly referred to as the driver LTC3723-2 offers voltage mode control operation. They dead-time. This function will come into play if the control- are best suited for moderate to high power isolated power ler is commanded for maximum duty cycle. The dead-time systems where small size and high efficiency are required. is set with an external resistor connected between DPRG The push-pull topology delivers excellent transformer and VREF (see Figure 1). The nominal regulated voltage on utilization and requires only two low side power MOSFET DPRG is 2V. The external resistor programs a current switches. Both controllers generate 180° out of phase which flows into DPRG. The dead-time can be adjusted 0% to <50% duty cycle drive signals on DRVA and DRVB. from 90ns to 300ns with this resistor. The dead-time can The external MOSFETs are driven directly by these power- also be modulated based on an external current source ful on-chip drivers. The external MOSFETs typically con- that feeds current into DPRG. Care must be taken to limit trol opposite primary windings of a centertapped power the current fed into DPRG to 350µA or less. An internal transformer. The centertap primary winding is connected 10µA current source sets a maximum deadtime if DPRG is to the input DC feed. The secondary of the transformer can floated. The internal current source causes the programmed be configured in different synchronous or nonsynchronous deadtime to vary non-linearly with increasing values of configurations depending on the application needs. RDPRG (see typical performance characteristics). An ex- The duty ratio is controlled by the voltage on COMP. A ternal 200k resistor connected from DPRG to GND will switching cycle commences with the falling edge of the compensate for the internal 10µA current source and internal oscillator clock pulse. The LTC3723-1 attenuates linearize the deadtime delay vs RDPRG characteristic. the voltage on COMP and compares it to the current sense signal to terminate the switching cycle. The LTC3723-2 Powering the LTC3723-1/LTC3723-2 compares the voltage on COMP to a timing ramp to The LTC3723-1/LTC3723-2 utilize an integrated VCC shunt terminate the cycle. The LTC3723-2’s CT waveform can be regulator to serve the dual purposes of limiting the voltage used for this purpose or separate R-C components can be applied to VCC as well as signaling that the chip’s bias connected to RAMP to generate the timing ramp. If the voltage is sufficient to begin switching operation (under voltage on CS exceeds 300mV, the present cycle is termi- voltage lockout). With its typical 10.2V turn-on voltage nated. If the voltage on CS exceeds 600mV, all switching and 4.2V UVLO hysteresis, the LTC3723-1/LTC3723-2 is stops and a soft-start sequence is initiated. tolerant of loosely regulated input sources such as an auxiliary transformer winding. The V shunt is capable of The LTC3723-1 / LTC3723-2 also provide drive signals for CC sinking up to 40mA of externally applied current. The secondary side synchronous rectifier MOSFETs. Synchro- UVLO turn-on and turn-off thresholds are derived from an nous rectification improves converter efficiency, espe- internally trimmed reference making them extremely ac- cially as the output voltages drop. Independent turn-off curate. In addition, the LTC3723-1/LTC3723-2 exhibits control of the synchronous rectifiers is provided via SPRG in order to optimize the benefit of the synchronous recti- VREF fiers. A resistor from SPRG to GND sets the desired turn RDPRG off delay. DPRG 10µA A host of other features including an error amplifier, + + OPTIONAL 200k TURN-ON system UVLO programming, adjustable leading edge blank- V 2V OUTPUT ing, slope compensation and programmable dead-time – 2.5V – provide flexibility for a variety of applications. 372312 F01 Figure 1. Delay Timeout Circuitry 372312f 10 LTC3723-1/LTC3723-2

OPERATIOU very low (145µA typ) start-up current that allows the use UVLO. The amount of DC feed hysteresis provided by this of 1/8W to 1/4W trickle charge start-up resistors. current is: 10µA • RTOP, (Figure 3). The system UVLO The trickle charge resistor should be selected as follows: threshold is: 5V • {(RTOP + RBOTTOM)/RBOTTOM}. If the RSTART(MAX) = VIN(MIN) – 10.7V/250µA voltage applied to UVLO is present and greater than 5V prior to the V UVLO circuitry activation, then the internal Adding a small safety margin and choosing standard CC UVLO logic will prevent output switching until the follow- values yields: ing three conditions are met: (1) VCC UVLO is enabled, (2) APPLICATION VIN RANGE RSTART VREF is in regulation and (3) UVLO pin is greater than 5V. DC/DC 36V to 72V 100k UVLO can also be used to enable and disable the power Off-Line 85V to 270VRMS 430k converter. An open drain transistor connected to UVLO as PFC Preregulator 390VDC 1.4M shown in Figure 3 provides this capability.

VCC should be bypassed with a 0.1µF to 1µF multilayer ceramic capacitor to decouple the fast transient currents RTOP demanded by the output drivers and a bulk tantalum or UVLO electrolytic capacitor to hold up the VCC supply before the bootstrap winding, or an auxiliary regulator circuit takes ON OFF RBOTTOM over.

372312 F03 CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V (minimum UVLO hysteresis) Figure 3. System UVLO Setup Regulated bias supplies as low as 7V can be utilized to Off-Line Bias Supply Generation provide bias to the LTC3723-1/LTC3723-2. Refer to Figure 2 for various bias supply configurations. If a regulated bias supply is not available to provide VCC voltage to the LTC3723-1/LTC3723-2 and supporting VIN circuitry, one must be generated. Since the power require- 12V ±10% VBIAS < VUVLO ment is small, approximately 1W, and the regulation is not 1N5226 1.5k 3V 1N914 RSTART critical, a simple open-loop method is usually the easiest + and lowest cost approach. One method that works well is 1µF 1µF CHOLD to add a winding to the main power transformer, and post

VCC VCC 372312 F02 regulate the resultant square wave with an L-C filter (see Figure 4a). The advantage of this approach is that it Figure 2. Bias Configurations maintains decent regulation as the supply voltage varies, Programming Undervoltage Lockout and it does not require full safety isolation from the input winding of the transformer. Some manufacturers include The LTC3723-1/LTC3723-2 provides undervoltage lock- a primary winding for this purpose in their standard out (UVLO) control for the input DC voltage feed to the power converter in addition to the V UVLO function VIN CC VCC described in the preceding section. Input DC feed UVLO is RSTART provided with the UVLO pin. A comparator on UVLO compares a divided down input DC feed voltage to the 5V + 2k 15V* 1 F precision reference. When the 5V level is exceeded on CHOLD µ

UVLO, the SS pin is released and output switching com- 372312 F04a *OPTIONAL mences. At the same time a 10µA current is enabled which flows out of UVLO into the voltage divider connected to Figure 4a. Auxiliary Winding Bias Supply 372312f 11 LTC3723-1/LTC3723-2

OPERATIOU product offerings as well. A different approach is to add a Figure 5, the leading edge of an external pulse is used to winding to the output inductor and peak detect and filter terminate the natural clock cycle. If the external frequency the square wave signal (see Figure 4b). The polarity of this is higher than the oscillator frequency, the internal oscil- winding is designed so that the positive voltage square lator will synchronize with the external input frequency. wave is produced while the output inductor is freewheeling. An advantage of this technique over the previous is LTC3723 that it does not require a separate filter inductor and since fOSC < fEXT < 1.25 • fOSC C the voltage is derived from the well-regulated output T voltage, it is also well controlled. One disadvantage is that EXTERNAL CT this winding will require the same safety isolation that is FREQUENCY SOURCE required for the main transformer. Another disadvantage 68pF 390Ω BAT54 is that a much larger V filter capacitor is needed, since 210µA CC fSW = fOSC/2 fOSC ≅ 2.56V • CT it does not generate a voltage as the output is first starting 372312 F05 up, or during short-circuit conditions. Figure 5. Synchronization from External Source

VIN VOUT LOUT Single-Ended Operation R + START ISO BARRIER In addition to push-pull and full-bridge topologies, single- ended topologies such as the forward and flyback converter can benefit from the many advanced features of the 1µF CHOLD LTC3723. In Figure 6, the LTC3723 is used with the LTC4440, 100V high side driver to implement a two- 372312 F04b VCC transistor forward converter. DRVB is used which limits the converter’s maximum duty cycle to 50% (less pro- Figure 4b. Output Inductor Bias Supply grammable driver dead time).

Programming the LTC3723-1/LTC3723-2 Oscillator VIN The high accuracy LTC3723-1/LTC3723-2 oscillator cir- TG LTC4440 cuit provides flexibility to program the switching fre- IN TS

GND • quency and slope compensation required for current mode control (LTC3723-1). The oscillator circuit produces a 2.35V peak-to-peak amplitude ramp waveform on C . Typical maximum duty cycles of 49% are possible. The T –VIN oscillator is capable of operation up to 1MHz by the following equation: DRVB TO SYNCHRONOUS SDRB SECONDARY MOSFET C = 1/(14.8k • F ) LTC3723 T OSC 210µA C GND fSW ≅ T 2 • 2.56V • C Note that this is the frequency seen on CT. The output T drivers switch at 1/2 of this frequency. Also note that higher switching frequency and added driver dead-time CT via DPRG will reduce the maximum duty cycle. 372312 F06 Figure 6. Two-Transistor Forward Converter (Duty Cycle < 50%) The LTC3723-1/LTC3723-2 can be synchronized to an external frequency source such as another PWM chip. In

372312f 12 LTC3723-1/LTC3723-2

OPERATIOU The 50% duty-cycle limit is overcome with the circuit Voltage Mode with LTC3723-2 shown in Figure 7. Operation is similar to external syn- Figure 9 shows how basic connections differ between chronization, except DRVA output is used to terminate its current mode LTC3723-1 and voltage mode LTC3723-2. own clock cycle early. Switching period is now equal to the Oscillator may be used as the ramp input or the LTC3723- oscillator period plus programmable driver dead time. 2 includes an internal 10mA ramp discharge useful when Maximum on time is equal to oscillator period minus implementing voltage feedforward. Open loop control in driver dead time. which the duty cycle varies inversely proportional to input Although near 100% duty cycle operation may be of voltage is shown in Figure 10. benefit with non-isolated converters, it is often desirable to limit the duty cycle of single-ended isolated converters.

Instead of immediately ending the unused clock’s output, LTC3723-1 Figure 8 uses a transistor to switch in additional timing CT DPRG VREF RLEB capacitor charge current. This allows one to preset the 819 12 maximum duty. CT RDPRG RLEB

DRVA DRVB TO INPUT VOLTAGE LTC3723-1 1 CT fSW ≅ ⎛ 256.•VCT ⎞ ⎜ + TDPRG⎟ LTC3723-2 LTC3723-2 ⎝ 210µA ⎠ C T CT RAMP VREF DPRG RAMPCT VREF DPRG ⎛ ⎞ 256.•VCT 8129 1 9128 1 DfMAX≅ SW⎜ – TDPRG⎟ 68pF ⎝ 210µA ⎠ 390Ω BAT54 R R CT DPRG CT DPRG

372312 F09

372312 F07 Figure 9. LTC3723-1 Current Mode and LTC3723-2 Voltage Figure 7. LTC3723-1 > 50% Duty Cycle Mode Connections

V TO INPUT IN • VOLTAGE

LTC3723-2 13 –V FB IN CT RAMP COMP 8119 DRVB DRVA SDRB TO SYNCHRONOUS SECONDARY MOSFET CT LTC3723-1 50k V REF CT 1 fSW ≅ ⎛ 1 1 ⎞ 372312 F10 R 256.•VCT ⎜ + ⎟ MMBT2369 ⎝ 210µAAR210µ+() 3 / ⎠ Figure 10. LTC3723-2 Open Loop Control (Duty Cycle is

CT ⎛ 256.•VCT ⎞ Inversely Proportional to Input Voltage) DfMAX≅ SW⎜ – TDPRG⎟ ⎝ 210µA ⎠ 372312 F08

Figure 8. LTC3723-1 One-Switch Forward or Flyback Converter (Maximum Duty Cycle 50% to 100%)

372312f 13 LTC3723-1/LTC3723-2

OPERATIOU The LTC3723-1 derives a compensating slope current The pulse-by-pulse comparator has a 300mV nominal from the oscillator ramp waveform and sources this threshold. If the 300mV threshold is exceeded, the PWM current out of CS. This function is disabled in the cycle is terminated. The overcurrent comparator is set LTC3723-2. The desired level of slope compensation is approximately 2x higher than the pulse-by-pulse level. If selected with an external resistor connected between CS the current signal exceeds this level, the PWM cycle is and the external current sense resistor, (Figure 11). terminated, the soft-start capacitor is quickly discharged and a soft-start cycle is initiated. If the overcurrent condi- Current Sensing and Overcurrent Protection tion persists, the LTC3723-1/LTC3723-2 halts PWM op- Current sensing provides feedback for the current mode eration and waits for the soft-start capacitor to charge up control loop and protection from overload conditions. The to approximately 4V before a retry is allowed. The soft- LTC3723-1/LTC3723-2 are compatible with either resis- start capacitor is charged by an internal 13µA current tive sensing or current transformer methods. Internally source. If the fault condition has not cleared when soft- connected to the LTC3723-1/LTC3723-2 CS pin are two start reaches 4V, the soft-start pin is again discharged and comparators that provide pulse-by-pulse and overcurrent a new cycle is initiated. This is referred to as hiccup mode shutdown functions respectively, (Figure 12). operation. In normal operation and under most abnormal conditions, the pulse-by-pulse comparator is fast enough to prevent hiccup mode operation. In severe cases, how- LTC3723 SWITCH V(CT) CURRENT ever, with high input voltage, very low RDS(ON) MOSFETs I = R CT 33k CS SLOPE and a shorted output, or with saturating magnetics, the ADDED RCS 33k SLOPE overcurrent comparator provides a means of protecting the power converter. CURRENT SENSE

WAVEFORM 372312 F11 Leading Edge Blanking Figure 11. Slope Compensation Circuitry The LTC3723-1/LTC3723-2 provides programmable leading edge blanking to prevent nuisance tripping of the H = SHUTDOWN PWM OUTPUTS LATCH UVLO current sense circuitry. Leading edge blanking relieves the PULSE BY PULSE PWM ENABLE Q CURRENT LIMIT LOGIC filtering requirements for the CS pin, greatly improving the + PWM SQ Q S CS response to real overcurrent conditions. It also allows the 300mV – R OVERLOAD use of a ground referenced current sense resistor or CURRENT LIMIT

RCS transformer(s), further simplifying the design. With a

+ –

4.1V 13µA SQ + 600mV – single 10k to 100k resistor from RLEB to GND, blanking SS

UVLO R + times of approximately 40ns to 320ns are programmed. If ENABLE 0.4V CSS

– not required, connecting RLEB to VREF can disable leading

Q edge blanking. Keep in mind that the use of leading edge blanking will slightly reduce the linear control range for the 372312 F12 pulse width modulator. Figure 12. Current Sense/Fault Circuitry Detail

372312f 14 LTC3723-1/LTC3723-2

OPERATIOU High Current Drivers new primary side power delivery pulse. This feature pro- The LTC3723-1/LTC3723-2 high current, high speed driv- vides optimized timing for the synchronous MOSFETs ers provide direct drive of external power N-channel which improves efficiency. At higher load currents it MOSFET switches. The drivers swing from rail to rail. Due becomes more advantageous to delay the turn-off of the to the high pulsed current nature of these drivers (1.5A synchronous rectifiers until the beginning of the new sink, 1A source), care must be taken with the board layout power pulse. This allows for secondary freewheeling current to flow through the synchronous MOSFET channel to obtain advertised performance. Bypass VCC with a 1µF minimum, low ESR, ESL ceramic capacitor. Connect this instead of its body diode. capacitor with minimal length PCB leads to both VCC and The turn-off delay is programmed with a resistor from GND. A ground plane is highly recommended. The driver SPRG to GND, (Figure 13). The nominal regulated voltage output pins (DRVA, DRVB) connect to the gates of the on SPRG is 2V. The external resistor programs a current external MOSFET switches. The PCB traces making these which flows out of SPRG. The delay can be adjusted from connections should also be as short as possible to mini- approximately 20ns to 200ns, with resistor values of 10k mize overshoot and undershoot of the drive signal. to 200k. Do not leave SPRG floating. The amount of delay can also be modulated based on an external current Synchronous Rectification source that sinks current out of SPRG. Care must be taken The LTC3723-1/LTC3723-2 produces the precise timing to limit the current out of SPRG to 350µA or less. signals necessary to control secondary side synchronous SPRG rectifier MOSFETs on SDRA and SDRB. Synchronous rectifiers are used in place of Schottky or silicon diodes on + + TURN-OFF RSPRG the secondary side to improve converter efficiency. As V 2V SYNC OUT – MOSFET RDS(ON) levels continue to drop, significant effi- – ciency improvements can be realized with synchronous 372312 F13 rectification, provided that the MOSFET switch timing is optimized. Synchronous rectification also provides bipo- Figure 13. Synchronous Delay Circuitry lar output current capability, that is, the ability to sink as well as source current.

Programming the Synchronous Rectifier Turn-Off Delay The LTC3723-1/LTC3723-2 controllers include a feature to program the turn-off edge of the secondary side synchronous rectifier MOSFETs relative to the beginning of a

372312f 15 LTC3723-1/LTC3723-2

TYPICAL APPLICATIOU S

OUT

372312 TA02

–V

Ω

OUT

1/4W

100

9.1V

–V

OUT

8.5V

OUT

–V

Ω

100

C4 3.3 50V

470

F, 100V TDK C3225X7R2A105M

1 C1-C3: SANYO 6TPB470M C4: TDK C3225X7R1H335M C5: AVX TPSE686M020R0150 C6: MURATA DE2E3KH222MB3B D1, D2: DIODES INC. ES1A D4, D5: BAS21 D6: MMBD5239B D7: BAT54 L4: COILCRAFT DO1608C-105 L5: VISHAY IHLP-2525CZ-01 L6: PULSE PA1294.650 Q1: FZT690B Q2: FMMT3904 R1, R2: IRC LRC-LR2512-01-R060-G T1: EFD25 TRANSPOWER TTI8696 T2: PULSE PA0785

40.2k

OUT

–V

Ω

390pF

0.68

330

316

C1, C2, C3 470 6.3V ×

OUT

ME V

TIMER

Ω

–

4.99k

Ω

CSE

0.022

270

4.99k 1/4W

CSE

Ω

2.49k

787

LTC3901EGN

OUT

Si7892DP

–V

GND PGND GND PGND

–

4.99k

Ω

CSF

L6 0.65

360

4.99k 1/4W

GND-S

CSF

SYNC PV

8.5V

7 8

11 12

LT1431CS8

Si7892DP

GND-F

Ω

220pF

• • COLL REF

100

H):9T:7T:1T:1T

µ • • •

3 2

5 49

9T(150

47nF

••

1(1.5mH):0.5

100k

0.1

1mH

20V

C5 68

250V

Ω

2.2nF

10V

MOC207

Ω

Si7450DP

0.47

Ω

100pF 200V

820

80 1W

165W, 36V to 72V to 3.3V at 50A Isolated Push-Pull Converter

REF

SDRA

COMP

150k

68nF

DPRG

DRVB SDRB

Ω

R2 0.06 1.5W

470

Ω

Si7450DP

GND

Ω

75k

100pF 200V

330pF

LTC3723EGN-1

33k

R1 0.06 1.5W

80 1W

LEB

10k

610

SPRG

DRVA CS

1 100V ×

UVLO V

220pF

Ω

100 1/4W

100V

10V

30k

383k

66.5k

–V

V 372312f 16 LTC3723-1/LTC3723-2

TYPICAL APPLICATIOU S

372312 TA03

OUT

–V

D1 4.3V

0.47

OUT

47 16V ×

1nF

F, 25V TDK C4532X5R1E106M F, 16V SANYO 16TQC47M

F, 100V TDK C3225X7R2A105M (1210)

µ µ

26.1k

10 47 D1: MMBZ5229B L1: COILCRAFT DO1813P-561HC L2: TDK SLF12575T-150M4R7 L3: TDK SLF10145T-330M1R6 1 L4: COILCRAFT DO1608C-105 T1: PULSE PA1040 T2: PULSE PA0785 (1:0.5T)

Ω

1.5nF

220pF

12 1/2W

12 1/4W

0.1

OUT

21.5k

1.13k

680pF

Ω

10k

2.7k

909

–

22nF

Si7456DP

MMBD914

GND

470pF

LTC3900ES8

1.00k

1.5k

10 25V

0.1

GND

LT4430ES6

SYNC TIMER

15nF

COMP

OPTO

2.7k

Si7456DP

MMBD914

Ω

560

5 • 4.7nF

Ω

Ω •

5 6

1 •

1/4W •

1/4W

220pF

• T1 •

EFD20

MOC207

220pF

250V

2.2nF

BAS21

Ω

to 12V/5A and –12V/1.6A Forward Converter

750

REF

1mH

1.5nF 200V

to 72V

10V

Ω

20V

22nF

SDRB

0.03 1W

158K

REF

COMP

REF

1.78K

REF

174k

Si7450DP

0.47

DPRG V

120pF

LTC3723-1 36V

RLEB

DRVB

33k

SPRG

LTC3723EGN-1

10k

220pF

813

10nF

DRVA

100V ×

GND SS FB

UVLO V

8.66k

MMBT2369

REF

OUTPUT POWER (W)

10V

Ω

40 50 60

4.7

1/4W

100

50k

30k

48V

100V

IN IN EFFICIENCY (%) EFFICIENCY

383k

–V

66.5k 372312f 17 LTC3723-1/LTC3723-2

TYPICAL APPLICATIOU S

D7 10V

372312 TA04

OUT

4.7

MMBT3904

OUT

Ω

OUT

12V/20A

–V

100

OUT

42.2k

–V

F, 100V TDK C3225X7R2A105M

Ω

1 C1,C2: SANYO 16TQC47M C3: AVX TPSE686M020R0150 C4: MURATA GHM3045X7R222K-GC D2: DIODES INC. ES1B D3-D6: BAS21 D7, D8: MMBZ5240B L4: COILCRAFT DO1608C-105 L5: COILCRAFT DO1813P-561HC L6: PULSE PA1294.132 OR PANASONIC ETQP1H1R0BFA R1, R2: IRC LRC2512-R03G T1: PULSE PA0805.004 T2: PULSE PA0785

470pF 100V

10 1W

470pF

C1, C2 47 16V ×

22nF

10k

V • 23 16

OUT

ME ME2

Ω

–V

9.53k

2.49k

–

866

1.25

CSE

Ω

6.19k 1/4W

1/4W

100

CSE

11 7 41013

GND-S

1 100V

LTC3901EGN

Si7370DP

1.45")

14 15

LT1431CS8

GND PGND GND2 PGND2 TIMER

MF MF2

GND-F

Ω

COLL REF

–

866

CSF

0.1

D8 10V

6.19k 1/4W

11 12

CSF

SYNC PV

22nF

Ω

11 9

Si7370DP • • 220pF

100

100k • • • 2

HMIN):6T:2T:2T

4 3

Ω

• C4

665

250V

2.2nF

MOC207

4T:6T(65 • 5

1(1.5mH):0.5

22nF

Si7852DP

0.1

1mH

to 12V/20A Isolated 1/4Brick (2.3"

Ω

SNS

12V

Ω

330pF

750

20V

4.7

COMP

to 56V

0.1

SDRA

243k

REF

SNS

BOOST

SDRB

12V

150k

GND

0.47

68nF

LTC4440ES6

1.5k

INP

Ω

DPRG V

R2 0.03 1.5W

RLEB

33k

Si7852DP

Ω

Si7852DP

LTC3723EGN-1

SPRG

R1 0.03 1.5W

10k

270pF

LTC3723-1 240W 42V

DRVB

Ω

GND SS

4.7

DRVA

FB C

0.1

UVLO

Ω

200 1/4W

BOOST

12V

GND

16 18 20

LTC4440ES6

1.5nF

INP

30k

1/4W

464k

1 100V ×

IN IN IN

42V 48V

56V

66.5k

LOAD CURRENT (A)

1 100V

0.56

81012

IN IN

–V EFFICIENCY (%) EFFICIENCY

42V TO 56V

372312f 18 LTC3723-1/LTC3723-2

TYPICAL APPLICATIOU S

LTC3723-1 300W 42VIN to 56VIN to 12V/25A Isolated Bus Converter

ES1B +VOUT L1 VIN VF 0.56µH 1nF 1.2k VIN 100V 0.5W 1µF 1µF 12V 12V 100V 100V BAS21 BAS21 10Ω 0.33µF T1 1W ES1B 100V –VIN ×3 V 29.46mm 25.4mm 10.2mm PLANAR E V 1 1 × × E –VOUT

V V • 3 CC 6 3 CC 6 2 11 +VOUT B INP BOOST A INP BOOST • 9

• +V LTC4440ES6 LTC4440ES6 OUT 5 4.7Ω 5 4.7Ω VF L2

TG TG 4 • 7 0.44µH GND TS GND TS 3 • HAT2169 HAT2169 2 4 Si7370DP 2 4 Si7370DP 0.1µF 0.1µF ×2 ×2 22µF 25V 2.2nF ×3 5 4.7µF 250V Si7370DP 5.1Ω 25V Si7370DP 1/4W 2x –VOUT A B –VOUT VF VE 1µF, 100V TDK C3225X7R2A105M +VOUT 100Ω L3 4.7µF, 25V TDK C4532X7R1E475M 12V 1mH BAS21 4.53k 4.53k 22 F, 25V TDK C4532X7R1E226M ISNS µ R1 2.67k 2.67k D1: MMBZ5240B • 0.015Ω 1 1k D2: MMBZ5242B + 1.5W 68µF BAS21 L1: COILCRAFT DO1813P-561HC 20V 1.27k 1.27k MMBT3904 L2: PULSE PA0513.441 6 L3: COILCRAFT DO1608C-105 11 12 14 15 6523 16 T1: PULSE PA0901.004 (4:4:4:4CT) + – + – 33.2k CSF CSF MF MF2 CSE CSE ME ME2 VCC T2: PULSE PA0785 (1:0.5T) 19T2 4 1 • • SYNCLTC3901EGN PVCC 22Ω D1 0.1µF GND PGND GND2 PGND2 TIMER 100Ω 1µF 10V 8 5 8 410137 4.7µF 220pF 470pF

VIN 12V –VOUT 30k MMBT3904 1/4W A B 97 13 ISNS 48VIN 6 4 2 3 53VIN 96 12 100 DRVA DRVB SDRB SDRA Ω 42V 1/4W IN 5 10 95 11 48VIN 464k VCC LTC3723EGN-1 CS 53VIN 15 11 UVLO COMP 94 10 FBGND CT SPRG RLEB SS DPRG VREF 42VIN

100pF 13 7 8 16 12 14 9 1 EFFICIENCY (%) 93 9

66.5k 150k OUTPUT VOLTAGE (V) 1µF 270pF 33k 24.9k D2 68nF 92 8 12V 10k 0.47µF 330pF 91 7 5 10 15 20 25 5 10 15 20 25

LOAD CURRENT (A) LOAD CURRENT (A) 372312 TA05

PACKAGE DESCRIPTIO U GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641)

.189 – .196* (4.801 – 4.978) .009 .015 ± .004 (0.229) × 45° .0532 – .0688 .004 – .0098 16 15 14 13 12 11 10 9 .045 ±.005 (0.38 ± 0.10) REF 0° – 8° (1.35 – 1.75) (0.102 – 0.249) .007 – .0098 TYP (0.178 – 0.249)

.229 – .244 .150 – .157** .016 – .050 .008 – .012 .0250 .254 MIN .150 – .165 (5.817 – 6.198) (3.810 – 3.988) (0.406 – 1.270) (0.203 – 0.305) (0.635) TYP BSC NOTE: 1. CONTROLLING DIMENSION: INCHES 3. DRAWING NOT TO SCALE INCHES 2. DIMENSIONS ARE IN *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH (MILLIMETERS) SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 123 4 5 6 7 8 .0165 ±.0015 .0250 BSC **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD RECOMMENDED SOLDER PAD LAYOUT FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 0204 372312f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3723-1/LTC3723-2

TYPICAL APPLICATIO U

LTC3723-1 100W, 36VIN to 72VIN to 3.3V/30A Isolated Forward Converter

L1 L2 VIN T1 VOUT 0.33µH 23.4mm × 20.1mm × 9.4mm PLANAR 0.85µH V V

IN • OUT 1 F 2 7 1 F µ µ 100V 4 2.2nF 100V 8 ×2 VX 100µF • –V •• IN 3 10 6.3V 5 Si7336ADP Si7336ADP 2 11 × + Si7450DP ×2 5.1Ω ×2 470µF 94 1/2W 6.3V 48VIN 2.2nF 2.2nF 630V 93 5.1Ω 1/2W 92 –VOUT

91 0.03Ω –VOUT 1W L3 90 10V 1mH BAS21 845Ω B0540W 89 • 15Ω EFFICIENCY (%) 1 VX + 1.00k 1/4W 68µF BAS21 88 820Ω 20V 6 B0540W 87 VREF 562Ω VB 86 5 10 15 20 25 30 5 1234 LOAD CURRENT (A) 120K + – 26.1k FG CS CS CG VCC 18T2 4 7 D1 VIN 10V • • SYNCLTC3900ES8 TIMER 10V 30k A 120pF 220pF 0.47 F 560Ω GND 1nF µ 6 4 10 8 5 25V 150 6 Ω 2 1/4W DRVA DRVB CS SDRB 5 –VOUT VCC 383k LTC3723EGN-1 15 10nF UVLO 11 COMP GND SSCT SPRG RLEB FB DPRG VREF 4.7nF 100pF 7 14 C 81316 12 9 1 330Ω 330Ω T V V 150k V REF OUT 10k REF 1µF 1 68nF MOC207 66.5k 33k 4.7nF 820Ω 220pF 0.47 F VB µ 6 1k 1 27.4k 5 V 1µF, 100V TDK C3225X7R2A105M (1210) COMP IN 470pF VREF 100µF, 6.3V TDK C3225X5R0J107M (1210) 5 2 4 LT4430ES6 FB A 2.2nF, 630V TDK C3216JB2J222K 6 50k 470µF, 6.3V SANYO 6TPD470M OPTO GND OC MMBT2369 D1: MMBZ5240B 2.2nF 6.04k L1: COILCRAFT DO1813P-331HC 2 3 250V 47nF 8.66k L2: PULSE PA1292.910 L3: COILCRAFT DO1608C-105 VIN C T1: PULSE PA810.007 (7:6:6:1:1:1T) T V T2: PULSE PA0184 (1:1T) OUT 372312 TA06

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372312f Linear Technology Corporation LT 1105 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 20 ● ● (408) 432-1900 FAX: (408) 434-0507 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003