Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials, Fukuoka, 2013, pp546-547 A-3-2

Chemical Vapor Deposition GeTe/Sb2Te 3 Super-Lattice Phase Change Memory

Masahito Kitamura, Takahiro Morikawa, Takasumi Ohyanagi, Mitsuharu Tai, Masaharu Kinoshita, Kenichi Akita, and Norikatsu Takaura

Low-power Electronics Association & Project West 7, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan Phone: +81-29-879-8262 E-mail: [email protected]

Abstract from the GeSbTe and GeTe/Sb2Te3 CVD films. The XRD This paper describes the fabrication and electrical data from the GeTe/Sb2Te3 CVD film had peak shifts in the properties of a CVD GeTe/Sb2Te3 Super-Lattice Phase hexagonal Sb2Te3. These peaks were different from those Change Memory. We present its excellent crystal of GeSbTe, and were caused by the c-axis orientation of structure and non-volatile operations for the first time GeTe on Sb2Te3. Therefore, they indicate the formation of in this paper. SL [4]. The TEM data showed atomic interference fringes, and those of the SL looked narrower than those of GeSbTe. 1. Introduction A GeTe/Sb2Te3 Super-lattice Phase Change Memory 3. Non-volatile Operation of CVD GeTe/Sb2Te3 (SL PCM) has been extensively investigated as the next We fabricated 2-terminal device implementing CVD generation of non-volatile memory. SL was proposed by J. GeTe/Sb2Te3 SL films. There were eight CVD GeTe/Sb2Te3 Tominaga [1, 2], and it is composed of thin GeTe and SL film periods, and the total thickness was 56 nm. The Sb2Te3 films. The GeTe is aligned in the direction of the contact size was 100 nm in diameter. Figures 9 and 10 c-axis of the Sb2Te3 in SL. This results in the short-range show the reset and set programming characteristics, respec- motion of the Ge atoms for changing the resistance states tively. The pulse timings (trailing edge/width/falling edge) (Fig. 1). A crystal-to-crystal change occurs in SL, which were 5/100/5 nsec for the reset operation and 100/700/1000 leads to a reduction in the write energies to less than 1/10 nsec for the set operation. A non-volatile recording between that for conventional GeSbTe [3, 4]. Rreset > 2 M and Rset < 30 kwas successfully confirmed On the other hand, not only the Physical Vapor Deposition at a resistance ratio of more than 10. Repeated operations at (PVD) but also Chemical Vapor Deposition (CVD) of a 1E+5 cycling endurance were demonstrated (Fig. 10). phase change materials have been investigated [5,6] to in- crease the bit density of PCM. In the long run, we believe 4. Further Improvement that CVD SL will become a key factor for continually in- We believe further improvement, such as longer endur- creasing the density of PCM. This paper presents a new ance and lower set and reset voltages, would be possible by CVD fabrication process for SL PCM. Set and reset char- optimizing the thickness of the GeTe/Sb2Te3 SL films. acteristics with good cycling endurance of 1E+5 times is also presented. 5. Conclusion CVD GeTe/Sb2Te3 Super-lattice phase change memory 2. GeTe/Sb2Te3 CVD on 300-mm Si wafer was created for the first time. The results from our XRD The main concerns when fabricating CVD GeTe / and TEM measurements verified that the synchronized and Sb2Te3 SL are the thickness and roughness of it (Table 1). unsynchronized supply of precursors made it possible to This work improved them by using a method that combines deposit a GeTe/Sb2Te3 super-lattice. We demonstrated a the synchronized and unsynchronized precursor supplies non-volatile SL CVD operation with a 1E+5 cycling en- (Fig. 2). This method was developed to fabricate GeTe and durance. Sb2Te3 using an identical deposition temperature. The SL films were deposited on Φ300-mm Si wafers (Table 2). A Acknowledgements bubbling method was used for the supply system of the This work was performed as an “Ultra-Low Voltage Device precursor, and nitrogen was used as the purge and carrier Project" funded and supported by METI and NEDO. A part of the gases. device processing was operated by the SCR operation office and Thin Sb Te , GeTe, and GeSbTe CVD films were suc- IBEC, AIST, Japan. We would like to thank the people at Hitachi 2 3 Kokusai Electrics Toyama Works for their fruitful discussions. cessfully fabricated using precursor molecules with planar

structures (Fig. 3). The composition of Sb-Te was depend- References ent on the Te precursor flow, and Sb Te was created using 2 3 [1] J. Tominaga et al., Jpn. J. Appl. Phys., 48 (2009) 03A053. a Te precursor flow rate of 30 cc (Fig. 4). The contaminants [2] R. E. Simpson et al., Nature Nanotech., 6 (2011) pp. 501-505. in the film were below the detection limit of XPS (Fig. 6). [3] N. Takaura et al., to be published in 2013 VLSI Technology. We also successfully created GeTe using a 3.6-cc Ge pre- [4] T. Ohyanagi et al., Proc. of ADMETAPlus 2012, pp152-153. cursor flow rate (Fig. 5). These films were deposited at a [5] H. Machida et al., Jpn. J. Appl. Phys., 49 (2010) 05FF06. temperature of 250 deg. (Figs. 7 and 8). [6] R. Y. Kim et al., APL, 89 (2006) 102107. Table 3 lists the XRD and TEM measurement results

- 546 - C‐axis Reset orientation Table 1 Main concern for GeTe/Sb2Te3 CVD. Table 2 CVD process conditions.

Sb2Te3 concern thickness roughness ideal Ge deposition Max. motion supply of Synchronized + GeTe Synchronized Unsynchronized temperature 400 deg Ge precursors Unsynchronized

motion Te Te Te Te Te Te Te Te Te Te Te Te Te Te Sb Te Te Te Te Te Te Te Te Te Te Te 2 3 Ge Ge Ge Ge Ge Ge Ge Ge Te Ge Ge Ge Ge Ge Ge wafer size 300 mm Ge Ge Ge Ge Ge Ge Ge Ge Ge Ge Ge Low Resistance State（ ） High Resistance State Ge Ge Ge Ge Ge Ge Ge Ge Ge Ge Activation State Ge Ge Ge Ge Ge Ge Ge Ge Ge Ge Ge Ge Te Te Te Te Te Te Te Te Ge Te Ge Te Ge Te Te Te Te Te Te Ge Te Te Te Te Te Te Te Te Te Te GeTe/Sb2Te3 Te Te Te Sb Te Set Te Te Te Te Te Te Te Te Te Te Te Te Te Te Sb Sb Te Te Te Te Te Te Te Te supply system bubbling Stacking Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Te Sb Te Sb Sb Sb Sb Sb Sb Sb Sb Sb Te Te Te Te • GeTe and Sb Te stacking in c-axis direction Te Te Te Te Te Te Te Te Te Te Sb Te Te Te Te Te Te Te Te Te 2 3 Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Sb Te Te Te • Crystal__ to crystal changg(e (short-range Ge motion) Te Te Te Te Te Te Te Te Te Te Te Te Te Te Te Te Te Te Te Te Te Te pgpurge gas N2 ⇒ reduction of operational power deposition T T T T T ＝ T temperature GeTe ≠ Sb2Te3 GeTe ≠ Sb2Te3 GeTe Sb2Te3 carrier gas N2 Fig. 1 GeTe/Sb2Te3 Super-Lattice films[1] 100 80 Si Unsynchronized Synchronized 100 100 Sb 60 Te Ge 40 precursor１ 80 Te 80 Te 20 Sb C O

Composition (%) Composition 0 precursor2 60 60 0246810 on (%) ition (%) i

s Sputter time (min .) Fig.6 XPS profile. The contaminants in Fig.2 Supply sequence of precursors. 40 40 the Sb-Te film were below the detection

Synchronized and unsynchronized Compo limit. 7

） 10

Composit atmospheric pressure sequence were combined. 20 20 5 Pa 10 region of interest

（ Te 10 3 Sb Sb precursor Te precursor 10 0 Ge Tris(dimethylamino)antimony Di‐tert‐butyltellurium 0 0 10-1 -3 Me N 10 2 0 1020304050 012345 10-5 NMe2 Sb (tert‐Bu) Te (tert‐Bu) 10-7 Flow of Te precursor (cc) 10-9 Flow of Ge precursor (cc) pressure Vapor Me N 0 500 1000 1500 2000 2 Temperature （℃） Fig.3 Sb and Te precursor molecules with Fig. 4 Sb-Te CVD. The Fig.5 Ge-Te CVD. The GeTe Fifig.7 Vapor pressure of Ge, Sb and

planar structures. Sb2Te3 was successfully was successfully obtained Te. Region of interest was near 1000 obtained using 30 cc of using 3.6 cc of Ge precursor. Pa and 250deg. Te precursor. 10 Table 3 XRD and TEM measurement results for GeSbTe and GeTe/Sb2Te3 CVD films. Sb2Te3 crystal XRD TEM 8 GeTe GeSbTe fcc fcc + + cp cp ) ) nm/min)

6 p(004) p(008) p(009) 0 0 h h h h ( ( GeSbTe c c c h h h (20 (40 hcp+fcc 4 Si Si

2

Deposition rate rate Deposition 0

1.8 1.85 1.9 1.95 2 GeTe/Sb2Te3 hcp(009) -1 hcp(0015) hcp(0018) (200) hcp (400)

1000/T (K ) Si Fig. 8 CVD deposition rates . It became possible Si

to deposit Sb2Te3, GeTe, and GeSbTe at an identical temperature of 250 deg. 1E+8 1E+8 1E+8 1E+7 1E+7 1E+7 ) ) ) Ω Ω 1E+6 1E+6 Ω 1E+6 1E+5 1E+5 1E+5 istance ( istance stance ( stance istance ( istance i i s s s s 1E+ 4 1E+4 1E+4 Re Re Res 1E+3 1E+3 1E+3 1E+2 1E+2 1E+2 00.511.52 0 0.5 1 1.5 2 1E+0 1E+1 1E+2 1E+3 1E+4 1E+5 Set Voltage (V) Reset Voltage (V) No. of Cycles

Fig. 9 Set operation of CVD GeTe/Sb2Te3 SL Fig. 10 Reset operation of CVD GeTe/Sb2Te3 SL Fig.11 Reset/set cycle operation of CVD device. We used a set pulse with a trailing device. We used a reset pulse with a trailing GeTe/Sb2Te3 SL device. edge/widths/falling edge = 100/700/1000 ns. edge/widths/falling edge = 5/100/5 ns.

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