Computer-Controlled Teletext Decoder

SDA5243 SDA5243/H

COMPUTER-CONTROLLED TELETEXT DECODER

. AUTOMATIC SELECTION OF UP TO SEVEN NATIONAL LANGUAGES . FOUR SIMULTANEOUS PAGE REQUESTS . DISPLAY OF THE 25TH STATUS ROW . MICROPROCESSOR CONTROL VIA AN I2C BUS (SLAVE ADDRESS 0010001 R/W) . DATA ACQUISITION AVAILABLE FROM LINES 2 TO 22 OR FROM A COMPLETE FIELD. . DIRECT INTERFACE TO A STATIC RAM OF DIP40 (Plastic Package) UP TO 8kBYTES . HIGH QUALITY DISPLAY USING A CHARAC- ORDER CODES : TER MATRIX OF 12 x 10 DOTS. SDA5243 - West European Languages . SINGLE + 5V SUPPLY VOLTAGE SDA5243/H - East European Languages . ON-CHIP MASK PROGRAMMABLE ROM CHARACTER GENERATORS . NMOSH2 PROCESS PIN CONNECTIONS

VDD 1 40 A10

A11 2 39 A9 A12 3 38 A8

OE 4 37 A7 WE 5 36 A6 TTD 6 35 A5

TTC 7 34 A4 DESCRIPTION ODD/EVEN 8 33 A3 The SDA5243 is a NMOSH2 integrated circuit 32 which performs all the processing of logical data F6 9 A2 within a 625 line system teletext decoder. It is VCS 10 31 A1 designed to operate in conjunction with at least two SAND 11 30 A0 chips : the SAA5231 integrated chip which extracts TCS/SCS 12 29 D7 Teletext information embedded in a composite video signal and up to eight kilobytes of static RAM R 13 28 D6 memory which can be used to store a maximum of G 14 27 D5 8 pages of display data. A complete system also B 15 26 D4 comprises a microprocessor controling the SDA5243 via a 2-wire serial bus. An on-chip ROM COR 16 25 D3 memory containsthe character sets. The SDA5243 BLAN 17 24 D2 performs automatic selection of one of up to seven Y 18 23 D1 natural languages. Data bytes may be decodedin 22 either 7-Bit plus parity or in full 8-Bit formats. The SCL 19 D0 chip set also supports facilities for reception and SDA 20 21 Vss

display of higher-level protocol data. 5243-01.EPS

September 1993 1/20 SDA5243 - SDA5243/H

PIN DESCRIPTION

Pin Symbol Function Description

1VDD +5V Positive supply voltage 2, 3, A11, A12, Chapter address Address selection outputs for 1 of 8 static RAM chapters each of 40 A10 1 kBytes. 4 OE Output enable Active-low RAM output enable control signal. 5 WE Write enable Active-low RAM write enable control signal. It supports write- cycles interleaved with read-cycles. 6 TTD Teletext data input An A.C. coupled teletext data input supplied by the SAA5231 chip is latched to VSS between 4 and 8µs after each TV line. 7 TTC Teletext clock input A 6.9375MHz clock signal, supplied by the SAA5231 chip, is internally A.C. coupled, clamped and buffered. 8 ODD/EVEN Interlaced mode state High for even numbered and low for odd-numbered frames. The output value is valid 2µs before the end of lines 311 and 624. 9 F6 Character display clock The 6MHz clock signal, supplied by the SAA5231 chip is internally signal A.C. coupled, clamped and buffered. 10 VCS Video composite Active high VCS input. synchronization input signal 11 SAND Sandcastle Three level output pulse to the SAA5231 device. Phase lock, blanking signal, and color burst components are contained in this signal. 12 TCS/SCS Input / output composite Scan composite input signal (SCS) for the display synchronization synchronization signal or Text composite sync. (TCS) output signal tothe SAA5231. Both signals are active low. 13, 14, R G B Red, green, Character and background colors active-high open-drain outputs. 15 blue 16 COR Contrast reduction Open-drain active-low output supporting optimal display of characters in ”mixed mode” operation. 17 BLAN Blanking signal output Open-drain active high output for TV-image blanking in normal and mixed-mode operation. 18 Y Foreground output Open-drain active-high output with foreground information. Can be used for printer command. 19 SCL Serial clock Microprocessor clock input via serial bus. 20 SDA Serial data input / output Open-drain microprocessor serial data input/output via serial bus.

21 VSS 0 Volt Ground. 22-29 D0-D7 Parallel data input / output Eight tri-state input/output for data read/write from/to an external RAM. 30-39 A0-A9 Address signals Ten addresses output pins for accessing to individual Bytes of a

1 kByte chapter stored in an external Static RAM. 5243-01.TBL

2/20 LC DIAGRAM BLOCK

To Ti

DISPLAY LINE ACQUISITION RS 1 COUNTER LINE COUNTER MUX 9 6MHz ÷ 312/313/N ÷ 312/313/N

DECODER DECODER 1MHz

19 MUX ÷ 2 64 IC DECODER & INTERFACE COMPOSITE ÷ 2 20 SYNC. ODD/EV GENERATOR FIELD To Ti FIELD SYNC & ÷ 32 LOCKOUT PL CBB MUX FLASH 21 3 LEVEL COUNTER ≥ 1 & ≥ 1 & OUTPUT 11 BUFFER SCS FIELD TCS SYNC. SIGNAL OUT FIELD INT. QUALITY 10 E BUFF. & SYNC DETECTOR INTEG.

8 12

SER/PAR CONVERSION HAMMING M HOK PARITY U SHIFT AND DATA CHECK X DELAY CHARACTER M REG. RESYNCHRO. ROM ADDRESS U 192 x 12 x 10 DECODING X CK D E PRIORITY SHIFT LOGIC REG. A A BYTE GRAPHICS M M COUNTER ROW ADD LATCH CC DECODER P P AND SEQ LO DECODER ROMLINE N. LAT. EN 7 ADD. DEC AT 18 MUX 6 RR CONTROL LATCH LOGIC 13 D D ROW CHARACTER DOUBLE + 14 E E ADDRESS DECODER H. CONT. OUTPUT L L GENERAT COMPARAT. 15 BUFFERS A A WRITE L R R R R PAGE 17 Y Y CONTR. A A A A ROW ATTRIBUTE LINES M M M M COUNT LATCHES COUNTER /25 CK 0 1 2 3 64µs SDA5243/H - SDA5243 RAM ADDR. DISPLAY MAGAZ CONTROL COLUM ROW DISPL R5 M T MUX T CIRCUITS 16 COUNTER COUNTER RAM DATA CHAPT U WRITE LOG. R6 X ROW R3 R4 COMP. DEL 0 1 24 C/R 40 COLUM 2 & CK COMP. 3 MUX MUX MUX ADDRESS MAPING MEMORY MUX WRITE TIMING CONTROL GENERATOR 3/20

30 31 32 33 34 35 36 37 38 39 5 4 22 23 24 2526 27 28 29

5243-02.EPS SDA5243 - SDA5243/H

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VDD Power Supply Range -0.3, +7.5 V INPUT VOLTAGE RANGE :

VI VCS,SDA,SCL,D0-D7 -0.3, +7.5 V TTD,F6,TCS/SCS,TTC -0.3, +10 V OUTPUT VOLTAGE RANGE :

VO SAND, A0-A12,OE, WE, D0-D7,SDA,ODD/EVEN,R,G,B, -0.3 , +7.5 V BLAN, COR, Y, TCS/SCS -0.3, +10 V o Tstg Storage Temperature Range -20, +125 C o TA Operating Ambient Temperature Range -20, +70 C 5243-02.TBL

ELECTRICAL CHARACTERISTICS o VDD =5V,VSS =0V,TA = - 20 to + 70 C Symbol Parameter Min Typ Max Unit

VDD Supply Voltage (pin 1) 4.5 5 5.5 V

IDD Supply Current - 140 200 mA INPUTS TTD (Pin 6)

CEXT Ext. Coupling Capacitor - - 50 nF VI(p-p) Input Voltage p-p 2 - 7 V tr ,tf Input Rise / Fall Times 10 - 80 ns

tDS Input Set-up Time 40 - - ns

tDH Input Hold Time 40 - - ns II(L) Input Leakage Current (VI = 0 to 10V) - - 20 µA

CI Input capacitance - - 7 pF TTC, F6 (Pins 7,9)

VI DC Input Voltage - 0.3 - +10 V VI(p-p) AC Input Voltage F6 1 - 7 V AC Input Voltage TTC 1.5 - 7 V

± VP Input Peak Rel. 50 % Duty 0.2 - 3.5 V

fTTC TTC Clock Frequency 4 6.9375 8 MHz

fF6 F6 Clock Frequency 4 6 8 MHz tr ,tf Clock Rise / Fall Times 10 - 80 ns

II(L) Input Leakage Current (VI = 0 to 10V) - - 20 µA

CI Input Capacitance - - 7 pF VCS (Pin 10)

VIL Low Level Input Voltage 0 - 0.8 V VIH High Level Input Voltage 2 - VDD V

tr ,tf Input Rise / Fall Times - - 500 ns

II(L) Input Leakage Current (VI = 5.5V) - - 10 µA

CI Input Capacitance - - 7 pF SCL (Pin 19)

VIL Low Level Input Voltage 0 - 1.5 V

VIH High Level Input Voltage 3 - VDD V fSCL SCL Clock Frequency - - 100 kHz

tr ,tf Input Rise / Fall Times - - 2 µs

II(L) Input Leakage Current (VI = 5.5V) - - 10 µA

CI Input Capacitance - - 7 pF 5243-03.TBL

4/20 SDA5243 - SDA5243/H

ELECTRICAL CHARACTERISTICS (continued) o VDD =5V,VSS =0V,TA = - 20 to + 70 C Symbol Parameter Min Typ Max Unit INPUT/OUTPUTS TCS(output), SCS(input) (Pin12)

VIL Low Level Input Voltage 0 - 1.5 V

VIH High Level Input Voltage 3 - 8 V

tr ,tf Input Rise / Fall Times - - 500 ns

± II(L) Input Leakage Current (VI = 0 to 5.5V and output in high impedance state) - - 10 µA

CI Input Capacitance - - 7 pF

VOL Low Level Output Voltage (IOL = 0.4mA) 0 - 0.4 V

VOH High Level Output Voltage -IOH = 0.2mA 2.4 - VDD V IOH = 0.1mA 2.4 - 5.5 V

tr ,tf Output Rise / Fall Times between 0.6V and 2.2V - - 100 ns

Cl Load Capacitance - - 50 pF SDA (Pin 20) (see Figure 4)

VIL Low Level Input Voltage 0 - 1.5 V

VIH High Level Input Voltage 3 - VDD V

tr,tf Input Rise / Fall Times - - 2 µs

II(L) Input Leakage Current (VI = 5.5V with output off) - - 10 µA

CI Input Capacitance - - 7 pF

VOL Low Output Voltage (IOL = 3mA) 0 - 0.5 V

tf Output Fall Time between 3.0V and 1.0V - - 200 ns

Cl Load Capacitance - - 400 pF D0-D7 (Pins 22-29), (see Figure 5)

VIL Low Level Input Voltage 0 - 0.8 V

VIH High Level Input Voltage 2 - VDD V

± II(L) Input Leakage Current (VI = 0 to 5.5V and output in high impedance state) - - 10 µA

CI Input Capacitance - - 7 pF

VOL Low Level Output Voltage (IOL = 1.6mA) 0 - 0.4 V

VOH Hogh Level Output Voltage (-IOH = 0.2mA) 2.4 - VDD V

tr,tf Output Rise / Fall Times between 0.6V and 2.2V - - 50 ns

Cl Load Capacitance - - 120 pF OUTPUTS A0-A12, OE, WE (Pins 30-40,2,3,4,5,)

VOL Low Level Output Voltage (IOL = 1.6mA) 0 - 0.4 V

VOH High Level Output Voltage (-IOH = 0.2mA) 0.4 - VDD V

tr ,tf Output Rise / Fall Times between 0.6V and 2.2V - - 50 ns

CL Load Capacitance - - 120 pF ODD/EVEN (Pin 8)

VOL Low Level Output Voltage (IOL = 0.4mA) 0 - 0.4 V

VOH HIgh Level Output Voltage (-IOH = 0.2mA) 2.4 - VDD V

tr ,tf Output Rise / Fall Times between 0.6V and 2.2V

CL Load Capacitance 5243-04.TBL

5/20 SDA5243 - SDA5243/H

ELECTRICAL CHARACTERISTICS (continued) o VDD =5V,VSS =0V,TA = - 20 to + 70 C Symbol Parameter Min Typ Max Unit OUTPUTS SAND (Pin 11)(see Figure 1)

VOL Low Level Output Voltage (IOL = 0.2mA) 0 - 0.25 V

VOI Middle Level Output Voltage (IOL = ± 10 µA) 1.1 - 2.9 V

VOH High Level Output Voltage (IOH = 0/-10µA) 4-VDD V Output Rise Time : ns tr1 VOL to VOI from 0.4 to 1.1V - - 400 tr2 VOI to VOH from 2.9 to 4.0V - - 200

tf Output Fall Time VOH to VOl from 4.0 to 0.4V - - 50 ns

Cl Load Capacitance - - 30 pF R, G, B, COR, BLAN, Y (Pins 13-18), (see Figure 4)

VOL Low Level Output Voltage : V IOL = 2mA 0 - 0.4 IOL = 5mA 0 - 1

VPU Pull-up Voltage (with R = 1kΩ to 5V) --5V

tf Output Fall Time from 4.5 to 1.5V (with R = 1kΩ to 5V) - - 20 ns

tSK Skew Delay on Falling Edges (at 3V with R = 1kΩ connected to 5V) - - 20 ns

CL Load Capacitance - - 25 pF

ILO Output Leakage Current (VPU = 0 to 6V output off) - - 20 µA TIMING

SERIAL BUS (referred to VIH = 3V, VIL = 1.5V)

tLOW Low Period Clock 4 - - µs

tHIGH High Period Clock 4 - - µs

tSU ,dAT Data Set-up Time 250 - - ns

tHD ,dAT Data Hold Time 170 - - ns

tSU ,sTO Stop Set-up Time from Clock High 4 - - µs

tBUF Start Set-up Time Following a Stop 4 - - µs

tHD ,sTA Start Hold Time 4 - - µs

tSU ,sTA Start Set-up Time Following Clock Low to High Transition 4 - - µs

MEMORY INTERFACE referred to VIL = 1.5V

tCY Cycle Time - 500 - ns - tOE Adress Change to OE Low 60 -ns

tADDR Address Active Time 450 500 - ns

tOEW OE Pulse Duration 320 - - ns

tACC Access Time from OE to Data Valid - - 200 ns

tDH Data Hold Time from OE High or Address Change 0 - - ns

tWE Address Change to WE Low 40 - - ns

tWEW WE Pulse Duration 200 - - ns

tDS Data Set-up Time to WE High 100 - - ns

tDHWE Data Hold Time from WE High 20 - - ns

tWR Write Recovery Time 25 - - ns 5243-05.TBL

6/20 SDA5243 - SDA5243/H

Figure 1 : F6, TTC, TTD Input Internal Connections

character display clock input F6 9 to timing chain

50% V duty cycle teletext clock input level TTC 7 to data acquistion circuit VP VI(p-p) VP

teletext data input TTD 6 to data acquisition circuit C EXT 0t clamping pulses from timing circuit from time 4µsto8µs of each television shaded regions equal in area line to maintain correct D.C. level following external A.C. coupling

F6, TTC, TTD INPUT CIRCUITRY INPUT WAVEFORM PARAMETERS 5243-03.EPS Figure 2 : Teletext Data Input Timing

t CY 144ns typ. 90% 90% TTC 10% 10%

t r t f t DS t DH 40ns min. 40ns min. 80ns max. 80ns max.

TTD Data Stable Data Stable

data may change data may change data may change Data Stable : 1 if ≥ 2V , 0 if ≤ 0.8V 5243-04.EPS Figure 3 : SynchronizationTiming

F1 continuous internal 1MHz clock

0 64

TCS

4.67 Phase lock

SAND Phase lock off

1.58.5 33.5 All timings in µs 5243-05.EPS

7/20 SDA5243 - SDA5243/H

Figure 4 : Composite Sync. Waveforms

LSP

0 4.66 64

0 2.33 32 34.33 64

0 27.3332 59.33 64 All timings in µs

TCS (interlaced) 621 622 623 624 625 12 3456 (308) (309) (310) (311) (312)

TCS (interlaced) 309 310 311 312 313 314 315 316 317 318 319 (1) (2) (3) (4) (5) (6)

TCS (non-interlaced) 308 309 310 311 312 1 2 3 4 5 6

The number positions indicate the end of lines. The Teletext composite synchronization signal (TCS), whether interlacing is present or not, comprise three components. a) the line-synchronization pulses (LSP). b) the equalization pulses (EP) c) the frame-synchronization pulses (BP).

The timing reference is specified by the descending edge of the signal LSP, with a tolerance spread of ± 100ns. 5243-06.EPS Figure 5 : Display Output Timing

A) LINE RATE

LSP (TCS)

0 4.66 64 40µs

R.G.B.Y (1) display period

0 16.67 56.67 All timings in µs

B) FIELD RATE lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced)

R.G.B.Y (1) display period

0 41 291 312 Line numbers

(1) Also BLAN in charac terand box blanking Horizontal directio n(line ) - Vertical direc tion (frame) 5243-07.EPS

8/20 SDA5243 - SDA5243/H

Figure 6 : Serial Bus Timing

SDA

t BUF t LOW t f

SCL

t HD,STA t r t HD,DAT t HIGH t SU,DAT

SDA

t SU,STA t SU,STO

VIH =3V,VIL = 1.5V 5243-08.EPS Figure 7 : Memory Interface Timing

A) READ t CY ADDRESS valid A0 - A12

t ADDR

t OE

t OEW

t ACC t DH DATA FROM valid data output RAM

B) WRITE t CY ADDRESS valid A0 - A12

t WE t WR

t WEW

t DS t DHWE DATA TO valid data output RAM 5243-09.EPS

9/20 10/20 5243-10.EPS SDA SCL +12V T S 22 µ H +5V 10k 22 Ω 4.7 BC558B µ H µ F 470 470 0.1 23nF Ω Ω µ +12V 10k F Ω 16 20 19 21 1 15 10nF µ H 15 12 14 20 6 V SS CS 12 17 22 28 27 27pF 5422 WE 11 22 OE 23 11 D0 9 68k 14 12 324 23 D1 7 Ω 10pF 523 2 25 10 13 D2 1k 20 15 25 560pF

D3 Ω 6MHz 627 26 16 D4 7F470pF 47nF 17 D5 21 18 18 28 D6 47nF 390 93 132 31 30 29 19 7-36 Kx8SRAM 8 x 8K

D7 19 Ω 15pF SAA5231 MK48H64 SDA5243 10 A0 11 9 A1 1nF 15pF 13.875MHz 8 A2 4 33 7 A3 43 637 36 35 34 7 6 A4 56 22nF 10k 5 A5 Ω 4 A6 270pF 10 3

10 A7 8 25 38 µ 100pF 470 820 F A8 8 940 39 24 Ω A9 Ω 16 +12V 9 2p 68nF 220pF 21 1 +5V

A10 18 26 23 23 24

A11 10 10 28 2 µ Ω

A12 F 47 26 1 µ F 82 TEA2014A 13 76 27 15 14 13 17 5 1 1k 3.7k 2.2 Ω 3 Ω µ F 1N4148 1k 10 Ω 1k µ Ω F 1k Ω 1k Ω 2.7k BC548B BC548B BC548B BC548B +5V 22 Ω µ F 150pF 100 2 Ω L7805 V 0 6.8k 1.2k GND Ω 3 Ω V 82 82 82 82 1 4.7k Ω Ω Ω Ω 1 Ω +12V

SYNC GND B G R BLK GND +12V VIDEO

PLCTO DIAGRAM APPLICATION D54 SDA5243/H - SDA5243 SDA5243 - SDA5243/H

APPLICATION NOTES ORGANIZATION OF A PAGE-MEMORY The organization of a page-memory is shown in character either ”white” or ”green” defining the Figure 6. In contrast with the first generation of ”search” status of the page. When it is ”white” the Teletext Decoders the new CCT (Computer Con- operationalstate is normaland the header appears trolled Teletext) chip provides a displayformat of25 white ; when it is ”green” the operational state rows of 40 characters per row. corresponds to ”search mode” and the header Row number twenty-four is used by the microproc- appears green. The following twenty-four charac- essor for the display of information. ters give the header of the requested page when the system is in search mode. The last eight char- Row zero contains the page header. acters display the time of day. The organizationis as follows : Row twenty-five comprises ten bytes of control The first seven characters (0 - 6) are used for data concerning the received page (see Table 1) messages regarding the operational status. and fourteen free bytes which can be used by the The eighth character is an alphanumeric control microprocessor. PAGE MEMORY ORGANIZATION Figure 8

Fixed characters written by CCT hardware Alphanumerics white for normal, green on search 7 Status Characters 24 characters from page header 8 scrolling rolling on page search time characters ROW

7 1 24 8 0 1 2 3 4 5 6 7 8 9 10 MAIN PAGE DISPLAY AREA 11 12 13 14 15 16 17 18 19 20 21 22 23 this row always free for status 24 10 14 25

10 bytes for received 14 bytes free page information for use by µC 5243-11.EPS

11/20 SDA5243 - SDA5243/H

Table 1 : Row 25 received control data format

D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0 D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0 D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0 D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0 D4 HAM HAM HAM HAM HAM HAM HAM HAM FOUND 0 D5000000000PBLF D60000000000 D70000000000 COLUMN 0123456789 Page number : - MAG = magazine, PU = page units, PT = page tens. Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens. PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits. 5243-06.TBL

REGISTER MAP (see Table 2) follows : all bits in registers R1 to R10 are cleared Registers R1 to R10 are write only whilst R11 is a to zero with the exception of bits D0 an D1 in read/write register respect to the microprocessor. registers R5 and R6 which are set to logical one. The automatic succession on a byte basis is indi- After power-up all the memory bytes are preset to cated by the arrows in Table 2. hexadecimalvalue 20 H (space) with the exception In the normal operating mode TAand TB should be of the byte corresponding to row 0 of column 7 of set to logic level 0. chapter 0 which is set to the value corresponding After power-up the contents of the registers are as to ”alpha white” hexadecimal value 07 H.

Table 2 : Register specification

D7 D6 D5 D4 D3 D2 D1 D0

TA 7 + P/ ACQ. GHOST DEW/ TCS T1 T0 8 BIT ON/OFF ROW FULL ON R1 Mode ENABLE FIELD ↵ - BANK ACQ. ACQ. TB START START START SELECT CCT CCT COLUMN COLUMN COLUMN A2 A1 A0 SC1 SC0 R2 Page request adress SC2 ↵ - - - PRD4 PRD3 PRD2 PRD1 PRD0 R3 Page request data --- --A2A1A0↵ R4 Display chapter

BKGND BKGND COR COR TEXT TEXT PON PON OUT IN OUT IN OUT IN OUT IN ↵ R5 Display control (normal) BKGND BKGND COR COR TEXT TEXT PON PON Display control R6 OUT IN OUT IN OUT IN OUT IN ↵ (newsflash / subtitle) STATUS CURSOR CONCEAL/ TOP/ SINGLE/ BOX ON BOX ON BOX ON ROW ON REVEAL BOTTOM DOUBLE 24 1-23 0 R7 Display mode BTM/TOP HEIGHT

- - - - CLEAR A2 A1 A0 ↵ R8 Active chapter MEM. ↵ - - - R4R3R2R1R0 R9 Active row - - C5 C4 C3 C2 C1 C0 ↵ R10 Active column D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) R11 Active data 5243-07.TBL - bit does not exist

12/20 SDA5243 - SDA5243/H

Register Function Bit(s) Description T0,T1 (D0,D1) These bits control the frame display format. Interlaced or non-interlaced,312/313 or 312/312. TCS ON (D2) This bit determines the character display synchronization mode. Teletext composite synchronism (TCS ON = 1) or direct broadcast synchronism (TCS ON = 0). DEW/FULLFIELD Selection of field flyback mode or full channel mode R1 Mode controls (D3) (D3 = 1) for recovering of Teletext data. GHOST ROW Selection of ghost row mode (D4 = 1) ENABLE (D4) ACQUISITION Control of acquisition operation (D5 = 0 enables ON/OFF (D5) acquisition) 7 bits + parity or 8 Selection of received data format either 7 bits with parity bits without parity (D6 = 0) or 8 bits without parity (D6 = 1). (D6) TA (D7) Test bit equal to ”0” in the normal operating mode. SC0,SC1,SC2 Address the first column of the on chip page request (D0,D1,D2) RAM to be written. Addressing TB (D3) Test bit equal to ”0” in the normal working mode. R2 information for a page request A0,A1 (D4,D5) Address a group of four consecutive pages currently used for data acquisition; A2 (D6) Address of one of the two groups of four pages for acquisition in normal mode. Data relative to the PRD0-PRD4 (D0-D4) Written data in the page request RAM, starting with the R3 requested page (see columns addressed by SC0,SC1,SC2. Table 3). Selection of one of A0,A1,A2 (D0,D1,D2) These three bits correspond to the logical states of the R4 eight pages to three address lines (A12,A11,A10) during memory read display. cycles. PON (D0,D1) Picture on (IN: D0, OUT: D1) TEXT (D2,D3) Text on (IN: D2, OUT: D3) Display control for R5 normal operation. COR (D4,D5) Contrast reduction on (IN: D4, OUT: D5) BKGND (D6,D7) Background colour on (IN: D6, OUT: D7) IN/OUT Enable inside/outside the box Display control for See R5 See R5 R6 news-flash subtitle generation. BOX ON 0,1-23,24 The ”boxing” function is enabled on row 0,1-23 and 24 (D0,D1,D2) by D0, D1 and D2 set to one. R7 Display mode STATUS ROW The 25th row is displayed before the ”Main text Area” BTM/TOP (D7) (lines 0-23) or after (D7 = 0). Active chapter address (R8), active row address (R9), active column address (R10). R8 to R11 2 Data contained in R11 read (written) from (to) memory by microprocessor via I C bus. 5243-08.TBL

13/20 SDA5243 - SDA5243/H

Table 3 : Register R3

START PRD4 PRD3 PRD2 PRD1 PRD0 COLUMN 0 Do care magazine HOLD MAG2 MAG1 MAG0 1 Do care page tens PT3 PT2 PT1 PT0 2 Do care page units PU3 PU2 PU1 PU0 3 Do care hours tens X X HT1 HT0 4 Do care hours units HU3 HU2 HU1 HU0 5 Do care minutes tens X MT2 MT1 MT0 6 Do care minutes units MU3 MU2 MU1 MU0

The abbreviations have the same significance as in Table 1 with the exception of the ”DO CARE” entries. It is only when this bit is ”1” that the corresponding digit is taken into consideration on page request. For example, a page defined as ”normal” or one difined as ”timed” may be selected. If ”HOLD” is low the page is held. The addressing of successive bytes via the I2C bus is automatic. 5243-09.TBL

CHARACTER SETS The complete character set with 8-bit decoding is sponding row and column integers : for example given in Table 4. the character ”3” may be indicated by 3/3. Characters in columns 0 and 1 are normally dis- A rectangle may be represented as follows : played as blanks. Black dots represent the charac- The characters 8/6, 8/7, 9/5, 9/7 are used as spe- ter shape whereas white dots represent the cial characters, always in conjunction with 8/5. background. The 13 national characters are placed in columns Each character can be identified by a pair of corre- with bit 8 = 0.

14/20 al a: 4a Table *Teecnrlcaatr r rsmdbfr ahrwbegins codes. row data each before other with presumed compatibility are for characters control reserved are These characters control ** These * Set) (German 001 = C14 C13 C12 using Case

B b 8 0 0 0 or 1 0 0or 1 0 0 0 0 0 1 1 1 1 1 1 I b 7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 T b 6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 S Languages European West - codes) bit 8 (with set character Complete b 5 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 b 4 b 3 b 2 b 1 column r 2 1 22a33a45 66a77a8 912131415 o w alphanumerics graphics 0000 0 black black

alphanumerics graphics 0001 1 red red

alphanumerics graphics 0010 2 green green

alphanumerics graphics 0011 3 yellow yellow

alphanumerics graphics 0100 4 blue blue

alphanumerics graphics 0101 5 magenta magenta

alphanumerics graphics 0110 6 cyan cyan ** alphanumerics graphics 0111 7 white white

conceal 1000 8 flash display ** ** continuous 1001 9 steady graphics ** separated 1010 10 end box graphics * 1011 11 start box ESC D54 SDA5243/H - SDA5243 ** ** normal black 1100 12 height background ** double new 1101 13 height background * hold 1110 14 SO graphics * ** release 1111 15 SI graphics 15/20

5243-12.EPS 16/20 : 4b Table SDA5243/H - SDA5243 *Teecnrlcaatr r rsmdbfr ahrwbegins codes. row data each before other with presumed compatibility are for characters control reserved are These characters control ** These * Set) (Rumanian 111 = C14 C13 C12 using Case

B b8 0 0 0 or 1 0 0or 1 0 0 0 0 0 1 1 1 1 1 1 I b 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 T 7 b6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1

S Languages European East - codes) bit 8 (with set character Complete b5 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 b 4 b3 b2 b 1 column r 2 1 22a33a4 5 66a77a8 912131415 o w alphanumerics graphics 0000 0 black black

alphanumerics graphics 0001 1 red red

alphanumerics graphics 0010 2 green green

alphanume rics graphics 0011 3 yellow yellow

alphanumerics graphics 0100 4 blue blue

alphanumerics graphics 0101 5 magenta magenta

alphanumerics graphics 0110 6 cyan cyan

** alphanumerics graphics 0111 7 white white

conceal 1000 8 flash display

** ** continuous 1001 9 steady graphics

** separated 1010 10 end box graphics

* 1011 11 start box ESC

** ** normal black 1100 12 height background

** double new 1101 13 height background

* hold 1110 14 SO graphics

* ** release 1111 15 SI graphics

5243-13.EPS SDA5243 - SDA5243/H

NATIONAL OPTION CHARACTER SETS The basic set of the 96 characters is shown in are shown in Table 5 whilst full national character Table 5.The location of the 13 national characters sets are depicted in Tables 6 and 7. Table 5 : Basic character set.

National National 2/0 3/0 4/0 5/0 6/0 7/0 Charact er Character

2/1 3/1 4/1 5/1 6/1 7/1

2/2 3/2 4/2 5/2 6/2 7/2

2/3 National 3/3 4/3 5/3 6/3 7/3 Character

National 2/4 3/4 4/4 5/4 6/4 7/4 Character

2/5 3/5 4/5 5/5 6/5 7/5

2/6 3/6 4/6 5/6 6/6 7/6

2/7 3/7 4/7 5/7 6/7 7/7

2/8 3/8 4/8 5/8 6/8 7/8

2/9 3/9 4/9 5/9 6/9 7/9

2/10 3/10 4/10 5/10 6/10 7/10

2/11 3/11 4/11 5/11 National 6/11 7/11 National Character Character

National National 2/12 3/12 4/12 5/12 6/12 7/12 Character Character

National National 2/13 3/13 4/13 5/13 6/13 7/13 Character Character

National National 2/14 3/14 4/14 5/14 6/14 7/14 Character Character

National 2/15 3/15 4/15 5/15 6/15 7/15 Character 5243-14.EPS 17/20 18/20 : 6 Table SDA5243/H - SDA5243 oe1: 1 Note

PHCB (1) CHARACTER POSITION (COLUMN/ROW) LANGUAGE

obntosdfutt nls.Ol h above the 5. Table in Only shown are characters set others English. basic All the PHCB. to Other in the bits. with Control change default characters Header Page the Combinations are PHCB Where C12 C13 C14 2/3 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13 7/14 uoenLanguages European West SDA5243 for Set Character ENGLISH 000

GERMAN 001

SWEDISH 001

ITALIAN 011

FRENCH 100

SPANISH 101

5243-15.EPS al : 7 Table oe1: 1 Note

PHCB (1) CHARACTERPOSITION(COLUMN/ROW) LANGUAGE

obntosdfutt emn nyteabove 5. the Table in shown Only are characters others set basic German. All the PHCB. Other in to the bits. with change Control default characters Header Page the Combinations are PHCB Where C12 C13 C14 2/3 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13 7/14 uoenLanguages European East SDA5243 for Set Character POLISH 000

GERMAN 001

SWEDISH 001

SERBO-CROAT 011

CZECHOSLOVAK 100

RUMANIAM 101

5243-16.EPS SDA5243 - SDA5243/H

Figure 9 : Character Format

Alphanumerics and Alphanumerics Alphanumerics or Alphanumerics Graphics ’space’ character blast-through character character 2/13 alphanumerics 7/15 2/0 character 4/8

Contiguous Separated Separated Contiguous graphics character graphics character graphics character graphics character 7/6 7/6 7/15 7/15

Background Display = = Color Color 5243-17.EPS

19/20 SDA5243 - SDA5243/H

PACKAGE MECHANICAL DATA 40 PINS - PLASTIC DIP I a1 L b1 b e b2 E e3

40 21 F

120 PM-DIP40.EPS

Millimeters Inches Dimensions Min. Typ. Max. Min. Typ. Max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 D 52.58 2.070 E 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 48.26 1.900 F 14.1 0.555 i 4.445 0.175 L 3.3 0.130 DIP40.TBL

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.

Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips.

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