switching circuits by a substantially- age requirements. The total cost using 2. HIGH SPEED CIR­ CUITS, S. Y. Wong;, A. K. Rapp. IRE-AIEE smaller number of components and con­ DCTL is comparable with other tech­ Transistor Circuits Conference, Phila., Pa., Feb. nections, and by extremely-low power niques, because the tightly specified 1956. (Not published.) consumption. Circuit simplicity and low 3. HIGH-TEMPERATURE SILICON-TRANSISTOR COM­ transistor eliminates considerable com­ PUTER CIRCUITS, James B. Angell. Proceed­ dissipation are obtained at the price of plexity in system design and manufac­ ings of the Eastern • Joint Computer Conference, AIEE Special Publication T-92, Dec. 10-12, 1956, limited gain, small voltage swings, and a ture. pp. 54-57. comparatively low upper limit on in­ 4. LARGE-SIGNAL BEHAVIOR OP JUNCTION TRAN­ ternal temperature. Rather severe re­ SISTORS, J. J. Ebeijs, J. L. Moll. Proceedings, References Institute of Radio Engineers, New York, N. Y., quirements on transistor parameters, vol. 42, Dec. 1954, ij>p. 1761-72. 1. SURFACE-BARRIER TRANSISTOR SWITCHING CIR­ particularly input impedance and satura­ CUITS, R. H. Beter, W. E. Bradley, R. B. Brown, 5. TWO-COLLECTOR TRANSISTOR FOR BINARY tion voltage, are compensated by almost M. Rubinoff. Convention Record, Institute of FULL ADDER, R. F. Rtitz. IBM Journal of Research Radio Engineers, New York, N. Y., pt. IV, 1955, and Development, N^w York, N. Y., vol. 1, July negligible dissipation and maximum volt­ p. 139. 1957, pp. 212-22.

I. Basic System Requirements Symmetrical Transistor Logic A. INITIAL The initial specific system for which the R. H. BAKER symmetrical cirpuit approach was in­ NONMEMBER AIEE tended had the following requirements: 1. General-purpose computer applicable HIS paper discusses symmetrical tran­ ment than do other types of circuitry to real time problem solution. sistor switching circuit techniques. that can be engineered to build the T 2. All solid-state machine. The circuitry is designated "symmetrical specific system. However, it is felt that circuits" because the basic circuits em­ this criticism is not justified in this case for 3. Nonairconditioned ground environment. ploy both p-n-p and n-p-n in two reasons. They are: 1, The addi­ 4. Synchronous : machine with a basic approximately equal numbers which re­ tional cost of components required for clock rate of 3 microseconds, (/AS). sult in networks that exhibit a high degree symmetrical logic is more than counter­ 5. Memory capacity of 8,192 registers, of operational and topological symmetry. balanced by the shorter system realiza­ 28 bits in length, with a memory cycle The major practical advantage of this tion time required. This is particularly time of 6 MS. circuitry over other types lies in the ease true for an establishment, such as the 6. Semiportable housing. with which basic circuits may be Massachusetts Institute of Technology 7. Minimum conception to completion integrated into a digital system. This Lincoln Laboratory, that is engaged in time with a minimum of staff. advantage is made possible through, 1, system research and development. And, 8. Maximum reliability with minimum keeping the circuit configurations flexible 2, that symmetrical logic techniques are maintenance. (to satisfy many different system applica­ more adaptable to future developments i tions), 2, worst-case circuit design with in the device, circuits and system area B. ADDITIONAL regard to component stability and sys­ than other types of circuit logic. It was also tlie goal of the circuit de­ tem loading requirements, 3, use of only It is the purpose of this paper to show signer to build circuitry that was suffi­ standard commercially available com­ why, when, and under what conditions ciently flexible fo meet requirements for ponents, and 4, insisting that all present- symmetrical circuit techniques should be all other groundi-based digital-data proc­ day circuit designs be applicable to known used, along with probable future develop­ essing systems contemplated at the time future device trends. The major criti­ ments, through the discussion of the cir­ (there were several). cism of the symmetrical circuit techniques cuit techniques and relating their circuit is that the circuits require a greater num­ capabilities to the solution of system prob­ II. Basic Circuit Modules ber of components for a specific equip- lems. A. GENERAL COMMENTS

+ (V+AV) Aside from the general system require­ ments of Section; I, there are several other component-circuit-system requirements worthy of special note. They are: i—l-^M-i- OFF-** ON--OFF 1. That the circuits require minimum- specification components (single-ended + V specifications when possible). .-i- INPUT OUTPUT • j_Vu o . • WV—| O 2. That all components be commercially available stock ijtems. 3. That the circuit techniques be suffi­ ON —OFF—-ON ciently flexible to incorporate future higher performance devices to satisfy future

Fig. 1 (right). R. H. BAKER is with the Massachusetts Institute Symmetrical buffer of Technology, Lincoln Laboratory, Lexington, inverter -(V+AV) Mass.

Baker—Symmetrical Transistor Logic 27 LOGIC + X E F R AND OR PNP AND 9 9 b ?J IL + 2L

T BIAS R {(ABCI + D}-E-F CLOCK iliii i -E

+ E -E -E

Fig. 6. Multilevel logic nets -(V + AV) -(V+AV) 25 AND NPN fig.

Fig. 2. Basic symmetrical flip-flop configura­ Fig. 4. A-c logic nets 1 2 tion 1 2 + 5 1us CLOCK A B JUL n Id" INPUT, CLOCK -W o JLi

GATE prn l INPUT IJ J I

Fig. 7. CRD gate Fig. 5. Trailing-edge logic

Transient Considerations equal to /3 (grounded emitter transistor The important transient considerations current gain), i.e., of the symmetrical flip-flop may be seen

J out 2v0l with the aid of Fig. 3. (1) Fig. 3. Symmetrical flip-flop ' 2vl ' vSalient points to note about the tran­ sient behavior of the network are: 6. The circuit is fast. This is so because higher-performance system requirements transistor hole/electron storage effects are 1. The hole storage of the saturated that may be needed. minimized. transistor is minimized because large current is drawn from its collector during 4. That the circuit designs concentrate 7. The transistor specifications are not critical. the storage time, thus clearing out the on fundamental device-network-system stored minority carriers quickly. principles, thereby pointing out future 8. The circuit has high utility and is 2. The rise and fall times, of the output, trends in these areas and furthering the flexible, i.e., the circuit may be: (a) used after the storage time is directly related state of the art. with any supply voltage within reason to the ability of the conducting transistor (note! Not necessarily equal positive and to delivery current at the collector terminal B. BUFFER INVERTER negative supplies), (b) designed with and the terminal capacitance. With the aforementioned system and different values of R and Rb for the p-n-p and n-p-n to accommodate nonsymmetrical 3. Transistor dissipation due to transient circuit requirements in mind and con­ loads; (c) used with different-type tran­ effect 1 and 2 set an upper limit to the sidering the transistor field as it existed in sistors to create unusual circuit effects, etc. average pulse repetition frequency of the 1955, it seemed advisible to utilize p-n-p circuit equal to approximately one-fifth transistors to generate fast "positive- C. FLIP-FLOP the value of the transistor frequency cutoff (txco), i-e., the use of 10 megacycles, (mc) going" transients and n-p-n transistors to D-C Considerations aco transistor result in a circuit pulse generate fast "negative-going" transients. repetition frequency (prf) of about 2 mc This was first done in the form of a buffer Two buffer inverters of the type shown maximum. in Fig. 1 may be connected together to inverter shown in Fig. 1. Some of the 4. The accumulation of charge on capaci­ salient features of the circuit shown in form a symmetrical flip-flop as shown in tors C by the transmission of trigger Fig. 1 are: Fig. 2. energy through it sets an upper limit to The d-c considerations of this circuit the maximum prf of about 0.15aco. 1. Each transistor has positive base are the same as for the buffer inverter 5. It is important to note that restrictions current applied while in the off condition number 3 and 4 allude to the average and the numerical value of this current is previously discussed. However it is maximum prf; the "burst" repetition rate equal to AF/Sj. worthwhile to point out that the ratio of can be considerably higher. This can be total power drain on the supplies to the 2. Resistor values R and i?& along with shown as follows: AV may be chosen to yield a small un­ power delivery at the output terminals Let g = accumulated charge on capacitor certainty region ( Vu). Vu may be centered is almost unity, i.e., C during one trigger pulse around ground or shifted up or down over a large range. 2vlr Since g = C AE (5) (2) 3. RL is merely a standby resistor and ^supplies -Pout + Pstanclby 2vIi/-\-4tvI where AE represents the change in voltage therefore can be almost any value. where IL = 7/3 (3) across C caused by one trigger pulse; 4. The circuit is current demand, that is, Pout 2w/57 1_ then g

28 Baker—Symmetrical Transistor Logic Thus, as T is made small, i.e., the pulse prf) current mode nets are used and 3. Capacitor j resistor diode gating repetition frequency is increased (1/7" delays are inserted to circumvent race (CRD Gating) ; = prf), then AE increases and at the limiting prf both transistors will be conducting at problems. (Current mode nets are nets A simple inexpensive method of pulse- the same time (which usually causes one of that operate with low voltage swings; level gating is shown in Figure 7. CRD them to burn out). In order to prevent the current is shunted from one path to gating also has the advantage of built-in AE from becoming too large, i must be another as in Fig. 4.) delay to circumvent circuit races. The increased (to discharge C in time T) by disadvantage to jthis gating method is that decreasing the values of R and i?&. There Low-Speed Logic is a practical limit to increasing i, however, it is inherently slow, the maximum speed because decreasing R increases the tran­ 1. Trailing-edge logic (or minimum tithe between gating opera­ sistor drive, thus lengthening the transistor An example of the trailing-edge logic is tions) being limited to about three times storage time which in turn increases the the time-constant RC. Another limita­ transistor dissipation. However, this is shown in Figure 5. Since each flip- an average effect and the burst prf (say flop can deliver 20 milliamperes, (ma) tion is the signal-to-noise ratio unless care for an interval of 100 trigger pulses) can and each gate draws 1 ma, the "fan is taken to limit the clock pulse amplitude be a factor of 3 to 5 higher. out" from a flip-flop to single level gates to less than the gate waveform amplitude. 6. It should also be noted that the net­ is 20. The ' 'fan in'' (number of gates that However, this latter limitation is easily work of Fig. 3 is triggered at all four points can drive a flip-flop) is almost unlimited. taken care of with symmetrical circuits simultaneously, which minimizes the delay When 2-level nets are used the fan out is 5. in that the wave-form amplitudes are time without resorting to speedup capaci­ tors across the coupling resistors R, and 2. Multilevel nets automatically limited to the supply consequently rendering a flip-flop that is When more than two levels of logic are voltage values. , exceedingly difficult to false-trigger through used, emitter followers are employed as load transients. shown in Fig. 6. This process "and-or-if- E. NEGATIVE RESISTANCE CIRCUITS (NRC) D. LOGIC and-or" can be carried on indefinitely with two exceptions. They are: 1. that General Comments General care is taken to guard against too much The fully symmetrical bistable circuit In most of the low-speed (below 500 kc negative power being fed from the nets discussed in Section II-C (Figs. 2 and 3) prf) data processing systems built by back into the flip-flops and, 2. that the can be used to generate very fast rising the group to date, the nets have been con­ nets do not oscillate. The first condition and falling transients (sharp leading and structed with utilizing trailing- can be overcome by shunting resistors falling-edge square waves for example). edge logic and pulse-level gating of the across the input to the nets (note that However, for the reasons discussed, the voltage mode. (Diodes must be able to this wastes power) or using clamp diodes circuit cannot b;e operated at a prf that sustain the full logic levels voltages in across the flip-flop outputs. The second would seem consistent with the fast tran­ the reverse direction.) Transistor condition is prevented by inserting buffer sients. There are several specific reasons emitter follower circuits have been used inverters after every fourth level in the why this is so; but generally one can say internal to the nets, where additional cur­ nets. The over-all fan out for general that the circuits employ a great deal of rent gain is needed. In higher-speed two level nets of the voltage mode is 5. "speedup" over drive (via the base-to- data processing systems (above 500 kc base capacitors) and since conventional speedup cannot be obtained without NON INVERTED INVERTED reactive elements, the energy stored OUTPUT OUTPUT during the transient period must be R \r , 0tNap JR. '-'- recovered during the circuit "rest" (static) interval. It happens, however, that circuits can be built with much higher rep­ etition rate With little sacrifice of transient time. I This is accomplished by -q gnT utilizing p-n-p and n-p-n transistors and coupling the two together to form a nega­ tive resistance circuit,1 then paralleling two such negative resistance circuits to- form a bistable circuit.2 Fig. 10. Para-phase buffer inverter Fig. 8. Negative resistance bistable circuit r T

OUTPUT OUTPUT ON-OFF .^ RESET Mi-ftl c^W- -H—O T IN] T

OR PP^.1 AND

z{\-a)' OR AND NP^I OR

Fig. 9. Transient state of NRC flip-flop Fig. 11. D-c logic nets Fig. 12. Thristoir NRC flip-flop

Baker—Symmetrical Transistor Logic 29 •V

Vi

1*L 1*

Fig. 13. Flip-flop module Fig. 14, Logical net circuit module

Bistable Negative Resistance Circuit half, can the conducting pairs have a gain tor parameters, b. supply changes, c. re­ 1. Static conditions less than unity.) Under these conditions sistor values, and d. temperature (note Consider the circuit of Fig. 8. When the four transistor combinations can be that under static conditions, the circuits two transistor of opposite types are con­ characterized by two parallel negative are effectively grounded base). nected as shown in Fig. 6(A), the resulting resistance supplied by a current source Experimental circuits designed on the circuit is as if a negative resistance was whereby one-half "avalanches on" while NRC principal utilizing graded-base connected between the emitter terminals.1 the other "avalanches off." Thus we transistors have been operated at pulse The gain of this network can be easily con­ see that; 1. circuit regeneration is accom­ repetition frequencies exceeding 30 mc and trolled by external means as indicated by plished without speedup reactive com­ are conveniently designed to operate at the loop current gain equation shown in ponents (this situation allows the circuit aprf of 10 mc. to be retriggered immediately after the the figure; i.e., the current gain GL is NRC Buffer primarily dependent upon the product of transient without waiting for reactive components to recover), and 2. the cir­ A buffer inverter is shown in Fig. 10. the ratios of Ri to i?2 and R3 to R4 (as­ cuits allow wide tolerance to: a. transis­ The same static and transient conditions suming a an, oip~ 1). Thus, if two such circuits are emitter-coupled as shown in Fig. 6(B), the "on" pair will be stable if i?i>i?2 and Rz>Ri. It is also important to note that from the application point of view this circuit is very designable in that +E, —E, Ri, R2, R3, andi?4maybe varied independently rendering design easy for a variety of power supply values, etc. Also, the stability of the circuit is grounded base current gain sensitivity; i.e., a sensitivity, not /3 sensitivity which the circuit stable for a wide range of tr ansi stor par am eter s. 2. Transient conditions The fact that the ultra-stable network of Fig. 8(B) may be made unstable is shown in Fig. 9. Referring Fig. 9 when the "off" pair (T3 and T4) is turned on, the emitter resistances (i?i and Rs) are shunted by the base resistors (Ri and Rt) of the opposite transistor pair (7\ and J2). This is an unstable situation as may be seen from the current gain equation of Figure 8(A). (Note: Under no condi­ tion, except when the transistors have a common base current gain less than one- Fig. 15. Subrack

30 Baker—Symmetrical Transistor Logic z? M'\ — J •l / 1 :| • LZl I«i §1 1

Fig. 16. Subrack holder

Fig. 17 (right). Computer console

that apply to the flip-flop are applicable in this case.

Fast Logical Nets 1. D-c coupled A practical approach to building fast 3. Symmetry concepts allow the use of p n-p-n transistors (RCA thyristor's) show diode direct coupled nets is to keep the "opposite polarity" designs. that it is possible to construct a bistable currents through the diodes low (thus 4. Optimum speed bias conditions may circuit utilizing fewer components than do ordinary techniques (see Fig. 12). enabling the diode to switch on and off be utilized for the transistor through the quickly), keep the voltage swings low freedom to vary the transformer turns- ratio. (thus minimizing the effects of shunt III. Features of Basic Circuit capacity) and to use high-gain NRC These considerations show why it is Modules buffers. This approach is shown in Fig. possible to construct a-c nets with a 11. In addition to keeping the power propagation time of 10 millimicroseconds, The various circuit features that level low, important considerations of this (m/is) (and-or amplifier propagation time). directly affect system design are discussed network are: in the form of Tables I through IV. The Extension of NRC Techniques author would like to point out that it is 1. The logic is buffered after two levels, difficult to disciuss the relative merits of i.e., and-or-buffer-and-or-etc. It is the author's belief that NRC different circuit approaches as applied 2. The circuit utility is increased from techniques offer one of the more attractive to systems with a finite amount of words. a system standpoint by having both approaches for both higher speed and The reason of this is that evaluation by inverted and non-inverted output available. simpler, more powerful circuit design. necessity rests heavily upon experience 3. The clip levels are easily adjusted by The reasons for this are: and, hence, judgment, which is difficult providing a bleeder network at the base 1. NRC techniques which utilize p-n-p of the right hand n-p-n transistor. and n-p-n transistors do give rise to high 4. The symmetry of the circuitry and the prf circuitry that is convenient to design FLIP-FLOP (500 kc) resulting system organization (supplies, and use. etc.) allow an n-p-n para-phase invertor 2. It has been shown1 that the four-termi­ (NPI) easily obtainable by inverting the nal p-n-p-n devices are equivalent to a supplies, diode polarity and transistor pair of transistors. types. 3. Circuitry work with three-terminal 2. Fast a-c logical nets An example of fast a-c nets is shown in Figure 4. As in the d-c nets the power BUILDING BLOCKS level is kept small. The net clip level T/ T8 oOUT is adjustable through varying the emitter potential (bias). Other important considerations for this type of pulse net are:

1. The a-c load per input reflected to the clock source is minimized because the clock source merely turns off the input diode. 2. The diode reverse breakdown voltage may be low (2 to 3 volts) which gives the diode manufacturer freedom to concentrate Fig. 19(A). Low-speed shift register stage upon diode speed. Fig. 18. Building block concept (B). High-speed shift register stage

Baker—Symmetrical Transistor Logic 31 Table I. E. COMPUTER COMMENTS This computer contains about 20,000 Gain transistors and approximately 150,000 Type Circuit Propagation Time Fan In Fan Out diodes. The computer (which is now a working prototype) was built in about Symmetrical buffer 0.3 /is—5 mc units 1 10 30 staff years. Original estimates for the 0.03 us—50 mc units See discussion time to build this system was about one- Appendix I hundred staff years. Considering the Symmetrical flip-flop 0.3 yus—5 mc units 10 10 0.03 jts—50 mc units cost of research and development in a Appendix I Trailing-edge logic depends upon clock-rise time and diode delay 15 1 modern research laboratory per staff year, 0.05 us it is difficult to see how any other possible CRD gating diode delay time 15 1 10 m us circuit-system techniques could have Multilevel diode transistor nets dependent upon power level Av, AI 5 5 yielded a lower total prototype system 0.1 MS le vel with ordinary diodes and 5 mc transistors cost. Indeed if one now projects the sav­ ing in time (staff years) along with the time advantage of having a working sys­ Table II. Reliability tem for research studies (our major goal), we believe one will find a total saving in Temperature, Design- Circuit Type Component Power Transistor Noise Degrees C. ability actual dollars by a factor of 2 to 4 over any other possible approach. If one Buffer Very good Very good Very good. . -35 +65. . .Excellent further projects the saving in time to Fig. 1 noncritical the circuits . positive base construct other data processing systems set own level current supplied with the powerful time-saving circuit Flip-flop Very good Very good Very good. . -35 +55. . .Good techniques discussed, it is difficult to see Fig. 3 noncritical sets own level. . .noncritical. operation dependent any other circuit solution for this work. upon tran­ sistor stor­ age times Trailing -edge Good Very good . Good Excellent. . .Good V. System Comments gating dependent not amplitude... . clock and upon Re time sensitivity Re gate set constant and time constant by supply Analysis of the difficulties that were en­ clock pulse dependent countered while constructing CG24 width CRD gate. . . Good Excellent . Good Excellent Excellent showed that some of the fundamental de­ amplitude vice circuit system problems that are sensitive amplitudes significant are: set by supply 1. Use of high-speed transistors. Al­ Multilevel diode, .Fair Fair. .Fair. . Fair Good transistor nets though this was impossible at. the time See Appendix II CG24 was started (early 1956), the use of high-speed devices throughout the machine would lessen the clock source problem by to set down on paper. This is why the realization time (the desirability of this allowing lower power nets to be used as data are presented in tabular form. is discussed further in Section V). Fig. well as utilizing fewer devices. Every effort has been made to make the 13 is a typical flip-flop board with asso­ 2. Build the machine into a smaller tables as complete as practically possible; ciated input and output nets. Fig. 14 volume. Surprising though it is, the and it is only after long deliberation and shows a typical logic board from the major trouble with nets arose, not from static considerations but rather from even then in some cases with reluctance Arithm etic Section of the machine. Note transient considerations. The fan out- that the quantitative values have been that the component density was kept rea­ fan in problems on a static basis are far assigned. The key to the qualitative sonably low to facilitate speedy imple­ less important than propagation time description is: mentation of the circuits for the system. considerations. This is because the solu­ tion to fan out-in problems are simple in nature, where the solutions to propagation Excellent. . . almost all that could be desired B. SUBRACK Very good. . noncritical, performs well time problems are not usually so. Indeed Good...... all right under almost all Fig. 15 shows the circuit broad recep­ some of the problems involving timing conditions with normal care tacle and subrack. One subrack holds have been found difficult to even analyze, Fair works, but some care in design requiring a subtle knowledge of program­ 32 circuit boards of the type shown in must be taken ming, devices, circuits, and hardware the two preceding slides. techniques. In special cases where further explana­ 3. Use of a-c nets. Closely coupled with tion than that given in the tables is C. SUBRACK DOOR the just preceding discussion is the practical needed, the comments appear in the Fig. 16 describes the type of rack used problem of "debugging" the machine. The more liberal use of a-c nets facilitates appendixes. for mounting the subrack. The door the partitioning of nets for trouble shooting (subrack holder) accommodates 10 sub- without the excessive use of dummy loads, IV. Physical Properties racks yielding a card density of 320 cir­ etc. cuit cards per door. 4. Use of larger modules. The reliability A. CIRCUIT MODULES of the machine has been extremely good from As noted in the introduction, the data D. COMPUTER CONSOLE the standpoint of component failures. It would seem justifiable then to utilize a processing group represented has chosen Fig. 17 shows a picture of the computer higher component packing density and to sacrifice economy of components in console containing 10 doors or about 3,000 more circuits per board with a resulting order to save on "the circuits-to-system" circuit cards. saving in space, lead length, etc.

32 Baker—Symmetrical Transistor Logic Table III. NRC Circuits sideration, realistic limitations, and prac­ tical experience. Gain Type Circuit Propagation Time Fan In Fan Out Appendix I. Propagation Time Flip-flop 30 ttiMS 15 Fig. 8.. . based on 50 mc transistors diode current nets transistor driven 1. Symmetrical buffer. Fig. 1 Buffer.. 30 m /ts 1 . 7 Fig. TO The delay time through the circuit is D-c n°ts 50 m /us 15. . 7 approximately equal to the sum of the through an and-or- buffer combination A-c n?ts. 10 m us 15. conducting transistor (old state) minority .15 carrier storage tjme, and the rise (or fall) time of the trahsistor to be turned on. Table IV. Reliability The minority carrier storage in the transistor to be turned off; is shortened by the fact that a large current is drawn from its Circuit Temperature, collector by the opposite conducting tran­ Type Power Transistor Noise Degrees C. Designability Component sistor. The fall (rise) time of the output is fast because; standby current is not NRC Excellent. . . .Good Excellent Excellent -35 +55. Excellent required and, therefore, all of the collector Flip-flop a sensitive cir- a sensitive current of the conducting transistor (new Fig. 8 cuits emitter current set state) is available to charge shunt capacity Buffer Excellent. Good Excellent Good -35 +55. Excellent and to drive the load. same as flip-flop . Excellent Excellent Good -35 +55. . .Good D-c nsts Excellent. 2. Symmetrical flip-flop. Fig. 3 A-c nets Excellent. . Excellent Excellent Fair -35 +55. . .Good low level nets inherently Since the symmetrical flip flop is formed have poor from two buffer inverters, the propagation S/N ratios time is about the same as that for the buffer inverter circuit, i.e., about 0.3/xs for 5 mc transistors, and •about 0.03MS for 50 mc transistors. 5. System packaging. Future trends in­ of the high-speed stage is the fast shift There is no lpop delay in the circuit dicate faster devices, circuits and systems. rate that can be attained. Present packaging techniques will prove because the initijal transient does not re­ the major stumbling block to the realization It is believed that these techniques are quire feedback ajs the circuit is triggered of fast systems. well suited to: 1. realizing digital-data at all four transistor base terminals. 6. One of the most powerful system aids processing systems from basic circuits in that exist is a flexible set of circuits, par­ a minimum length of time, 2. advancing ticularly in this era of rapid technology the circuit art as such, 3. rendering feed­ Appendix ill. Multilevel Net advances. With this in mind, the building back information to the device field, 4. block concept shown in Fig. 18 is considered Propagation Time utilizing the most powerful logical tech­ to be important. The circuit makes use niques. Therefore, they should prove of a basic NRC flip-flop (7\ through Tt) The propagation time of a multilevel along with a set of delayed outputs (7V interesting to and be used by: 1. any net (type shown Jn Fig. 4) is difficult to set and T8) and a set of input amplifiers (T& industrial concern interested in prototype because the time! depends upon the power and Tis). The circuit may be made more machine design, large or small, 2. any re­ (impedance) lev

Baker—Symmetrical Transistor Logic 33