Symmetrical Transistor Logic A

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Symmetrical Transistor Logic A switching circuits by a substantially- age requirements. The total cost using 2. HIGH SPEED TRANSISTOR COMPUTER CIR­ CUITS, S. Y. Wong;, A. K. Rapp. IRE-AIEE smaller number of components and con­ DCTL is comparable with other tech­ Transistor Circuits Conference, Phila., Pa., Feb. nections, and by extremely-low power niques, because the tightly specified 1956. (Not published.) consumption. Circuit simplicity and low 3. HIGH-TEMPERATURE SILICON-TRANSISTOR COM­ transistor eliminates considerable com­ PUTER CIRCUITS, James B. Angell. Proceed­ dissipation are obtained at the price of plexity in system design and manufac­ ings of the Eastern • Joint Computer Conference, AIEE Special Publication T-92, Dec. 10-12, 1956, limited gain, small voltage swings, and a ture. pp. 54-57. comparatively low upper limit on in­ 4. LARGE-SIGNAL BEHAVIOR OP JUNCTION TRAN­ ternal temperature. Rather severe re­ SISTORS, J. J. Ebeijs, J. L. Moll. Proceedings, References Institute of Radio Engineers, New York, N. Y., quirements on transistor parameters, vol. 42, Dec. 1954, ij>p. 1761-72. 1. SURFACE-BARRIER TRANSISTOR SWITCHING CIR­ particularly input impedance and satura­ CUITS, R. H. Beter, W. E. Bradley, R. B. Brown, 5. TWO-COLLECTOR TRANSISTOR FOR BINARY tion voltage, are compensated by almost M. Rubinoff. Convention Record, Institute of FULL ADDER, R. F. Rtitz. IBM Journal of Research Radio Engineers, New York, N. Y., pt. IV, 1955, and Development, N^w York, N. Y., vol. 1, July negligible dissipation and maximum volt­ p. 139. 1957, pp. 212-22. I. Basic System Requirements Symmetrical Transistor Logic A. INITIAL The initial specific system for which the R. H. BAKER symmetrical cirpuit approach was in­ NONMEMBER AIEE tended had the following requirements: 1. General-purpose computer applicable HIS paper discusses symmetrical tran­ ment than do other types of circuitry to real time problem solution. sistor switching circuit techniques. that can be engineered to build the T 2. All solid-state machine. The circuitry is designated "symmetrical specific system. However, it is felt that circuits" because the basic circuits em­ this criticism is not justified in this case for 3. Nonairconditioned ground environment. ploy both p-n-p and n-p-n transistors in two reasons. They are: 1, The addi­ 4. Synchronous : machine with a basic approximately equal numbers which re­ tional cost of components required for clock rate of 3 microseconds, (/AS). sult in networks that exhibit a high degree symmetrical logic is more than counter­ 5. Memory capacity of 8,192 registers, of operational and topological symmetry. balanced by the shorter system realiza­ 28 bits in length, with a memory cycle The major practical advantage of this tion time required. This is particularly time of 6 MS. circuitry over other types lies in the ease true for an establishment, such as the 6. Semiportable housing. with which basic circuits may be Massachusetts Institute of Technology 7. Minimum conception to completion integrated into a digital system. This Lincoln Laboratory, that is engaged in time with a minimum of staff. advantage is made possible through, 1, system research and development. And, 8. Maximum reliability with minimum keeping the circuit configurations flexible 2, that symmetrical logic techniques are maintenance. (to satisfy many different system applica­ more adaptable to future developments i tions), 2, worst-case circuit design with in the device, circuits and system area B. ADDITIONAL regard to component stability and sys­ than other types of circuit logic. It was also tlie goal of the circuit de­ tem loading requirements, 3, use of only It is the purpose of this paper to show signer to build circuitry that was suffi­ standard commercially available com­ why, when, and under what conditions ciently flexible fo meet requirements for ponents, and 4, insisting that all present- symmetrical circuit techniques should be all other groundi-based digital-data proc­ day circuit designs be applicable to known used, along with probable future develop­ essing systems contemplated at the time future device trends. The major criti­ ments, through the discussion of the cir­ (there were several). cism of the symmetrical circuit techniques cuit techniques and relating their circuit is that the circuits require a greater num­ capabilities to the solution of system prob­ II. Basic Circuit Modules ber of components for a specific equip- lems. A. GENERAL COMMENTS + (V+AV) Aside from the general system require­ ments of Section; I, there are several other component-circuit-system requirements worthy of special note. They are: i—l-^M-i- OFF-** ON--OFF 1. That the circuits require minimum- specification components (single-ended + V specifications when possible). .-i- INPUT OUTPUT • j_Vu o . • WV—| O 2. That all components be commercially available stock ijtems. 3. That the circuit techniques be suffi­ ON —OFF—-ON ciently flexible to incorporate future higher performance devices to satisfy future Fig. 1 (right). R. H. BAKER is with the Massachusetts Institute Symmetrical buffer of Technology, Lincoln Laboratory, Lexington, inverter -(V+AV) Mass. Baker—Symmetrical Transistor Logic 27 LOGIC + X E F R AND OR PNP AND 9 9 b ?J IL + 2L T BIAS R {(ABCI + D}-E-F CLOCK iliii i -E + E -E -E Fig. 6. Multilevel logic nets -(V + AV) -(V+AV) 25 AND NPN fig. Fig. 2. Basic symmetrical flip-flop configura­ Fig. 4. A-c logic nets 1 2 tion 1 2 + 5 1us CLOCK A B JUL n Id" INPUT, CLOCK -W o JLi GATE prn l INPUT IJ J I Fig. 7. CRD gate Fig. 5. Trailing-edge logic Transient Considerations equal to /3 (grounded emitter transistor The important transient considerations current gain), i.e., of the symmetrical flip-flop may be seen J out 2v0l with the aid of Fig. 3. (1) Fig. 3. Symmetrical flip-flop ' 2vl ' vSalient points to note about the tran­ sient behavior of the network are: 6. The circuit is fast. This is so because higher-performance system requirements transistor hole/electron storage effects are 1. The hole storage of the saturated that may be needed. minimized. transistor is minimized because large current is drawn from its collector during 4. That the circuit designs concentrate 7. The transistor specifications are not critical. the storage time, thus clearing out the on fundamental device-network-system stored minority carriers quickly. principles, thereby pointing out future 8. The circuit has high utility and is 2. The rise and fall times, of the output, trends in these areas and furthering the flexible, i.e., the circuit may be: (a) used after the storage time is directly related state of the art. with any supply voltage within reason to the ability of the conducting transistor (note! Not necessarily equal positive and to delivery current at the collector terminal B. BUFFER INVERTER negative supplies), (b) designed with and the terminal capacitance. With the aforementioned system and different values of R and Rb for the p-n-p and n-p-n to accommodate nonsymmetrical 3. Transistor dissipation due to transient circuit requirements in mind and con­ loads; (c) used with different-type tran­ effect 1 and 2 set an upper limit to the sidering the transistor field as it existed in sistors to create unusual circuit effects, etc. average pulse repetition frequency of the 1955, it seemed advisible to utilize p-n-p circuit equal to approximately one-fifth transistors to generate fast "positive- C. FLIP-FLOP the value of the transistor frequency cutoff (txco), i-e., the use of 10 megacycles, (mc) going" transients and n-p-n transistors to D-C Considerations aco transistor result in a circuit pulse generate fast "negative-going" transients. repetition frequency (prf) of about 2 mc This was first done in the form of a buffer Two buffer inverters of the type shown maximum. in Fig. 1 may be connected together to inverter shown in Fig. 1. Some of the 4. The accumulation of charge on capaci­ salient features of the circuit shown in form a symmetrical flip-flop as shown in tors C by the transmission of trigger Fig. 1 are: Fig. 2. energy through it sets an upper limit to The d-c considerations of this circuit the maximum prf of about 0.15aco. 1. Each transistor has positive base are the same as for the buffer inverter 5. It is important to note that restrictions current applied while in the off condition number 3 and 4 allude to the average and the numerical value of this current is previously discussed. However it is maximum prf; the "burst" repetition rate equal to AF/Sj. worthwhile to point out that the ratio of can be considerably higher. This can be total power drain on the supplies to the 2. Resistor values R and i?& along with shown as follows: AV may be chosen to yield a small un­ power delivery at the output terminals Let g = accumulated charge on capacitor certainty region ( Vu). Vu may be centered is almost unity, i.e., C during one trigger pulse around ground or shifted up or down over a large range. 2vlr Since g = C AE (5) (2) 3. RL is merely a standby resistor and ^supplies -Pout + Pstanclby 2vIi/-\-4tvI where AE represents the change in voltage therefore can be almost any value. where IL = 7/3 (3) across C caused by one trigger pulse; 4. The circuit is current demand, that is, Pout 2w/57 1_ then g<iT it draws current (power) from the supplies then (6) in accordance with the load require­ * supplies 2 1+ where P=time between trigger pulses ments. , and i = charge current necessary to just 5. The circuit power gain is approximately = efficiency (4) discharge C in time T 28 Baker—Symmetrical Transistor Logic Thus, as T is made small, i.e., the pulse prf) current mode diode nets are used and 3.
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