The Design Philosophy of a Small Electronic Automatic
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Nanotechnology ? Nram (Nano Random Access
International Journal Of Engineering Research and Technology (IJERT) IFET-2014 Conference Proceedings INTERFACE ECE T14 INTRACT – INNOVATE - INSPIRE NANOTECHNOLOGY – NRAM (NANO RANDOM ACCESS MEMORY) RANJITHA. T, SANDHYA. R GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE 13. containing elements, nanotubes, are so small, NRAM technology will Abstract— NRAM (Nano Random Access Memory), is one of achieve very high memory densities: at least 10-100 times our current the important applications of nanotechnology. This paper has best. NRAM will operate electromechanically rather than just been prepared to cull out answers for the following crucial electrically, setting it apart from other memory technologies as a questions: nonvolatile form of memory, meaning data will be retained even What is NRAM? when the power is turned off. The creators of the technology claim it What is the need of it? has the advantages of all the best memory technologies with none of How can it be made possible? the disadvantages, setting it up to be the universal medium for What is the principle and technology involved in NRAM? memory in the future. What are the advantages and features of NRAM? The world is longing for all the things it can use within its TECHNOLOGY palm. As a result nanotechnology is taking its head in the world. Nantero's technology is based on a well-known effect in carbon Much of the electronic gadgets are reduced in size and increased nanotubes where crossed nanotubes on a flat surface can either be in efficiency by the nanotechnology. The memory storage devices touching or slightly separated in the vertical direction (normal to the are somewhat large in size due to the materials used for their substrate) due to Van der Waal's interactions. -
Technical Details of the Elliott 152 and 153
Appendix 1 Technical Details of the Elliott 152 and 153 Introduction The Elliott 152 computer was part of the Admiralty’s MRS5 (medium range system 5) naval gunnery project, described in Chap. 2. The Elliott 153 computer, also known as the D/F (direction-finding) computer, was built for GCHQ and the Admiralty as described in Chap. 3. The information in this appendix is intended to supplement the overall descriptions of the machines as given in Chaps. 2 and 3. A1.1 The Elliott 152 Work on the MRS5 contract at Borehamwood began in October 1946 and was essen- tially finished in 1950. Novel target-tracking radar was at the heart of the project, the radar being synchronized to the computer’s clock. In his enthusiasm for perfecting the radar technology, John Coales seems to have spent little time on what we would now call an overall systems design. When Harry Carpenter joined the staff of the Computing Division at Borehamwood on 1 January 1949, he recalls that nobody had yet defined the way in which the control program, running on the 152 computer, would interface with guns and radar. Furthermore, nobody yet appeared to be working on the computational algorithms necessary for three-dimensional trajectory predic- tion. As for the guns that the MRS5 system was intended to control, not even the basic ballistics parameters seemed to be known with any accuracy at Borehamwood [1, 2]. A1.1.1 Communication and Data-Rate The physical separation, between radar in the Borehamwood car park and digital computer in the laboratory, necessitated an interconnecting cable of about 150 m in length. -
Solid State Drives Data Reliability and Lifetime
Solid State Drives Data Reliability and Lifetime White Paper Alan R. Olson & Denis J. Langlois April 7, 2008 Abstract The explosion of flash memory technology has dramatically increased storage capacity and decreased the cost of non-volatile semiconductor memory. The technology has fueled the proliferation of USB flash drives and is now poised to replace magnetic hard disks in some applications. A solid state drive (SSD) is a non-volatile memory system that emulates a magnetic hard disk drive (HDD). SSDs do not contain any moving parts, however, and depend on flash memory chips to store data. With proper design, an SSD is able to provide high data transfer rates, low access time, improved tolerance to shock and vibration, and reduced power consumption. For some applications, the improved performance and durability outweigh the higher cost of an SSD relative to an HDD. Using flash memory as a hard disk replacement is not without challenges. The nano-scale of the memory cell is pushing the limits of semiconductor physics. Extremely thin insulating glass layers are necessary for proper operation of the memory cells. These layers are subjected to stressful temperatures and voltages, and their insulating properties deteriorate over time. Quite simply, flash memory can wear out. Fortunately, the wear-out physics are well understood and data management strategies are used to compensate for the limited lifetime of flash memory. Floating Gate Flash Memory Cells Flash memory was invented by Dr. Fujio Masuoka while working for Toshiba in 1984. The name "flash" was suggested because the process of erasing the memory contents reminded him of the flash of a camera. -
Embedded DRAM
Embedded DRAM Raviprasad Kuloor Semiconductor Research and Development Centre, Bangalore IBM Systems and Technology Group DRAM Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example References Slide 1 Acknowledgement • John Barth, IBM SRDC for most of the slides content • Madabusi Govindarajan • Subramanian S. Iyer • Many Others Slide 2 Topics Introduction to memory DRAM basics and bitcell array eDRAM operational details (case study) Noise concerns Wordline driver (WLDRV) and level translators (LT) Challenges in eDRAM Understanding Timing diagram – An example Slide 3 Memory Classification revisited Slide 4 Motivation for a memory hierarchy – infinite memory Memory store Processor Infinitely fast Infinitely large Cycles per Instruction Number of processor clock cycles (CPI) = required per instruction CPI[ ∞ cache] Finite memory speed Memory store Processor Finite speed Infinite size CPI = CPI[∞ cache] + FCP Finite cache penalty Locality of reference – spatial and temporal Temporal If you access something now you’ll need it again soon e.g: Loops Spatial If you accessed something you’ll also need its neighbor e.g: Arrays Exploit this to divide memory into hierarchy Hit L2 L1 (Slow) Processor Miss (Fast) Hit Register Cache size impacts cycles-per-instruction Access rate reduces Slower memory is sufficient Cache size impacts cycles-per-instruction For a 5GHz -
Chapter 1 Computer Basics
Chapter 1 Computer Basics 1.1 History of the Computer A computer is a complex piece of machinery made up of many parts, each of which can be considered a separate invention. abacus Ⅰ. Prehistory /ˈæbəkəs/ n. 算盘 The abacus, which is a simple counting aid, might have been invented in Babylonia(now Iraq) in the fourth century BC. It should be the ancestor of the modern digital calculator. Figure 1.1 Abacus Wilhelm Schickard built the first mechanical calculator in 1623. It can loom work with six digits and carry digits across columns. It works, but never /lu:m/ makes it beyond the prototype stage. n. 织布机 Blaise Pascal built a mechanical calculator, with the capacity for eight digits. However, it had trouble carrying and its gears tend to jam. punch cards Joseph-Marie Jacquard invents an automatic loom controlled by punch 穿孔卡片 cards. Difference Engine Charles Babbage conceived of a Difference Engine in 1820. It was a 差分机 massive steam-powered mechanical calculator designed to print astronomical tables. He attempted to build it over the course of the next 20 years, only to have the project cancelled by the British government in 1842. 1 新编计算机专业英语 Analytical Engine Babbage’s next idea was the Analytical Engine-a mechanical computer which 解析机(早期的机 could solve any mathematical problem. It used punch-cards similar to those used 械通用计算机) by the Jacquard loom and could perform simple conditional operations. countess Augusta Ada Byron, the countess of Lovelace, met Babbage in 1833. She /ˈkaʊntɪs/ described the Analytical Engine as weaving “algebraic patterns just as the n. -
TX-0 Computer After 10,000 Hours of Operation", L
tX If ,@8s~~~I 17A .:~- I-:· aTg Dc''n'_ !-41 2 . LK - ! v M IT6u i ~~6:illn -jW-~ 4 1 2 The RESEARCH LABORATORY of ELECTRONICS at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139 TX-O Computer History John A. McKenzie RLE Technical Report No. 627 June 1999 MASSACHUSETTS INSTITUTE OF TECHNOLOGY RESEARCH LABORATORY OF ELECTRONICS CAMBRIDGE, MASSACHUSETTS 02139 TX-O COMPUTER HISTORY John A. McKenzie October 1, 1974 TX-O COMPUTER HISTORY OUTLINE ABSTRA CT PART I (at LINCOLN ABORATORY) INTRODUCTION 1 DESCRIPTION 2 LOGIC 4 CIRCUITRY 5 MARGINAL CHECKING 6 TRANSISTORS MEMORY (S Memory) SOFTWARE (Initial) 9 TX-2 10 TRANSISTORIZED MEMORY (T Memory) 11 POWER CONTROL 12 IN-OUT RACK 13 CONSOLE 13 PART II (at CAMBRIDGE) INTRODUCTION 14 MOVE to CAMBRIDGE 15 EXTENDED INPUT/OUTPUT FACILITY, Addition of 16 FIRST YEAR at CAMBRIDGE 18 MODE of OPERATION 19 MACHINE EXPANSION PHASE 20 T-MEMORY EXPANSION 21 ORDER CODE ENLARGEMENT 22 DIGITAL MAGNETIC TAPE SYSTEM 24 SOFTWARE DEVELOPMENT 25 APPLICATIONS 29 TIMESHARING (PDP-1) 34 CONCLUSION 34 A CKNOWLEDGEMENT 35 BIBLIOGRAPHY TX-O COMPUTER HISTORY A BSTRA CT The TX-O Computer (meaning the Zeroth Transistorized Computer) was designed and constructed, in 1956, by the Lincoln Laboratory of the Massachusetts Institute of Tech- nology, with two purposes in mind. One objective was to test and evaluate the use of transistors as the logical elements of a high-speed, 5 MHz, general-purpose, stored-program, parallel, digital computer. The second purpose was to provide means for testing a large capacity (65,536 word) magnetic-core memory. -
Symmetrical Transistor Logic A
switching circuits by a substantially- age requirements. The total cost using 2. HIGH SPEED TRANSISTOR COMPUTER CIR CUITS, S. Y. Wong;, A. K. Rapp. IRE-AIEE smaller number of components and con DCTL is comparable with other tech Transistor Circuits Conference, Phila., Pa., Feb. nections, and by extremely-low power niques, because the tightly specified 1956. (Not published.) consumption. Circuit simplicity and low 3. HIGH-TEMPERATURE SILICON-TRANSISTOR COM transistor eliminates considerable com PUTER CIRCUITS, James B. Angell. Proceed dissipation are obtained at the price of plexity in system design and manufac ings of the Eastern • Joint Computer Conference, AIEE Special Publication T-92, Dec. 10-12, 1956, limited gain, small voltage swings, and a ture. pp. 54-57. comparatively low upper limit on in 4. LARGE-SIGNAL BEHAVIOR OP JUNCTION TRAN ternal temperature. Rather severe re SISTORS, J. J. Ebeijs, J. L. Moll. Proceedings, References Institute of Radio Engineers, New York, N. Y., quirements on transistor parameters, vol. 42, Dec. 1954, ij>p. 1761-72. 1. SURFACE-BARRIER TRANSISTOR SWITCHING CIR particularly input impedance and satura CUITS, R. H. Beter, W. E. Bradley, R. B. Brown, 5. TWO-COLLECTOR TRANSISTOR FOR BINARY tion voltage, are compensated by almost M. Rubinoff. Convention Record, Institute of FULL ADDER, R. F. Rtitz. IBM Journal of Research Radio Engineers, New York, N. Y., pt. IV, 1955, and Development, N^w York, N. Y., vol. 1, July negligible dissipation and maximum volt p. 139. 1957, pp. 212-22. I. Basic System Requirements Symmetrical Transistor Logic A. INITIAL The initial specific system for which the R. -
A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 6, JUNE 2011 1495 A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H. Kim, Senior Member, IEEE Abstract—Circuit techniques for enabling a sub-0.9 V logic-com- for achieving low static power and high operating speed. patible embedded DRAM (eDRAM) are presented. A boosted 3T SRAMs have been the embedded memory of choice due to gain cell utilizes Read Word-line (RWL) preferential boosting to their logic compatibility and fast access time. Recently, em- increase read margin and improve data retention time. Read speed is enhanced with a hybrid current/voltage sense amplifier that al- bedded DRAMs (eDRAMs) have been gaining popularity in lows the Read Bit-line (RBL) to remain close to VDD. A regu- the research community due to features such as small cell size, lated bit-line write scheme for driving the Write Bit-line (WBL) is low cell leakage, and non-ratioed circuit operation. There have equipped with a steady-state storage node voltage monitor to over- been a number of successful eDRAM designs based on tradi- come the data ‘1’ write disturbance problem of the PMOS gain cell without introducing another boosted supply for the Write Word- tional 1T1C DRAM cells as well as logic-compatible gain cells line (WWL) over-drive. An adaptive and die-to-die adjustable read [2]–[9]. 1T1C cells are denser than gain cells, but at the cost of a reference bias generator is proposed to cope with PVT variations. -
Charles Lindsey the Mechanical Differential Analyser Built by Metropolitan Vickers in 1935, to the Order of Prof
Issue Number 51 Summer 2010 Computer Conservation Society Aims and objectives The Computer Conservation Society (CCS) is a co-operative venture between the British Computer Society (BCS), the Science Museum of London and the Museum of Science and Industry (MOSI) in Manchester. The CCS was constituted in September 1989 as a Specialist Group of the British Computer Society. It is thus covered by the Royal Charter and charitable status of the BCS. The aims of the CCS are: To promote the conservation of historic computers and to identify existing computers which may need to be archived in the future, To develop awareness of the importance of historic computers, To develop expertise in the conservation and restoration of historic computers, To represent the interests of Computer Conservation Society members with other bodies, To promote the study of historic computers, their use and the history of the computer industry, To publish information of relevance to these objectives for the information of Computer Conservation Society members and the wider public. Membership is open to anyone interested in computer conservation and the history of computing. The CCS is funded and supported by voluntary subscriptions from members, a grant from the BCS, fees from corporate membership, donations, and by the free use of the facilities of both museums. Some charges may be made for publications and attendance at seminars and conferences. There are a number of active Projects on specific computer restorations and early computer technologies and software. -
An Electronic Digital Computor Using Cold Cathode Counting Tubes for Storage
An Electronic Digital Computor Using Cold Cathode Counting Tubes for Storage By R. C. M. Barnes, B.Sc., E. H. Cooke-Yarborough, M.A., A.M.I.E.E., and D. G. A. Thomas, M.A. Electronic Engineering - August 1951. A small sequence-controlled computor is described; it has storage capacity for up to 90 numbers each of eight decimal digits. Cold cathode counting tubes (Dekatrons) are used as storage elements. Parallel operation is employed, and the speed of operation is comparable with that of a desk calculating machine. Apart from speed, however, the computor provides most of the facilities found in larger, faster digital computors. Information is fed into the machine from perforated paper tapes and a teleprinter or tape perforator records the results. SEVERAL large-scale computors have been described in recent years, including the ENIAC with hard valve circuits, the EDSAC with mercury delay storage, the University of Manchester computor with cathode-ray storage and the Birkbeck College computor with magnetic storage. These computors are intended primarily to carry out enormous computations, too lengthy to perform by other means. In addition smaller scale relay computors have been built for general work. The machine described here is not intended to deal with the long calculations for which the large computors have been designed. It is intended rather to do the work of a few operators with desk calculating machines where the work to be done is of a routine or repetitive nature, As a result, simplicity and reliability have been regarded as of more importance than speed of operation and the machine performs the operations of addition, subtraction, multiplication and division little faster than a desk calculator. -
SRAM Edram DRAM
Technology Challenges and Directions of SRAM, DRAM, and eDRAM Cell Scaling in Sub- 20nm Generations Jai-hoon Sim SK hynix, Icheon, Korea Outline 1. Nobody is perfect: Main memory & cache memory in the dilemma in sub-20nm era. 2. SRAM Scaling: Diet or Die. 6T SRAM cell scaling crisis & RDF problem. 3. DRAM Scaling: Divide and Rule. Unfinished 1T1C DRAM cell scaling and its technical direction. 4. eDRAM Story: Float like a DRAM & sting like a SRAM. Does logic based DRAM process work? 5. All for one. Reshaping DRAM with logic technology elements. 6. Conclusion. 2 Memory Hierarchy L1$ L2$ SRAM Higher Speed (< few nS) Working L3$ Better Endurance eDRAM Memory (>1x1016 cycles) Access Speed Access Stt-RAM Main Memory DRAM PcRAM ReRAM Lower Speed Bigger Size Storage Class Memory NAND Density 3 Technologies for Cache & Main Memories SRAM • 6T cell. • Non-destructive read. • Performance driven process Speed technology. eDRAM • Always very fast. • 1T-1C cell. • Destructive read and Write-back needed. • Leakage-Performance compromised process technology. Standby • Smaller than SRAM and faster than Density Power DRAM. DRAM • 1T-1C cell. • Destructive read and Write-back needed. • Leakage control driven process technology. • Not always fast. • Smallest cell and lowest cost per bit. 4 eDRAM Concept: Performance Gap Filler SRAM 20-30X Cell Size Cell eDRAM DRAM 50-100X Random Access Speed • Is there any high density & high speed memory solution that could be 100% integrated into logic SoC? 5 6T-SRAM Cell Operation VDD WL WL DVBL PU Read PG SN SN WL Icell PD BL VSS BL V SN BL BL DD SN PD Read Margin: Write PG PG V Write Margin: SS PU Time 6 DRAM’s Charge Sharing DVBL VS VBL Charge Sharing Write-back VPP WL CS CBL V BL DD 1 SN C V C V C C V S DD B 2 DD S B BL 1/2VDD Initial Charge After Charge Sharing DVBL T d 1 1 V BL SS DVBL VBL VBL VDD 1 CB / CS 2 VBBW Time 1 1 I t L RET if cell leakage included Cell select DVBL VDD 1 CB / CS 2 CS 7 DRAM Scalability Metrics BL Cell WL CS • Cell CS. -
Talking About the Development Trend of Modern Computer Technology
2019 3rd International Conference on Computer Engineering, Information Science and Internet Technology (CII 2019) Talking about the Development Trend of Modern Computer Technology Yongpan Wang North China Electric Power University, Baoding 071000, China [email protected] Keywords: modern computer technology; development status; development trend. Abstract: Along with the development of the times and the advancement of society, the popularity of computer technology has not only changed the way people communicate, but also brought more help to economic development. Computer technology promotes the development of China's social economy and information security industry, but security risk management is still an urgent problem in the development of modern computer technology. The analysis from the development history of the computer can explore its technological development direction, and can also predict its development trend and contribute to the overall development of society. Therefore, this paper mainly discusses the development history of computer technology, analyzes its development status, and explores its development direction based on the above research. 1. Introduction The so-called computer is a modern intelligent electronic device that can be used for high-speed data and logic computing and with storage and modification functions. Computer belongs to a common item in our work life. It mainly has two parts of the main structure, some of which can be called hardware system, which is composed of hardware, which maintains the operation of the computer, and the other part is the software system to realize the function of the computer. The two together guarantee the normal operation of the computer. With the continuous advancement of science and technology, modern computer technology is also developing.