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Altivec Technology Programming Environments Manual for Power ISA Processors

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Altivec Technology Programming Environments Manual for Power ISA Processors AltiVec Technology Programming Environments Manual for Power ISA Processors ALTIVECPOWERISAPEM Rev 0 06/2014 How to Reach Us: Information in this document is provided solely to enable system and software Home Page: implementers to use Freescale products. There are no express or implied copyright freescale.com licenses granted hereunder to design or fabricate any integrated circuits based on the Web Support: information in this document. freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2014 Freescale Semiconductor, Inc. Document Number: ALTIVECPOWERISAPEM Rev 0, 06/2014 Contents Paragraph Page Number Title Number About ThisCont ents Book Audience ............................................................................................................................xv Organization..................................................................................................................... xvi Suggested Reading........................................................................................................... xvi General Information..................................................................................................... xvi Related Documentation............................................................................................... xvii Conventions .................................................................................................................... xvii Acronyms and Abbreviations......................................................................................... xviii Terminology Conventions..................................................................................................xx Chapter 1 Overview 1.1 History and Classification................................................................................................ 1-1 1.2 Overview.......................................................................................................................... 1-1 1.3 AltiVec Technology Overview......................................................................................... 1-3 1.3.1 Features Not Defined by AltiVec Architecture............................................................ 1-4 1.4 AltiVec Programming Model........................................................................................... 1-5 1.4.1 AltiVec Registers and Programming Model ................................................................ 1-5 1.4.2 Operand Conventions................................................................................................... 1-6 1.4.2.1 Byte Ordering .......................................................................................................... 1-6 1.4.2.2 Floating-Point Conventions ..................................................................................... 1-7 1.4.3 AltiVec Element Operations ........................................................................................ 1-7 1.4.4 AltiVec Instruction Set................................................................................................. 1-9 1.4.5 AltiVec Interrupt Model............................................................................................. 1-10 1.5 Changes from the Original AltiVec Definition .............................................................. 1-10 Chapter 2 AltiVec Register Set 2.1 AltiVec Register Set Overview ........................................................................................ 2-1 2.2 Registers Defined by AltiVec........................................................................................... 2-2 2.2.1 AltiVec Vector Register File (VRF)............................................................................. 2-2 2.2.2 Vector Status and Control Register (VSCR)................................................................ 2-3 2.2.3 Vector Save/Restore Register (VRSAVE).................................................................... 2-4 2.2.4 AltiVec IVOR Registers............................................................................................... 2-5 2.3 Non-Vector Category Registers Affected ........................................................................ 2-6 AltiVec Technology Programming Environments Manual for Power ISA Processors, Rev 0 Freescale Semiconductor iii Contents Paragraph Page Number Title Number 2.4 AltiVec Specific Fields in Supervisor Registers .............................................................. 2-6 Chapter 3 Operand Conventions 3.1 Data Organization in Memory ......................................................................................... 3-1 3.1.1 Aligned and Misaligned Accesses ............................................................................... 3-1 3.1.2 AltiVec Byte Ordering ................................................................................................. 3-2 3.1.2.1 Big-Endian Byte Ordering....................................................................................... 3-2 3.1.3 Quad Word Byte Ordering Example............................................................................ 3-2 3.1.4 Vector Register and Memory Access Alignment......................................................... 3-3 3.1.5 Quad-Word Data Alignment........................................................................................ 3-3 3.1.5.1 Accessing a Misaligned Quad Word in Big-Endian Mode...................................... 3-4 3.1.5.2 Scalar Loads and Stores........................................................................................... 3-5 3.1.5.3 Misaligned Scalar Loads and Stores........................................................................ 3-6 3.1.6 Mixed-Endian Systems ................................................................................................ 3-6 3.2 AltiVec Floating-Point Instructions ................................................................................. 3-6 3.2.1 Floating-Point Modes .................................................................................................. 3-7 3.2.1.1 Java Mode ................................................................................................................3-7 3.2.1.2 Non-Java Mode........................................................................................................ 3-7 3.2.2 Floating-Point Infinities............................................................................................... 3-8 3.2.3 Floating-Point Rounding ............................................................................................. 3-8 3.2.4 Floating-Point Exceptions............................................................................................ 3-8 3.2.4.1 NaN Operand Exception.......................................................................................... 3-8 3.2.4.2 Invalid Operation Exception .................................................................................... 3-9 3.2.4.3 Zero Divide Exception............................................................................................. 3-9 3.2.4.4 Log of Zero Exception........................................................................................... 3-10 3.2.4.5 Overflow Exception ............................................................................................... 3-10 3.2.4.6 Underflow Exception............................................................................................. 3-10 3.2.5 Floating-Point NaNs .................................................................................................. 3-11 3.2.5.1 NaN Precedence..................................................................................................... 3-11 3.2.5.2 SNaN Arithmetic ..................................................................................................
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