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Document Number: ALTIVECPOWERISAPEM Rev 0, 06/2014 Contents Paragraph Page Number Title Number About ThisCont ents Book Audience ............................................................................................................................xv Organization..................................................................................................................... xvi Suggested Reading........................................................................................................... xvi General Information..................................................................................................... xvi Related Documentation............................................................................................... xvii Conventions .................................................................................................................... xvii Acronyms and Abbreviations......................................................................................... xviii Terminology Conventions..................................................................................................xx Chapter 1 Overview 1.1 History and Classification................................................................................................ 1-1 1.2 Overview.......................................................................................................................... 1-1 1.3 AltiVec Technology Overview......................................................................................... 1-3 1.3.1 Features Not Defined by AltiVec Architecture............................................................ 1-4 1.4 AltiVec Programming Model........................................................................................... 1-5 1.4.1 AltiVec Registers and Programming Model ................................................................ 1-5 1.4.2 Operand Conventions................................................................................................... 1-6 1.4.2.1 Byte Ordering .......................................................................................................... 1-6 1.4.2.2 Floating-Point Conventions ..................................................................................... 1-7 1.4.3 AltiVec Element Operations ........................................................................................ 1-7 1.4.4 AltiVec Instruction Set................................................................................................. 1-9 1.4.5 AltiVec Interrupt Model............................................................................................. 1-10 1.5 Changes from the Original AltiVec Definition .............................................................. 1-10 Chapter 2 AltiVec Register Set 2.1 AltiVec Register Set Overview ........................................................................................ 2-1 2.2 Registers Defined by AltiVec........................................................................................... 2-2 2.2.1 AltiVec Vector Register File (VRF)............................................................................. 2-2 2.2.2 Vector Status and Control Register (VSCR)................................................................ 2-3 2.2.3 Vector Save/Restore Register (VRSAVE).................................................................... 2-4 2.2.4 AltiVec IVOR Registers............................................................................................... 2-5 2.3 Non-Vector Category Registers Affected ........................................................................ 2-6 AltiVec Technology Programming Environments Manual for Power ISA Processors, Rev 0 Freescale Semiconductor iii Contents Paragraph Page Number Title Number 2.4 AltiVec Specific Fields in Supervisor Registers .............................................................. 2-6 Chapter 3 Operand Conventions 3.1 Data Organization in Memory ......................................................................................... 3-1 3.1.1 Aligned and Misaligned Accesses ............................................................................... 3-1 3.1.2 AltiVec Byte Ordering ................................................................................................. 3-2 3.1.2.1 Big-Endian Byte Ordering....................................................................................... 3-2 3.1.3 Quad Word Byte Ordering Example............................................................................ 3-2 3.1.4 Vector Register and Memory Access Alignment......................................................... 3-3 3.1.5 Quad-Word Data Alignment........................................................................................ 3-3 3.1.5.1 Accessing a Misaligned Quad Word in Big-Endian Mode...................................... 3-4 3.1.5.2 Scalar Loads and Stores........................................................................................... 3-5 3.1.5.3 Misaligned Scalar Loads and Stores........................................................................ 3-6 3.1.6 Mixed-Endian Systems ................................................................................................ 3-6 3.2 AltiVec Floating-Point Instructions ................................................................................. 3-6 3.2.1 Floating-Point Modes .................................................................................................. 3-7 3.2.1.1 Java Mode ................................................................................................................3-7 3.2.1.2 Non-Java Mode........................................................................................................ 3-7 3.2.2 Floating-Point Infinities............................................................................................... 3-8 3.2.3 Floating-Point Rounding ............................................................................................. 3-8 3.2.4 Floating-Point Exceptions............................................................................................ 3-8 3.2.4.1 NaN Operand Exception.......................................................................................... 3-8 3.2.4.2 Invalid Operation Exception .................................................................................... 3-9 3.2.4.3 Zero Divide Exception............................................................................................. 3-9 3.2.4.4 Log of Zero Exception........................................................................................... 3-10 3.2.4.5 Overflow Exception ............................................................................................... 3-10 3.2.4.6 Underflow Exception............................................................................................. 3-10 3.2.5 Floating-Point NaNs .................................................................................................. 3-11 3.2.5.1 NaN Precedence..................................................................................................... 3-11 3.2.5.2 SNaN Arithmetic ..................................................................................................