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Power Architecture™ Technology Primer Power Architecture™ Technology Primer Power Architecture™ technology addresses a wide range of implementations from high-performance general purpose processors to revolutionary communication processors and highly integrated embedded microcontrollers. This book offers an introduction to Power Architecture technology as it applies to the amazingly diverse world of Freescale microprocessors and microcontrollers. freescale.com/powerarchitecture Power Architecture™ Technology Primer PWRARCPRMRM Rev. 1 05/2007 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support Information in this document is provided solely to enable system and software USA/Europe or Locations Not Listed: implementers to use Freescale Semiconductor products. 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[email protected] All other product or service names are the property of their respective owners. The For Literature Requests Only: Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. Freescale Semiconductor Literature Distribution Center © Freescale Semiconductor, Inc., 2006, 2007. All rights reserved. P.O. Box 5405 Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: PWRARCPRMRM Rev. 1, 05/2007 Contents Section Title Page Coevolution—Power Architecture™ Technology and its Environments....................................................1 The Power.org Community..........................................................................................................................2 History: The PowerPC Architecture ............................................................................................................2 The PowerPC Architecture Matures ......................................................................................................3 Architectural Extensibility—Alternatives to Book III’s Hardware-Based MMU Model......................4 Architectural Extensibility—AltiVec Technology.................................................................................4 Architectural Extensibility, Phase II—Book E, APUs, and Freescale’s EIS.........................................5 Auxiliary Processing Units (APUs).................................................................................................5 The Freescale Book E Implementation Standards (EIS) .................................................................5 Architectural Extensibility Phase III—The Power ISA Definition .......................................................6 Stability, Flexibility, Familiarity ......................................................................................................7 What’s New?..........................................................................................................................................9 What Has Changed?...............................................................................................................................9 Book I Changes and Extensions ......................................................................................................9 Book II Changes ............................................................................................................................11 Book III Changes...........................................................................................................................11 Power Architecture Details ........................................................................................................................12 The Common User Instruction Set Architecture .................................................................................12 An Overview of Categories .................................................................................................................13 The Embedded Category ...............................................................................................................13 AltiVec Technology (Category.Vector)..........................................................................................15 Floating-Point Categories—Floating-Point (FP) and Floating-Point with Record (FP.R) ............15 Move Assist (Category.MA)..........................................................................................................16 Signal Processing Engine (Category.SPE).....................................................................................16 Embedded Vector and Scalar Single-Precision Floating-Point Categories ...................................16 Book VLE Category ......................................................................................................................17 Wait (Category WT) ......................................................................................................................17 Instruction Model.......................................................................................................................................18 Simplified Mnemonics.........................................................................................................................19 Instruction Set Overview .....................................................................................................................19 Integer Instructions ........................................................................................................................19 Floating-Point Instructions (Category FP, FP.R) ...........................................................................21 Branch and Flow Control Instructions (Base Category)................................................................22 Processor Control Instructions (Base Category)............................................................................23 Memory Synchronization Instructions...........................................................................................24 Memory Control Instructions.........................................................................................................24 Register Model...........................................................................................................................................25 Register Files .......................................................................................................................................28 Instruction-Accessible Registers..........................................................................................................29 Power Architecture™ Technology Primer, Rev. 1 Freescale Semiconductor iii Contents
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