VXS, a High Speed Cu Switch Fabric Interconnect for VME
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Allgemeines Abkürzungsverzeichnis
Allgemeines Abkürzungsverzeichnis L. -
(12) United States Patent (10) Patent No.: US 7,676,600 B2 Davies Et Al
USOO7676600B2 (12) United States Patent (10) Patent No.: US 7,676,600 B2 Davies et al. (45) Date of Patent: Mar. 9, 2010 (54) NETWORK, STORAGE APPLIANCE, AND 4,245,344 A 1/1981 Richter METHOD FOR EXTERNALIZING AN INTERNAL AO LINK BETWEEN A SERVER AND A STORAGE CONTROLLER (Continued) INTEGRATED WITHIN THE STORAGE APPLIANCE CHASSIS FOREIGN PATENT DOCUMENTS (75) Inventors: Ian Robert Davies, Longmont, CO WO WOO21 O1573 12/2002 (US); George Alexander Kalwitz, Mead, CO (US); Victor Key Pecone, Lyons, CO (US) (Continued) (73) Assignee: Dot Hill Systems Corporation, OTHER PUBLICATIONS Longmont, CO (US) Williams, Al. “Programmable Logic & Hardware.” Dr. Dobb's Jour nal. Published May 1, 2003, downloaded from http://www.dd.com/ (*) Notice: Subject to any disclaimer, the term of this architect 184405342. pp. 1-7. patent is extended or adjusted under 35 U.S.C. 154(b) by 1546 days. (Continued) Primary Examiner Hassan Phillips (21) Appl. No.: 10/830,876 Assistant Examiner—Adam Cooney (22) Filed: Apr. 23, 2004 (74) Attorney, Agent, or Firm—Thomas J. Lavan: E. Alan pr. A5, Davis (65) Prior Publication Data (57) ABSTRACT US 2005/0027751A1 Feb. 3, 2005 Related U.S. Application Data A network Storage appliance is disclosed. The storage appli (60) Provisional application No. 60/473,355, filed on Apr. ance includes a port combiner that provides data COU1 23, 2003, provisional application No. 60/554,052, cation between at least first, second, and third I/O ports; a filed on Mar. 17, 2004. storage controller that controls storage devices and includes s the first I/O port; a server having the second I/O port; and an (51) Int. -
From Camac to Wireless Sensor Networks and Time- Triggered Systems and Beyond: Evolution of Computer Interfaces for Data Acquisition and Control
Janusz Zalewski / International Journal of Computing, 15(2) 2016, 92-106 Print ISSN 1727-6209 [email protected] On-line ISSN 2312-5381 www.computingonline.net International Journal of Computing FROM CAMAC TO WIRELESS SENSOR NETWORKS AND TIME- TRIGGERED SYSTEMS AND BEYOND: EVOLUTION OF COMPUTER INTERFACES FOR DATA ACQUISITION AND CONTROL. PART I Janusz Zalewski Dept. of Software Engineering, Florida Gulf Coast University Fort Myers, FL 33965, USA [email protected], http://www.fgcu.edu/zalewski/ Abstract: The objective of this paper is to present a historical overview of design choices for data acquisition and control systems, from the first developments in CAMAC, through the evolution of their designs operating in VMEbus, Firewire and USB, to the latest developments concerning distributed systems using, in particular, wireless protocols and time-triggered architecture. First part of the overview is focused on connectivity aspects, including buses and interconnects, as well as their standardization. More sophisticated designs and a number of challenges are addressed in the second part, among them: bus performance, bus safety and security, and others. Copyright © Research Institute for Intelligent Computer Systems, 2016. All rights reserved. Keywords: Data Acquisition, Computer Control, CAMAC, Computer Buses, VMEbus, Firewire, USB. 1. INTRODUCTION which later became international standards adopted by IEC and IEEE [4]-[7]. The design and development of data acquisition The CAMAC standards played a significant role and control systems has been driven by applications. in developing data acquisition and control The earliest and most prominent of those were instrumentation not only for nuclear research, but applications in scientific experimentation, which also for research in general and for industry as well arose in the early sixties of the previous century, [8]. -
Making the Switch to Rapidio
QNX Software Systems Ltd. 175 Terence Matthews Crescent Ottawa, Ontario, Canada, K2M 1W8 Voice: +1 613 591-0931 1 800 676-0566 Fax: +1 613 591-3579 Email: [email protected] Web: www.qnx.com Making the Switch to RapidIO Using a Message-passing Microkernel OS to Realize the Full Potential of the RapidIO Interconnect Paul N. Leroux Technology Analyst QNX Software Systems Ltd. [email protected] Introduction Manufacturers of networking equipment have hit a bottleneck. On the one hand, they can now move traffic from one network element to another at phenomenal speeds, using line cards that transmit data at 10 Gigabits per second or higher. But, once inside the box, data moves between boards, processors, and peripherals at a much slower clip: typically a few hundred megabits per second. To break this bottleneck, equipment manufacturers are seeking a new, high-speed — and broadly supported — interconnect. In fact, many have already set their sights on RapidIO, an open-standard interconnect developed by the RapidIO Trade Association and designed for both chip-to-chip and board-to-board communications. Why RapidIO? Because it offers low latency and extremely high bandwidth, as well as a low pin count and a small silicon footprint — a RapidIO interface can easily fit Making the Switch to RapidIO into the corner of a processor, FPGA, or ASIC. Locked Out by Default: The RapidIO is also transparent to software, allowing Problem with Conventional any type of data protocol to run over the intercon- Software Architectures nect. And, last but not least, RapidIO addresses the demand for reliability by offering built-in While RapidIO provides a hardware bus that is error recovery mechanisms and a point-to-point both fast and reliable, system designers must find or architecture that helps eliminate single points develop software that can fully realize the benefits of failure. -
Putting Switched Fabric to Work for Software Radio
PUTTING SWITCHED FABRIC TO WORK FOR SOFTWARE RADIO Rodger H. Hosking (Pentek, Inc., Upper Saddle River, NJ, USA, [email protected]) ABSTRACT In order to take advantage of the wealth of high- volume, low-cost devices for mass-market electronics, and The most difficult problem for designers of high- to reap the same benefits of easier connectivity, even the performance, software radio systems is simply moving data most powerful high-end software radio RISC and DSP within the system because of data throughput limitations. processors from Freescale and Texas Instruments are now Driving this dilemma are processors with higher clock rates sporting gigabit serial interfaces. and wider buses, data converter products with higher sampling rates, more complex digital communication 2. GIGABIT SERIAL STANDARDS standards with increased bandwidths, disk storage devices with faster I/O rates, FPGAs and DSPs offering incredible The descriptive phrase “gigabit serial” covers a truly diverse computational rates, and system connections and network range of implementations and application spaces. Figure 1 links operating at higher speeds. shows most of the popular standards used in embedded Traditional system architectures relying on buses and systems suitable for software radio, along with how each parallel connections between system boards and mezzanines standard is normally deployed in a system. fall far short of delivering the required peak rates, and suffer even worse if they must be shared and arbitrated. New Standard Main Application strategies for solving these problems exploit gigabit serial Gigabit Ethernet Computer Networking links and switched fabric standards to create significantly FibreChannel Data Storage more powerful architectures ideally suited for embedded software radio systems. -
VME, Gig-E, Serial Rapidio (Srio) Or PCI Express (Pcie) CONTROL
Model 67C3 6U, OpenVPX, MULTI-FUNCTION I/O CARD VME, Gig-E, Serial RapidIO (sRIO) or PCI Express (PCIe) CONTROL A/D, D/A, Discrete/TTL/CMOS/Differential I/O, RTD, Synchro/Resolver/LVDT/RVDT Measurement and Simulation, Encoder/Counter ARINC 429/575, RS-422/485/232, MIL-STD-1553, CANbus FEATURES Multiple functions on a single slot 6U OpenVPX card OpenVPX Slot Profile: SLT6-BRG-4F1V2T-10.5.1 User can specify up to six different function modules Automatic background BIT testing continually checks and reports the health of each channel Control via VME or Dual Gig-E interfaces PCIe (x1) options or sRIO (1x) Front and/or Rear I/O Conduction or Convection cooled versions Commercial and Rugged applications Software Support Kit and Drivers are available Front I/O GigE Front I/O DESCRIPTION The 67C3 is a single slot 6U OpenVPX Function Function Function Function Function Function (0.8” pitch) multi-function I/O and serial Module Module Module Module Module Module # 1 # 2 # 3 # 4 # 5 # 6 communications card. With VME, Gigabit Ethernet (Gig- E) and High Speed sRIO or PCIe control interface Module Module Module Module Module Module resources resources resources resources resources resources selections, users can confidently choose to take advantage of the OpenVPX form-factor offering higher speed switched fabric communication options. Inter Module Bus The motherboard contains six independent module slots, each of which can be populated with a function- specific module, and can now be controlled by the VME, Optional Board Resources Reference Gig-E and sRIO or PCIe. This enhanced motherboard, Generator using multiple DSPs, allows for higher processing power and dedicated control for each module. -
VXS Created in the First Place? VXS and VPX Are Both Based on the Same Multigig RT2 Connector Family
Frequently Asked Questions on 1. Why was VXS created in the first place? VXS and VPX are both based on the same MultiGig RT2 connector family. Mesh versions of VXS can match the slot-to-slot The VITA community needed a way to expand beyond the bandwidth of VPX. The primary advantage of VXS is the backward performance limitations of the solely parallel bus architectures compatibility with millions of existing VMEbus boards with the and incorporate serial fabrics. VXS offers backward compatibility edition of high-speed serial switch fabrics. to the VMEbus while adopting the use of serial signals such as Gigabit Ethernet, PCI Express, Serial RapidIO, and other fabrics. Each architecture has its own advantages that must be carefully considered. Designers should review factors such as A well-established ecosystem exists for VXS products. With more the ecosystem, architecture maturity/stability, pricing, power/ than 80 unique products offered in the market and deployed cooling requirements, I/O availability, bandwidth, and backwards throughout the world, the VXS architecture provides developers compatibility. with a logical extension and performance upgrade to their VME- based applications. 6. What’s the difference between VXS and VPX? 2. What are the general VXS features? VXS offers backwards compatibility for existing VME/VME64x • Backwards compatible to the VME/VME64x architecture. line cards for payload slots. VPX can offer compatibility through Enabling re-use of existing hardware and software. the use of hybrid backplanes with VME/VME64x slots. As VXS is • Uses high-speed Multi-Gig RT2 for P0 connector. based on a 0.8” pitch versus a typical 1.0” pitch for VPX, VXS offers • Switch card slot(s) in Star or Dual Star configurations. -
Rapidio™: an Embedded System Component Network Architecture
February 22, 2000 RapidIOª: An Embedded System Component Network Architecture Architecture and Systems Platforms Motorola Semiconductor Product Sector 7700 West Parmer Lane, MS: PL30 Austin, TX 78729 Abstract This paper describes RapidIO, a high performance low pin count packet switched sys- tem level interconnect architecture. The interconnect architecture is intended to be an open standard which addresses the needs of a variety of applications from embedded infrastructure to desktop computing. Applications include interconnecting microproces- sors, memory, and memory mapped I/O devices in networking equipment, storage sub- systems, and general purpose computing platforms. This interconnect is intended primarily as an intra-system interface, allowing chip to chip and board to board com- munications at giga-byte per second performance levels. Supported programming mod- els include globally shared distributed memory and message-passing. In its simplest form, the interface can be implemented in an FPGA end point. The interconnect archi- tecture deÞnes a protocol independent of a physical implementation. The physical fea- tures of an implementation utilizing the interconnect are deÞned by the requirements of the implementation, such as I/O signalling levels, interconnect topology, physical layer protocol, error detection, etc. The interconnect is deÞned as a layered architecture which allows scalability and future enhancements while maintaining compatibility. 1 of 25 Introduction 1 Introduction Computer and embedded system development continues to be burdened by divergent requirements. On one hand the performance must increase at a nearly logarithmic rate, while on the other hand system cost must stay the same or decrease. Several applica- tions, such as those found in telecommunications infrastructure equipment, are also bur- dened with increasing capabilities while decreasing the board size and ultimately the ßoor space which equipment occupies. -
2013 State of the VITA Technology Industry
2013 State of the VITA Technology Industry September 2013 P.O. Box 19658 Fountain Hills, AZ 85269 480.837.7486 [email protected] www.vita.com This page intentially left blank for double sided printing. State of the VITA Technology Industry September 2013 by: Ray Alderman, Executive Director, VITA This report provides the reader with updates on the state of the VITA Technology industry in particular and of the board industry in general, from the perspective of Ray Alderman, the executive director of VITA. VITA is the trade association dedicated to fostering American National Standards Institute (ANSI) accredited, open system architectures in critical embedded system applications. The complete series of reports can be found at Market Reports. (www.vita.com) Introduction This issue of the “State of the VITA Technology Industry” recaps our current economic Contents conditions We will also take a close look at unmanned vehicles of all types Optical backplanes have been on the horizon for many years, new innovation keeps moving us Introduction . 1 so ever slowly forward, but we are quickly running out of runway There have been a few deals made in the mergers and acquisition department, and to wrap it up, we will close Business Conditions . 1 with “Alderman’s Business Rules ” Markets. 3 MIL/Aero 3 Business Conditions Telecom 7 Optical Developments. 8 The final numbers for Q1 2013 U S GDP growth1 came in at a disappointing 1 8% after two earlier estimates of 2 4% The final Q1 GDP was revised to 1 1% by the Bureau of Mergers and Acquisitions 10 Economic Analysis (the Bureau of Economic Analysis issues a preliminary GDP number, and revises it three times until the next quarter GDP estimate is announced) While this Changing Business Models 10 is not exciting, it beats the situation we have seen in China2 and Europe3 in Q1 Market Estimates . -
Analysis and Optimisation of Communication Links for Signal Processing Applications
Analysis and Optimisation of Communication Links for Signal Processing Applications ANDREAS ÖDLING Examensarbete inom elektronik- och datorsystem, avancerad nivå, 30 hp Degree Project, in Electronic- and Computer Systems, second level School of Information and Communication Technology, ICT Royal Institute of Technology, KTH Supervisor: Johnny Öberg Examiner: Ingo Sander Stockholm, November 12, 2012 TRITA-ICT-EX-2012:287 Abstract There are lots of communication links and standards cur- rently being employed to build systems today. These meth- ods are in many way standardised, but far from everyone of them are. The trick is to select the communication method that best suit your needs. Also there is currently a trend that things have to be cheaper and have shorter time to market. That leads to more Component Off The Shelf (COTS) systems being build using commodity components. As one part of this work, Gigabit Ethernet is evaluated as a COTS-solution to building large, high-end systems. The computers used are running Windows and the pro- tocol used over Ethernet will be both TCP and UDP. In this work an attempt is also made to evaluate one of the non-standard protocols, the Link Port protocol for the TigerSHARC 20X-series, which is a narrow-bus, double- data-rate protocol, able to provide multi-gigabit-per-second performance. The studies have shown lots of interesting things, e.g. that using a standard desktop computer and network card, the theoretical throughput of TCP over Gigabit Ethernet can almost be met, reaching well over 900 Mbps. UDP performance gives on the other hand birth to a series of new questions about how to achieve good performance in a Windows environment, since it is constantly outperformed by the TCP connections. -
ISO/IEC JTC 1/SC 25 N 4Chi008 Date: 2004-06-22
ISO/IEC JTC 1/SC 25 N 4Chi008 Date: 2004-06-22 ISO/IEC JTC 1/SC 25 INTERCONNECTION OF INFORMATION TECHNOLOGY EQUIPMENT Secretariat: Germany (DIN) DOC TYPE: Administrative TITLE: Status of projects of SC25/WG 4, Chitose, Japan, 2004-06-22/24. SOURCE: ISO/IEC JTC 1/SC 25/WG 4 Convener PROJECT: All projects of SC 25/WG 4 STATUS: Agenda ACTION ID: FYI DUE DATE: n/a REQUESTED: For information ACTION MEDIUM: Open DISTRIBUTION: ITTF, JTC 1 Secretariat P-, L-, O-Members of SC 25 No of Pages: 08 (including cover) Page 1 of 8 Status of projects of WG 4, Chitose, Japan, 2004-06-22/24 6 Project 1.25.13.01.XX - Channel Interface Specifications: Fibre Distributed Data Interface (FDDI) 6.1. Project 1.25.13.01.03 - FDDI - Part 1: Physical Layer Protocol (PHY) [ISO 9314-1:1989] no action required 6.2. Project 1.25.13.01.04 - FDDI - Part 2: Media Access Control (MAC) [ISO 9314-2:1989] - - no action required 6.3. Project 1.25.13.01.05 - FDDI - Part 3: Physical Layer Medium Dependent (PMD) [ISO/IEC 9314-3:1990] no action required 6.4. Project 1.25.13.01.06 - FDDI - Part 4: Single-Mode Fibre Physical Layer Medium Dependent (SMF-PMD) [ISO/IEC 9314-4:1999] -- no action required 6.5. Project 1.25.13.01.07 - FDDI - Part 5: Hybrid Ring Control (HRC) [ISO/IEC 9314- 5:1995] no action required 6.6. Project 1.25.13.01.08 - FDDI - Part 6: Station Management (SMT) [ISO/IEC 9314- 6:1998] no action required 6.7. -
Serial Rapidio (SRIO)
TMS320C6472/TMS320TCI648x DSP Serial RapidIO (SRIO) User's Guide Literature Number: SPRUE13J October 2006–Revised February 2011 2 SPRUE13J–October 2006–Revised February 2011 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Preface ...................................................................................................................................... 15 1 Overview .......................................................................................................................... 16 1.1 General RapidIO System ............................................................................................. 16 1.2 RapidIO Feature Support in SRIO ................................................................................... 19 1.3 Standards ............................................................................................................... 20 1.4 External Devices Requirements ..................................................................................... 20 1.5 TI Devices Supported By This Document .......................................................................... 20 2 SRIO Functional Description ............................................................................................... 21 2.1 Overview ................................................................................................................ 21 2.2 SRIO Pins ............................................................................................................... 26 2.3 Functional Operation