ADC-VXS.1 AD001156

DUAL VME/VXS PMC Carrier

Design Specification

Version 1.02

Alpha Data

Copyright © 2006-7 Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Limited Alpha Data 4 West Silvermills Lane Edinburgh EH3 5BD Scotland UK Phone: +44 (0) 131 558 2600 Fax: +44 (0) 131 558 2700 Email: [email protected]

ADC-VXS.1 Board Design Specification Version 1.0

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Table of Contents

1. Introduction...... 1 2. Items Covered ...... 1 3. Standards ...... 1 4. Overview...... 2 5. VME Interface...... 5 5.1. Reset ...... 5 5.2. Configuration ...... 5 5.3. Keying...... 5 6. PMC/XMC Sites...... 5 6.1. PCI Central Resources...... 5 6.1.1. Arbiter...... 5 6.1.2. PCI-X and PCI Modes ...... 6 6.2. PrPMC Support ...... 6 6.3. Jx4 Interfaces ...... 6 6.4. Jx5 Primary XMC Interface...... 6 6.4.1. Jumper Options ...... 7 6.5. Jx6 Secondary XMC Interface ...... 7 6.6. Power Resources ...... 7 7. Copper / Optical Front Panel I/O Interfaces...... 8 8. Connector Pin Assignments...... 9 8.1. VME P1 and P2 ...... 9 8.2. PMC Sites (Jx1, Jx2, Jx3)...... 9 8.3. PMC Sites (Jx4)...... 9 8.4. XMC Sites (Jx5, Jx6) ...... 9 9. Revision History...... 10

ADC-VXS.1 Board Design Specification Version 1.0

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Figure 1 ADC-VXS.1 Board Block Diagram ...... 3 Figure 2 ADC-VXS.1 Board Layout...... 4 Figure 3 J16/J26 Interconnect ...... 7

ADC-VXS.1 Board Design Specification Version 1.0

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1. Introduction The ADC-VXS.1 Carrier is a 6U VXS VMEbus compatible board that can carry two PCI Mezzanine Cards, XMCs or hybrid PMC/XMC designs. The board can be configured as a simple PMC/XMC carrier card, or can be fitted with 2 Virtex5 LX110T devices for bridging and/or processing capabilities. The board is highly versatile and supports many different possible configurations for processing data between the 4 different interfaces. • VME Slave / Master • VXS Payload • PMC/XMC Host • Optical or copper Gigabit front I/O

2. Items Covered The Alpha Data drawing references allocated to the following units covered in this specification are listed below. AD01156 ADC-VXS.1 Board

3. Standards The ADC-VXS.1 is designed to meet VITA 41.0-200x VXS VME Switched Serial Standard. The ADC-VXS.1 card is designed for RoHS-6 compliance. The ADC-VXS.1 supports two PMC sites compliant to IEE1386-2001 and ANSI/VITA 39-2003. Additionally, each PMC/XMC site supports two XMC connectors compatible with VITA 42.0-2005 and VITA 42.2-2006 / VITA 42.3-2006. Other relevant standards. VITA35 Pn4 to P2 mapping ANSI/VITA1.1 VME64 Extensions ANSI/VITA39 PCI-X for PMC/PrPMC IEEE1101.2,.10 Mechanicals

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4. Overview The ADC-VXS.1 Card is a 6U VXS VME style carrier. It uses a Tundra Universe II bridge device to interface between a VME and a shared PCI bus capable of 33MHz operation. The PCI bus connects two PMC sites, and one of the Virtex5 devices. The Universe bridge can also be isolated from the bus for PCI-X 100MHz operation. The ADC-VXS.1 Card has connections between the J4 connectors of each PMC site and the backplane P2 for conventional I/O or other VME P2 add on busses including RACE++. Two Virtex-5 devices can connect the PMC/XMC sites to backplane fabric and provide the resources to support protocol conversion. There are also high speed switches to bypass the Virtex-5 devices for a direct connection to P0. Furthermore, these links are routed via high speed switches to allow 3 different configurations. 1. Each XMC site can connect to the Virtex-5 or P0 (x4) 2. XMC #2 can connect to the Virtex-5 devices or P0 (x8) 3. XMC #2 can connect to to the Virtex-5 or P0 (x4) and XMC #1 can connect to XMC #2 (x4)

The ADC-VXS.1 Card has Gigabit I/O on the front panel for optical (SFP) or copper (HSSDC2) connections. These serial links are routed via high speed switches to provide three different configurations. 1. Both Virtex-5 devices can interface with x2 full duplex lanes. 2. XMC site #1 can interface with x4 full duplex lanes. 3. XMC site #1 can interface with x2 full duplex lanes and one Virtex-5 can interface with x2 full duplex lanes. In addition, the Jx6 connectors of each PMC/XMC site are cross-wired to allow direct high speed communication between FPGA or other processor devices. For debug purposes, the ADC-VXS.1 has a JTAG interface that can be used to debug either or both PMC/XMC sites simultaneously with the ADC-VXS devices.

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5V0 to 3V3 Signal PCI-X 100 PCI 33 Universe P1 Conditioning / VME Disconnect II / P2

PCI-X 100

64

46

x4 x2 x4 X4 Signal X Repeater PMC/XMC x4 R 110T #1 M x4 x4 X4 P0 Local PCI-X 100 x8

x4 X x2 x4 X4 PMC/XMC R 110T #2 M x4 x4 x4

x4

HSSDC2 SFP x4 x4 Figure 1 ADC-VXS.1 Board Block Diagram

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Figure 2 ADC-VXS.1 Board Layout Note. PMC #2 is the upper of the two PMC sites shown in the layout diagram above. PMC #x1 is the lower in accordance with VITA35.

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5. VME Interface

5.1. Reset The ADC-VXS.1 is normally reset by the VMEBUS through the Tundra Universe II bridge. This in turn controls the reset of the PCI/PCI-X bus to the PMC sites. The on board CPLD also has the capability to route the reset from the PMC sites, XMC sites or from the Virtex-5 FPGA’s. The board has a 2 pin jumper that can connect to a push button for user reset input.

5.2. Configuration The ADC-VXS.1 supports both VME Slave and VME Master operation. The VME Slave supports A16, A24, A32, and A64 address spaces and D8, D16, D32, and D64 data transfer sizes. As a VME Master the ADC-VXS.1 can generate A16, A24, A32, and A64 VMEbus address cycles and D8 even, D8 odd, D16, D32, and D64 data transfers. The VME base address is selected via 2 rotary encoding switches. The addressing mode is selected via 4 DIP switches.

5.3. Keying The ADC-VXS.1 Card complies with the keying requirements for VXS cards and supports both A0 and K0. A0 by default has the value “1”. K0 is colour steel blue (key 1256) for VXS.4 PCI Express. K0 is colour pale orange (key 1247) for VXS.2 Serial RapidIO.

6. PMC/XMC Sites The ADC-VXS.1 Card provides two PMC/XMC sites, each of which can accept a PMC capable of PCI or PCI-X protocol. These sites have the full set of PMC connectors and are named [J11,J12,J13,J14] and [J21,J22,J23,J24] for site 1 and site 2 respectively. These are subsequently referred to as Jx1, Jx2, Jx3 and Jx4 when used for either site.

6.1. PCI Central Resources

6.1.1. Arbiter The ADC-VXS.1 Card contains a PCI arbiter capable of allocating the bus to 6 devices in a round-robin priority scheme. This configuration supports PrPMC cards which contain 2 REQ/GNT lines each.

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6.1.2. PCI-X and PCI Modes The ADC-VXS.1 Card is fitted with a fixed 33MHz oscillator which is buffered and routed to all PCI devices. There is a resistor option to route the clock source from a Virtex-5 device which can act as the PCI clock generator. The Virtex-5 device connected to the PCI bus is capable of auto-detecting the type of protocol supported by the plugged-in PMC. The board has circuitry to detect levels of PCIXCAP and M66EN to determine the type and speed of bus. The FPGA can then provide the clock and PCI-X initialization pattern to the PMC sites. In addition, 32 or 64 bit widths are supported and these too are auto-detected using standard procedures. Only PCI at 33MHz is available in the VME configuration when using the Universe II.

6.2. PrPMC Support The ADC-VXS.1 is capable of supporting a PrPMC as the bus controller. There are 2 DIP switches to assert the Monarch signals to the Jx2 connectors.

6.3. Jx4 Interfaces The ADC-VXS.1 is compatible with FPGA cards that provide signalling on Jx4 and provides a path that connects J14 and J24 to VME connector P2 using a direct route without any other circuits in place. The signals are wired in accordance with VITA35. PMC #1 is configured using VITA35 P4V2-46dz. PMC #2 is configured using VITA35 P4V2-64ac.

6.4. Jx5 Primary XMC Interface The ADC-VXS.1 Card routes 4 pairs of TX and RX serial signalling through an LX110T from each PMC/XMC site to the high speed P0 connector as shown in Fig 1. These links can also bypass the LX110T devices for a direct connection to P0. Mgt resources in the LX110T’s are allocated to support use of the embedded PCIe hard core on the P0 interfaces A clock source is provided on the ADC-VXS.1 using a 100MHz reference oscillator and this is fed through a PLL to provide buffered reference clocks to the REFCLK inputs on each of the Jx5 connectors and also the mgt refclk inputs to the respective LX110T devices. The frequency output by the PLL is selected by a CPLD on the ADC-VXS.1 and, by default, 100MHz is produced. This can be changed via a DIP switch to 125MHz and other frequencies are available with a CPLD firmware change.

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6.4.1. Jumper Options The ROOT signal can be asserted on either J15 or J25 by DIP switches. A CPLD on the ADC-VXS.1 can detect this and alter the reset strategy of the PMC sites but this only affects the Jx5 connections. The NVMRO signals can be asserted on either J15 or J25 by DIP switches to prevent memory writes on the XMC boards.

6.5. Jx6 Secondary XMC Interface The J16 and J26 connectors are configured to allow high speed communication between PMC/XMC sites local to the carrier card. There are 8 channels of TX/RX provided between the two secondary XMC connectors, sufficient for x8 PCI Express or other serial protocols. A reference clock is provided to both J16 and J26, similarly to that provided on J15 and J26.

J16 J26

TX TX

RX RX

PLL RefClk RefClk Buffer

100MHz

Figure 3 J16/J26 Interconnect

6.6. Power Resources Power is supplied to the PMC/XMC connectors directly from the VME backplane connectors on the +5V, +12V and -12V rails. 3.3V power is also supplied from the VME backplane connectors, or via an on-board power supply of the ADC-VXS.1. There is a jumper that must be installed to enable this power supply, and it should only be used if the VME bus does not provide this supply and no other loads are connected to the 3.3V power pins of the VME system.

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7. Virtex-5 Resources

7.1. Local Bus There is a 64 bit local bus connecting the 2 Virtex-5 devices, with either capable of being the master. There are also x4 duplex Gigabit links between the 2 FPGAs for a high speed local bus.

7.2. DRAM Each Virtex-5 Device supports 2 banks of DDR2 SDRAM x 32 bits.

7.3. Programming Each Virtex-5 Device has a XC32F platform flash for device programming, and a 32Mb SPI flash. Both FPGAs can be configured from their corresponding platform flashes, or one FPGA can program the other. There is a dedicated 25MHz oscillator for the programming interface which drives all of these devices. The oscillator will auto-disable after both FPGAs are configured. It can also be used as a user clock by fitting a jumper to keep it enabled. The ADC-VXS.1 Board has 2 DIP switches to select the programming modes of the FPGAs.

7.4. Clocks The ADC-VXS.1 Board provides a 200MHz reference oscillator for IODELAY calibration and user clocks. The board also provides a GTP reference clock with 8 selectable frequencies. There is dedicated routing between the 2 FPGAs for LCLK signalling. Either device can act as the local bus bridge, and generate the LCLK to the other.

7.5. System Monitoring The ADC-VXS.1 Board has a LM87 system monitor accessible from either Virtex-5. In addition, the power supply status signals are routed to both FPGAs.

8. Copper / Optical Front Panel I/O Interfaces

4 Copper/Optical interfaces are provided via the front panel using SFP modules and/or HSSDC2 connectors. Each LX110T will provide two channels. The links can also be routed to XMC site #1. The Virtex-5 Devices are able to interface with the SFP control signals, and drive 4 LED’s each.

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9. Connector Pin Assignments

9.1. VME P1 and P2 Standard pin-outs are used here.

9.2. PMC Sites (Jx1, Jx2, Jx3) Standard pin-outs are used here.

9.3. PMC Sites (Jx4) TBD

9.4. XMC Sites (Jx5, Jx6) As per XMC specification, VITA 42.2 and VITA 42.3.

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10. Revision History

Date Revision Nature of Change 24-09-2007 1.0 Created from ADC-VXS.0 Specification

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