DOCSLIB.ORG

Ensemble® 6000 Series Openvpx™ Intel® Xeon® D-15Xx Processor

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Ensemble® 6000 Series Openvpx™ Intel® Xeon® D-15Xx Processor Ensemble® 6000 Series OpenVPX™ Intel® Xeon® D-15xx Processor Family LDS6526 Low Density Server Blade with embedded I/O Xeon D processing performance, mezzanine sites, and built-in sensor I/O routed directly to the fabric via open architecture POET interface DATASHEET • 6U OpenVPX single server blade • Intel® Xeon® D (Broadwell microarchitecture) server-class processing • 40 Gigabit Ethernet high bandwidth SW defined fabrics • Four channels built-in sensor I/O • Dual XMC mezzanine sites • 16 GB DDR4-2400 SDRAM • PCIe connectivity to OpenVPX expansion plane The Ensemble LDS6526 is a 6U, OpenVPX™ processing blade Broadwell DE-Based Xeon D Ecosystem that seamlessly integrates the latest Intel® Xeon® D server- The Ensemble LDS6526 features a 64-bit Xeon D family processor class, general purpose processing capability with configurable which is protected and cooled by Mercury’s fifth generation of high- data plane and built-in sensor I/O pipes to form an ultra-wide- performance packaging, which has previously been deployed in prior band, powerful ingestion processing engine. generations of 6U OpenVPX LDS and HDS processing modules. The The Ensemble LDS6526 is an innovative integration of the best Xeon D family of processors includes a System on Chip (SoC) approach, general processing capability, configurable mezzanine sites, built-in combining the processor and the Intel platform controller hub (PCH) and SW defined I/O and data plane interfaces which are efficiently function within a single device. As a solderable BGA, the Xeon D family managed by FPGA-based Processing Packet Offload Engine Technol- extends the capability of the LDS architecture. As an example, the ogy (POET™). POET enables these interfaces to be bonded directly D-1559 device delivers up to 576 GFLOPS of processing power, which to the Intel processor or to remote endpoints connected to the data is a significant performance boost for the LDS architecture. With two plane fabric. high-speed DDR4-2400 memory controllers, the Xeon D processor is able to support up to 16 GB of DRAM, with future capabilities of up to The Ensemble LDS6526 is part of Mercury’s Xeon server-class eco- 32 GB per module. Significant PCIe interface capabilities are built in to system of building blocks that includes Xeon D-based high density the chip, which enable data interfaces both on and off-board. servers (HDS), high-speed switch modules, and FPGA- or GPU-based pre-processing modules. The inclusion of Xeon D based low-density The on-device PCH functionality enables the Ensemble LDS6526 to servers (LDS) brings additional processing resources to bear, access additional I/O, including USB and SATA on the backplane. The enabling processing and I/O on the module to remain balanced, Xeon D family of processors have dual 10 Gigabit Ethernet interfaces, avoiding data starvation or processor overload. enabling backplane access for sensor data or additional inter-processor communication and support for the AVX 2.0 instruction set that boosts www.mrcy.com floating-point algorithm performance and is portable to future Intel architectures. Mercury Systems is a leading commercial provider of secure processing subsystems designed and made in the USA. Optimized for customer and 100101010 100101010 100101010 100101010 100101010 001101011 001101011 001101011 001101011 001101011 mission success, Mercury’s solutions power a wide variety of critical 110101100 110101100 110101100 110101100 110101100 defense and intelligence programs. ACQUIRE ACQUIREDIGITIZE ACQUIREPROCESDIGITIZES ACQUIRESTORAGEPROCESDIGITIZES ACQUIRESTORAGEPROCESDIGITIZEEXPLOITS DISSEMINAACQUIRESTORAGEPROCESDIGITIZEEXPLOITSTE WARNING: “600 Series” and/or National Security Controls - These commodities, technology, or software are controlled for export from the United States in accor- dance with the Export Administration Act of 1979 as amended (Title 50 U.S.C.; App. 2401, et seq.), through the Export Administration Regulations (EAR). Transfers to foreign persons requires prior approval from the U.S. Department of Commerce, Bureau of Industry and Security. Integrated FPGA Resources High Speed Fabric Interfaces The Ensemble LDS6526 integrates an Altera Arria 10 FPGA device with The Ensemble LDS6526 continues the Mercury tradition of combining the Intel Xeon D processor to provide Mercury’s POET integrated data the processing power of Intel processors with high speed switched plane functionality and sensor I/O capabilities. The FPGA resources fabric interfaces. By scaling the data plane bandwidth to match the support the full OpenVPX data plane for flexible 40 Gigabit Ether- increase in processing performance, the Ensemble LDS6526 architec- net configurations, with the ability to support additional protocols, ture ensures that the processor is never starved for data. integrated switching, and high-speed DMA engines in a single device. By utilizing the Altera Arria 10 FPGA and innovative OpenVPX in- In addition to the data plane, the Ethernet control plane is integrated terconnect technology; the Ensemble LDS6526 is a model for open with the Altera device to allow for additional flexibility in configuration architecture high performance computing throughout the embedded and capability. By offloading traditional ASIC-based functionality in a industry. Mercury OpenVPX subsystems feature robust signal rates that FPGA, the Ensemble LDS6526 blade reduces DMS/EOL concerns for comfortably exceed the margin of the channel to surpass the rate of long-term support of program requirements. modern fabrics, delivering the fastest compute solution in the industry In addition to the data plane interfaces, the Ensemble LDS6526 deliv- with future proof performance headroom. ers four channels of protocol-configurable sensor I/O to the P6 user I/O PCIe Architecture connector. These high-speed sensor interfaces are interfaced with the The Ensemble LDS6526 provides on-board Gen3 PCIe switches for both POET FPGA-based switch and DMA functionality such that incoming on-board switching and off-board expansion. This switch complex pro- sensor data can be routed to the local Intel processor, or to remotely vides an x8 PCIe interface to each of the two XMC sites, as well as an connected fabric endpoints over the OpenVPX data plane. This elimi- x4 connection to a PCIe to PCI-X® bridge for the single PMC site. This nates the need for XMC-based sensor data feeds for many applica- allows mezzanines to operate at full bandwidth, optimizing the flow of tions, providing a significant cost advantage over similar OpenVPX I/O into the processing subsystem. Externally, the Ensemble LDS6526 products. PMC2/XMC2 IPMB-A / IPMB-B 5 5 5 P25 P2 P21 P23 Thermal, Optional – air-cooled only Voltage, P64s/X38s to Mezz. System Signals (P0/P1) PMC/XMC Current IPMC I/O on P3 P0 P22 P24 P26 Sensors REF_CLK Accessory AUX_CLK X12d+X8d to Mezz. PCIe to PCIx I/O on P4 Bridge x8 PCIe3 MUX x8 PCIe3 4x - SerDes P D XMC1 PCIe Switch 4x - SerDes P1 DDP D P15 Arria 10 x8 PCIe3 Gen3 4x - SerDes p x8 PCIe3 Ap POET FPGA XMC TA 4x - SerDes AT X38s to Mezz. SA eS e I/O on P5 P16 X12d+X8d to Mezz. F I/O on P6 R 16 SERDES to P6 O N T P2 x8 PCIe3 x8 PCIe3 P DDR4DDR4 8GB+E DDR4DDR4 8GB+E x16 PCIe3 A SSDRAMDRAM SSDRAMDRAM 10GBASE-KR from Xeon D CC CC 10GBASE-KR from Xeon D N DDP USB2.0 E SATA P3 DDR4 DDR 2600 RS-232/422/485 2600 L 4 P64S/X38s to Mezz X12d + X8d to Mezz 9 9 - RS-232 1000BASE-BX – CP2 DB uDB- u SATA x16 PCIe3 NAND Flash Intel Xeon D-15xx 1000BASE-BX – CP1 Ethernet interfaces to P4 PCH processor B USB (8-16 Cores) 1000BASE-T-Enet2 US MUX LPC TPM 1000BASE-T-Enet1 www.mrcy.com USB 2. USB 2. USB 3. x4 PCIe SA SA TA TA 0 0 0 USB 3.0 P5 USB 2.0 SATA Subsystem RTO SATA RJ-45RJ-45 16 SERDES to POET FPGA Air-cooledAir-cooled P6 only LDS6526 Figure 1 - LDS6525 functional block diagram WARNING: “600 Series” and/or National Security Controls - These commodities, technology, or software are controlled for export from the United States in accor- dance with the Export Administration Act of 1979 as amended (Title 50 U.S.C.; App. 2401, et seq.), through the Export Administration Regulations (EAR). Transfers to foreign persons requires prior approval from the U.S. Department of Commerce, Bureau of Industry and Security. implements a full Gen3 x16 PCIe connection to the OpenVPX expan- Additional Features sion plane on the P2 VPX connector. This expansion plane interface The Ensemble LDS6526 module provides all the features typically enables the Ensemble LDS6526’s compatibility with Mercury’s GPU or found on an avionics-class single-board computer. In addition to the FPGA based co-processing modules. These configuration options let sophisticated management subsystem and fabric interconnect, the En- the module effectively act as an upstream/downstream PCIe switch to semble LDS6526 module provides users with a toolkit enabling many allow the “chaining” of PCIe devices. different application features including: System Management • Thermal and voltage sensors integrated on-board The Ensemble LDS6526 module implements the advanced system man- • Real-time clock with accuracy better than 10ppm<1second per agement functionality inherent to the VITA 46.11 standard to enable day remote monitoring, alarm management, hardware revision and health • General purpose timers status. Using the standard IPMI-A and IPMI-B bus, intelligent platform management controller (IPMC), and IPMI protocol, the on-board system • Global clock synchronization capabilities via utility plane clock signals management block implementation is designed to comply with the VITA 46.11 standard. This allows the Ensemble LDS6526 module to: • Watchdog timer to support interrupt or reset • Read sensor values • Multiple boot paths, include netboot, USB boot, boot from SATA, • Read and write sensor thresholds, allowing an application to or from the on-board SATA flash device react to thermal, voltage, or current variations that exceed those thresholds Open Software Environment • Reset the entire module Mercury leverages over 30 years of multi-computing software exper- tise, including multicore processor expertise, across its many plat- • Power up/down the entire module forms.
Load more

Recommended publications
  • Allgemeines Abkürzungsverzeichnis
    Allgemeines Abkürzungsverzeichnis L.
    [Show full text]
  • From Camac to Wireless Sensor Networks and Time- Triggered Systems and Beyond: Evolution of Computer Interfaces for Data Acquisition and Control
    Janusz Zalewski / International Journal of Computing, 15(2) 2016, 92-106 Print ISSN 1727-6209 [email protected] On-line ISSN 2312-5381 www.computingonline.net International Journal of Computing FROM CAMAC TO WIRELESS SENSOR NETWORKS AND TIME- TRIGGERED SYSTEMS AND BEYOND: EVOLUTION OF COMPUTER INTERFACES FOR DATA ACQUISITION AND CONTROL. PART I Janusz Zalewski Dept. of Software Engineering, Florida Gulf Coast University Fort Myers, FL 33965, USA [email protected], http://www.fgcu.edu/zalewski/ Abstract: The objective of this paper is to present a historical overview of design choices for data acquisition and control systems, from the first developments in CAMAC, through the evolution of their designs operating in VMEbus, Firewire and USB, to the latest developments concerning distributed systems using, in particular, wireless protocols and time-triggered architecture. First part of the overview is focused on connectivity aspects, including buses and interconnects, as well as their standardization. More sophisticated designs and a number of challenges are addressed in the second part, among them: bus performance, bus safety and security, and others. Copyright © Research Institute for Intelligent Computer Systems, 2016. All rights reserved. Keywords: Data Acquisition, Computer Control, CAMAC, Computer Buses, VMEbus, Firewire, USB. 1. INTRODUCTION which later became international standards adopted by IEC and IEEE [4]-[7]. The design and development of data acquisition The CAMAC standards played a significant role and control systems has been driven by applications. in developing data acquisition and control The earliest and most prominent of those were instrumentation not only for nuclear research, but applications in scientific experimentation, which also for research in general and for industry as well arose in the early sixties of the previous century, [8].
    [Show full text]
  • Putting Switched Fabric to Work for Software Radio
    PUTTING SWITCHED FABRIC TO WORK FOR SOFTWARE RADIO Rodger H. Hosking (Pentek, Inc., Upper Saddle River, NJ, USA, [email protected]) ABSTRACT In order to take advantage of the wealth of high- volume, low-cost devices for mass-market electronics, and The most difficult problem for designers of high- to reap the same benefits of easier connectivity, even the performance, software radio systems is simply moving data most powerful high-end software radio RISC and DSP within the system because of data throughput limitations. processors from Freescale and Texas Instruments are now Driving this dilemma are processors with higher clock rates sporting gigabit serial interfaces. and wider buses, data converter products with higher sampling rates, more complex digital communication 2. GIGABIT SERIAL STANDARDS standards with increased bandwidths, disk storage devices with faster I/O rates, FPGAs and DSPs offering incredible The descriptive phrase “gigabit serial” covers a truly diverse computational rates, and system connections and network range of implementations and application spaces. Figure 1 links operating at higher speeds. shows most of the popular standards used in embedded Traditional system architectures relying on buses and systems suitable for software radio, along with how each parallel connections between system boards and mezzanines standard is normally deployed in a system. fall far short of delivering the required peak rates, and suffer even worse if they must be shared and arbitrated. New Standard Main Application strategies for solving these problems exploit gigabit serial Gigabit Ethernet Computer Networking links and switched fabric standards to create significantly FibreChannel Data Storage more powerful architectures ideally suited for embedded software radio systems.
    [Show full text]
  • VXS Created in the First Place? VXS and VPX Are Both Based on the Same Multigig RT2 Connector Family
    Frequently Asked Questions on 1. Why was VXS created in the first place? VXS and VPX are both based on the same MultiGig RT2 connector family. Mesh versions of VXS can match the slot-to-slot The VITA community needed a way to expand beyond the bandwidth of VPX. The primary advantage of VXS is the backward performance limitations of the solely parallel bus architectures compatibility with millions of existing VMEbus boards with the and incorporate serial fabrics. VXS offers backward compatibility edition of high-speed serial switch fabrics. to the VMEbus while adopting the use of serial signals such as Gigabit Ethernet, PCI Express, Serial RapidIO, and other fabrics. Each architecture has its own advantages that must be carefully considered. Designers should review factors such as A well-established ecosystem exists for VXS products. With more the ecosystem, architecture maturity/stability, pricing, power/ than 80 unique products offered in the market and deployed cooling requirements, I/O availability, bandwidth, and backwards throughout the world, the VXS architecture provides developers compatibility. with a logical extension and performance upgrade to their VME- based applications. 6. What’s the difference between VXS and VPX? 2. What are the general VXS features? VXS offers backwards compatibility for existing VME/VME64x • Backwards compatible to the VME/VME64x architecture. line cards for payload slots. VPX can offer compatibility through Enabling re-use of existing hardware and software. the use of hybrid backplanes with VME/VME64x slots. As VXS is • Uses high-speed Multi-Gig RT2 for P0 connector. based on a 0.8” pitch versus a typical 1.0” pitch for VPX, VXS offers • Switch card slot(s) in Star or Dual Star configurations.
    [Show full text]
  • 2013 State of the VITA Technology Industry
    2013 State of the VITA Technology Industry September 2013 P.O. Box 19658 Fountain Hills, AZ 85269 480.837.7486 [email protected] www.vita.com This page intentially left blank for double sided printing. State of the VITA Technology Industry September 2013 by: Ray Alderman, Executive Director, VITA This report provides the reader with updates on the state of the VITA Technology industry in particular and of the board industry in general, from the perspective of Ray Alderman, the executive director of VITA. VITA is the trade association dedicated to fostering American National Standards Institute (ANSI) accredited, open system architectures in critical embedded system applications. The complete series of reports can be found at Market Reports. (www.vita.com) Introduction This issue of the “State of the VITA Technology Industry” recaps our current economic Contents conditions We will also take a close look at unmanned vehicles of all types Optical backplanes have been on the horizon for many years, new innovation keeps moving us Introduction . 1 so ever slowly forward, but we are quickly running out of runway There have been a few deals made in the mergers and acquisition department, and to wrap it up, we will close Business Conditions . 1 with “Alderman’s Business Rules ” Markets. 3 MIL/Aero 3 Business Conditions Telecom 7 Optical Developments. 8 The final numbers for Q1 2013 U S GDP growth1 came in at a disappointing 1 8% after two earlier estimates of 2 4% The final Q1 GDP was revised to 1 1% by the Bureau of Mergers and Acquisitions 10 Economic Analysis (the Bureau of Economic Analysis issues a preliminary GDP number, and revises it three times until the next quarter GDP estimate is announced) While this Changing Business Models 10 is not exciting, it beats the situation we have seen in China2 and Europe3 in Q1 Market Estimates .
    [Show full text]
  • Vmebus Extensions for Instrumentation
    VMEbus Extensions for Instrumentation bus System Specification VXI-1 Revision 4.0 May 27, 2010 NOTICE The information contained in this document is subject to change without notice. The VXIbus Consortium, Inc. makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The VXIbus Consortium, Inc. shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance or use of this material. VMEbus Extensions for Instrumentation System Specification VXI-1, Revision 4.0 is authored by the VXIbus Consortium, Inc. and its sponsor members: Agilent Technologies Bustec EADS North America Defense Holding Informtest National Instruments Teradyne VTI Instruments ZTEC Certain portions of this document are derived, with permission, from the following VMEbus International Trade Organization (VITA) standards documents: ANSI/VITA 1.1-1994 (VME64), ANSI/VITA 1.1-1997 (VME64x), ANSI/VITA 1.5-2003 (2eSST), ANSI/VITA 41.0x-2006 (VXS Core), and VITA 41.6 (Control Channel on VXS). NOTE: The user‟s attention is called to the possibility that compliance with this standard may require use of one or more inventions covered by patent rights. By publication of this standard, no position is taken with respect to the validity of such claims or of any patent rights in connection therewith. The patent holders have, however, filed a statement of willingness to grant a license under these rights on reasonable and nondiscriminatory terms and conditions to applicants desiring to obtain such a license for use of this standard.
    [Show full text]
  • Ivme7210 Vmebus Processor Board
    iVME7210 VMEbus Processor Boardnnn Front page PRELIMINARY DATA SHEET FeaturingnIntel®nCore™ni7nprocessornvariantsnupnton2.0nGHznandnthenmobilenIntel®n QM57nExpressnchipset,nEmersonnNetworknPower’snnewniVME7210nisndesignednfornan The iVME7210 VMEbus rangenofnindustrial,nmedicalnandnmilitary/aerospacenapplicationsnincludingnrobotics,n processor board is compliant imagenprocessing,nradar/sonar,nC4ISRnandnsignalnintelligence.nOn-boardnmemoryn includesnupnton8GBnDDR3nmemorynandn256KBnnon-volatilenFerroelectricnRandomn with the VITA 41.3 VXS AccessnMemoryn(FeRAM).nFeRAMndoesnnotnrequirenbatteriesnornperiodicnrefreshesn Interior page specification andnoffersnmanynmorenread/writencyclesnandnfasternperformancenthannflashnmemory,n whichnbenefitsncriticalnnon-volatilendatanstorage,ndatanlogsnandndynamicnprogramn ® nnIntel nCore™ni7ndual-coren updates.nConnectivitynincludesnDVI-I,nfournGigabitnEthernetnports,nupntonthreenUSBn2.0n integratednprocessorn(1.06nGHzn ports,nfivenserialnports,nsinglenorndualnPMC/XMCnsitesnandnon-boardnSATAndrive. ULVnorn2.0nGHznLV) nn4GBnorn8GBnECC-protectedn Thenboard’snDigitalnVisualnInterfacen(DVI)nprovidesnsupportnfornhighnqualityndigitaln DDR3-1066n(soldered) graphicsnandnthenTrustednPlatformnModulen(TPM)nenhancesndatansecuritynandnencryp- ®n tionncapabilities.nTheniVME7210nsupportsnanrangenofnoperatingnsystemnandnsoftwaren nnMobilenIntel 5nSeriesnchipset:n optionsnincludingnWindnRivernVxWorks,nFedoran11/RednHatn6nLinuxnandnLynuxWorksn IbexnPeak-MnPlatformnn LynxOS.nExtendedntemperaturenandnruggednversionsnwillnbenavailablenvianEmersonn
    [Show full text]
  • System Solutions
    System Solutions Networked with the technologies of the future Your Partner FOR SINGLE-SOURCE MECHANICAL AND ELECTRONIC SYSTEMS nVent, with SCHROFF brand products, has been one of TABLE OF CONTENTS the worldwide leading developers and manufacturers of components and systems for over 50 years. Together we Scope of services ............................................................................... 3 can solve any technical challenge. Throughout this process innovation, cost optimization, component standardization as Open standards .................................................................................. 4 well as short development times are our focus. Markets ................................................................................................. 5 Whether they are system solutions that conform to standards, AdvancedTCA ...................................................................................... 6 modified standard components or even custom developments, we offer our expertise in mechanical and electronic systems. MicroTCA .............................................................................................. 7 Our development capabilities extend to backplanes, power CompactPCI ........................................................................................ 8 supplies and system management solutions. We provide fully-equipped and tested systems from a single source with VME, VXS and VPX ............................................................................. 9 design, project management,
    [Show full text]
  • Aurora Over Fiber Xilinx Reference Design
    Aurora Over Fiber Xilinx Reference Design Ransell often rubber motherless when unhallowed Filbert nitrogenizing ridiculously and plague her penetrant. Wye submerge his hammerhead trademarks alertly, but shelvy Bogart never subtotalling so seriatim. Anagrammatic Albert sometimes creolizes his photocopies innumerably and counterchecks so evenly! To low and with advanced xilinx fsbl example comes to write tlp that the device over fiber optics, using pcie extended capabilities by enclustra will be deleted Ethernet has evolved significantly over the past 35 years and similar by the. Reliability concerns with logical constants in Xilinx FPGA designs. Gtp_dual tile calorimeter of aurora over fiber xilinx reference design plays vital purposes only. Cash box and EPS All stock D R provides a edge of Xilinx aurora. The reference design? Data Acquisition and IO Digital Signal Processing FMC FPGA Optical Links. The mezzanine sites and xilinx_edk environment, and application we will be setup, opening of balancing between functional layers of future development board on isotropic semivariogram using aurora over fiber xilinx reference design and. Data Center Products reference designs and OpenPOWER support information. Over already last 15 years the one-man operation has evolved into an. VPX551 VadaTech. Is agnostic to the protocol any protocol such as PCIe SRIO 40GbE 10GbE GbE Aurora etc. About the FMC daughter card via an image sensor connected via. Fpga board Hillblooms School Mananthavady. AR 21263 Aurora Solution Center Xilinx. Flow and both memory write a whole new fpga over fiber optic data center aims to the eye scan instrument is desired when stress. This paper proposes a design and implementation of AFIFO using BRAM and high speed data.
    [Show full text]
  • VXS, a High Speed Cu Switch Fabric Interconnect for VME
    VXS, A High Speed Cu Switch Fabric Interconnect for VME Henry Wong Motorola [email protected] James Lee Fedder Tyco Electronics [email protected] James L Thompson Crane Division, Naval Surface [email protected] VME Renaissance • VME is a +20 year old technology. • VME Renaissance is an intense period of intellectual activity and technology infusion surrounding VMEbus • Many innovations, including but not limited to – Faster 2eSST parallel bus – Multi-gigabit switched serial interconnects – PCI-X chip to chip interconnect – PCI-X mezzanines – Point to point intra-connects – Point-to-point mezzanines 2 VMEbus Technology Roadmap Serial Data Parallel Serial NextNext Gen Gen Parallel Switched Fabric Plane SwitchedSwitched Switched Fabric Inter- • Ethernet, Fibre Ch • Raceway™ • Infiniband™ • HA fabric Connect • SKYchannel • Serial RapidIO™ • Mesh • 3GIO, etc. etc. etc. • Optical VME64 2eSST/PCI-X 2eSST/P2P Control VME64 2eSST/PCI-X 2eSST/P2P NextNext Gen Gen Plane VMEbusVMEbus VMEbusVMEbus VMEbusVMEbus VMEbusVMEbus Inter- • Universe II from Tundra • 8X speed improvement • 2eSST VME side Connect • Other proprietary chips • Backwards compatible • P-P Host side connect • QDR Technology • VXS – VMEbus Switched• VITA 1.5 Serial • Adds multi-gigabit per second Point-to-Point PMC PMCX Point-to-Point NextNext Gen Gen Mezzanine PMC PMCX Mezzanine switched serial links to VME Mezzanine MezzanineMezzanine Inter- Connect • Via• PCI a Mezzanine new CardsP0 connector• PCI-X Mezzanine Cards • P/S RapidIO™ • PMC & PrPMC • PMCX & PrPMCX • 3GIO • Hot plug • Dual• 64b/66MHz star based configuration• 64b/133MHz uses based one • Hypertransport • Front Access • VITA 39 • Infiniband™, etc. etc. or two switch cards Chip • MultiplePCI link technologies PointPoint-to-to-Point-Point to PCI PCIPCI-X-X Chip Connect Chip supported by structured Chip Connect Inter- • 64b/66MHz • 64b/133MHz • P/S RapidIO™ specification• Proprietary connects also • 3GIO Connect • Hypertransport • Additional power brought onto • etc.
    [Show full text]
  • ADC-VXS.0 Design Specification
    ADC-VXS.1 AD001156 DUAL VME/VXS PMC Carrier Design Specification Version 1.02 Alpha Data Copyright © 2006-7 Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Limited Alpha Data 4 West Silvermills Lane Edinburgh EH3 5BD Scotland UK Phone: +44 (0) 131 558 2600 Fax: +44 (0) 131 558 2700 Email: [email protected] ADC-VXS.1 Board Design Specification Version 1.0 Alpha Data Table of Contents 1. Introduction...............................................................................................1 2. Items Covered ..........................................................................................1 3. Standards .................................................................................................1 4. Overview...................................................................................................2 5. VME Interface...........................................................................................5 5.1. Reset .................................................................................................5 5.2. Configuration .....................................................................................5 5.3. Keying................................................................................................5 6. PMC/XMC Sites........................................................................................5
    [Show full text]
  • Embedded Computing Design November 2006 / 11 ©2006 Opensystems Publishing
    FFor o rSingle Sing Print le PrintOnly O n ly ©2006 OpenSystems Publishing. Not for distribution. FFor o rSingle Sing Print le PrintOnly O n ly RSC# 2 @ www.embedded-computing.com/rscRSC# 2 @ www.embedded-computing.com/rsc ©2006 OpenSystems Publishing. Not for distribution. FFor o rSingle Sing Print le PrintOnly O n ly RSC# 3 @ www.embedded-computing.com/rsc ©2006 OpenSystems Publishing. Not for distribution. www.embedded-computing.com VOLUME 4 • NUMBER 8 N O V EMBER 2 0 0 6 COLUMNS FEATURES 8 Editor’s Foreword SPECIAL: Telematics Embedded computing – the final definition 14 The evolution of telematics continues By Jerry Gipper By Steve Rosebaugh, Freescale 10 Eclipse Perspective and News Easing embedded Linux software development for SBCs TECHNOLOGY: RapidIO – current state of affairs By Nathan Gustavson and Eric Rossi 20 The state of RapidIO: strong, proud, open By Tom Cox, RapidIO Trade Association 26 Core of next-generation base station architectures utilize DEPARTMENTS Serial RapidIO switches to interconnect multiple DSPs 39 Editor’s Choice Products By Bill Beane, IDT, and Manish N. Patel, Texas Instruments By Jerry Gipper 27 Embedded systems: the future of RapidIO technology 40 New Products By Ernie Bergstrom, Crystal Cube Consulting By Chad Lumsden APPLICATION: Intelligent transportation systems, infrastructure, vehicles 28 Mobile cellular communication: not just for people EVENTS By Peter Fowler, Siemens electronica November 14-17 Wireless devices – handheld, New Munich Trade Fair Centre Munich, Germany APPLICATION: www.global-electronics.net/id/20308 instrumentation, control 32 The rise of Linux for the handset By Paxton Cooper, Monta Vista COVER FFor o rSingle Sing Print le PrintOnly O n ly Telematics is continually integrating new functions, adding complexity to 34 Why memory matters: the future of the mobile handset OEM solutions.
    [Show full text]