DOCSLIB.ORG

Serial Rapidio (SRIO)

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Serial Rapidio (SRIO) TMS320C6472/TMS320TCI648x DSP Serial RapidIO (SRIO) User's Guide Literature Number: SPRUE13J October 2006–Revised February 2011 2 SPRUE13J–October 2006–Revised February 2011 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Preface ...................................................................................................................................... 15 1 Overview .......................................................................................................................... 16 1.1 General RapidIO System ............................................................................................. 16 1.2 RapidIO Feature Support in SRIO ................................................................................... 19 1.3 Standards ............................................................................................................... 20 1.4 External Devices Requirements ..................................................................................... 20 1.5 TI Devices Supported By This Document .......................................................................... 20 2 SRIO Functional Description ............................................................................................... 21 2.1 Overview ................................................................................................................ 21 2.2 SRIO Pins ............................................................................................................... 26 2.3 Functional Operation .................................................................................................. 26 3 Logical/Transport Error Handling and Logging ..................................................................... 90 4 Interrupt Conditions ........................................................................................................... 92 4.1 CPU Interrupts ......................................................................................................... 92 4.2 General Description ................................................................................................... 92 4.3 Interrupt Condition Status and Clear Registers .................................................................... 93 4.4 Interrupt Condition Routing Registers ............................................................................. 101 4.5 Interrupt Status Decode Registers ................................................................................. 105 4.6 Interrupt Generation .................................................................................................. 107 4.7 Interrupt Pacing ....................................................................................................... 108 4.8 Interrupt Handling .................................................................................................... 108 5 SRIO Registers ................................................................................................................ 110 5.1 Peripheral Identification Register (PID) ............................................................................ 120 5.2 Peripheral Control Register (PCR) ................................................................................. 120 5.3 Peripheral Settings Control Register (PER_SET_CNTL) ....................................................... 122 5.4 Peripheral Settings Control Register 1 (PER_SET_CNTL1) (TMS320TCI6484 only) ...................... 125 5.5 Peripheral Global Enable Register (GBL_EN) .................................................................... 126 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) ................................................... 127 5.7 Block n Enable Register (BLKn_EN) .............................................................................. 129 5.8 Block n Enable Status Register (BLKn_EN_STAT) .............................................................. 130 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) .............................................................. 131 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) .............................................................. 132 5.11 RapidIO DEVICEID3 Register (DEVICEID_REG3) .............................................................. 133 5.12 RapidIO DEVICEID4 Register (DEVICEID_REG4) .............................................................. 134 5.13 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) ...................................... 135 5.14 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) ......................................... 136 5.15 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) ......................... 137 5.16 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) ........................ 140 5.17 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) .......................................... 142 5.18 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) ..................................... 144 5.19 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) ...................................... 145 5.20 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ........................................................... 146 SPRUE13J–October 2006–Revised February 2011 Table of Contents 3 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated www.ti.com 5.21 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) ............................................................ 147 5.22 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) ........................................................... 148 5.23 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ............................................................ 149 5.24 LSU Interrupt Condition Status Register (LSU_ICSR) .......................................................... 150 5.25 LSU Interrupt Condition Clear Register (LSU_ICCR) ........................................................... 153 5.26 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) .......... 154 5.27 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) ........... 155 5.28 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and DOORBELLn_ICRR2) ........................................................................................................................... 156 5.29 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) ................ 157 5.30 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) ................. 158 5.31 LSU Interrupt Condition Routing Registers (LSU_ICRR0-LSU_ICRR3) ...................................... 159 5.32 Error, Reset, and Special Event Interrupt Condition Routing Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) .................................................... 161 5.33 Interrupt Status Decode Register (INTDSTn_DECODE) ........................................................ 162 5.34 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) .......................................... 166 5.35 LSUn Control Register 0 (LSUn_REG0) .......................................................................... 167 5.36 LSUn Control Register 1 (LSUn_REG1) .......................................................................... 168 5.37 LSUn Control Register 2 (LSUn_REG2) .......................................................................... 169 5.38 LSUn Control Register 3 (LSUn_REG3) .......................................................................... 170 5.39 LSUn Control Register 4 (LSUn_REG4) .......................................................................... 171 5.40 LSUn Control Register 5 (LSUn_REG5) .......................................................................... 172 5.41 LSUn Control Register 6 (LSUn_REG6) .......................................................................... 173 5.42 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) ..................................... 174 5.43 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) ..................... 176 5.44 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) ............................. 177 5.45 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) ..................... 178 5.46 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) ............................. 179 5.47 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) ........................................... 180 5.48 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0-7]) .......................... 181 5.49 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) ........................................... 184 5.50 Receive CPPI Control Register (RX_CPPI_CNTL) .............................................................. 185 5.51 Transmit CPPI Weighted Round-Robin Control Registers (TX_QUEUE_CNTL[0-3]) ....................... 186 5.52 Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn) ................................. 190 5.53 Flow Control Table Entry Register n (FLOW_CNTLn) .......................................................... 194 5.54 Device Identity CAR (DEV_ID) ..................................................................................... 195 5.55 Device Information CAR (DEV_INFO) ............................................................................
Load more

Recommended publications
  • (12) United States Patent (10) Patent No.: US 7,676,600 B2 Davies Et Al
    USOO7676600B2 (12) United States Patent (10) Patent No.: US 7,676,600 B2 Davies et al. (45) Date of Patent: Mar. 9, 2010 (54) NETWORK, STORAGE APPLIANCE, AND 4,245,344 A 1/1981 Richter METHOD FOR EXTERNALIZING AN INTERNAL AO LINK BETWEEN A SERVER AND A STORAGE CONTROLLER (Continued) INTEGRATED WITHIN THE STORAGE APPLIANCE CHASSIS FOREIGN PATENT DOCUMENTS (75) Inventors: Ian Robert Davies, Longmont, CO WO WOO21 O1573 12/2002 (US); George Alexander Kalwitz, Mead, CO (US); Victor Key Pecone, Lyons, CO (US) (Continued) (73) Assignee: Dot Hill Systems Corporation, OTHER PUBLICATIONS Longmont, CO (US) Williams, Al. “Programmable Logic & Hardware.” Dr. Dobb's Jour nal. Published May 1, 2003, downloaded from http://www.dd.com/ (*) Notice: Subject to any disclaimer, the term of this architect 184405342. pp. 1-7. patent is extended or adjusted under 35 U.S.C. 154(b) by 1546 days. (Continued) Primary Examiner Hassan Phillips (21) Appl. No.: 10/830,876 Assistant Examiner—Adam Cooney (22) Filed: Apr. 23, 2004 (74) Attorney, Agent, or Firm—Thomas J. Lavan: E. Alan pr. A5, Davis (65) Prior Publication Data (57) ABSTRACT US 2005/0027751A1 Feb. 3, 2005 Related U.S. Application Data A network Storage appliance is disclosed. The storage appli (60) Provisional application No. 60/473,355, filed on Apr. ance includes a port combiner that provides data COU1 23, 2003, provisional application No. 60/554,052, cation between at least first, second, and third I/O ports; a filed on Mar. 17, 2004. storage controller that controls storage devices and includes s the first I/O port; a server having the second I/O port; and an (51) Int.
    [Show full text]
  • Making the Switch to Rapidio
    QNX Software Systems Ltd. 175 Terence Matthews Crescent Ottawa, Ontario, Canada, K2M 1W8 Voice: +1 613 591-0931 1 800 676-0566 Fax: +1 613 591-3579 Email: [email protected] Web: www.qnx.com Making the Switch to RapidIO Using a Message-passing Microkernel OS to Realize the Full Potential of the RapidIO Interconnect Paul N. Leroux Technology Analyst QNX Software Systems Ltd. [email protected] Introduction Manufacturers of networking equipment have hit a bottleneck. On the one hand, they can now move traffic from one network element to another at phenomenal speeds, using line cards that transmit data at 10 Gigabits per second or higher. But, once inside the box, data moves between boards, processors, and peripherals at a much slower clip: typically a few hundred megabits per second. To break this bottleneck, equipment manufacturers are seeking a new, high-speed — and broadly supported — interconnect. In fact, many have already set their sights on RapidIO, an open-standard interconnect developed by the RapidIO Trade Association and designed for both chip-to-chip and board-to-board communications. Why RapidIO? Because it offers low latency and extremely high bandwidth, as well as a low pin count and a small silicon footprint — a RapidIO interface can easily fit Making the Switch to RapidIO into the corner of a processor, FPGA, or ASIC. Locked Out by Default: The RapidIO is also transparent to software, allowing Problem with Conventional any type of data protocol to run over the intercon- Software Architectures nect. And, last but not least, RapidIO addresses the demand for reliability by offering built-in While RapidIO provides a hardware bus that is error recovery mechanisms and a point-to-point both fast and reliable, system designers must find or architecture that helps eliminate single points develop software that can fully realize the benefits of failure.
    [Show full text]
  • VME, Gig-E, Serial Rapidio (Srio) Or PCI Express (Pcie) CONTROL
    Model 67C3 6U, OpenVPX, MULTI-FUNCTION I/O CARD VME, Gig-E, Serial RapidIO (sRIO) or PCI Express (PCIe) CONTROL A/D, D/A, Discrete/TTL/CMOS/Differential I/O, RTD, Synchro/Resolver/LVDT/RVDT Measurement and Simulation, Encoder/Counter ARINC 429/575, RS-422/485/232, MIL-STD-1553, CANbus FEATURES Multiple functions on a single slot 6U OpenVPX card OpenVPX Slot Profile: SLT6-BRG-4F1V2T-10.5.1 User can specify up to six different function modules Automatic background BIT testing continually checks and reports the health of each channel Control via VME or Dual Gig-E interfaces PCIe (x1) options or sRIO (1x) Front and/or Rear I/O Conduction or Convection cooled versions Commercial and Rugged applications Software Support Kit and Drivers are available Front I/O GigE Front I/O DESCRIPTION The 67C3 is a single slot 6U OpenVPX Function Function Function Function Function Function (0.8” pitch) multi-function I/O and serial Module Module Module Module Module Module # 1 # 2 # 3 # 4 # 5 # 6 communications card. With VME, Gigabit Ethernet (Gig- E) and High Speed sRIO or PCIe control interface Module Module Module Module Module Module resources resources resources resources resources resources selections, users can confidently choose to take advantage of the OpenVPX form-factor offering higher speed switched fabric communication options. Inter Module Bus The motherboard contains six independent module slots, each of which can be populated with a function- specific module, and can now be controlled by the VME, Optional Board Resources Reference Gig-E and sRIO or PCIe. This enhanced motherboard, Generator using multiple DSPs, allows for higher processing power and dedicated control for each module.
    [Show full text]
  • Rapidio™: an Embedded System Component Network Architecture
    February 22, 2000 RapidIOª: An Embedded System Component Network Architecture Architecture and Systems Platforms Motorola Semiconductor Product Sector 7700 West Parmer Lane, MS: PL30 Austin, TX 78729 Abstract This paper describes RapidIO, a high performance low pin count packet switched sys- tem level interconnect architecture. The interconnect architecture is intended to be an open standard which addresses the needs of a variety of applications from embedded infrastructure to desktop computing. Applications include interconnecting microproces- sors, memory, and memory mapped I/O devices in networking equipment, storage sub- systems, and general purpose computing platforms. This interconnect is intended primarily as an intra-system interface, allowing chip to chip and board to board com- munications at giga-byte per second performance levels. Supported programming mod- els include globally shared distributed memory and message-passing. In its simplest form, the interface can be implemented in an FPGA end point. The interconnect archi- tecture deÞnes a protocol independent of a physical implementation. The physical fea- tures of an implementation utilizing the interconnect are deÞned by the requirements of the implementation, such as I/O signalling levels, interconnect topology, physical layer protocol, error detection, etc. The interconnect is deÞned as a layered architecture which allows scalability and future enhancements while maintaining compatibility. 1 of 25 Introduction 1 Introduction Computer and embedded system development continues to be burdened by divergent requirements. On one hand the performance must increase at a nearly logarithmic rate, while on the other hand system cost must stay the same or decrease. Several applica- tions, such as those found in telecommunications infrastructure equipment, are also bur- dened with increasing capabilities while decreasing the board size and ultimately the ßoor space which equipment occupies.
    [Show full text]
  • Analysis and Optimisation of Communication Links for Signal Processing Applications
    Analysis and Optimisation of Communication Links for Signal Processing Applications ANDREAS ÖDLING Examensarbete inom elektronik- och datorsystem, avancerad nivå, 30 hp Degree Project, in Electronic- and Computer Systems, second level School of Information and Communication Technology, ICT Royal Institute of Technology, KTH Supervisor: Johnny Öberg Examiner: Ingo Sander Stockholm, November 12, 2012 TRITA-ICT-EX-2012:287 Abstract There are lots of communication links and standards cur- rently being employed to build systems today. These meth- ods are in many way standardised, but far from everyone of them are. The trick is to select the communication method that best suit your needs. Also there is currently a trend that things have to be cheaper and have shorter time to market. That leads to more Component Off The Shelf (COTS) systems being build using commodity components. As one part of this work, Gigabit Ethernet is evaluated as a COTS-solution to building large, high-end systems. The computers used are running Windows and the pro- tocol used over Ethernet will be both TCP and UDP. In this work an attempt is also made to evaluate one of the non-standard protocols, the Link Port protocol for the TigerSHARC 20X-series, which is a narrow-bus, double- data-rate protocol, able to provide multi-gigabit-per-second performance. The studies have shown lots of interesting things, e.g. that using a standard desktop computer and network card, the theoretical throughput of TCP over Gigabit Ethernet can almost be met, reaching well over 900 Mbps. UDP performance gives on the other hand birth to a series of new questions about how to achieve good performance in a Windows environment, since it is constantly outperformed by the TCP connections.
    [Show full text]
  • ISO/IEC JTC 1/SC 25 N 4Chi008 Date: 2004-06-22
    ISO/IEC JTC 1/SC 25 N 4Chi008 Date: 2004-06-22 ISO/IEC JTC 1/SC 25 INTERCONNECTION OF INFORMATION TECHNOLOGY EQUIPMENT Secretariat: Germany (DIN) DOC TYPE: Administrative TITLE: Status of projects of SC25/WG 4, Chitose, Japan, 2004-06-22/24. SOURCE: ISO/IEC JTC 1/SC 25/WG 4 Convener PROJECT: All projects of SC 25/WG 4 STATUS: Agenda ACTION ID: FYI DUE DATE: n/a REQUESTED: For information ACTION MEDIUM: Open DISTRIBUTION: ITTF, JTC 1 Secretariat P-, L-, O-Members of SC 25 No of Pages: 08 (including cover) Page 1 of 8 Status of projects of WG 4, Chitose, Japan, 2004-06-22/24 6 Project 1.25.13.01.XX - Channel Interface Specifications: Fibre Distributed Data Interface (FDDI) 6.1. Project 1.25.13.01.03 - FDDI - Part 1: Physical Layer Protocol (PHY) [ISO 9314-1:1989] no action required 6.2. Project 1.25.13.01.04 - FDDI - Part 2: Media Access Control (MAC) [ISO 9314-2:1989] - - no action required 6.3. Project 1.25.13.01.05 - FDDI - Part 3: Physical Layer Medium Dependent (PMD) [ISO/IEC 9314-3:1990] no action required 6.4. Project 1.25.13.01.06 - FDDI - Part 4: Single-Mode Fibre Physical Layer Medium Dependent (SMF-PMD) [ISO/IEC 9314-4:1999] -- no action required 6.5. Project 1.25.13.01.07 - FDDI - Part 5: Hybrid Ring Control (HRC) [ISO/IEC 9314- 5:1995] no action required 6.6. Project 1.25.13.01.08 - FDDI - Part 6: Station Management (SMT) [ISO/IEC 9314- 6:1998] no action required 6.7.
    [Show full text]
  • VXS, a High Speed Cu Switch Fabric Interconnect for VME
    VXS, A High Speed Cu Switch Fabric Interconnect for VME Henry Wong Motorola [email protected] James Lee Fedder Tyco Electronics [email protected] James L Thompson Crane Division, Naval Surface [email protected] VME Renaissance • VME is a +20 year old technology. • VME Renaissance is an intense period of intellectual activity and technology infusion surrounding VMEbus • Many innovations, including but not limited to – Faster 2eSST parallel bus – Multi-gigabit switched serial interconnects – PCI-X chip to chip interconnect – PCI-X mezzanines – Point to point intra-connects – Point-to-point mezzanines 2 VMEbus Technology Roadmap Serial Data Parallel Serial NextNext Gen Gen Parallel Switched Fabric Plane SwitchedSwitched Switched Fabric Inter- • Ethernet, Fibre Ch • Raceway™ • Infiniband™ • HA fabric Connect • SKYchannel • Serial RapidIO™ • Mesh • 3GIO, etc. etc. etc. • Optical VME64 2eSST/PCI-X 2eSST/P2P Control VME64 2eSST/PCI-X 2eSST/P2P NextNext Gen Gen Plane VMEbusVMEbus VMEbusVMEbus VMEbusVMEbus VMEbusVMEbus Inter- • Universe II from Tundra • 8X speed improvement • 2eSST VME side Connect • Other proprietary chips • Backwards compatible • P-P Host side connect • QDR Technology • VXS – VMEbus Switched• VITA 1.5 Serial • Adds multi-gigabit per second Point-to-Point PMC PMCX Point-to-Point NextNext Gen Gen Mezzanine PMC PMCX Mezzanine switched serial links to VME Mezzanine MezzanineMezzanine Inter- Connect • Via• PCI a Mezzanine new CardsP0 connector• PCI-X Mezzanine Cards • P/S RapidIO™ • PMC & PrPMC • PMCX & PrPMCX • 3GIO • Hot plug • Dual• 64b/66MHz star based configuration• 64b/133MHz uses based one • Hypertransport • Front Access • VITA 39 • Infiniband™, etc. etc. or two switch cards Chip • MultiplePCI link technologies PointPoint-to-to-Point-Point to PCI PCIPCI-X-X Chip Connect Chip supported by structured Chip Connect Inter- • 64b/66MHz • 64b/133MHz • P/S RapidIO™ specification• Proprietary connects also • 3GIO Connect • Hypertransport • Additional power brought onto • etc.
    [Show full text]
  • Serial Multiprotocol Transmission with the Latticesc FPGA
    SERIAL MULTI-PROTOCOL TRANSMISSION WITH THE LatticeSC FPGA A Lattice Semiconductor White Paper February 2006 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com 1 Serial Multi-Protocol Transmission with the LatticeSC FPGA A Lattice Semiconductor White Paper Introduction The movement towards serial chip to chip and backplane interconnects continues at a frantic pace, particularly in the communications and storage arena. Standardization forums such as the OIF, RapidIO TA, PCI-SIG, OBSAI and CPRI have solidified their work and various packet-based protocols are in the process of being adopted by system and chip vendors. In addition to these emerging protocols, there is also a broad installed base of more mature serial-based protocols such as GbE, 10G Ethernet, SONET and Fibre Channel that must be addressed as they undergo a facelift to accommodate the multi-protocol nature of the network. As the PHY and protocol layers of these new standards are being established and work continues to upgrade existing technology in the field, system vendors now have to decide how best to transmit these various protocols over existing transmission infrastructures, both inter- and intra-board. Although each protocol is unique, one thing that they all have in common is a layered protocol stack. However, all protocol stacks are not created equal: their implementation can vary greatly from one layer to the next. Typically, the physical layer consists of fixed functionality that is common to multiple packet-based protocols, while the upper layers tend to be more customizable. The dynamic of upper layer functionality is necessitated by both the natural evolution that takes place when dealing with an emerging standard as well as the desire of system vendors to create their own “value add” via proprietary functionality.
    [Show full text]
  • Portovi Personalnih Računara 50
    Elektronski fakultet u Nišu Katedra za elektroniku Portovi i magistrale Student: Mentor: Vladimir Stefanović 11422 prof. dr Mile Stočev Milan Jovanović10236 Sadržaj Uvod 3 1.Magistrale 4 2.Portovi dati alfabetnim redom 36 3.Portovi personalnih računara 50 4.Poređenja i opisi PC interfejsa i portova 59 5.Hardver – mehaničke komponente 126 2 Uvod Sam rad se sastoji iz 5 dela u kojima su detaljno opisani PC portovi, magistrale, kao i razlike i sličnosti koje među njima postoje. U prvom poglavlju data je opšta podela magistrala, ukratko je opisan njihov način funkcionisanja, dati su odgovarajući standardi, generacije, a ukratko su opisane i suerbrze magistrale. U drugom poglavlju dat je alfabetni spisak portova, od kojih je većina obuhvaćena ovim radom. Treće poglavlje odnosi se na portove personalnih računara, kako Pentium tako i Apple i Mackintosh. Četvrti deo odnosi se na opisane portove i interfejse i njihovo međusobno poređenje. U ovom poglavlju date su i detaljne tabele u kojima su navedene i opisane neke od najvažnijih funkcija. I konačno, peto poglavlje se odnosi na hardver – USB portove, memorijske kartice SCSI portove. U Nišu, 03.10.2008. godine 3 1. Magistrale Prilagodljivost personalnog računara - njegova sposobnost da se proširi pomoću više vrsta interfejsa dozvoljavajući priključivanje mnogo različitih klasa dodatnih sastavnih delova i periferijskih uredjaja - bila je jedan od ključnnih razloga njegovog uspeha. U suštini, moderni PC računarski sistem malo se razlikuje od originalne IBM konstrukcije - to je skup komponenata, kako unutrašnjih tako i spoljašnjih, medjusobno povezanih pomoću elektronskih magistrala, preko kojih podaci putuju, dok se obavlja ciklus obrade koji ih pretvara od podataka ulaza u podatke izlaza.
    [Show full text]
  • Modular Electronics the Past, the Present and the Future Markus Joos CERN
    Modular Electronics the past, the present and the future Markus Joos CERN • The past: • NIM • The present: • PCI and PCIe • SHB Express • The future: • Serial interconnects • VXS • ATCA • µTCA NIM basics • Initially: NIM = Nuclear Instrument Modules • But it was used outside of "nuclear science" • Therefore: NIM = National Instrument Modules • But is was used outside of the USA • Therefore: NIM stands for NIM • 1st NIM standard: July 1964 • 1st commercial module: November 1964 • Module dimensions: 34 x 221 x 246 mm • NIM logic levels: • 0 = 0A (0V) • 1 = -12 to -32 (typical -16) mA at 50 Ω (-0.8V) • NIM connector • 42 pins in total • 11 pins used for power • 2 logic pins (reset & gate) • pin 1 & 2 = +/- 3V (claimed by Wikipedia) • 29 reserved / spare pins • 1983 NIM digital bus (IEEE 488 – GPIB) • Rarely used NIM – the next generation • NIM is still very alive – General purpose NIM module with programmable logic (LabView, USB) – 16 Channel 12 bit 5 GS/s Flash ADC Waveform Digitizer with USB 2.0 read- out PCI basics • PCI (Peripheral Component Interconnect): first standardized in 1991 • Initially intended for PC cards – Later spin-offs : CompactPCI, PXI, PMC • Main features – Synchronous timing • But wait cycles possible – Clock rates • Initially 33 MHz. Later: 66 MHz, (PCI-X: 100 and 133 MHz) – Bus width • Initially 32 bit. Later: 64 bit – Signaling voltage • Initially 5 V. Later 3.3 V (->slot keying) – Terminology • A data transfer takes place between an INITIATOR (master) and a TARGET (slave) – Bus topology • 1 to 8 (depending on clock
    [Show full text]
  • Vita 41.X Vxs Switch Fabric Backplanes
    VITA 41.X VXS SWITCH FABRIC BACKPLANES BENEFITS DATASHEET • Adds high-speed serial fabric while maintaining VME P1 and P2 compatibility • Supports high-speed serial interfaces such as: Infiniband, Serial RapidIO, Gigabit Ethernet, PCI Express. Atrenne Integrated Solutions supports a family of • Able to support system 6-21 slot VXS backplanes for rugged applications. management IPMB per The VXS standard is fully compatible with VME, VITA 38 but adds a high-speed serial fabric interface which is able to run Infiniband, Serial RapidIO, Gigabit Ethernet, PCI Express and more. This backplane series is part of the industry leading Atrenne Integrated Solutions’ product line of high performance chassis and backplanes. FEATURES • Compliant to the latest VXS switch fabric VITA standards • Stiffeners placed every two slots ensure board rigidity • 20-layer low noise stripline design with outside layers incorporating a chassis ground EMI shield • Standard versions 6, 8 12, 21 slots · 6-slot and 8-slot versions feature one VITA 41.x switch slot and up to seven VITA 41.x payload slots, each payload slot connects both links to the one switch slot · 12-slot and 21-slot versions features two VITA 41.x switch slots and up to 18 VITA 41.x payload slots with 4x links to two switch slots • High-performance, low noise • Electronic Bus Grant (EBG) • Compliant to the latest VITA standards: · VITA 41.0 VXS VMEbus Switched Serial standard · VITA 41.10-200 x Live Insertion System Requirements for VITA 41 Boards Trial use standard • ANSI/VITA 1.7-2003 increased current
    [Show full text]
  • Rapidio™ Interconnect Specification
    RapidIO™ Interconnect Specification Rev. 1.2, 6/2002 © Copyright 2002 RapidIO Trade Association RapidIO Trade Association Revision History Revision Description Date 1.1 First public release 03/08/2001 1.2 Technical changes: incorporate Rev. 1.1 errata rev. 1.1.1, errata 3, showing 02-02-00009 06/26/2002 NO WARRANTY.THE RAPIDIO TRADE ASSOCIATION PUBLISHES THE SPECIFICATION “AS IS”. THE RAPIDIO TRADE ASSOCIATION MAKES NO WARRANTY, REPRESENTATION OR COVENANT, EXPRESS OR IMPLIED, OF ANY KIND CONCERNING THE SPECIFICATION, INCLUDING, WITHOUT LIMITATION, NO WARRANTY OF NON INFRINGEMENT, NO WARRANTY OF MERCHANTABILITY AND NO WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. USER AGREES TO ASSUME ALL OF THE RISKS ASSOCIATED WITH ANY USE WHATSOEVER OF THE SPECIFICATION. WITHOUT LIMITING THE GENERALITY OF THE FOREGOING, USER IS RESPONSIBLE FOR SECURING ANY INTELLECTUAL PROPERTY LICENSES OR RIGHTS WHICH MAY BE NECESSARY TO IMPLEMENT OR BUILD PRODUCTS COMPLYING WITH OR MAKING ANY OTHER SUCH USE OF THE SPECIFICATION. DISCLAIMER OF LIABILITY. THE RAPIDIO TRADE ASSOCIATION SHALL NOT BE LIABLE OR RESPONSIBLE FOR ACTUAL, INDIRECT, SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, WITHOUT LIMITATION, LOST PROFITS) RESULTING FROM USE OR INABILITY TO USE THE SPECIFICATION, ARISING FROM ANY CAUSE OF ACTION WHATSOEVER, INCLUDING, WHETHER IN CONTRACT, WARRANTY, STRICT LIABILITY, OR NEGLIGENCE, EVEN IF THE RAPIDIO TRADE ASSOCIATION HAS BEEN NOTIFIED OF THE POSSIBILITY OF SUCH DAMAGES. Questions regarding the RapidIO Trade Association, specifications, or membership should be forwarded to: RapidIO Trade Association Suite 325, 3925 W. Braker Lane Austin, TX 78759 512-305-0070 Tel. 512-305-0009 FAX. RapidIO and the RapidIO logo are trademarks and service marks of the RapidIO Trade Association.
    [Show full text]