TMS320C6472/TMS320TCI648x DSP Serial RapidIO (SRIO) User's Guide Literature Number: SPRUE13J October 2006–Revised February 2011 2 SPRUE13J–October 2006–Revised February 2011 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated Preface ...................................................................................................................................... 15 1 Overview .......................................................................................................................... 16 1.1 General RapidIO System ............................................................................................. 16 1.2 RapidIO Feature Support in SRIO ................................................................................... 19 1.3 Standards ............................................................................................................... 20 1.4 External Devices Requirements ..................................................................................... 20 1.5 TI Devices Supported By This Document .......................................................................... 20 2 SRIO Functional Description ............................................................................................... 21 2.1 Overview ................................................................................................................ 21 2.2 SRIO Pins ............................................................................................................... 26 2.3 Functional Operation .................................................................................................. 26 3 Logical/Transport Error Handling and Logging ..................................................................... 90 4 Interrupt Conditions ........................................................................................................... 92 4.1 CPU Interrupts ......................................................................................................... 92 4.2 General Description ................................................................................................... 92 4.3 Interrupt Condition Status and Clear Registers .................................................................... 93 4.4 Interrupt Condition Routing Registers ............................................................................. 101 4.5 Interrupt Status Decode Registers ................................................................................. 105 4.6 Interrupt Generation .................................................................................................. 107 4.7 Interrupt Pacing ....................................................................................................... 108 4.8 Interrupt Handling .................................................................................................... 108 5 SRIO Registers ................................................................................................................ 110 5.1 Peripheral Identification Register (PID) ............................................................................ 120 5.2 Peripheral Control Register (PCR) ................................................................................. 120 5.3 Peripheral Settings Control Register (PER_SET_CNTL) ....................................................... 122 5.4 Peripheral Settings Control Register 1 (PER_SET_CNTL1) (TMS320TCI6484 only) ...................... 125 5.5 Peripheral Global Enable Register (GBL_EN) .................................................................... 126 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) ................................................... 127 5.7 Block n Enable Register (BLKn_EN) .............................................................................. 129 5.8 Block n Enable Status Register (BLKn_EN_STAT) .............................................................. 130 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) .............................................................. 131 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) .............................................................. 132 5.11 RapidIO DEVICEID3 Register (DEVICEID_REG3) .............................................................. 133 5.12 RapidIO DEVICEID4 Register (DEVICEID_REG4) .............................................................. 134 5.13 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) ...................................... 135 5.14 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) ......................................... 136 5.15 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) ......................... 137 5.16 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) ........................ 140 5.17 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL) .......................................... 142 5.18 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) ..................................... 144 5.19 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR) ...................................... 145 5.20 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ........................................................... 146 SPRUE13J–October 2006–Revised February 2011 Table of Contents 3 Submit Documentation Feedback © 2006–2011, Texas Instruments Incorporated www.ti.com 5.21 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) ............................................................ 147 5.22 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) ........................................................... 148 5.23 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ............................................................ 149 5.24 LSU Interrupt Condition Status Register (LSU_ICSR) .......................................................... 150 5.25 LSU Interrupt Condition Clear Register (LSU_ICCR) ........................................................... 153 5.26 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) .......... 154 5.27 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR) ........... 155 5.28 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and DOORBELLn_ICRR2) ........................................................................................................................... 156 5.29 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) ................ 157 5.30 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) ................. 158 5.31 LSU Interrupt Condition Routing Registers (LSU_ICRR0-LSU_ICRR3) ...................................... 159 5.32 Error, Reset, and Special Event Interrupt Condition Routing Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) .................................................... 161 5.33 Interrupt Status Decode Register (INTDSTn_DECODE) ........................................................ 162 5.34 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) .......................................... 166 5.35 LSUn Control Register 0 (LSUn_REG0) .......................................................................... 167 5.36 LSUn Control Register 1 (LSUn_REG1) .......................................................................... 168 5.37 LSUn Control Register 2 (LSUn_REG2) .......................................................................... 169 5.38 LSUn Control Register 3 (LSUn_REG3) .......................................................................... 170 5.39 LSUn Control Register 4 (LSUn_REG4) .......................................................................... 171 5.40 LSUn Control Register 5 (LSUn_REG5) .......................................................................... 172 5.41 LSUn Control Register 6 (LSUn_REG6) .......................................................................... 173 5.42 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) ..................................... 174 5.43 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) ..................... 176 5.44 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) ............................. 177 5.45 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) ..................... 178 5.46 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) ............................. 179 5.47 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) ........................................... 180 5.48 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0-7]) .......................... 181 5.49 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) ........................................... 184 5.50 Receive CPPI Control Register (RX_CPPI_CNTL) .............................................................. 185 5.51 Transmit CPPI Weighted Round-Robin Control Registers (TX_QUEUE_CNTL[0-3]) ....................... 186 5.52 Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn) ................................. 190 5.53 Flow Control Table Entry Register n (FLOW_CNTLn) .......................................................... 194 5.54 Device Identity CAR (DEV_ID) ..................................................................................... 195 5.55 Device Information CAR (DEV_INFO) ............................................................................