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Fourth-Edition Index 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. INDEX Note: Page numbers for defining references are given in color. &*%$#@! - (ABEL subtraction) 253 := (ABEL clocked assignment) - (Verilog subtraction) 301 612 (ceiling function) 53 ∆ - (VHDL subtraction) 488 := (VHDL variable assignment) ICC 145 * (ABEL multiplication) 497 280 ∨ (vee) 187 * (optional sections) xvi :> (ABEL clocked truth-table ∧ (wedge) 186 * (Verilog multiplication) 301 operator) 613 !$ (ABEL XNOR) 245 * (VHDL multiplication) 502 < (ABEL less than) 253 ! (ABEL NOT) 245, 246, 397 ∗ suffix 544, 546 < (Verilog less than) 304 ! (Verilog logical NOT) 304 + (ABEL addition) 253, 719 < (VHDL less than) 276 != (ABEL inequality) 253 + (Verilog addition) 301 << (Verilog shift left) 301 != (Verilog logical inequality) 304 + (VHDL addition) 488 <= (ABEL less than or equal) 253 ! vs. ~, Verilog 304 ⊕, Exclusive OR symbol 234, 447 <= (Verilog less than or equal) 304 # (ABEL OR) 245 .AP suffix, ABEL 612 <= (Verilog nonblocking # (Verilog delay specifier) 330 .AR suffix, ABEL 612 assignment) 315 # (Verilog parameter substitution) <= (VHDL less than or equal) 276 309 .C. symbol, ABEL 622 <= vs. =, Verilog 316 $ (ABEL XOR) 245 .CLK suffix, ABEL 612 = (ABEL unclocked assignment) $ (Verilog built-in functions and .FB suffix, ABEL 616, 617 246, 248 tasks) 293, 329 .OE suffix, ABEL 424, 612 = (Verilog blocking assignment) % (Verilog modulus) 301 .PIN suffix, ABEL 617 315 && (Verilog logical AND) 304 .Q suffix, ABEL 617 = (VHDL equality) 276, 466 & (ABEL AND) 245 .SP suffix, ABEL 612 == (ABEL equality) 253 & (Verilog AND) 296 .SR suffix, ABEL 612 == (Verilog logical equality) 304 & (VHDL concatenation operator) .X. symbol, ABEL 245 265, 751 / (Verilog division) 301 = vs. <=, Verilog 316 -> (ABEL test-vector operator) 253 /= (VHDL inequality) 276, 466 > (ABEL greater than) 253 -> (ABEL unclocked truth-table / prefix, ABEL 244 > (Verilog greater than) 304 operator) 250 :, in bus name 359 > (VHDL greater than) 276 863 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 864 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. >= (ABEL greater than or equal) 128V64 840 74ALS (Advanced Low-power 253 16V8C 694, 703 Schottky TTL) 166 >= (Verilog greater than or equal) 16V8R 703, 740 74ALS74 775 304 16V8S 703, 703 74ALVC164245 155 >= (VHDL greater than or equal) 1-bit parity code 60 74AS (Advanced Schottky TTL) 276 1-out-of-10 code 51 166 >> (Verilog shift right) 301 1-out-of-m code 384 74F (Fast TTL) 166 ?: (Verilog conditional operator) 1-out-of-n code 55, 562 74F373 774 305, 311, 431, 445, 492 1s catching 539, 540 74F374 774 ? bit value, Verilog 323 1s-counting machine 566 74F74 686, 774 @ALTERNATE directive, ABEL 245 1-set 230 74FCT (Fast CMOS, TTL @CARRY directive, ABEL 488 compatible) 128, 135, 149 20V8 706, 719 [] (Verilog part-select operator) timing 367 22V10 706 752 74FCT-T (Fast CMOS, TTL 2421 code 50 ^ (Verilog XOR) 296 compatible with TTL V ) 28C010 811 OH ^~ (Verilog XNOR) 296 149 28C040 811 ^b binary prefix, ABEL 253 74HC (High-speed CMOS) 142 28C256 811 ^h hexadecimal prefix, ABEL 253 74HCT (High-speed CMOS, TTL 28C64 811 828 _L suffix 348, 387, 390 , compatible) 142 2n-to-n encoder 408 {} (ABEL equation-block timing 366, 367 delimiters) 250 2-to-4 decoder 384, 389, 390 74HCT00 360 {} (Verilog concatenation operator) 3-to-8 decoder 386, 387, 390 74HCT04 360 300, 752 4000-series CMOS 141 74LS (Low-power Schottky TTL) | (Verilog OR) 296 4B5B code 779 166, 689 || (Verilog logical OR) 304 4-to-16 decoder 390 timing 366, 367 ~ (Verilog NOT) 296 4-to-2 encoder 412 74LS00 166, 360 ~^ (Verilog XNOR) 296 54 prefix 99, 141 74LS138 368 ~ vs. !, Verilog 304 54-series parts 143, 167 74LS139 368 ’ prefix, as in ’139 387 5-to-32 decoder 390 74LS74 534, 540, 611, 773, 774, 5-variable Karnaugh map 235, 564 775 74LS74 circuit 535, 611 0 5-V-tolerant inputs 153, 154 5-V-tolerant outputs 154 74LS86 368 0 3 6-variable Karnaugh map 236 74 prefix 99, 141 0 and 1 3, 7, 8, 25, 80, 86, 185, 7497 793 74S (Schottky TTL) 166, 493 348, 804 74AC (Advanced CMOS) 128, 148 74S174 774 0s catching 539, 540 74ACT (Advanced CMOS, TTL 74S373 774 0-set 230 compatible) 128, 135, 148 74S374 774 0x prefix 29 74ACT74 686 74S74 774 1 3 74AHC (Advanced High-speed 74-series parts 141, 143, 342 10’s complement 35 CMOS) 143 74VHC (Very High-speed CMOS) 10’s-complement representation 50 74AHCT (Advanced High-speed 143 1076, IEEE VHDL standard 270 CMOS, TTL compatible) 74VHC1G08 14 1164, IEEE standard logic package 143 74VHCT (Very High-speed CMOS, 261, 265, 266, 270 timing 366, 367 TTL compatible) 143 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 865 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. 74x00 143, 166, 361 74x194 730–730, 738, 740, 765 74x86 361, 448, 458, 738 timing 366 74x20 361 timing 366 74x02 361 timing 366 74x999 477 timing 366 74x21 361 74x prefix 144, 387 74x03 361 timing 366 82S100 373 74x04 361, 4 74x240 422 8421 code 50 timing 366 74x241 765 8B10B code 56, 71, 74 74x08 361 74x245 423 8-input priority encoder 411 timing 366 74x251 436, 436 8-to-3 encoder 408 74x10 361, 2 74x257 436 9s’ complement 38 timing 366 74x266 361 74x109 540, 686 74x27 361, 4 A 74x11 361 timing 366 a, asynchronous event frequency timing 366 74x273 773 74x138 143, 149, 367, 386, 387, timing 685 ABEL (Advanced Boolean 387–395, 399, 403, 418, 424, 74x280 449, 450, 451, 454, 455, Equation Language) 9, 15, 452, 717 456 238, 243–255 74x139 389, 440, 813 timing 367 !$ (XNOR) 245 timing 367 74x283 460, 461, 479–482 ! (NOT) 245, 246, 397 74x14 361 timing 367 != (inequality) 253 timing 366 74x30 361 # (OR) 245 74x148 411–413 timing 366 $ (XOR) 245 74x151 433–438 74x32 361 & (AND) 245 timing 367 timing 366 -> (test-vector operator) 253 74x153 436 74x32244 422 -> (unclocked truth-table timing 367 74x373 527, 693 operator) 250 74x157 434–436, 440 timing 685 - (subtraction) 253 timing 367 74x374 527, 692, 717, 765 * (multiplication) 497 74x160 716 timing 685 + (addition) 253, 719 74x161 716 74x375 686 .AP suffix 612 74x162 716, 725 74x377 693, 717, 765, 767, 4 .AR suffix 612 74x163 713–719, 725, 765, 2, 4 timing 685 .C., clock edge 622 74x164 4 74x381 484, 492–493 .CLK suffix 612 74x16540 422 timing 367 .FB suffix 616, 617 74x166 2 74x382 484 .OE suffix 424, 612 74x169 716, 725 74x540 422, 431 .PIN suffix 617 74x174 692 74x541 421, 450 .Q suffix 617 timing 684 74x682 463, 463, 466, 470 .SP suffix 612 74x175 691 timing 367 .SR suffix 612 timing 685 74x74 686 .X. symbol 245 74x181 482–484 timing 684 / prefix 244 74x182 367, 485–487 74x83 479 := (clocked assignment) 612 timing 367 74x85 460, 461–463, 470–473 < (less than) 253 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 866 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. ABEL (continued) ABEL (continued) ABEL (continued) <= (less than or equal) 253 input-list 250, 253 unclocked assignment operator, == (equality) 253 intermediate equation 247 = 246, 248 = operator 248 invert keyword 248 unclocked truth-table operator, = unclocked assignment 246 istype keyword 244, 612 -> 250 > (greater than) 253 language processor 244 when statement 248 >= (greater than or equal) 253 latches 694–697 with statement 620 @ALTERNATE directive 245 module statement 244 abnormal state 584, 732, 733 @CARRY directive 488 neg keyword 248 absolute maximum ratings 153 ^b binary prefix 253 next-state-variables 618 absolute maximum ratings, TTL ^h hexadecimal prefix 253 NOT prefix 244 169 {} (equation-block delimiters) operator precedence 245 AC (Advanced CMOS) 128, 148 250 other declarations 245 access time from address 815, 825 addition 719 output-list 250, 253 access time from chip select 815, attribute suffix 424, 612, 616 pin declarations 244 826 buffer keyword 248 pin definitions 397 AC fanout 111 case sensitivity 244 pos keyword 248 AC load 116, 763 case statement 614 precedence 245 ACT (Advanced CMOS, TTL clocked assignment operator, := property list, istype 244 compatible) 128, 135, 148 612 range 251 Actel Corporation 859 clocked truth-table operator, :> Active-HDL xx, 337 613 registers 694–697 active high 348 com keyword 244 reg keyword 612 active-high clock 522 comments 244 relation 253 active-high pin 349 compiler 244, 554 relational expression 253 active level 348 351 352 353 constant expression
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