 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

INDEX

Note: Page numbers for defining references are given in color.

&*%$#@! - (ABEL subtraction) 253 := (ABEL clocked assignment) (Verilog subtraction) 301 612   (ceiling function) 53 - (VHDL subtraction) 488 := (VHDL variable assignment) ∆I 145 - CC (ABEL multiplication) 497 280 ∨ (vee) 187 * * (optional sections) xvi :> (ABEL clocked truth-table ∧ (wedge) 186 * (Verilog multiplication) 301 operator) 613 !$ (ABEL XNOR) 245 * (VHDL multiplication) 502 < (ABEL less than) 253 ! (ABEL NOT) 245, 246, 397 ∗ suffix 544, 546 < (Verilog less than) 304 ! (Verilog logical NOT) 304 + (ABEL addition) 253, 719 < (VHDL less than) 276 != (ABEL inequality) 253 + (Verilog addition) 301 << (Verilog shift left) 301 != (Verilog logical inequality) 304 + (VHDL addition) 488 <= (ABEL less than or equal) 253 ! vs. ~, Verilog 304 ⊕, Exclusive OR symbol 234, 447 <= (Verilog less than or equal) 304 # (ABEL OR) 245 .AP suffix, ABEL 612 <= (Verilog nonblocking # (Verilog delay specifier) 330 .AR suffix, ABEL 612 assignment) 315 # (Verilog parameter substitution) <= (VHDL less than or equal) 276 309 .C. symbol, ABEL 622 <= vs. =, Verilog 316 $ (ABEL XOR) 245 .CLK suffix, ABEL 612 = (ABEL unclocked assignment) $ (Verilog built-in functions and .FB suffix, ABEL 616, 617 246 248 tasks) 293, 329 .OE suffix, ABEL 424, 612 , = (Verilog blocking assignment) % (Verilog modulus) 301 .PIN suffix, ABEL 617 315 && (Verilog logical AND) 304 .Q suffix, ABEL 617 = (VHDL equality) 276, 466 & (ABEL AND) 245 .SP suffix, ABEL 612 == (ABEL equality) 253 & (Verilog AND) 296 .SR suffix, ABEL 612 == (Verilog logical equality) 304 & (VHDL concatenation operator) .X. symbol, ABEL 245 265, 751 / (Verilog division) 301 = vs. <=, Verilog 316 -> (ABEL test-vector operator) 253 /= (VHDL inequality) 276, 466 > (ABEL greater than) 253 -> (ABEL unclocked truth-table / prefix, ABEL 244 > (Verilog greater than) 304 operator) 250 :, in bus name 359 > (VHDL greater than) 276

863  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 864 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. >= (ABEL greater than or equal) 128V64 840 74ALS (Advanced Low-power 253 16V8C 694, 703 Schottky TTL) 166 >= (Verilog greater than or equal) 16V8R 703, 740 74ALS74 775 304 16V8S 703, 703 74ALVC164245 155 >= (VHDL greater than or equal) 1-bit parity code 60 74AS (Advanced Schottky TTL) 276 1-out-of-10 code 51 166 >> (Verilog shift right) 301 1-out-of-m code 384 74F (Fast TTL) 166 ?: (Verilog conditional operator) 1-out-of-n code 55, 562 74F373 774 305, 311, 431, 445, 492 1s catching 539, 540 74F374 774 ? bit value, Verilog 323 1s-counting machine 566 74F74 686, 774 @ALTERNATE directive, ABEL 245 1-set 230 74FCT (Fast CMOS, TTL @CARRY directive, ABEL 488 compatible) 128, 135, 149 20V8 706, 719 [] (Verilog part-select operator) timing 367 22V10 706 752 74FCT-T (Fast CMOS, TTL 2421 code 50 ^ (Verilog XOR) 296 compatible with TTL V ) 28C010 811 OH ^~ (Verilog XNOR) 296 149 ^b binary prefix, ABEL 253 28C040 811 74HC (High-speed CMOS) 142 28C256 811 ^h hexadecimal prefix, ABEL 253 74HCT (High-speed CMOS, TTL 28C64 811 828 _L suffix 348, 387, 390 , compatible) 142 2n-to-n encoder 408 {} (ABEL equation-block timing 366, 367 delimiters) 250 2-to-4 decoder 384, 389, 390 74HCT00 360 {} (Verilog concatenation operator) 3-to-8 decoder 386, 387, 390 74HCT04 360 300, 752 4000-series CMOS 141 74LS (Low-power Schottky TTL) | (Verilog OR) 296 4B5B code 779 166, 689 || (Verilog logical OR) 304 4-to-16 decoder 390 timing 366, 367 ~ (Verilog NOT) 296 4-to-2 encoder 412 74LS00 166, 360 ~^ (Verilog XNOR) 296 54 prefix 99, 141 74LS138 368 ~ vs. !, Verilog 304 54-series parts 143, 167 74LS139 368 ’ prefix, as in ’139 387 5-to-32 decoder 390 74LS74 534, 540, 611, 773, 774, 5-variable Karnaugh map 235, 564 775 74LS74 circuit 535, 611 0 5-V-tolerant inputs 153, 154 5-V-tolerant outputs 154 74LS86 368 0 3 6-variable Karnaugh map 236 74 prefix 99, 141 0 and 1 3, 7, 8, 25, 80, 86, 185, 7497 793 74S (Schottky TTL) 166, 493 348, 804 74AC (Advanced CMOS) 128, 148 74S174 774 0s catching 539, 540 74ACT (Advanced CMOS, TTL 74S373 774 0-set 230 compatible) 128, 135, 148 74S374 774 0x prefix 29 74ACT74 686 74S74 774 1 3 74AHC (Advanced High-speed 74-series parts 141, 143, 342 10’s complement 35 CMOS) 143 74VHC (Very High-speed CMOS) 10’s-complement representation 50 74AHCT (Advanced High-speed 143 1076, IEEE VHDL standard 270 CMOS, TTL compatible) 74VHC1G08 14 1164, IEEE standard logic package 143 74VHCT (Very High-speed CMOS, 261, 265, 266, 270 timing 366, 367 TTL compatible) 143  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 865 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. 74x00 143, 166, 361 74x194 730–730, 738, 740, 765 74x86 361, 448, 458, 738 timing 366 74x20 361 timing 366 74x02 361 timing 366 74x999 477 timing 366 74x21 361 74x prefix 144, 387 74x03 361 timing 366 82S100 373 74x04 361, 4 74x240 422 8421 code 50 timing 366 74x241 765 8B10B code 56, 71, 74 74x08 361 74x245 423 8-input priority encoder 411 timing 366 74x251 436, 436 8-to-3 encoder 408 74x10 361, 2 74x257 436 9s’ complement 38 timing 366 74x266 361 74x109 540, 686 74x27 361, 4 A 74x11 361 timing 366 a, asynchronous event frequency timing 366 74x273 773 74x138 143, 149, 367, 386, 387, timing 685 ABEL (Advanced Boolean 387–395, 399, 403, 418, 424, 74x280 449, 450, 451, 454, 455, Equation Language) 9, 15, 452, 717 456 238, 243–255 74x139 389, 440, 813 timing 367 !$ (XNOR) 245 timing 367 74x283 460, 461, 479–482 ! (NOT) 245, 246, 397 74x14 361 timing 367 != (inequality) 253 timing 366 74x30 361 # (OR) 245 74x148 411–413 timing 366 $ (XOR) 245 74x151 433–438 74x32 361 & (AND) 245 timing 367 timing 366 -> (test-vector operator) 253 74x153 436 74x32244 422 -> (unclocked truth-table timing 367 74x373 527, 693 operator) 250 74x157 434–436, 440 timing 685 - (subtraction) 253 timing 367 74x374 527, 692, 717, 765 * (multiplication) 497 74x160 716 timing 685 + (addition) 253, 719 74x161 716 74x375 686 .AP suffix 612 74x162 716, 725 74x377 693, 717, 765, 767, 4 .AR suffix 612 74x163 713–719, 725, 765, 2, 4 timing 685 .C., clock edge 622 74x164 4 74x381 484, 492–493 .CLK suffix 612 74x16540 422 timing 367 .FB suffix 616, 617 74x166 2 74x382 484 .OE suffix 424, 612 74x169 716, 725 74x540 422, 431 .PIN suffix 617 74x174 692 74x541 421, 450 .Q suffix 617 timing 684 74x682 463, 463, 466, 470 .SP suffix 612 74x175 691 timing 367 .SR suffix 612 timing 685 74x74 686 .X. symbol 245 74x181 482–484 timing 684 / prefix 244 74x182 367, 485–487 74x83 479 := (clocked assignment) 612 timing 367 74x85 460, 461–463, 470–473 < (less than) 253  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 866 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. ABEL (continued) ABEL (continued) ABEL (continued) <= (less than or equal) 253 input-list 250, 253 unclocked assignment operator, == (equality) 253 intermediate equation 247 = 246, 248 = operator 248 invert keyword 248 unclocked truth-table operator, = unclocked assignment 246 istype keyword 244, 612 -> 250 > (greater than) 253 language processor 244 when statement 248 >= (greater than or equal) 253 latches 694–697 with statement 620 @ALTERNATE directive 245 module statement 244 abnormal state 584, 732, 733 @CARRY directive 488 neg keyword 248 absolute maximum ratings 153 ^b binary prefix 253 next-state-variables 618 absolute maximum ratings, TTL ^h hexadecimal prefix 253 NOT prefix 244 169 {} (equation-block delimiters) operator precedence 245 AC (Advanced CMOS) 128, 148 250 other declarations 245 access time from address 815, 825 addition 719 output-list 250, 253 access time from chip select 815, attribute suffix 424, 612, 616 pin declarations 244 826 buffer keyword 248 pin definitions 397 AC fanout 111 case sensitivity 244 pos keyword 248 AC load 116, 763 case statement 614 precedence 245 ACT (Advanced CMOS, TTL clocked assignment operator, := property list, istype 244 compatible) 128, 135, 148 612 range 251 Actel Corporation 859 clocked truth-table operator, :> Active-HDL xx, 337 613 registers 694–697 active high 348 com keyword 244 reg keyword 612 active-high clock 522 comments 244 relation 253 active-high pin 349 compiler 244, 554 relational expression 253 active level 348 351 352 353 constant expression 392 relational operators 253 , , , , 386, 390, 399–400, 404–405 counters 719–721 retain property 695 active-level naming convention current-state-variables 618 set 251, 614, 618 348 device declaration 244 shift registers 740–748 active-level suffix 355 don’t-care state_diagram 613 active low 348 input combination 251 state diagram 614–621 active-low clock 522 else clause 248, 614 state keyword 614 active-low pin 349 ENABLE keyword 246 state-machine coding style 629 active mode 815 end statement 245 state-value 614 equation block 250 state-vector 614 active pull-up 133 equations 245 string 244 active region 158 state variable on lefthand side test_vectors 245 actual parameters, VHDL 265 614 test_vectors keyword 253 adders 474–487 equations statement 245 test vectors 245, 253–255, 622 ABEL 487–488 goto statement 614 title 244 Verilog 490–493 identifier 244 truth_table keyword 250 VHDL 488–490 if statement 614 truth table 250, 613 adding out 189, 202, 203, 476  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 867 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. addition 32 analog vs. digital 3–6, 7–8, 79 array types, VHDL 263 ABEL 719 analysis, combinational-circuit 183 arrow, state-diagram 548 Verilog 301 AND gate 6, 82, 186, 194, 210 ASCII (American Standard Code address hold time 826 CMOS 93 for Information Interchange) address input 800 symbol 346 53 address setup time 826 and gate, Verilog 306 Ashenden, Peter J. 336 adjacency diagram 605 AND operation 187 ASIC adjacent states 606 AND-OR circuit 193, 202, 204, place-and route 242 advanced courses xvi 208, 209, 211, 215, 226, 229 ASIC (application-specific Advanced Micro Devices (AMD) AND-OR device 370 integrated circuit) 16–17, 508, 859 AND-OR-INVERT (AOI) gate, 237, 343, 543, 566, 590, 758, after keyword, VHDL 284 CMOS 94, 175 763 AHC (Advanced High-speed Angell, R. 508 ASIC design 370, 765 CMOS) 143, 153, 154 anode 156 ASIC routing 763 AHCT (Advanced High-speed ANSI (American National ASM (algorithmic state machine) CMOS, TTL compatible) Standards Institute) 347 664 143 ANSI-style port declarations, ASM chart 664 A-law PCM 816, 820 Verilog 298 assert 348 Aldec, Inc. xx application-specific integrated asserted 3 circuit (ASIC) 16 17 237 Alfke, Peter 788 – , , assert statement, VHDL 288 343, 543, 566, 590, 758, 763 algebraic operator 186 assign keyword, Verilog 293, design 22, 342, 526 algorithmic state machine (ASM) 310, 330 architecture, VHDL 257 664 assignment-statement sizing, chart 664 architecture-control fuses, Verilog 300 GAL16V8 378 all inclusion 553, 574 associative law 188 almost one-hot coding 633 architecture definition, VHDL 257, 259 asterisk (optional sections) xvi alpha particle 58 asymmetric output drive 143 Alred, G. J. 508 architecture keyword, VHDL 258 asynchronous clear input 725 Alternate Mark Inversion (AMI) 72 arguments, VHDL 265 asynchronous design 2 ALU 474 arithmetic and logic unit (ALU) asynchronous inputs, flip-flop 533 always block, Verilog 312 482, 759 asynchronous input signal 759, 767 always keyword, Verilog 312 arithmetic operators, Verilog 301 asynchronous reset, 22V10 706 amandarin 12 arithmetic shift 748 asynchronous signals 679, 758 ambiguous state diagram 571, 573, array, Verilog 302 576 asynchronous SRAM 829 array, VHDL 263 American National Standards Asynchronous Transfer Mode Institute (ANSI) 347 type matching 276 (ATM) 171 American Standard Code for array index, Verilog 302 ATM (Asynchronous Transfer Information Interchange array index, VHDL 263 Mode) 171 (ASCII) 53 array keyword, VHDL 263 Atmel Corporation 859 amplifier 158 array literal, VHDL 264 attribute statement, VHDL 633 analog 3 array slice, VHDL 265 attribute suffix, ABEL 424, 612, analog electronics 1 array type, unconstrained 265 616  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 868 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. automatic test-pattern-generation binary adder, serial 758 bitwise boolean operators, Verilog program 625, 644, 662 binary addition 32 295 auto-refresh cycle, SDRAM 839 binary-addition table 32 BJT (bipolar junction transistor) axiom 185 binary-coded decimal (BCD) 48 84, 158–160 binary counter 719 Blake, Gary 508 block, Verilog 317 B binary decoder 384, 440 block diagram 343, 344, 355, 357, baby from hell 5 binary digit 25, 26, 80 438, 11 back annotator 240 binary division 47–48 blocking assignment operator, back-end design process 242–243 binary encoder 408 Verilog = 315 Bakeman, Ken xxiii binary operator 189 blocking assignment statement, balanced code 71 binary point 27 Verilog 315, 331, 648 bank, DRAM 834 binary prefix, ABEL 253 blocking vs. non-blocking barrel shifter 516 binary radix 26 assignments, Verilog 648, base, number system 26 binary rate multiplier 793 755 base, transistor 158 binary subtraction 32 Bly, Robert W. 508 basis step 190 binary-subtraction table 32 board-level design 22 Baylis, John 74 binary-to-hexadecimal conversion Bolton, Martin 789 ^b binary prefix, ABEL 253 27 BOM (bill of materials) 343 BCD (binary-coded decimal) 48 binary-to-octal conversion 27 Boole, George 184, 229 BCD addition 50 binomial coefficient 49, 56, 561 boolean, VHDL 261 BCD code 384, 408 bipolar junction transistor (BJT) Boolean algebra 184, 229 BCD decoder 386 84, 158–160 See also switching algebra begin-end block, Verilog 317 bipolar logic family 85 boolean operators, Verilog 295 begin keyword, Verilog 317 bipolar PAL devices 703 boolean reduction operators, begin keyword, VHDL 258 bipolar PROM 810 Verilog 302 behavioral description, Verilog 312 Bipolar Return-to-Zero (BPRZ) 72 boolean type, VHDL 260 behavioral description, VHDL 278 bipolar ROM 808 boolean vs. logical, Verilog 304 behavioral design, Verilog biquinary code 50 bootstrap ROM module 805 borrow 32 43 476 312–329 bird 571 , , behavioral design, VHDL 278–284 boundary inputs, iterative-circuit Birkner, John 508 behavioral specification, Verilog 459, 756 bistable 523–526, 590 292 boundary outputs, iterative-circuit bit 26 80 bias 39 , 459, 756 BiCMOS logic 155 bit_vector type, VHDL 260 boxed comments xviii bidirectional bus 423 bit cell 69 BPRZ (Bipolar Return-to-Zero) 72 bidirectional data bus 828 bit line 804 bps 69 bidirectional pins, PLD 375, 424 bit rate 69 branching method 221 bidirectional shift register 730 bit select, Verilog 300 Brown, Charlie 526 big picture 23 bits per second 69 Brusaw, C. T. 508 billions and billions 48, 55, 341, bit time 69 bubble 83, 90 509, 520, 821, 861 bit type, VHDL 260 bubble-to-bubble logic design bill of materials (BOM) 343 bit vector, Verilog 295, 299–302 351–353, 389, 390, 438, 448  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 869 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. buffer 80, 350 call, VHDL procedure 269 casez keyword, Verilog 323 symbol 346 canonical product 198, 205, 210, casez statement, Verilog 323 buffer keyword, ABEL 248 222 CAS latency 837 buffer keyword, VHDL 259 canonical sum 198, 199, 205, 210, cathode 156 buf gate, Verilog 306 214 causality 362, 527 bufif0 gate, Verilog 306 Cantoni, Antonio 789 CCD (charge-coupled device) 822 bufif1 gate, Verilog 306 capacitance, stray 115 CD (compact disc) 4, 81 bugs 5 capacitive load 115, 116, 365, 370 CD-R (writeable compact disc) 81 capacitive loading 170 built-in gate types, Verilog 306 ceiling function 53 capacitors, decoupling 124 buried flip-flops 588 central office (CO) 4 capacitors, filtering 124 buried macrocell 841 central processing unit (CPU) 799 carburetor 4 burst length 839 Chandrakasan, A. 174, 508 car heater 521 burst mode 830 Chaney, Thomas J. 775, 789 carpet 113 burst-read cycle, SDRAM 838 character, VHDL 260, 261 carry 32, 43 burst-write cycle, SDRAM 839 characteristic equation 540, 544, carry generate 478, 492 bus 344–346, 358–359, 364 550, 551, 564, 578 carry lookahead 478 bidirectional 423 characteristic impedance 182 carry-lookahead adder 479 open-drain 137 charge-coupled device (CCD) 822 carry out 474 bus, open-drain 137–138 charge pump 812 carry propagate 478, 492 bus fighting 826 Charlie Brown 526 carry-save addition 496 bus holder circuit 690, 788 check bits 60 cascaded elements 680 business practices 3 checksum 68 cascaded synchronizers 777 bus transceiver 423, 424, 431 checksum code 68 cascading inputs, comparator 461 BUT (function) 233 chip 6 cascading inputs, iterative-circuit chip-select (CS) input 813 BUT flop 674 459, 756 chip-select setup time 826 BUT gate 233, 511 cascading outputs, iterative-circuit butification 512 459, 756 chip viewer 240 byte 28 case keyword, Verilog 321 chip vs. IC 12 case keyword, VHDL 282 Chua, H. T. 508 case sensitivity 354 Ciletti, Michael D. 336 C ABEL 244 CINmax 146 C 10 Verilog 293 circle 548 C++ 10 VHDL 258 circuit description 184, 343 CAD See computer-aided design case statement, ABEL 614 circuit specification 342 Cadence Design Systems 290 case statement, Verilog 310, 321, circular reasoning 559 CAE (computer-aided engineering) 404 circular shift 748 9 full 322 Cisco Systems iii, xxiii See also computer-aided design parallel 321 CL 123 call, Verilog function 327 case statement, VHDL 282 clamp diode 153, 160 call, Verilog task 328 casex keyword, Verilog 323 Clare, Christopher R. 664 call, VHDL function 265 casex statement, Verilog 323 Clark Kent 526  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 870 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. CLB (configurable logic block) CMOS (complementary MOS) combinational-circuit synthesis 850–854 (continued) 183, 205–222 clear input 527, 533, 680 transfer characteristic 130 combinational multiplier 494 clock 7, 522, 523 transmission gate 129–130 combinational vs. combinatorial distribution 172 unused inputs 112 376 frequency 522 TTL interfacing 103, 106, 142 combination lock 568 gated 765–767 CMOS/TTL interfacing 103, 106, combination-lock state machine 620, 623, 637, 656 in synchronous system 758 142 combining theorem 189, 211 jitter 684 CMOS vs. TTL 85 com keyword, ABEL 244 period 522 CO (central office) 4 comma in Verilog sensitivity list recovery 740 Coburn, James 73 314 code 48–56, 384 skew 683, 684, 759, 766 command input 760 coded state 560, 572, 605 tick 522, 542 comments coded states 606 clocked assignment operator, ABEL ABEL 244 := 612 code rate 78 Verilog 293 clocked synchronous state machine code word 48 VHDL 258 523, 542 coding 241 committee, designed by 629 clocked truth-table operator, ABEL coding style common-emitter configuration 159 :> 613 state-machine 682 common-mode signal 172 clock-enable input 534 Verilog 291, 298, 299, 303, communication 3, 344 clock skew 759, 762–765 304, 305, 314, 316, 317, CML (current-mode logic) 321, 322, 323, 325, 327, commutative law 188 170–173 333, 407, 648, 650, 652, compact disc (CD) 4, 81, 816 See also emitter-coupled logic 657 compact-disc player 799 (ECL) Verilog state-machine 649 companded encoding 816 CMOS (complementary MOS) VHDL 289–290, 628, 632 comparators 319, 326, 458–473, 85–151, 171, 421, 763 VHDL state-machine 628 759 4000-series 141 collector, transistor 158 ABEL 466 AND 93 colon, in bus name 359 HDL 463–466 AND-OR-INVERT (AOI) gate 94, color iterative 459 175 for ABEL keywords 244 parallel 459 gates 368 for expressions 186 serial 756 inverter 88–90 for Verilog keywords 293 Verilog 469–473 latch-up 113 for VHDL keywords 258 VHDL 466–468 load 147 column address, DRAM 836 comparing numbers 33 comparison, Verilog 304 logic 80, 81, 88 column-address register, SDRAM NAND gate 90 836 compatible states 599 NOR gate 91 combinational carry output 721 compilation 241 OR-AND-INVERT (OAI) gate 95, combinational circuit 6, 82, 183, compiler 175 521 ABEL 244 OR gate 93 speed 210 HDL 239 PLD circuits 380–382 combinational-circuit analysis 183, Verilog 305, 307, 322, 330 technology 18, 19 199–204 VHDL 257, 266, 269, 270, 294  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 871 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. complement 186 conditional operator ?:, Verilog counters 710–718, 759 of a logic expression 192 305, 311, 431, 445, 492 ABEL 719–721 complementary MOS See CMOS condition input 760 cascaded 680 complement number system 35 conductive wrist strap 113 synchronous 711 complete set 233 conference circuit 818 synchronous parallel 712 complete sum 218, 229, 236 configurable logic block (CLB) synchronous serial 712 850 854 complex programmable logic – Verilog 725–727 configuration management device (CPLD) 15, 23, 378, VHDL 721–725 543, 840, 841–849, 859 Verilog 293 cover 189 fitter 379 VHDL 258 covering theorem 189 fitting 242 configuration register, SDRAM covers 217 macrocell 379, 452 839 CPLD See complex programming technology 382 consensus 190, 226 programmable logic device Xilinx XC9500 841–849 consensus term 602, 611, 694 CPU (central processing unit) 799 component declaration, VHDL 272 consensus theorem 190, 223 CRC (cyclic-redundancy check) 65 component instantiation, Verilog constant, VHDL 261 critical race 597, 597 307 constant declaration, VHDL 263 CS-controlled write 826 component keyword, VHDL 272 constant expression 299 Cummings, Clifford E. 336, 648, component statement, VHDL 272 ABEL 392 664 computer-aided design (CAD) 9, constant logic value 112 189, 347, 350 CUPL (Compiler Universal for constant outputs, PLA 372 Programmable Logic) 238 program 577 constants, Verilog 299, 305 current software 577, 763, 764 constants, VHDL 263 tools 9–10, 576 direction, CMOS 106 constraints 242 direction, TTL 164 computer-aided engineering (CAE) fitter 379 9 flow, CMOS 106 contact bounce 687 See also computer-aided design flow, TTL 164 continuous-assignment statement, leakage 88, 133 Computer History Museum 809 Verilog 310, 313, 431 sinking 106 computer-science students xvii control unit 759 computing the radix complement sourcing 106 CONV_INTEGER function, VHDL 36 268 TTL sinking 162 concatenation operator , VHDL & converting VHDL types 267 TTL sourcing 162 265, 751 Conway, Lynn 663, 789 current-mode logic (CML) concatenation operator {}, Verilog 170–173 300, 752 cooling 171 core logic 151 See also emitter-coupled logic concurrent signal-assignment (ECL) statement, VHDL 276 cosmic rays 58, 79, 98 current spikes 124 concurrent statement, Verilog 306 cost 2, 6, 16, 17, 22, 23, 284, 443, current-state-variables, ABEL 618 concurrent statement, VHDL 271 584, 828 custom LSI 16 condition, Verilog 318 combinational-circuit 211, 216, 220 custom VLSI 381 conditional assignment, VHDL 278 cut off (OFF) 159 conditional concurrent signal- of PLD-based designs 710 assignment statement, VHDL state-machine 560, 563, 565 cut set 594 276 Costello, D. J. Jr. 74 CV2f power 123, 142  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 872 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. cyclic-redundancy-check (CRC) declarations, Verilog 291 design flow 241 code 65 decode 384 VHDL 241 Cypress Semiconductor 775, 789 decoders 384–408, 717, 801 design time 22 ABEL 390–397 device declaration, ABEL 244 D Verilog 403–408 device testing 535 data bit 364 VHDL 398–403 Devo 663, 789 dataflow description, Verilog decoding 61 D flip-flop 532–537 310–312 decoding glitches 717, 735, 736 CMOS 600 dataflow description, VHDL decomposed state assignment 561, with enable 534 275–278 562 dice 12 dataflow design, Verilog 310–312 decomposition, state-machine 587 die, IC 12 dataflow design, VHDL 275–278 decoupling capacitors 124 plural of 12 data hold time 826 directive, Verilog 305 `define dielectric 113 Data I/O Corporation 243 vs. parameter 305 difference, in subtraction 32 data output 800 defparam keyword, Verilog 309 differential amplifier 171 data setup time 826 delay 224, 242, 362–370, 528, 763 differential inputs 172 data sheet 98 maximum 363, 365 differential outputs 172 CMOS 98–100 minimum 365, 368 digital 3 TTL 166 three-state-buffer 419 digital abstraction 96, 185 data unit 759 TTL 165 digital attenuator 817, 817, 818 dating 208 typical 363, 365 digital camera 3 DC balance 71, 740 See also propagation delay digital conference circuit 818 DC fanout 111 delay, feedback-sequential-circuit DC load 103, 116, 149, 763 608 digital design 1, 5 DC noise margin 97, 103, 112, 169 delay line 822 levels of abstraction 18 HIGH-state 148 delay-locked loop (DLL) 840 digital devices 6–7 LOW-state 148 delay path 683 digital logic 80 TTL 164 delay statement, Verilog 331 digital phase-locked loop (DPLL) DC noise margin, TTL 165 delay value, Verilog 310 70, 778 DDPPonline xvi, xxi–xxii, 3 delta delay, Verilog 331 digital revolution 3, 5 dead time 419 delta delay, VHDL 286 digital versatile disc (DVD) 4 deassert 348 delta time 645, 662, 755 digital voice coding 820 debounce 688 DeMorgan’s theorem 190 digital vs. analog 3–6, 7–8, 79 debugging 3, 113 generalized 192, 194, 196, 202 diminished radix-complement decade counter 716 DeMorgan equivalent symbols 347 system 38 decade counting 725 demultiplexer 438 diode 84, 804 decimal codes 48–51 descrambler 740 clamp 153 decimal counter 725 design 590 forward-biased 156 decimal decoder 386 hierarchical 241 parasitic 130 decimal point 26 state-machine 553, 554, 559, reverse-biased 156 decimal-to-radix-r conversion 30 566, 577 Schottky 160 decision window 772 vs. synthesis 184 diode action 156 declarations, ABEL 244, 245 designed-by-committee project 629 diode AND gate 157, 160  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 873 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. diode-drop 156 DRAM (dynamic RAM) electrically erasable programmable diode logic 155 bank 834 read-only memory DIP (dual inline pin) 12 column address 836 (EEPROM) 811–812 diphase 73 See also dynamic RAM electronics concepts xvi DIP switch 687 drills vs. exercises xix electrostatic discharge (ESD) 98, 113 directed arc, state-diagram 548 drive strength, Verilog 310 else clause, ABEL 248, 614 disable keyword, Verilog 326 dual in-line-pin (DIP) package 687 else keyword, Verilog 318 disable statement, Verilog 326 dual inline-pin (DIP) package 12 else keyword, VHDL 258, 276, dual-inline-pin (DIP) package 362 Disanno, Scott xxiii 281 duality 185, 186, 193, 209 disk, magnetic 81 elsif, VHDL 281 dual of a logic expression 193 $display task, Verilog 329 emitter, transistor 158 dumb errors 262, 358 distance 58 emitter-coupled logic (ECL) 155, distinguished 1-cell 218 duty cycle 522, 716 170–173 distributive law 189 DVD (digital versatile disc) 4 100K family 170, 173 divide-by-m counter 710 dynamic circuit behavior 97, 114 10K family 170, 173 division 47–48, 284 dynamic hazard 227, 758 enable, Verilog task 328 overflow 48 dynamic-input indicator 316, 532, enable input 384, 388 680 Verilog 301 D flip-flop 534 dynamic memory 81 D latch 530, 686, 694, 822 multiplexer 436, 440 dynamic power dissipation 122, documentation 2, 3, 186, 243, 256, 145 three-state-buffer 421 342 362 386 387 528 – , – , , dynamic RAM (DRAM) 821, ENABLE keyword, ABEL 246 680–686 833–840 encoders 408–412 flip-flop 680 synchronous (SDRAM) ABEL 412–415 state machine 680 835–840 VHDL 416–417 dominance, flip-flop control inputs dynamic range 816 encoders, Verilog 417 647 end, VHDL 259 don’t-care E end-around carry 44 bit 58 endcase keyword, Verilog 321 ECL See emitter-coupled logic in excitation tables 608 endgenerate keyword, Verilog eclipse 220 input combination 222 310 edge-triggered behavior 532 ABEL 251 end keyword, Verilog 317 edge-triggered D flip-flop 523, in state coding 585 end keyword, VHDL 258 532–537, 697 minimization 222 endmodule keyword, Verilog 293, with enable 534 signal value 684 294 edge-triggered J-K flip-flop 539 end statement, ABEL 245 truth-table notation 385 EEPLD 381 energy 145 don’t-care states 583 EEPROM (electrically erasable double-data-rate (DDR) SDRAM programmable read-only engineering 2 839 memory) 811–812 engineering design margins 96 downto keyword, VHDL 263, 265 electrical characteristics, TTL 167 Eniac 84 DPLL (digital phase-locked loop) electrical loading 242 entity, VHDL 256 70 electrically erasable programmable entity declaration, VHDL 257 drain, CMOS transistor 87 logic device (EEPLD) 381 entity keyword, VHDL 258, 259  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 874 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. entrepreneur 344 event list, VHDL simulator FALSE 3 enum_encoding attribute, VHDL 285–286, 645 false, Verilog 303 m−1 633 excess-2 system 39 false keyword, VHDL 261 enumerated type, VHDL 261, 630 excess-3 code 50 fan 522 EPROM (erasable programmable excess-3 sequence 719, 725 fan-in 92 read-only memory) 810 excess-B representation 39 fanout 97, 111, 133, 148, 170, equation block, ABEL 250 excitation 546 388, 438, 763 equations, ABEL 245 excitation equation 546, 551, 578, AC 111 reverse-polarity 248 591 CMOS 111 state variable on lefthand side excitation logic, VHDL 628, 649 DC 111 614 excitation maps 564 HIGH-state 111, 148 equations statement, ABEL 245 excitation table 563 LOW-state 111, 148 Equivalence gate 447 459 , Exclusive-NOR (XNOR) gate 233, overall 111 equivalent load circuit 116 447 TTL 164–165 equivalent states 558 comparator 458, 459 fault detection 230 equivalent symbols 347 Exclusive-OR (XOR) gate 233, 447 FCT (Fast CMOS, TTL compatible) erasable programmable read-only comparator 458 128, 135, 149 memory (EPROM) 810 executing statement, Verilog 312 FCT-T (Fast CMOS, TTL erasing 810 exercises vs. drills xix compatible with TTL VOH) flash 811 exit statement, VHDL 283 149 erasing an EPROM 810–811 exponent 816 feedback input 708 Ercegovac, Miloš 73 expression feedback loop 183, 523, 524, 525, error 58 ABEL relational 253 526, 527, 529, 590, 595, 600 error-correcting code 61, 451, 740 product-of-sums 193, 197, 204, feedback sequential circuit 523, error-correcting decoder 64 209 526, 590–611, 613 error correction 61 sum-of-products 193, 197, 201, hazards 228 error-detecting codes 58–68, 449, 204, 207, 208, 209 fiber optics 81 740 switching algebra 186, 187 fiber-optic transceiver 171 error model 58 expression, ambiguous 188 Fibonacci sequence 673 errors in this book xxii expression, Verilog 303 fictional buffer 590, 591, 594, 595 ESD See electrostatic discharge extended Hamming code 65 field, finite 73, 737 Espresso-II 224 external feedback, PLD 708 field effect 88 Espresso-MV 224 extra negative number 37, 42 field-programmable gate array essential hazard 609, 697, 762 eyeball 223, 594 (FPGA) 11, 15, 15, 23, 96, essential prime implicant 219 199, 343, 379, 543, 566, 850–859 Ethernet 740, 778, 779 F gigabit 171 place-and route 242 f, synchronizer frequency 773 even-parity circuit 448 programming technology 382 failure 58 even-parity code 59, 449 Xilinx XC4000 850–858 intermittent 112 event attribute, VHDL 289, 625, FIFO (first-in, first-out memory) 698 Fairchild Semiconductor 508, 788 859 event list, Verilog simulator fall time 112, 131, 149, 763 fighting outputs 133, 138, 419, 826 331–332, 662 fall time (tf) 115 file input/output, Verilog 329  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 875 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. filtering capacitors 124 for keyword, Verilog 324 GAL16V8 376, 378, 394, 424, fine-line PCB technology 17 for loop, Verilog 324 426, 440, 441, 442, 703, 707, finite field 73, 737 for loop, VHDL 282 709 finite induction 190 formal parameters, VHDL 265 GAL16V8C 377, 378, 703 finite-memory design 638, 656 for statement, Verilog 310, 324 GAL16V8R 703 finite-memory machine 672 forward-biased diode 156 GAL16V8S 703, 703 finite-state machine 522, 558, 672 forward resistance 156 GAL20V8 378, 412, 424, 706, 709 first-in, first-out (FIFO) memory FPGA See field-programmable GAL22V10 378, 706, 709 859 gate array GAL devices 376–376, 703–710 fitter 240, 242, 849, 853 Franaszek, Peter 74 Galois, Évariste 73, 737 constraints 379 free-running counter 715 Galois-field arithmetic 589 fitter, CPLD 379 Frisbee xvii Galois fields 788 fitting 242 front-end design process 241 gate 6 fixed-OR element (FOE) 373 full adder 474, 475, 476, 477 of CMOS transistor 87 flash EPROM 811, 812 full case, Verilog 322 symbols 346–347 flash memory 812 full subtractor 476 gate array 16, 600 flat schematic structure 357 function, Verilog 326 gate-array design 17 Fleischer, Bruce M. 174 function, VHDL 265 Gateway Design Automation 290 flip-flop 7, 526, 532–541, 590, functional decomposition 311 gating the clock 765–767 686 functional verification 242, 242 generalized DeMorgan’s theorem 192, 194, 196, 202, 346 asynchronous inputs 533 function block (FB), Xilinx 841 generate block 310 CMOS D 600 function call, Verilog 327 generate keyword, Verilog 310 control-input dominance 647 function call, VHDL 265 generate statement, Verilog 506 documentation 680 function declaration, VHDL 271 generate statement, VHDL 273, reset-dominant 647 function definition, Verilog 326 500 set-dominant 647 function definition, VHDL 265 generic array logic (GAL) 376 flip-flop vs. latch 526–527 function generator 852 854 – See also GAL device floating gate 382 function hazard 717, 758, 788 floating-gate MOS transistor 381 generic constant, VHDL 274 , function keyword, Verilog 326 810 generic declaration, VHDL 274 function keyword, VHDL 265 floating input 112, 690 generic keyword, VHDL 274 function table 388 floating output 418 generic map, VHDL 274 fundamental-mode circuit 590, 592 floating-point representation 816 genvar keyword, Verilog 310 fun stuff xvi, 2, 566, 589 floating signal 421 Ghausi, M. 174 fuse pattern 254 floating state 132, 421 giga- (G) 72 fuses, PLA 371 flowchart 664 gigabit Ethernet 171 fuses, PLD 376 flow table 597 glitch 224, 373, 717, 735, 736, 766 fusible link 810 flow-table minimization 604–605 glue ICs 13 Flynn, Michael J. 73 Goldstine, Herman H. 229 G fmax 708 Golson, Steve 664 Ford Thunderbird 571 G (giga-) 72 Google xxiii, 12 forever statement, Verilog 325 Gagliardi, R. M. 74 goto statement, ABEL 614  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 876 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. Graham, Martin 174, 790 HCT (High-speed CMOS, TTL hold time 242, 532, 533, 540, 541, Gray code 51, 57, 385 compatible) 142, 153, 689 697, 816, 825 Greek philosophers 663, 789 HDL (hardware description hold-time margin 683, 762 ground (GND) 126 language) 5, 8, 9, 15, 18, hold-time requirements 370 187, 205, 237 ground bounce 126, 127, 128, 149, Holley, Michael 336, 629 152 compiler 9, 239, 576 Horton, Marcia xxiii group carry-generate signals 492 signal naming 354–355 Huntington, E. V. 229 group-carry lookahead 483, 484, simulator 9 Huntington postulates 229 484 synthesis tool 239 hysteresis 130, 360, 421 group carry-propagate signals 492 synthesizer 9, 239 Hz (hertz) 69 group-ripple adder 482 test bench 10 guessing game 580, 588 tool suites 239–240 I Gunawan, Hendra 336 HDL text editor 9, 239 I/O block (IOB) 846, 854–855 Hellerman, Herbert 522 I/O pin, PAL 375 H helper output, PLD 395 IC (integrated circuit) 11–14, 84 helper terms 375, 376 ∆I 145 half adder 474 CC Hennie, Frederick C. 664 I , TTL 167 half sum 474 CCH henries 124 I , TTL 167 Hamlet circuit 236 CCL hertz 69 I 145 Hamming, R. W. 61 CCT hertz (Hz) 69 IC type 360 Hamming code 61, 451 hexadecimal addition 34 IC vs. chip 12 Hamming distance 58 hexadecimal digits A–F 27 identifier 354 hardware description language ABEL 244 (HDL) 5, 8, 9, 15, 18, 187, hexadecimal number system 27–29 Verilog 293 205, 237 hexadecimal prefix ^h, ABEL 253 VHDL 258 compiler 9 hexadecimal-to-binary conversion idle state 560 hardware model 5 28 hierarchical design 241 IEEE (Institute of Electrical and Haseloff, Eilhard 789 Electronics Engineers) 256, hazard 224–229, 602, 758 hierarchical schematic structure 357 336, 347 dynamic 227, 758 IEEE 1164 standard logic package HIGH 3, 80, 86, 157, 194, 348 essential 609, 697, 762 261, 265, 266, 270, 427 high-impedance state 132, 418 function 717, 758, 788 IEEE 1364 (Verilog) 291 high-order bit 27 in feedback sequential circuit IEEE standard 1076 270 228 high-order digit 26 IEEE standard 1149.1 383 static 694, 717, 758 HIGH-state DC noise margin 148 IEEE standard logic symbols 347, static-0 225 HIGH-state fanout 111, 148 681 static-1 225 TTL 165 if keyword, Verilog 318 hazard-free excitation logic 602, Hi-Z state 132, 418, 420, 421 if statement, ABEL 614 602 multiplexer output 436 if statement, Verilog 318, 404 hazards HM62256 828 if statement, VHDL 280 in synchronous design 228 HM6264 828 II, TTL 167 HC (High-speed CMOS) 102, 142, HM628128 828 IIH 103 153, 154 HM628512 828 IIHmax, TTL 165  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 877 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

IIL 103 input state 592 ISE (Integrated Software Environment) xx IImax 146 instance statement 309 impedance vs. resistance 88 instance statement, Verilog 307, is keyword, VHDL 258, 259 implicit sensitivity list, Verilog 313 313 ISO (International Standards imply 217 instantiate 257, 272, 292 Organization) 261, 264 ispLEVER xx 337 in, VHDL 259 instantiatiation 357 , istype keyword, ABEL 244 612 `include directive, Verilog 305 instructors xxii , iterative circuit 459 462 756 includes 217 insulation 113 , , boundary inputs 756 inconsistent state-machine in-system programmability 383 representations 681 integer keyword, Verilog 297 boundary outputs 756 independent error model 58 integer type, VHDL 260, 261 cascading inputs 756 index 23 integrated circuit (IC) 11–14, 84 cascading outputs 756 inductance, stray 124 Integrated Device Technology 859 primary output 756 induction step 190 intermediate equation, ABEL 247 iterative comparator 459 inductive effects 124–128 intermittent failure 112 iterative consensus 190, 223 inductor 124 internal feedback, PLD 708 iterative widget 756 infer (in synthesis) 239 internal state 592 infer a latch, Verilog 314, 320, 322 Internet Protocol (IP) 4 J inferred latch 698, 702 introductory courses xvi Jackson, Tom 859 inferring latches 471, 472 invalid logic level 8 Jacobs, Joanne v, xxiv information bit 59 inversion bubble 83, 90, 208, 346, Jain, Prem xxiii initial block, Verilog 332 346, 347, 349, 351–353, 389, J-K flip-flop 553 initial keyword, Verilog 332 390 J-K flip-flop 686 initial state 556, 561, 562, 563 inverted 1-out-of-n code 55 job xvii in keyword, VHDL 258 inverter 7, 82, 159–160, 186, 350 Johnson, Howard 174, 790 inout declaration, Verilog 295 CMOS 88–90 Johnson counter 735 inout keyword, Verilog 295, 328 symbol 346 self-correcting 736 inout keyword, VHDL 259 inverting gate 210, 388 Joint Photographic Experts Group inout port, Verilog 295 invert keyword, ABEL 248 (JPEG) 4 input IOH 102 joke 522 5-V-tolerant 153, 154 IOHmax 106 really bad 588 floating 112 IOHmax, TTL 165 joule 145 PLA 370 IOHmaxC 148 JPEG (Joint Photographic Experts Group) 4 input/output declarations, Verilog IOL 102 JTAG port 383 327 IOLmax 106 juxtaposition 187 input combination 6 IOLmax, TTL 165 input declaration, Verilog 295 IOLmaxC 147 input keyword, Verilog 293, 295, IOLmaxT 147 K 327 IOS, TTL 167 K (kilo-) 72 input-list, ABEL 250, 253 IP (Internet Protocol) 4 Karnaugh map 212 input port, Verilog 294–295 irredundant sum 234 5-variable 235, 564 inputs, unused 112 ISE 337 6-variable 236  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 878 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. Karnaugh, M. 230 leakage current 88, 103, 109, 133, logical vs. bitwise negation, Verilog Kaufman, Jennie xxiii 156 755 Kent, Clark 526 least significant bit (LSB) 27 logical vs. boolean, Verilog 304 keywords, Verilog 293 least significant digit 26 logic circuit 183 keywords, VHDL 258 LED (light-emitting diode) 103, combinational 183 kilo- (K) 72 135–137, 408 sequential 183 Kleeman, Lindsay 789 left, shift-register direction 730 logic design 1, 5 Klir, George J. 174 level shifter 155 logic designer 344 levels of abstraction, digital design kludge 766 logic-design template 8 18 Knuth, Donald E. 73, 376 logic diagram 306, 343, 355–358 level translator 155 Kohavi, Zvi 230, 664, 788 logic-drawing template 237 Levesque, A. H. 74, 788 logic equation 348 LFSR (linear feedback shift logic expression 187, 348 L register) counter 737, 788 complement of 192 _L suffix 387, 390 libraries 239 dual of 193 laboratory courses xvi library, Verilog 308 parenthesized 201 Láng, Tomas 73 library, VHDL 269 logic expressions vs. signal names larger-scale logic element 349, library, Xilinx ISE unisims 272 349 355, 386–387 library clause, VHDL 269 logic families, TTL 166 large-scale integration (LSI) 13, 13 light-emitting diode (LED) 103, logic family 85 functions 16 135–137, 408 logic inverter 159 Larsen, Ib 788 Lin, S. 74 CMOS 88 latches 526, 527–532, 590, 686 linear feedback shift register logic levels 101–103 (LFSR) 588, 589 ABEL 694–697 invalid 8 counter 737, 788 Verilog 701–702 TTL 162 line code 69 VHDL 697–699 logic minimization programs liquid-crystal display (LCD) 408 latch inference 471, 472, 652 223–224 literal 197 latch inference, Verilog 314, 320, logic symbol 390 322 Verilog 298–299 traditional 386 latching decoder 696 load logic value 80 latch-up, CMOS 113 AC 116 CMOS undefined 86 latch vs. flip-flop 526–527 capacitive 116 constant 112 DC 103 116 late-write SSRAM with flow- , lookahead carry circuit 485 through outputs 830 resistive 103 looping statement, Verilog 324 late-write SSRAM with pipelined load capacitance 115, 170 LOW 3, 80, 86, 157, 194, 348 outputs 830 logic, multivalued 224 low-order bit 27 Lattice ispLEVER 337 logic 0 8 low-order digit 26 Lattice Semiconductor xx, 378, logic 1 8 Low-power Schottky TTL (LS- 508, 859 logical addition 187 TTL) 160, 689 ispLEVER xx logical expression, Verilog 304 LOW-state DC noise margin 148 lawyers 132, 373 logical multiplication 186 LOW-state fanout 111, 148 LCD (liquid-crystal display) 408 logical operators, Verilog 303–305 TTL 165  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 879 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. Low-Voltage CMOS (LVC) 154, mathematicians 594 microprocessor 13, 358, 410, 421, 690 Maxfield, Clive 508 450, 523, 773, 777, 799, 811, LSB (least significant bit) 27 maximum delay 363, 365 813, 828 LSI (large-scale integration) 13 maximum-length sequence 737 microsecond (µsec) 6 LSI Logic Corporation 600 maximum-length sequence mil 17 LS-TTL (Low-power Schottky generator 737 Mills, Don 664 TTL) 160, 689 maxterm 197, 210, 222 minimal-cost equations 563, 565, 566 _L suffix 348 maxterm i 198 minimal cut set 594 lunch 3 maxterm list 199, 211 minimal product 222 LVC (Low-Voltage CMOS) 154 McCluskey, Edward J. xxiii, 223, 229, 230, 663, 788, 789 minimal-risk equations 563, 565 MCM (multichip module) 17 minimal sum 216, 218, 219, 220, M 221 Mead, Carver 663, 789 M (mega-) 72 minimization programs 223–224 Mealy machine 543, 547, 548, macrocell, PLD and CPLD 379, 549, 556, 558, 568, 590 minimize 210 452 Mealy-type output 543, 550, 620, minimum delay 363, 365, 368 macros 342 761 minimum distance 59 magnetic bubbles 822 mean time between failures minimum pulse width 121, 526, magnetic disk 81 (MTBF) 772, 774, 776, 777 528, 531 magnetic tape 81 mechanical encoding disk 385 minterm 197, 210, 212, 214, 215 magnitude comparator 458 medium-scale integration (MSI) minterm i 198 main machine 587 13, 22, 392 minterm list 198, 210 majority function 499 functions 16, 342 minterm number 198, 213 3-input 309 mega- (M) 72 minuend 32 Manchester code 73, 81 memory 7, 13, 450 model, hardware 5 mandarin 12 first-in, first-out (FIFO) 859 modeling language 256 Mano, M. Morris 229 Mercedes 508 modem 740 module, Verilog 291 mantissa 816 Mercury Capri 571 module declaration, Verilog 294 marginal notes xvii metal-oxide semiconductor field- module keyword, Verilog 293, 294 marginal pun xvii effect transistor (MOSFET) 85–88 module statement, ABEL 244 marginal triggering condition 526 metastability 525, 525–526, 528, modulo-m counter 710 margins, engineering design 96 529, 530, 532, 533, 538, 594, modulus 710 marketing people 851 645, 663, 762, 767, 769–778, Verilog 301 Marquand, A. 230 859 Moebius counter 735 Mars 76 metastability resolution time 771 $monitor task, Verilog 329 mask 809 metastable state 525, 769 $monitoroff task, Verilog 329 mask charge 809 metatheorem 193 $monitoron task, Verilog 329 mask-programmable ROM 809 Michels, Diana 12 Monolithic Memories, Inc. (MMI) mask ROM 809 Michelson, A. M. 74, 788 508 master/slave J-K flip-flop 538 microampere 88 Moore’s Law 18 master/slave S-R flip-flop 537 microampere (uA) 88 Moore machine 543, 548, 549, master latch 532 Micron Technology 859 552, 555, 572, 590  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 880 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. Moore-type output 543, 548, 550, multiplexer 18–21, 311, 432–446 NAND vs. NOR gate 529 616, 761 ABEL program 20 CMOS 92 MOS (“moss,” metal-oxide Boolean equation 19 nanohenries (nH) 124 semiconductor) 86 CMOS 18 nanosecond (ns) 6 MOSFET (metal-oxide enable input 436, 440 nasty realities 762 semiconductor field-effect gate-level design 19 transistor) 85–88 National Semiconductor MSI building block 20 Corporation 132 MOS ROM 808 PLD realization 20 natural subtype, VHDL 263 MOS transistor 85 switch model 18 n-bit binary code 384 floating-gate 381 truth table 19 n-bit binary counter 711 most significant bit (MSB) 27, 34, 37 Verilog program 22 NBUT gate 674 most significant digit 26 VHDL program 20 n-channel MOS (NMOS) transistor 87 Motion Picture Experts Group multiplexers (MPEG) 4 ABEL 440–443 n-cube 57, 58 Mountain View, CA 809 expanding 436–438 NEC Electronics 859 m-out-of-n code 56 Verilog 445–446 negate 348 movies 5 VHDL 444–445 negated 3 MPEG (Motion Picture Experts multiplication 45–47 negative BCD numbers 49 Group) 4 ABEL 497 negative-edge-triggered D flip-flop MSB (most significant bit) 27, 34, signed 46–47 533 37 using ROM 803 negative logic 80 MSI (medium-scale integration) Verilog 301, 503–507 negative-logic convention 185, 194 13, 22, 392 VHDL 497–502 negative numbers 34–39 functions 16, 342 multiplication dot (⋅) 186, 187 negedge keyword, Verilog 334, m-subcube 58 multipliers 494–502 646, 702 MTBF (mean time between multiplying out 189, 201, 203, neg keyword, ABEL 248 failures) 772 207, 208, 476 nerds 185, 230 µ-law PCM 816 multivalued logic 224 nested expansion formula 30 multichip module (MCM) 17 Murphy’s law 366 nested if statement, Verilog 318 multidimensional array mutual exclusion 553, 574 nested when statement, ABEL 250 Verilog 503 mux 432 nesting, if-then-else, ABEL Verilog-2001 302 616 VHDL 264, 497 N net, Verilog 296 net declaration, Verilog 296 multiple-cycle synchronizer 776 n{}, Verilog replication operator multiple-emitter transistor 161 300 net list 242, 273, 306 multiple error 58 named state 572, 605 nets vs. variables, Verilog 297–298 multiple-output circuits 184 NAND gate 83, 191, 210, 529 next-state function 545 multiple-output function 223 CMOS 90 next-state logic 542 multiple-output minimization 222, symbol 346 VHDL 628 224 nand gate, Verilog 306 next-state logic, Verilog 649 multiple-valued logic 230 NAND-NAND circuit 204, 208, next statement, VHDL 283 multiplexed address inputs 835 209, 211, 229 next-state-variables, ABEL 618  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 881 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. nH (nanohenries) 124 NOT prefix 244 operator precedence 193 nibble 29 npn transistor 158 ABEL 245 Nikolic, B. 174, 508 NRE (nonrecurring engineering Verilog 303 NMOS (n-channel MOS) 87 cost) 16 VHDL 276 node, state-diagram 548 NRZ (Non-Return-to-Zero) 69 optional sections xvi, 38 noise 98, 131 NRZI (Non-Return-to-Zero Invert- OR-AND circuit 193, 202, 209, noise immunity, ECL 172 on-1s) 71 211, 227, 229 n-to-2n decoder 384 noise margin 7, 101–103, 169 OR-AND-INVERT (OAI) gate, null statement, Verilog 317 DC 97, 103, 112 CMOS 95, 175 null statement, VHDL 268 TTL 164, 165 OR gate 6, 82, 187, 194, 210 numeric_std VHDL package 270 noise margins CMOS 93 TTL 162 symbol 346 O nonblocking assignment, Verilog or gate, Verilog 306 331 octal 421, 692 or keyword, Verilog 312, 313, 314 nonblocking assignment operator, octal number system 27–29 OR operation 187 Verilog <= 315 octal-to-binary conversion 28 Osborne, Thomas E. 664 non-blocking assignment statement, odd-parity circuit 448 other declarations, ABEL 245 Verilog 648 odd-parity code 60 others, VHDL 264, 277, 282, 429 noncode word 58 off-set 199 OTP-ROM (one-time noncritical race 597 "off" transistor 87 programmable ROM) 811 noninverting gate 210, 388 Ohm’s law 100 out, VHDL 259 nonrecurring engineering (NRE) Oliu, W. E. 508 outkeyword, VHDL 258 cost 16, 22 one-hot state assignment 562 output Non-Return-to-Zero (NRZ) 69 almost 562 5-V-tolerant 154 Non-Return-to-Zero Invert-on-1s one-hot state encoding 658 open-collector 133, 360 (NRZI) 71 OneKey xx–xxi, xxii open-drain 133–136 nonvolatile, erasable memory 81 ones’ complement 38, 77 output-coded state assignment 543, nonvolatile memory 801, 810, 822 ones’-complement addition 44 584 NOR gate 83, 192, 210, 529 ones’-complement arithmetic 44 output declaration, Verilog 295 CMOS 91 ones’-complement subtraction 44 output-disable time 815, 826 symbol 346 ones-counting machine 635, 655 output-enable (OE) input 813 nor gate, Verilog 306 one-time programmable (OTP) output-enable gate 375 normal term 197 ROM 811 output-enable time 815, 826 NOR-NOR circuit 209, 211, 229 one-to-one mapping 384 output equation 547, 552, 592 NOR vs. NAND gate, CMOS 92 on-set 198, 248, 612 output function, state-machine 545 notation 144 "on" transistor 87 output-hold time 815, 826 NOT gate 7, 82 ooze 134 output keyword, Verilog 293, not gate, Verilog 306 open-collector output 133, 360 295, 328 notif0 gate, Verilog 306 open-drain bus 137, 137–138 output-list, ABEL 250, 253 notif1 gate, Verilog 306 open-drain output 133–136, 360 output loading 101, 102, 111 not keyword, VHDL 258 operator overloading, VHDL 266, output logic, state-machine 542 NOT operation 186 276 output logic, Verilog 649  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 882 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. output logic, VHDL 629 parallel-in, parallel-out shift register PDP-11 minicomputer 805 output logic macrocell 703 728 Pedroni, Volnei A. 336 output polarity, GAL 378 parallel-in, serial-out shift register Pellerin, David 290, 336, 629 output-polarity control 378 728 pepperoni 12 output port, Verilog 294–295 parallel-to-serial conversion 728 perfect induction 188, 196 outputs, fighting 133, 138 parameter, Verilog 309 perfume 101 outputs, PLA 370 parameter declaration, Verilog 299 PERL 10 output-select multiplexer 617 parameterized modules, Verilog Perl 10 309 output stage, TTL 161 permanent failure 58 parameter keyword, Verilog 299 output table 552 Peterson, W. W. 74 parameter substitution, Verilog phase splitter 161 output timing skew 747 309, 506 Philips Semiconductor 508, 788 overall fanout 111 parasitic diode 130 picosecond (ps) 6 TTL 165 parasitic SCR 113 pin declarations, ABEL 244 overbar notation 186, 390 parenthesization pin definitions, ABEL 397 overflow 43 switching algebra 188 pin diagram 12 rules 41 parenthesized logic expression 201 pin locking 849 two’s-complement 41, 42 parity bit 59 pin number 360 overlaid functions, VHDL 468, parity-check matrix 61 488, 502 pinout 12 parity function, ABEL 452 overloaded output, TTL 165 pipelined Mealy outputs 761 parity function, Verilog 456–457 overshoot 153 pipelined outputs 544, 620, 629, parity function, VHDL 453–454 634, 649, 652 partial product 46 P Pixar 5 part-select operator [], Verilog pizza 12 package, VHDL 269 300, 752 PL 123 package body keywords, VHDL party line 418, 419, 420, 421 PLA (programmable logic array) 271 passive pull-up 133 14, 199 package keyword, VHDL 271 patents 74 See also programmable logic packed-BCD representation 49 path, signal 120 device (PLD) pad, IC 12 path sensitization 230 place and route 242 pad ring 151 PayPal xxii PLA fuses 371 page, SDRAM 838 PBX (Private Branch Exchange) 4 PLCC package 128 PAL16L8 374, 375, 376, 378, 394, PCB (printed-circuit board) 17–18, PLD (programmable logic device) 424 362, 763 11, 243 PAL20L8 376, 378 PCB design 765 CMOS circuits 380–382 PALASM (PAL Assembler) 237 PCB-level design 22 fitting 242 PALCE16V8 378, 707 PCB routing 763 fuses 376 PALCE20V8 378 PCB traces 17 macrocell 379, 452 Palnitkar, Samir 336 p-channel MOS (PMOS) transistor minimization 222, 247–248 parallel case, Verilog 321 87 programming 254 parallel comparator 459 PCI bus 778 PLD-based design 342, 578, 584 parallel data 69 PCI Express 69 PLD-based synchronizer 777  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 883 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. PMOS (p-channel MOS) 87 precedence procedure call, VHDL 269 pneumatic logic 81, 174 ABEL operator 245 process, Verilog simulator 331 pnp transistor 158 switching algebra 187, 193 process, VHDL 278 politics 3 Verilog operator 303 process keyword, VHDL 278 polymer memory 81 VHDL operator 276 process statement, VHDL 278 Porsche 508 precharge 834 product code 66 port, VHDL 259 predefined types, VHDL 260 product component 494, 495 port, VHDL 259 preset input 527, 533, 680 product of sums 189 port-association list, Verilog 307, primary inputs and outputs, product-of-sums expression 193, 308 iterative-circuit 459 197, 202, 204, 209 port declaration 259 primary output, iterative-circuit product-of-sums minimization 222 port keyword, VHDL 258 756 product term 197 port map, VHDL 272 prime (′) 186 product-term allocation 843 ports, Verilog 294–295 prime, definition of 206, 231 product-term allocator 844 posedge keyword, Verilog 334, prime implicant 217 product terms, PLA 370 646, 702 essential 219 programmable array logic (PAL) positional number system 26 secondary essential 221 device 14, 373–376 positive ECL (PECL) 173 prime-implicant theorem 218, 229 programmable interconnect 856–858 positive-edge-triggered D flip-flop prime notation 186 programmable logic array (PLA) 532–537 prime number 206 positive logic 80, 388 14, 199, 370–373 prime-number detector 205, 211, constant outputs 372 positive-logic convention 185, 194, 216, 217, 231, 272, 276, 277, 195, 348 280, 281, 282, 283, 311, 318, diagram 371 pos keyword 248 319, 320, 322, 324 programmable logic device (PLD) 11, 13, 14–15, 22, 23, 237, post-fitting timing verification 242 test bench 333 243, 343, 541, 543, 554, 564, postponed-output indicator 537 primitive flow table 603, 603 566, 588, 703–709 postulate 185 principle of duality 193 CMOS circuits 380–382 power 103 printed-circuit board 124 compiler 424 power consumption 109, 123 printed-circuit board (PCB) 17–18, complex See complex CMOS 97, 114 124, 362, 763 programmable logic TTL 124 printed-circuit-board (PCB) layout device (CPLD) power dissipation 123 189 fitting 242 dynamic 122, 145 printed-wiring board (PWB) 17 fuses 376 quiescent 122 priority 410 macrocell 379, 452 static 122 priority encoder 410 minimization 222, 247–248 power-dissipation capacitance 122, private branch exchange (PBX) 4 programmer 382 145 problem solving 2 programming 254 power-down input 814 procedural code 297 vs. simulation 11 power supply 124 Verilog 312–329 programmable read-only memory power-supply rails 102, 108 procedural statement, Verilog 312, (PROM) 382, 809 power-supply voltage 101, 102, 313, 315 biploar 810 170, 363, 365, 593, 597, 775 procedure, VHDL 269 programmer 382, 809  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 884 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. programmable switch matrix (PSM) pushbutton 687 read cycle, SDRAM 836 857 push-pull output, TTL 161 read-only memory (ROM) 696, programmer vs. logic designer 344 800–821 programming 349 Q one-time programmable (OTP) CPLD 382 811 QDR SSRAM 832 EEPLD 381 realization 207 quad-data-rate (QDR) SSRAM 832 EEPROM 811 realize 207 quad gate 98 EPROM 810 recommended operating conditions, quadruple gate 98 FPGA 382 TTL 167 quantizing distortion 817 mask ROM 809 reconfigurable hardware 382 quiescent power dissipation 122 PROM 809 recovery time 529 Quine, W. V. 223, 229 programming and state machines rectangular sets of 1s 215 555 Quine-McCluskey algorithm 223 redundant array of inexpensive programming an EPROM 810–812 Q vs. QN 592, 669 disks (RAID) 67 programming voltage, EEPROM Q vs. QN 528 reference designator 360 812 reflected code 52 programming vs. state-machine R reflections, transmission-line 131, 153 design 555, 681 Raaum, Dave xxiii, 325, 339 refresh counter, SDRAM 839 programs, logic minimization Rabaey, J. M. 174, 508 223–224 refresh cycle 834 race 596, 605, 758 project leader 344 refresh operations, DRAM 839 race-free state assignment 605–608 PROM (programmable read-only register 691–694, 759 radix 26 memory) 809 cascaded 680 radix-complement system 35 propagation delay 97, 111, 115, registered carry output 721 120 122 144 364 368 528 radix point 26, 35 – , , , , , registered output 612 528, 531, 532, 608, 697, 708 radix-r-to-decimal conversion 29 registers, ABEL 694–697 property list, istype 244 RAID (redundant array of registers, Verilog 701–702 P-set 230 inexpensive disks) 67 registers, VHDL 697–701 pseudorandom counting sequence rails, power-supply 102, 108 740 random-access memory (RAM) register-transfer language 239 pseudorandom sequence generator 821–840, 859 reg keyword, ABEL 612 588, 589 static (SRAM) 822–829 reg keyword, Verilog 297 pull-up, active 133 range, ABEL 251 reg vs. register, Verilog 404, 405 pull-up, passive 133 range, VHDL 262 relation, ABEL 253 pull-up resistor 133, 421, 690 range attribute, VHDL 268 relational expression, ABEL 253 pull-up-resistor calculation 139 range keyword, VHDL 262 relational operators pulse-catching circuit 603–611 range specification, Verilog 295 ABEL 253 pulse input 663 RAS-CAS delay 836 Verilog 303–304 pulse-mode circuit 663 rate of a code 78 VHDL 276 pulse-triggered flip-flop 537 RC time constant 117, 690 relay 103 pulse width, minimum 526, 528, read/write memory (RAM) 696, relay logic 81, 174 531 759 reliability 112, 145, 810 punctuation 77 read/write memory (RWM) 821 Renesas Technology 859  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 885 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. repeat statement, Verilog 325 Robbins, Tom xxiii SDRAM (synchronous DRAM) replication operator n{}, Verilog rollover, loop counter 333 (continued) 300 rotating drum 822 burst-write cyle 839 report statement, VHDL 288 row address, SDRAM 836 column-address register 836 reserved words 354 row-address register, SDRAM 836 configuration register 839 Verilog 293 row latch, SDRAM 836 page 838 VHDL 258 running disparity 71 read cyle 836 reset running process, VHDL 279 refresh counter 839 state-machine 558, 560, 561 RZ (Return-to-Zero) 71 row address 836 reset, synchronous versus row-address register 836 asynchronous 664 S row latch 836 reset circuit 558 safe state 583, 616, 733 write cyle 838 reset-dominant flip-flop 647 sales pitch 5–6 second, s 69 reset input 527, 623, 624, 632, SanDisk Corporation 812, 859 secondary essential prime implicant 641, 644, 652, 660 221 saturated (ON) 159 resistance, forward 156 secret sauce 849 saturation 170 resistance vs. impedance 88 security fuse 383 scan capability 535, 663 resistive load 103 Seitz, Charles L. 789 latch 663 resistor selected signal assignment, VHDL scan chain 536 pull-up 421, 690 278 schematic 273, 306, 680 calculation 139 selected signal-assignment schematic diagram 237 343 346 resolution function, VHDL 427 , , , statement, VHDL 277 355–358 resolved type, VHDL 427 select statement, VHDL 399 schematic drawing 204 result, VHDL 265 self-complementing code 50 schematic editor 237 retain property, ABEL 695 self-correcting counter 733 schematic entry 9 return keyword, VHDL 265, 266 self-correcting Johnson counter schematic viewer 240 Return-to-Zero (RZ) 71 736 Schmid, Hermann 73 reverse-biased diode 156 self-correcting ring counter 733 Schmitt-trigger input 130–131, self-documenting code 682 reverse-polarity equation 248 770 self-dual logic function 234 reviewers xvii, xviii Schmitt-trigger inverter 805 self-timed systems 789 revolution 3, 5 Schottky-clamped transistor 160 semicolon, Verilog 317 right, shift-register direction 730 Schottky diode 160 semiconductor diode 84, 156 ring counter 718, 732, 742 Schottky transistor 160, 166 semicustom IC 16 self-correcting 733 scope,Verilog 293 sense amplifier 834 ripple 461 scope of signal name 355 sensitivity list ripple adder 460, 475 SCR (silicon-controlled rectifier) ripple carry out, 74x163 counter 113 Verilog 312–314, 331 715 scrambler 740 implicit 313 ripple counter 711 SDRAM (synchronous DRAM) VHDL process 279 rise time 112, 131, 149, 763 835–840 sensitivity matrix, Verilog 331, 332 rise time (tr) 115 auto-refresh cyle 839 sensor 51 risk 3 burst-read cyle 838 sequential circuit 7, 82, 183, 521  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 886 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. sequential multiplier 495 signal names 350 simultaneous switching 126, 127, sequential PLD 376 case sensitivity 354 128 sequential signal-assignment in HDLs 354–355 single-ended input 172 statement, VHDL 279 vs. logic expressions 349 single error 58 sequential statements, VHDL 265, signal-names single stuck-at fault model 255 278–284 scope 355 sinking current 106 serial-access memory 822 signal naming 355 TTL 162 serial binary adder 758 signal path 120 six-variable Karnaugh map 236 serial comparator 756 signal-sensitivity list, VHDL Skahill, Kevin 336 serial data 69 285–286 skew 172 serial-in, parallel-out shift register signal-sensitivity matrix, VHDL slash (/) 344 728 285 slave latch 532 serial input, shift-register 727 signals vs. variables, VHDL 500, sledgehammer 113 serial output, shift-register 727 752 small-scale integration (SSI) 12, serial-to-parallel conversion 728 sign bit 34, 37 22, 392, 566, 686 serial widget 756 signed arithmetic, Verilog 301 sneak path 806 set 527 signed division 48 Social Security 663 set, ABEL 251, 614, 618 signed-magnitude adder 35 software tools 8–10 set-dominant flip-flop 647 signed-magnitude representation for logic design 186 setup time 242, 532, 533, 540, 50 soldering iron 8 541, 697, 709, 825 signed-magnitude subtractor 35 solder paste 17 signed-magnitude system 34 setup-time margin 683 source, CMOS transistor 87 signed multiplication 46 47 seven-segment decoder 408 – sourcing current 106 signed vs. unsigned numbers 43 seven-segment display 408 TTL 162 sign extension 35 37 47 77 Shannon, Claude E. 185, 229 , , , space/time trade-off 756, 758 silicon-controlled rectifier (SCR) shift-and-add multiplication 45 specifications 8, 98–100, 102 113 shift-and-add multiplier 761 specs 8, 102, 342 parasitic 113 shift-and-subtract division 47 speed 5 shift register 727–740, 759 simulation 11, 238, 241, 279, 282, 301, 310, 645, 662, 663 CMOS 97, 114 cascaded 680 Verilog 331–332 combinational-circuit 208, 210 shift-register counter 730 VHDL 285–286 PAL 378 shift registers vs. PLDs 11 PLD 378 ABEL 740–748 simulation cycle, Verilog 331, 332 speed-power product 145 Verilog 752–755 simulation cycle, VHDL 286 Spencer, R. 174 VHDL 748–752 simulation time, Verilog 331 spikes, current 124 sidebars xviii simulation time, VHDL 285 S-R latch 121, 527, 530, 531, 534, sign 816 537 645 662 694 simulator 9–10, 200, 240, 330, , , , signal, Verilog 296 337, 369, 507 with enable 530 signal declaration, VHDL 260 Verilog 331–332 S-R latch 529 signal flags 356, 359 VHDL 285–286 S-set 230 signal keyword, VHDL 260 simultaneous input changes 590, SSI (small-scale integration) 12 signal name 348, 353, 386 593, 594 stable 525  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 887 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. stable total state 592, 603 state memory 542 string standard cell 16, 342 Verilog 649 ABEL 244 standard-cell design 16 VHDL 628 VHDL 264 standard logic package, IEEE 1164 statements, Verilog 292 strong typing, VHDL 262 261, 265, 266, 270 state minimization 599, 604–605 structural description standard MSI functions 342 state name 547, 548 Verilog 306–310 standby mode 815 states, total number of 560 VHDL 273–274 state 7, 522, 545 states, unused 560, 561, 563 structural design abnormal 584, 732, 733 state table 82, 547, 555, 592, 680 Verilog 306–310 coded 560 state-table reduction 663 VHDL 273–274 idle 560 state-value, ABEL 614 structural specification, Verilog initial 561, 562, 563 state variable 522 292 safe 616, 733 state-vector, ABEL 614 structural Verilog code 505 unused 584, 616 static-0 hazard 225 structural VHDL code 500 state/output table 545, 547, 552 static-1 hazard 225 structured logic device description 343 state adjacency diagram 605 static behavior 101 Strunk, William, Jr. 508 state assignment 567, 569 static circuit behavior 97, 101 subcube 58 state diagram 545, 548, 552, 555, static electricity 98, 113 submachine 587 570–576, 577, 680 static hazard 602, 694, 717, 758 subtraction 32 ABEL 614–621 static power dissipation 122 subtraction, Verilog 301 synthesis 682 static RAM (SRAM) 822–829 subtractor 474 state_diagram, ABEL 613 asynchronous 829 full 476 state keyword, ABEL 614 cell 823 subtractors 476–478 state machine 542–570, 759, 769 std_logic_1164 VHDL package See also adders ABEL coding style 629 270 subtrahend 32, 32 cost 563, 565 std_logic_arith VHDL package 270, 467–468, 488, 502, 635, subtype, VHDL 262, 427 decomposition 587 637, 721 subtype keyword, VHDL 261 design 2 553 554 559 566 , , , , , std_logic_signed VHDL suggestive drawings 550 577 package 270, 468 sum bit 478 documentation 680 std_logic_unsigned VHDL sum-of-products expression 189, inconsistent descriptions 681 package 270, 468 193, 197, 201, 204, 207, 208, pipelined output 629, 649 std_logic_vector type, VHDL 209 programs 682 265 sum term 197 reset 560 std_logic type, VHDL 261, 427 Sunnyvale, California 5 synthesis 577 std_ulogic type, VHDL 427 Superman 526 Verilog coding style 649 steady-state behavior 101, 224 surface-mount technology (SMT) VHDL coding style 628 Stone, Harold S. 229 17 state-machine description language $stop task, Verilog 329 suspended statement, Verilog 312 613, 680 storage time 160 suspended VHDL process 279 state-machine design vs. stray capacitance 115 switch 687 programming 555, 681 stray inductance 124 switch debouncing 687–689  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 888 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. switching, simultaneous 126, 127, synchronous preset, 22V10 707 tAH 826 128 synchronous serial counter 712 tail lights 571 switching algebra 184, 185–199, synchronous SRAM (SSRAM) 829 tape, magnetic 81 229 late-write with flow-through tAS 826 adding out 189 outputs 830 task, Verilog 328 ambiguous expression 188 late-write with pipelined outputs task call, Verilog 328 associative law 188 830 task definition, Verilog 328 binary operator 189 QDR 832 task enable, Verilog 328 combining theorem 189 turn-around penalty 831, 832 task keyword, Verilog 328 commutative law 188 ZBT with flow-through outputs Taylor, Douglas 290, 336 831 consensus theorem 190 T-bird tail lights 571–576 cover 189 ZBT with pipelined outputs 832 tCF 708 covering theorem 189 zero-bus-turnaround (ZBT) 831 tclk 771 DeMorgan’s theorem 190 synchronous systems 679, 758–761 tCO 708 distributive law 189 syndrome 64, 451, 452 tcomb 771 duality 193 Synopsys 270, 467, 502 tCSW 826 expression 186, 187 Synopsys, Inc. 290, 633 tDH 826 juxtaposition 187 synthesis 238, 242, 284, 289, 301, tDS 826 multiplying out 189 304, 309, 311, 319, 325, 326, 330, 335, 470–472, 474, telephone system 4, 799, 816 parenthesization 188 490–493, 500, 502, 627, 647, temperature 101, 102, 105, 363, precedence 187, 193 651, 656, 698, 701, 702, 727, 365, 593, 597, 775 theorem 188 752 template generator 240 switching characteristics, TTL 169 combinational-circuit 183 temporary failure 58 switching noise 149, 152 state-machine 577 tera- (T) 72 switch model, CMOS 89 vs. design 184 termination 103, 182 symbols, gate 346–347 synthesis tools 337 test_vectors, ABEL 245 symmetric output drive 143, 149, HDL 239 test_vectors keyword, ABEL 368 Verilog 290 253 synchronization signal 70 VHDL 256 test bench 10, 240, 241, 336 synchronizer 2, 759, 767 synthesizer 205, 314 Verilog 294, 326, 506, 648, failure 770, 797 HDL 239 659–662 synchronizer, PLD-based 777 system architect 344 VHDL 279, 285, 287–289, 628, 641 644 synchronizing sequence 624 system clock signal 628 – synchronous 542 test enable (TE) 536 synchronous counter 711 testing 535, 536, 623 T synchronous design methodology test input, TI 536 683 T (tera-) 72 test-input generation 740 hazards in 228 τ, metastability-resolution time test vectors 383, 625, 644, 662 synchronous DRAM (SDRAM) constant 773, 775 ABEL 245, 253–255, 622 835–840 T1 link 72, 73 Texas Instruments 508, 775, 788, See also SDRAM tAA 815, 825 789, 859 synchronous parallel counter 712 tACS 815, 826 text 53  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 889 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. text editor, HDL 239 timing analysis 368, 764 tpHZ 419 tf 115 program 369 tpLH 121 T flip-flop 541, 711, 713, 727 tools 369 tpLZ 419 with enable 541 timing analyzer 10, 240, 369 tpZH 419 tH 708 timing control, Verilog 325–326, tpZL 419 theorem, switching algebra 188 330–331 tr 115, 771 The Phone Company (TPC) 4, 72, timing diagram 83, 343, 362, 550, trace, PCB 17 73 554, 557, 680, 682–686 trademarks 373 Thévenin equivalent 104 timing generator 744 traditional logic symbols 386 Thévenin resistance 104 timing hazard 190 traffic-light controller 53 Thévenin termination 182 timing margin 112, 683 See also Sunnyvale Thévenin voltage 104 timing parameters, PLD 708–709 traffic lights 4 three-state buffer 132, 418–424 timing skew 610 transceiver 423, 424, 431 three-state bus 132, 690 output 747 transfer characteristic, CMOS 101, Verilog 431 three-state-buffer 419 130 VHDL 427 timing specifications 362, transfer function 524 three-state driver 418 365–368, 680, 682–686 transient behavior 224 three-state enable 418 MSI parts 367 transistor 804 three-state output 132–133, 436, SSI parts 366 bipolar junction 84, 158–160 690 timing table 363, 683 MOS 85 Verilog 430 timing verification 242 n-channel MOS (NMOS) 87 VHDL 427 post-fitting 242 p-channel MOS (PMOS) 87 three-state output pin 424 timing verifier 10 Schottky-clamped 160 three-state outputs 154 Tin Toy 5 transistor-transistor logic (TTL) 81, ABEL 424–427 tiny-scale integration 14 85, 155, 160–168, 171 CMOS interfacing 103 106 Verilog 430–432 title statement, ABEL 244 , , 142 VHDL 427–430 TL7705 558 families 166 threshold 8 T 773 o fanout 164–165 threshold function 499 t 815, 826 OE gates 368 threshold logic 230 t 815, 826 OH load 147 tick 542 543 to keyword, VHDL 263, 265 , logic levels 162 tools 2 tilde notation 186 noise margin 164, 165 total number of states 560 $time function, Verilog 329 noise margins 162 time, modeling 284 total state 592, 593 output stage 161 time keyword, Verilog 330 totem-pole output, TTL 161 overall fanout 165 `timescale directive, Verilog 330 Tower of Babel 270 power consumption 124 time scale tOZ 815, 826 totem-pole output 161 Verilog 330 tp (propagation delay) 120–122 transition/excitation table 564 time to market 15, 23, 205 TPC See The Phone Company transition equation 547, 551, 577, timing 362–364, 708–709 tPD 708 578 closure 370 tpHL 121 transition expression 552, 553  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 890 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. transition frequency 122, 145 two’s-complement multiplication underscore 354 transition list 576–580, 680 46 Verilog 293 transition p-term 577 two’s-complement subtraction 41 VHDL 258 transition-sensitive media 71 two-dimensional code 66 underscore, Verilog 293 transition statement 614 two-dimensional decoding 807, undershoot 153 transition s-term 579 827, 834 unidirectional error 68 transition table 547, 552, 563, 591 two-level AND-OR circuit 204, 208 unidirectional shift register 730 transition time 97, 115–120, 131 two-level NAND-NAND circuit 204, unisims library, Xilinx ISE 272 TTL 165 208 unit under test (UUT) 287, 332, translator 240 two-level NOR-NOR circuit 209 641, 659 transmission gate 18, 129–130, two-level OR-AND circuit 209 universal shift register 730 516, 600 two-level sum-of-products unreset 558 transmission line expression 466 unresolved type, VHDL 427 reflections 131, 153 two-pass logic, PLD 395 unsigned binary multiplication 45 termination 103 two-phase latch design 765 unsigned division 47–48 transparent latch 531, 822 two-phase latch machine 663 unsigned multiplication 45–46 tri net type, Verilog 296 tWP 826 unstable total state 592 tri-state output 132 type, VHDL 260 unused inputs 112 TRUE 3 unresolved 427 unused states 560, 561, 563, 584, true, Verilog 303 type conversion, VHDL 267 616 truth_table keyword, ABEL 250 type keyword, VHDL 261 up/down counter 716, 725 truth table 10, 19, 82, 196–199, typical delay 363, 365 U.S. Department of Defense (DoD) 212, 213, 385, 564, 800 256 ABEL 250, 613 use clause, VHDL 270 notation 385, 388, 434 U user-defined type, VHDL 261 tsetup 771, 771 U.S. patents 74 µA (microampere) 88 t 708 SU µ UUT (unit under test) 287, 332, T suffix 143 -law PCM 816 641, 659 TTL See transistor-transistor logic unambiguous state diagram 573, 574 TTL/CMOS interfacing 103, 106, V 142 unary minus, Verilog 301 TTL vs. CMOS 85 unary plus, Verilog 301 vacuum-tube logic 174 Turing machine 522 unclocked assignment operator, = Vantis Corporation 508 turn-around penalty, SSRAM 831, 248 variable, Verilog 297 832 unclocked assignment operator, variable, VHDL 260, 279 turning the crank 2, 184, 554, 563, ABEL = 246 variable-assignment statement, 576, 603, 608, 681, 710 unclocked truth-table operator, VHDL 280 TV 522 ABEL -> 250 variable declaration, Verilog 297 twisted-ring counter 735 unconstrained array type, VHDL variable declaration, VHDL 260 two’s complement 37, 77 265 variable keyword, VHDL 260, two’s-complement addition 39 undefined logic level 8 279 two’s-complement arithmetic undefined logic value, CMOS 86 variables vs. nets, Verilog 297–298 39–43 undefined region 115 variables vs. signals, VHDL 752  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 891 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

VCC 89 Verilog (continued) Verilog (continued) VCC bounce 128 ^ (XOR) 296 casez keyword 323 VDD 89 ^~ (XNOR) 296 casez statement 323 vector, Verilog 295, 299–302 {} (concatenation operator) coding style 291, 298, 299, 303, vector net, Verilog 296 300, 752 304, 305, 314, 316, 317, vector padding, Verilog 300 | (OR) 296 321, 322, 323, 325, 327, vector variable, Verilog 297 || (logical OR) 304 333, 407, 648, 650, 652, 657 vee ∨ 187 ~ (NOT) 296 comma in sensitivity list 314 Veitch, E. W. 229 ~^ (XNOR) 296 comments 293 Veitch diagram 229 ~ vs. ! 304 comparison 304 verification 241 addition 301 compiler 305, 307, 322, 330 Verilog 9, 15, 22, 290–335 always block 312 component instantiation 307 ! (logical NOT) 304 always keyword 312 concatenation operator {} 300, != (logical inequality) 304 ANSI-style port declarations 752 ! vs. ~ 304 298 concurrent statement 306 # (delay specifier) 330 arithmetic operators 301 executing 312 # (parameter substitution) 309 array 302 suspended 312 $ (built-in functions and tasks) array index 302 293, 329 assign keyword 293, 310, 330 condition 318 % (modulus) 301 assignment-statement sizing 300 conditional operator ?: 305, 311, 431, 445, 492 && (logical AND) 304 begin-end block 317 configuration management 293 & (AND) 296 begin keyword 317 constants 299, 305 - (subtraction) 301 behavioral description 312 continuous-assignment * (multiplication) 301 behavioral design 312–329 statement 310, 313, 431 + (addition) 301 behavioral specification 292 counters 725–727 / (division) 301 bit select 300 dataflow description 310–312 < (less than) 304 bit vector 295, 299–302 dataflow design 310–312 << (shift left) 301 bitwise boolean operators 295 declarations 291 <= (less than or equal) 304 blocking assignment operator, = `define directive 305 <= (nonblocking assignment) 315 315 blocking assignment statement `define vs. parameter 305 <= vs. = 316 315, 331, 648 defparam keyword 309 = (blocking assignment) 315 blocking vs. non-blocking delay statement 331 == (logical equality) 304 assignments 648, 755 delta delay 331 = vs. <= 316 boolean operators 295 disable keyword 326 > (greater than) 304 boolean reduction operators 302 disable statement 326 >= (greater than or equal) 304 built-in gate types 306 $display task 329 >> (shift right) 301 case keyword 321 division 301 ?: (conditional operator) 305, case sensitivity 293 else keyword 318 311, 431, 445, 492 case statement 310, 321, 404 end 317 ? bit value 323 casex keyword 323 endcase keyword 321 [] (part-select operator) 752 casex statement 323 endgenerate keyword 310  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 892 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. Verilog (continued) Verilog (continued) Verilog (continued) end keyword 317 logical operators 303–305 procedural code 312–329 endmodule keyword 293, 294 logical vs. bitwise negation 755 procedural statement 312, 313, expression 303 looping statement 324 315 false 303 module 291 process, simulator 331 file input/output 329 module declaration 294 range specification 295 forever statement 325 module keyword 293, 294 registers 701–702 for keyword 324 modulus 301 reg variable 297 for loop 324 $monitor task 329 reg vs. register 404, 405 for statement 310, 324 $monitoroff task 329 relational operators 303–304 full case 322 $monitoron task 329 repeat statement 325 function 326 multidimensional array 302, replication operator n{} 300 function call 327 503 reserved words 293 function definition 326 multiplication 301 scope 293 function keyword 326 negedge keyword 334, 646, semicolon 317 702 gate types, built-in 306 sensitivity list 312–314, 331 nested if statement 318 generate keyword 310 implicit 313 net 296 generate statement 506 sensitivity matrix 331, 332 net declaration 296 genvar keyword 310 shift registers 752–755 nets vs. variables 297–298 identifiers 293 signal 296 next-state logic 649 if keyword 318 signed arithmetic 301 nonblocking assignment 331 if statement 318, 404 simulation 331–332 nonblocking assignment implicit sensitivity list 313 simulation cycle 331 operator, <= 315 simulation time 331 `include directive 305 non-blocking assignment infer a latch 314, 320, 322 statement 648 simulator 331–332 initial block 332 null statement 317 event list 331–332, 662 initial keyword 332 operator precedence 303 state-machine coding style 649 inout keyword 295, 328 or keyword 312, 313, 314 state memory 649 inout port 295 output keyword 293, 295, 328 statements 292 input/output declarations 295, output logic 649 executing 312 327 output port 294–295 suspended 312 input keyword 293, 295, 327 parallel case 321 $stop task 329 input port 294–295 parameter 309 structural description 306–310 instance statement 307, 313 parameter declaration 299 structural design 306–310 integer keyword 297 parameterized modules 309 structural specification 292 integer variable 297 parameter keyword 299 subtraction 301 keywords 293 parameter substitution 309, 506 synthesis tools 290 latches 701–702 part-select operator [] 300, 752 task 328 latch inference 314, 320, 322 port-association list 307, 308 task call 328 library 308 ports 294–295 task definition 328 literals 298–299 posedge keyword 334, 646, task enable 328 logical expression 304 702 task keyword 328  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices, Index 893 Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. Verilog (continued) VHDL (continued) VHDL (continued) test bench 326, 659–662 /= (inequality) 276, 466 concurrent signal-assignment three-state bus 431 := (variable assignment) 280 statement 276 three-state output 430 < (less than) 276 conditional 276 $time function 329 <= (less than or equal) 276 concurrent statement 271 time keyword 330 = (equality) 276, 466 conditional assignment 278 time scale 330 > (greater than) 276 configuration management 258 `timescale directive 330 >= (greater than or equal) 276 constant declaration 263 timing control 325–326, actual parameters 265 constant keyword 261 330–331 after keyword 284 constants 263 tri net type 296 architecture 257 CONV_INTEGER function 268 true 303 architecture definition 257, 259 converting types 267 unary minus 301 architecture keyword 258 counters 721–725 unary plus 301 arguments 265 dataflow description 275–278 variable 297 array 263 dataflow design 275–278 variable declaration 297 array index 263 delta delay 286 variables vs. nets 297–298 array keyword 263 design flow 241 vector 295, 299–302 array literal 264 downto keyword 263, 265 vector net 296 array slice 265 else keyword 258, 276, 281 vector padding 300 array types 263 elsif keyword 281 vector variable 297 assert statement 288 end keyword 258, 259 vs. VHDL 295, 302, 310, 418 attribute statement 633 entity 256 while statement 325 begin keyword 258 entity declaration 257 wire net type 296 behavioral description 278 entity keyword 258, 259 $write task 329 behavioral design 278–284 enum_encoding attribute 633 z bit value 323 bit_vector type 260 enumerated type 261, 630 Verilog-1995 291, 293, 298, 303, bit type 260 equality operator (=) 466 503 boolean type 260, 261 event attribute 289, 625, 698 Verilog-2001 291, 293, 298, 314 buffer keyword 259 excitation logic 628, 649 Verilog HDL See Verilog case keyword 282 exit statement 283 very large-scale integration (VLSI) false keyword 261 13, 223 case sensitivity 258 for loop 282 custom 381 case statement 282 formal parameters 265 VHC (Very High-speed CMOS) character type 260, 261 143 coding style 289–290 function 265 VHCT (Very High-speed CMOS, comments 258 function call 265 TTL compatible) 143 compiler 257, 266, 269, 270, function declaration 271 VHDL 9, 15, 20–21, 256–290 294 function definition 265 & (concatenation operator) 265, component declaration 272 function keyword 265 751 component keyword 272 generate statement 273, 500 - (subtraction) 488 component statement 272 generic constant 274 * (multiplication) 502 concatenation operator & 265, generic declaration 274 + (addition) 488 751 generic keyword 274  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 894 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4. VHDL (continued) VHDL (continued) VHDL (continued) generic map clause 274 port keyword 258, 259 standard, IEEE 1076 270 identifiers 258 port map keywords 272 state-machine coding style 628 IEEE 1164, standard logic predefined types 260 state memory 628 package 261, 265, 266, procedure 269 std_logic_vector type 265 270 procedure call 269 std_logic type 261, 427 IEEE standard 1076 270 process 278 std_ulogic type 427 if statement 280 running 279 string 264 in keyword 258, 259 sensitivity list 279 strong typing 262 inout keyword 259 suspended 279 structural description 273–274 integer type 260, 261 process keyword 278 structural design 273–274 is keyword 258, 259 process statement 278 subtype 262, 427 keywords 258 range 262 subtype keyword 261 latches 697–699 range attribute 268 synthesis tools 256 library 269 range keyword 262 test bench 287 289 641 644 library clause 269 – , – registers 697–701 three-state bus 427 multidimensional array 264, relational operators 276 497 three-state output 427 report statement 288 natural subtype 263 to keyword 263, 265 reserved words 258 next-state logic 628 type 260 resolution function 427 next statement 283 type keyword 261 resolved type 427 not operator 258 uncontrained array type 265 result 265 null statement 268 unresolved type 427 return keyword 265, 266 operator overloading 266, 276 use clause 270 selected signal assignment 278 operator precedence 276 user-defined type 261 selected signal-assignment others keyword 264 277 282 variable 260 279 , , , statement 277 , 429 variable-assignment statement select statement 399 out keyword 258, 259 280 sequential signal-assignment output logic 629 statement 279 variable declaration 260 overlaid functions 468, 488, 502 sequential statements 265, variable keyword 260, 279 package 269 278–284 variables vs. signals 752 numeric_std 270 shift registers 748–752 vs. Verilog 295, 302, 310, 418 std_logic_1164 270 signal declaration 260 wait statement 285 std_logic_arith 270, signal keyword 260 when keyword 258, 276 467–468, 488, 502, signal-sensitivity list 285–286 while loop 284 635, 637, 721 signal-sensitivity matrix 285 work library 269, 269 std_logic_signed 270, 468 signals vs. variables 500, 752 VHDL-1987 256, 336 std_logic_unsigned 270, simulation 285–286 VHDL-1993 256, 336 468 simulation cycle 286 VHDL-2002 256, 336 package body keywords 271 simulation time 285 VHSIC (Very High Speed package keyword 271 simulator 285–286 Integrated Circuit) 256 port 259 event list 285–286, 645 VIHmin 102, 147  2006 Pearson Education, Inc., Upper Saddle River, NJ. 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VIHmin , TTL 162 wired AND 138 XOR gate 233, 234, 447 VILmax 102, 146 wired logic 138 as comparator 458 VILmax, TTL 164 wire keyword, Verilog 296 xor gate, Verilog 306 VLSI See very large-scale wire lengths 242 XOR operation 234 integration with statement, ABEL 620 XOR structure 719 VOHmin 102 word line 804 VOHmin, TTL 162 word processor 9, 10 Z V 148 OHminC working digital designers xvi z bit value, Verilog 323 V 148 OHminT work library, VHDL 269, 269 ZBT SSRAM with flow-through volatile memory 822 worst-case delay 368 outputs 831 VOLmax 102 wrapper 257 ZBT SSRAM with pipelined VOLmax, TTL 164 wrist strap, conductive 113 outputs 832 VOLmaxC 148 $write task, Verilog 329 zero-bus-turnaround (ZBT) VOLmaxT 148 writeable compact disc (CD-R) 81 SSRAM 831 Volpi, Mike xxiii write cycle 825 zero-code suppression 73 voltage, power-supply 365, 593, SDRAM 838 597, 775 write-enable (WE) input 822 Vulcan 184 write-pulse width 826 writing 344 W www.ddpp.com xx–xxiii wafer 11 www.DDPPonline.com xxi wait statement, VHDL 285 www.prenhall.com/wakerlyinfo xxii Wakerly, John F. xxiv, 1, 73, 74 Wakerly, Kate xxiv X Waser, Shlomo 73 waveform editor 240 XC9500 CPLD 471, 493 waveform viewer 337 Xilinx, Inc. xx, 508, 775, 789, 859 WE-controlled write 826 ISE (Integrated Software Environment) xx wedge ∧ 186 Xilinx ISE 272, 336, 337, 493, weight 26, 37, 46 502, 627, 727 of MSB 37 Xilinx University Program xxii weighted code 50 Xilinx XC4000 FPGAs 850–858 Weldon, E. J. Jr. 74 Xilinx XC9500 CPLDs 471, 493, when keyword, VHDL 258, 276 841–849 when statement, ABEL 248 Xilinx XST synthesis tool 418 while loop, VHDL 284 XNOR gate 233, 447, 463, 715, while statement, Verilog 325 719 White, E. B. 508 xnor gate, Verilog 306 widget, iterative 756 XOR function 234 widget, serial 756 ABEL 452 Widmer, Albert 74 Verilog 454–457 wimpy logic families 689 VHDL 452–454  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing by the publisher. 896 Index For exclusive use of adopters of the book Digital Design Principles and Practices, Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.