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Trabajo Fin De Carrera UNIVERSIDAD POLITÉCNICA DE MADRID FACULTAD DE INFORMÁTICA TRABAJO FIN DE CARRERA TRADUCTOR DE VHDL A SYSTEMC AUTOR: Grande Lobo, Eduardo TUTORES: Antonio García Dopico Mariano Hermida de la Rica A tod@s l@s que me habéis ayudado y animado a seguir adelante. Pero sobre todo, a mi madrina. ¡Tía Nieves, he cumplido! Traductor de VHDL a SystemC ÍNDICE CAPÍTULO I: INTRODUCCIÓN ............................................................................ 1 1 OBJETIVOS ................................................................................................................................................... 4 2 CONTENIDOS ............................................................................................................................................... 4 CAPÍTULO II: FUNDAMENTOS TEÓRICOS ....................................................... 7 1 EL LENGUAJE VHDL .................................................................................................................................. 7 2 EL LENGUAJE SYSTEMC ............................................................................................................................. 8 2.1 INTRODUCCIÓN ..................................................................................................................... 8 2.2 EL LENGUAJE C++ ................................................................................................................ 9 2.3 CARACTERÍSTICAS PROPIAS DE SYSTEMC ........................................................................ 9 3 COMPARACIÓN ENTRE AMBOS LENGUAJES ........................................................................................ 10 4 TRADUCTOR VS COMPILADOR ............................................................................................................... 11 CAPÍTULO III: ANÁLISIS ................................................................................. 15 1 ESTRUCTURA BÁSICA DE UN PROGRAMA SYSTEMC .......................................................................... 16 1.1 MÓDULOS ............................................................................................................................ 17 1.2 PROGRAMA PRINCIPAL ..................................................................................................... 21 2 SIMULACIÓN ............................................................................................................................................. 24 2.1 SIMULACIÓN EN VHDL .................................................................................................... 24 2.2 SIMULACIÓN EN SYSTEMC ............................................................................................... 25 2.3 KERNEL DE SYSTEMC ....................................................................................................... 26 3 REGLAS DE TRADUCCIÓN ....................................................................................................................... 27 3.1 UNIDADES DE DISEÑO Y BIBLIOTECAS .......................................................................... 27 3.1.1 ENTIDADES (ENTITY) Y ARQUITECTURAS (ARCHITECTURE) ................... 28 3.1.2 PAQUETES (PACKAGE Y PACKAGE BODY) .................................................... 37 3.1.3 CONFIGURACIONES (CONFIGURATION) ........................................................ 40 3.2 CLÁUSULAS DE CONTEXTO: LIBRARY Y USE ................................................................. 41 i Traductor de VHDL a SystemC 3.3 TIPOS DE DATOS ................................................................................................................ 42 3.3.1 PREDEFINIDOS .................................................................................................. 42 3.3.2 IEEE STANDARD 1164 ................................................................................... 43 3.3.3 DECLARACIÓN DE NUEVOS TIPOS DE DATOS ............................................... 43 3.3.3.1 ESCALARES .......................................................................................... 44 a) Enumerados .................................................................................. 44 b) Enteros ............................................................................................ 44 c) Reales ............................................................................................... 45 d) Físicos .............................................................................................. 45 3.3.3.2 COMPUESTOS ...................................................................................... 46 a) Matriciales ..................................................................................... 46 b) Registros ......................................................................................... 47 3.3.3.3 PUNTEROS ........................................................................................... 47 3.3.3.4 FICHEROS ............................................................................................. 47 3.3.4 DECLARACIÓN DE SUBTIPOS ........................................................................... 48 3.4 TIPOS DE OBJETOS ............................................................................................................ 49 3.4.1 CONSTANTES ..................................................................................................... 49 3.4.2 VARIABLES ......................................................................................................... 50 3.4.3 SEÑALES ............................................................................................................. 50 3.4.4 FICHEROS ........................................................................................................... 51 3.5 OTRAS DECLARACIONES .................................................................................................. 54 3.5.1 DECLARACIÓN DE SUBPROGRAMAS ............................................................... 54 3.5.1.1 DECLARACIÓN DE FUNCIONES ......................................................... 54 a) Especificación de la cabecera ................................................. 54 b) Definición de la implementación .......................................... 55 3.5.1.2 DECLARACIÓN DE PROCEDIMIENTOS .............................................. 55 a) Especificación de la cabecera ................................................. 56 b) Definición de la implementación .......................................... 56 3.5.2 ATRIBUTOS ........................................................................................................ 56 3.5.3 COMPONENTES .................................................................................................. 57 3.5.4 ALIAS .................................................................................................................. 57 3.6 SENTENCIAS SECUENCIALES ............................................................................................ 58 3.6.1 SENTENCIA WAIT ............................................................................................. 58 3.6.2 SENTENCIAS DE ASIGNACIÓN ......................................................................... 60 3.6.2.1 SENTENCIA DE ASIGNACIÓN DE VARIABLE .................................... 60 3.6.2.2 SENTENCIA DE ASIGNACIÓN DE SEÑAL .......................................... 61 a) Asignación básica (no retardada) ........................................ 61 b) Asignación de una forma de onda ........................................ 61 c) Asignación retardada dependiente de otras señales ... 64 3.6.3 SENTENCIAS CONDICIONALES ........................................................................ 66 3.6.3.1 SENTENCIA IF...................................................................................... 66 3.6.3.2 SENTENCIA CASE ................................................................................ 67 ii Traductor de VHDL a SystemC 3.6.4 BUCLES ............................................................................................................... 68 3.6.4.1 BUCLE INFINITO .................................................................................69 3.6.4.2 BUCLE WHILE .....................................................................................69 3.6.4.3 BUCLE FOR ..........................................................................................69 3.6.4.4 SENTENCIA NEXT ...............................................................................70 3.6.4.5 SENTENCIA EXIT .................................................................................71 3.6.5 SENTENCIA DE LLAMADA A SUBPROGRAMAS .............................................. 71 3.6.6 SENTENCIA RETURN......................................................................................... 72 3.6.7 SENTENCIA ASSERT .......................................................................................... 72 3.6.8 SENTENCIA REPORT ......................................................................................... 73 3.6.9 SENTENCIA NULL .............................................................................................. 74 3.7 SENTENCIAS CONCURRENTES ......................................................................................... 74 3.7.1 SENTENCIA PROCESS ........................................................................................ 74 3.7.2 SENTENCIA BLOCK ..........................................................................................
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