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Junction Capacitance Conduction in Semiconductors -Review • Intrinsic (undoped) Semiconductors 10 -3 – intrinsic carrier concentration ≡ ni = 1.45x10 cm , at room temp. – n = p = ni, in intrinsic (undoped) material •n ≡ number of electrons, p ≡ number of holes 2 – mass-action law, np = ni =1.45E10, applies to undoped and doped material • Extrinsic (doped) Semiconductors – dopants added to modify material/electrical properties n-type Donor p-type Acceptor + - P P + - B + + electron B hole group V free free ion group III ion element carrier element carrier •n-type (n+), add elements with extra an electron •p-type = p+, add elements with an extra hole -3 -3 –Nd ≡ conc. of donor atoms [cm ] –Na ≡ concentration of acceptor atoms [cm ] ≡ –nn = Nd, nn conc. of electrons in n-type material –pp = Na, pp ≡ conc. of holes in p-type material –p = n 2/N , using mass-action law, 2 n i d –np = ni /Na, using mass-action law, –pn ≡ conc. of holes in n-type material –np ≡ conc. of electrons in p-type material –always a lot more n than p in n-type material –always a lot more p than n in p-type material ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.1 1 Conduction in Semiconductors • doping provides free charge carriers, alters conductivity • conductivity, σ, in semic. w/ carrier densities n and p -19 – σ = q(μnn + μpp), q ≡ electron charge, q = 1.6x10 [Coulombs] 2 • μ≡mobility [cm /V-sec], μn ≅ 1360, μp ≅ 480 (typical values) • in n-type region, nn >> pn mobility = average velocity per – σ≈qμnnn unit electric field μn > μp • in p-type region, pp >> np electrons more mobile than holes – σ≈qμpnp ⇒conductivity of n+ > p+ •resistivity, ρ = 1/σ t • resistance of an n+ or p+ region –R = ρ l , A = wt w l A • drift current (flow of charge carriers in presence of an electric field, Ex) – n/p drift current density: Jxn = σn Ex = qμnnnEx, Jxp = σp Ex = qμpppEx –total drift current densityin x direction Jx = q(μnn + μpp) Ex = σ Ex ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.2 2 pn Junctions: Intro contact contact • What is a pn Junction? to p-side to n-side depletion region boundaries p+ n+ – interface of p-type and dielectric n “well” pn diode insulator n-type semiconductor junction (oxide) p-type Si wafer – junction of two materials forms a diode p-type n-type p-type + + + + - - - n-type • In the Beginning… - - - - + + + -+ -+ -+ -+ + + - - - - 3 - - – ionization of dopants + + + + 3 N acceptors/cm N donors/cm A D hole diffusion - at material interface hole current + donor ion and electron free carrier electron diffusion + electron current - acceptor ion and hole free carrier •Diffusion -movement of charge to regions of lower concentration electric field – free carriers diffuse out depletion region E – leave behind immobile ions p-type - + + n-type – region become depleted of - - + - + + free carriers - 3 - + 3 N acceptors/cm - N donors/cm – ions establish an electric field A - + + D x x immobile acceptor ions p n immobile donor ions • acts against diffusion (negative-charge) (positive-charge) W ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.3 3 pn Junctions: Equilibrium Conditions electric field E • Depletion Region depletion region p-type - + + n-type – area at pn interface - - + - + + void of free charges NA - ND 3 - + 3 N acceptors/cm - N donors/cm A - + + D –charge neutrality x x immobile acceptor ions p n immobile donor ions • must have equal charge on both sides (negative-charge) (positive-charge) W •q A xp NA = q A xn ND , A=junction area; xp, xn depth into p/n side • ⇒ xp NA = xn ND • depletion region will extend further into the more lightly doped side of the junction • Built-in Potential – diffusion of carriers leaves behind immobile charged ions – ions create an electric field which generates a built-in potential ⎛ N N ⎞ Ψ = V ln⎜ A D ⎟ 0 T ⎜ 2 ⎟ ⎝ ni ⎠ • where VT = kT/q = 26mV at room temperature ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.4 4 pn Junctions: Depletion Width electric field E •Depletion Width depletion region use Poisson’s equation & charge neutrality p-type - + + n-type - - + - + + –W = xp + xn NA - ND 3 - + 3 N acceptors/cm - N donors/cm 1 1 A - + + D 2 2 ⎡2ε()Ψ0 + VR N D ⎤ ⎡ 2ε()Ψ0 + VR N A ⎤ x x x = x = immobile acceptor ions p n immobile donor ions p ⎢ ⎥ n ⎢ ⎥ (negative-charge) (positive-charge) ⎣ qN A ()N D + N A ⎦ ⎣ qN D ()N D + N A ⎦ W ⎛ N N ⎞ • where VR is applied reverse bias Ψ = V ln⎜ A D ⎟ ε is the permittivity of Si 0 T ⎜ 2 ⎟ 1 ⎝ ni ⎠ ⎡2ε()Ψ + V N + N ⎤ 2 ε = 1.04x10-12 F/cm 0 R D A -14 W = ⎢ ⎥ ε = KSε0, where ε0 = 8.85x10 F/cm q N N ⎣ D A ⎦ and KS = 11.8 is the relative permittivity of silicon • One-sided Step Junction 1 ⎡ ⎤ 2 –if N>>N (p+n diode) 2ε()Ψ0 + VR A D W ≅ xn = ⎢ ⎥ • most of junction on n-side ⎣ qN D ⎦ 1 –if ND>>NA (n+p diode) 2 ⎡2ε()Ψ0 + VR ⎤ • most of junction on p-side W ≅ x p = ⎢ ⎥ ⎣ qN A ⎦ ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.5 5 pn Junctions - Depletion Capacitance • Free carriers are separated by the depletion layer • Separation of charge creates junction capacitance –Cj = εA/d ⇒ (d = depletion width, W) 1 ε is the permittivity of Si ⎡ qεN N ⎤ 2 ⎛ 1 ⎞ A D ⎜ ⎟ ε = 11.8 ε = 1.04x10-12 F/cm C j = A⎢ ⎥ 0 2()N + N ⎜ ⎟ V = applied reverse bias ⎣ A D ⎦ ⎝ Ψ0 + VR ⎠ R – A is complex to calculate in semiconductor diodes • consists of both bottom of the well and side-wall areas ⎛ ⎞ ⎜ ⎟ – Cj is a strong function of biasing 1 ⎜ C jo ⎟ ⎡ qεN N ⎤ 2 C j = ⎜ ⎟ A D C jo = A⎢ ⎥ • must be re-calculated if ⎜ VR ⎟ 2Ψ N + N ⎜ 1+ ⎟ ⎣ 0 ()A D ⎦ bias conditions change ⎝ Ψ0 ⎠ ⎛ ⎞ – CMOS doping is not linear/constant ⎜ ⎟ ⎜ C jo ⎟ C j = ⎜ ⎟ • graded junction approximation ⎜ VR ⎟ 3 1+ ⎜ Ψ ⎟ •Junction Breakdown ⎝ 0 ⎠ – if reverse bias is too high (typically > 30V) can get strong reverse current flow ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.6 6 Diode Biasing and Current Flow I + V - + V - D D D p n V V I I f D D D • Forward Bias; VD > Ψ0 – acts against built-in potential – depletion width reduced – diffusion currents increase with VD • minority carrier diffusion ⎛ 1 1 ⎞ VD VT I ∝ A⎜ + ⎟ I = I (e −1) S ⎜ N N ⎟ D S ⎝ D A ⎠ • Reverse Bias; VR = -VD > 0 – acts to support built-in potential –depletion width increased – electric field increased – small drift current flows • considered leakage • small until VR is too high and breakdown occurs ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.7 7 MOSFET Capacitor • MOSFETs move charge from drain to source underneath the gate, if a conductive channel exists under the gate • Understanding how and why the conductive channel is produced is important • MOSFET capacitor models the gate/oxide/substrate region G – source and drain are ignored S D gate G – substrate changes with applied gate voltage gate oxide • Consider an nMOS device channel = – Accumulation, VG < 0, (-)ve charge on gate Si substrate = bulk B • induces (+)ve charge in substrate B • (+)ve charge accumulate from substrate p+ –Depletion, V > 0 but small V < 0 V > 0 V >> 0 G G G G • creates depletion region in subst. + + + + + + + + + + + - - - - - - - + + + + + + + + + + + + + + + + + • (-) charge but no free carriers + + + + + + + - - - - - - - - - - - - depletion- - -layer - - - - depletion- - - layer - - –Inversion, VG > 0 but larger • further depletion requires high energy p-type Si substrate p-type Si substrate p-type Si substrate BB B • (-) charge pulled from Ground Accumulation Depletion Inversion • e- free carriers in channel ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.8 8 Capacitance in MOSFET Capacitor • In Accumulation – Gate capacitance = Oxide capacitance 2 –Cox = εox/tox [F/cm ] •In Depletion – Gate capacitance has 2 components –1) oxide capacitance Cox – 2) depletion capacitance of the substrate depletion region Cdep •Cdep= εsi/xd, xd = depth of depletion region into substrate – Cgate = Cox || Cdep = Cox Cdep / (Cox+Cdep) < Cox Cgate •In Inversion Cox – free carries at the surface –Cgate= Cox V accumulation inversion G depletion ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.9 9 Inversion Operation • MOSFET “off” unless in inversion – look more deeply at inversion operation • Define some stuff – Qs = total charge in substrate –VG = applied gate voltage – Vox = voltage drop across oxide – φs = potential at silicon/oxide interface (relative to substrate-ground) –Qs = -Cox VG –VG = Vox + φs • During Inversion (for nMOS) –VG > 0 applied to gate – Vox drops across oxide (assume linear) – φs drops across the silicon substrate, most near the surface ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.10 10 Surface Charge •QB = bulk charge, ion charge in depletion region under the gate recall from pn junction, 1 –QB = - q NA xd, xd = depletion depth ⎡2ε Ψ + V ⎤ 2 when ND>>NA ()0 R 1/2 W ≅ xn = ⎢ ⎥ –QB = - (2q εSi NA φs) = f(VG) ⎣ qN DA ⎦ – charge per unit area • Qe = charge due to free electrons at substrate surface •Qs = QB + Qe < 0 (negative charge for nMOS) depletion electron region QB, bulk layer, Qe charge ECE 410, Prof. F. Salem/Prof. A. Mason with updates Lecture Notes 6.11 11 Surface Charge vs. Gate Voltage • Surface Charge vs.
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