Intel® Xeon Phi™ Processor Datasheet - Volume 2 December 2016 Contents

Intel® Xeon Phi™ Processor

Datasheet - Volume 2 - Registers

December 2016

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2 Intel® Xeon Phi™ Processor Datasheet - Volume 2 December 2016 Contents

1 Registers Overview and Configuration Processor...... 19 1.1 Platform Configuration Structure ...... 19 1.1.1 Processor IIO Devices (CPUBUSNO (0))...... 19 1.1.2 Processor Uncore Devices (CPUBUSNO (1) & CPUBUSNO (2))...... 20 1.2 Configuration Registers Rules...... 22 1.2.1 CSR Access ...... 22 1.2.2 Memory-Mapped I/O Registers ...... 26 1.3 Terminology ...... 26 1.4 Register Terminology ...... 28 1.5 Notational Conventions ...... 30 2On Package IO (OPIO) Registers ...... 31 2.1 Bus: 2, Devices: 23, Function: 4 (CFG) ...... 31 2.1.1 VID_2_23_4_CFG...... 31 2.1.2 DID_2_23_4_CFG ...... 32 2.1.3 PCICMD_2_23_4_CFG...... 32 2.1.4 PCISTS_2_23_4_CFG...... 33 2.1.5 RID_2_23_4_CFG...... 33 2.1.6 CCR_2_23_4_CFG ...... 34 2.1.7 CLSR_2_23_4_CFG ...... 34 2.1.8 PLAT_2_23_4_CFG ...... 34 2.1.9 HDR_2_23_4_CFG...... 34 2.1.10 BIST_2_23_4_CFG ...... 35 2.1.11 CAPPTR_2_23_4_CFG ...... 35 2.1.12 INTL_2_23_4_CFG ...... 35 2.1.13 INTPIN_2_23_4_CFG ...... 35 2.1.14 MINGNT_2_23_4_CFG ...... 35 2.1.15 MAXLAT_2_23_4_CFG...... 36 2.2 Bus: 2, Device: 24, Function: 4 (CFG)...... 36 2.2.1 VID_2_24_4_CFG...... 36 2.2.2 DID_2_24_4_CFG ...... 37 2.2.3 PCICMD_2_24_4_CFG...... 37 2.2.4 PCISTS_2_24_4_CFG...... 37 2.2.5 RID_2_24_4_CFG...... 38 2.2.6 CCR_2_24_4_CFG ...... 38 2.2.7 CLSR_2_24_4_CFG ...... 38 2.2.8 PLAT_2_24_4_CFG ...... 39 2.2.9 HDR_2_24_4_CFG...... 39 2.2.10 BIST_2_24_4_CFG ...... 39 2.2.11 CAPPTR_2_24_4_CFG ...... 39 2.2.12 INTL_2_24_4_CFG ...... 39 2.2.13 INTPIN_2_24_4_CFG ...... 39 2.2.14 MINGNT_2_24_4_CFG ...... 40 3 Memory Controller (MC) Registers...... 41 3.1 Bus: 2, Device: 10, Function: 0 (CFG)...... 43 3.1.1 MAXLAT_2_10_0_CFG...... 43 3.1.2 PXPCAP_KDMI ...... 43 3.1.3 PXPENHCAP_KDMI...... 44 3.1.4 scrb0_cfg ...... 44 3.1.5 scrb1_cfg ...... 45 3.1.6 scrb2_cfg ...... 45 3.1.7 scrb3_cfg ...... 45

Intel® Xeon Phi™ Processor 3 Datasheet - Volume 2, December 2016 3.1.8 scrb4_cfg ...... 45 3.1.9 scrb5_cfg ...... 45 3.1.10 scrb6_cfg ...... 46 3.1.11 scrb7_cfg ...... 46 3.2 Bus: 2, Device: 10, Function: 1 (CFG) ...... 46 3.2.1 VID_2_10_1_CFG ...... 47 3.2.2 DID_2_10_1_CFG...... 47 3.2.3 PCICMD_2_10_1_CFG ...... 47 3.2.4 PCISTS_2_10_1_CFG ...... 48 3.2.5 RID_2_10_1_CFG ...... 49 3.2.6 CCR_2_10_1_CFG ...... 49 3.2.7 CLSR_2_10_1_CFG ...... 49 3.2.8 PLAT_2_10_1_CFG ...... 49 3.2.9 HDR_2_10_1_CFG ...... 49 3.2.10 BIST_2_10_1_CFG...... 50 3.2.11 SVID_MCXKDRWDBU_CFG...... 50 3.2.12 CAPPTR_2_10_1_CFG ...... 50 3.2.13 INTL_2_10_1_CFG...... 50 3.2.14 INTPIN_2_10_1_CFG ...... 50 3.2.15 MINGNT_2_10_1_CFG...... 51 3.2.16 MAXLAT_2_10_1_CFG ...... 51 3.2.17 PXPCAP_KDRWDBU...... 51 3.2.18 PXPENHCAP_KDRWDBU...... 51 3.2.19 devtag_cntl_0 ...... 52 3.2.20 devtag_cntl_1 ...... 52 3.2.21 devtag_cntl_2 ...... 53 3.2.22 mcmtr_cfg ...... 54 3.3 Bus: 2, Device: 10, Function: 2 (CFG) ...... 55 3.3.1 VID_2_10_2_CFG ...... 56 3.3.2 DID_2_10_2_CFG...... 56 3.3.3 PCICMD_2_10_2_CFG ...... 56 3.3.4 PCISTS_2_10_2_CFG ...... 56 3.3.5 RID_2_10_2_CFG ...... 57 3.3.6 CCR_2_10_2_CFG ...... 57 3.3.7 CLSR_2_10_2_CFG ...... 58 3.3.8 PLAT_2_10_2_CFG ...... 58 3.3.9 HDR_2_10_2_CFG ...... 58 3.3.10 BIST_2_10_2_CFG...... 58 3.3.11 SVID...... 59 3.3.12 SDID ...... 59 3.3.13 CAPPTR_2_10_2_CFG ...... 59 3.3.14 INTL_2_10_2_CFG...... 59 3.3.15 INTPIN_2_10_2_CFG ...... 59 3.3.16 MINGNT_2_10_2_CFG...... 59 3.3.17 MAXLAT_2_10_2_CFG ...... 60 3.3.18 visaaddr ...... 60 3.3.19 visadata ...... 60 3.4 Bus: 2, Device: 8, Function: 0 (CFG) ...... 60 3.4.1 VID_2_8_0_CFG...... 62 3.4.2 DID_2_8_0_CFG...... 62 3.4.3 PCICMD_2_8_0_CFG...... 62 3.4.4 PCISTS_2_8_0_CFG...... 63 3.4.5 RID_2_8_0_CFG...... 64 3.4.6 CCR_2_8_0_CFG ...... 64 3.4.7 CLSR_2_8_0_CFG...... 64 3.4.8 PLAT_2_8_0_CFG ...... 64

4 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3.4.9 HDR_2_8_0_CFG ...... 64 3.4.10 BIST_2_8_0_CFG...... 65 3.4.11 SVID_MCXKDMC_CFG...... 65 3.4.12 CAPPTR_2_8_0_CFG...... 65 3.4.13 INTL_2_8_0_CFG ...... 65 3.4.14 INTPIN_2_8_0_CFG...... 65 3.4.15 MINGNT_2_8_0_CFG ...... 66 3.4.16 MAXLAT_2_8_0_CFG ...... 66 3.4.17 PXPCAP_KDMC...... 66 3.4.18 mcdecs_chicken_bits_CFG...... 66 3.4.19 CREDIT_CONTROL_REG ...... 67 3.4.20 PXPENHCAP_KDMC...... 67 3.4.21 rsp_func_mcctrl_err_inj_CFG...... 67 3.4.22 ddr_trace_throttle_ctl_CFG...... 68 3.4.23 mcwdb_chkn_bit_CFG...... 68 3.4.24 rsp_func_crc_err_inj_dev0_xor_msk_CFG ...... 69 3.4.25 rsp_func_crc_err_inj_dev1_xor_msk_CFG ...... 69 3.4.26 rsp_func_crc_err_inj_extra_CFG ...... 69 3.4.27 dft_rdret_control_CFG ...... 70 3.4.28 demand_scrub_cfg ...... 71 3.4.29 x4modesel_CFG ...... 72 3.4.30 mc_tad0_limit_lo_CFG ...... 72 3.4.31 mc_tad0_offset_lo_CFG ...... 72 3.4.32 mc_tad0_limit_offset_hi_CFG ...... 72 3.4.33 mc_tad1_limit_lo_CFG ...... 73 3.4.34 mc_tad1_offset_lo_CFG ...... 73 3.4.35 mc_tad1_limit_offset_hi_CFG ...... 73 3.4.36 mc_tad2_limit_lo_CFG ...... 73 3.4.37 mc_tad2_offset_lo_CFG ...... 74 3.4.38 mc_tad2_limit_offset_hi_CFG ...... 74 3.4.39 mc_tad3_limit_lo_CFG ...... 74 3.4.40 mc_tad3_offset_lo_CFG ...... 74 3.4.41 mc_tad3_limit_offset_hi_CFG ...... 75 3.4.42 mc_tad4_limit_lo_CFG ...... 75 3.4.43 mc_tad4_offset_lo_CFG ...... 75 3.4.44 mc_tad4_limit_offset_hi_CFG ...... 75 3.4.45 mc_tad5_limit_lo_CFG ...... 75 3.4.46 mc_tad5_offset_lo_CFG ...... 76 3.4.47 mc_tad5_limit_offset_hi_CFG ...... 76 3.4.48 mc_tad6_limit_lo_CFG ...... 76 3.4.49 mc_tad6_offset_lo_CFG ...... 76 3.4.50 mc_tad6_limit_offset_hi_CFG ...... 77 3.4.51 mc_tad7_limit_lo_CFG ...... 77 3.4.52 mc_tad7_offset_lo_CFG ...... 77 3.4.53 mc_tad7_limit_offset_hi_CFG ...... 77 3.4.54 mc_tag_mask_lo_CFG ...... 78 3.4.55 mc_tag_mask_hi_CFG ...... 78 3.4.56 controller_throttle_reg ...... 78 3.4.57 errinj_addr_lo_reg ...... 78 3.4.58 errinj_addr_hi_reg ...... 78 3.4.59 errinj_mask_lo_reg ...... 79 3.4.60 errinj_mask_hi_reg ...... 79 3.4.61 errinj_lfsr_reg...... 79 3.4.62 errinj_limit_reg ...... 80 3.5 Bus: 2, Device: 8, Function: 1 (CFG) ...... 80 3.5.1 VID_2_8_1_CFG ...... 81

Intel® Xeon Phi™ Processor 5 Datasheet - Volume 2, December 2016 3.5.2 DID_2_8_1_CFG...... 81 3.5.3 PCICMD_2_8_1_CFG...... 82 3.5.4 PCISTS_2_8_1_CFG...... 82 3.5.5 RID_2_8_1_CFG...... 83 3.5.6 CCR_2_8_1_CFG ...... 83 3.5.7 CLSR_2_8_1_CFG...... 84 3.5.8 PLAT_2_8_1_CFG ...... 84 3.5.9 HDR_2_8_1_CFG...... 84 3.5.10 BIST_2_8_1_CFG ...... 84 3.5.11 SVID_MCXKDMISC_CFG ...... 84 3.5.12 CAPPTR_2_8_1_CFG ...... 84 3.5.13 INTL_2_8_1_CFG ...... 85 3.5.14 INTPIN_2_8_1_CFG ...... 85 3.5.15 MINGNT_2_8_1_CFG ...... 85 3.5.16 MAXLAT_2_8_1_CFG...... 85 3.5.17 PXPCAP_KDMISC ...... 85 3.5.18 PXPENHCAP_KDMISC ...... 86 3.5.19 mc_init_state_g ...... 86 3.5.20 rcomp_timer ...... 87 3.5.21 dly_pma_cmp_done_timer...... 87 3.5.22 mh_min_asrt_cntr_cfg ...... 87 3.5.23 mh_chn_astn_cfg ...... 88 4 Power Control Unit (PCU) Registers ...... 89 4.1 Bus: 1, Device: 30, Function: 0 (CFG) ...... 89 4.1.1 SMB_TSOD_POLL_RATE_CNTR_0...... 89 4.1.2 SMB_STAT_1 ...... 90 4.1.3 SMBCMD_1...... 90 4.1.4 SMBCNTL_1 ...... 91 4.1.5 SMB_TSOD_POLL_RATE_CNTR_1...... 92 4.1.6 SMB0_PERIOD_CFG ...... 92 4.1.7 SMB1_PERIOD_CFG ...... 93 4.1.8 SMB0_TLOW_TIMEOUT_CNTR ...... 93 4.1.9 SMB1_TLOW_TIMEOUT_CNTR ...... 93 4.1.10 SMB_PERIOD_CNTR...... 94 4.1.11 SMB0_TSOD_POLL_RATE...... 94 4.1.12 SMB1_TSOD_POLL_RATE...... 94 4.1.13 SMB0_TSOD_SAMPLE_0_3...... 94 4.1.14 SMB0_TSOD_SAMPLE_4_7...... 95 4.1.15 SMB1_TSOD_SAMPLE_0_3...... 96 4.1.16 SMB1_TSOD_SAMPLE_4_7...... 96 4.2 Bus: 1, Device: 30, Function: 1 (CFG) ...... 97 4.2.1 SSKPD_CFG ...... 97 4.2.2 C2C3TT_CFG...... 98 4.2.3 CSR_DESIRED_CORES_CFG ...... 98 4.2.4 CSR_DESIRED_CORES_CFG_1 ...... 98 4.3 Bus: 1, Device: 30, Function: 2 (CFG) ...... 99 4.3.1 VID_1_30_2_CFG ...... 99 4.3.2 DID_1_30_2_CFG...... 99 4.3.3 PCICMD_1_30_2_CFG ...... 100 4.3.4 PACKAGE_POWER_SKU_CFG...... 100 4.3.5 PACKAGE_RAPL_PERF_STATUS...... 101 4.3.6 PACKAGE_POWER_SKU_UNIT_CFG ...... 101 4.3.7 PACKAGE_ENERGY_STATUS_CFG ...... 102 4.3.8 PACKAGE_TEMPERATURE_CFG ...... 102 4.3.9 PP0_TEMPERATURE_CFG ...... 102 4.3.10 DRAM_RAPL_PERF_STATUS_CFG ...... 102

6 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 4.3.11 PACKAGE_THERM_MARGIN_CFG ...... 102 4.3.12 TEMPERATURE_TARGET_CFG ...... 103 4.4 Bus: 1, Device: 30, Function: 3 (CFG)...... 103 4.4.1 CAP_HDR_CFG...... 103 4.4.2 CAPID0_CFG ...... 104 4.4.3 CAPID1_CFG ...... 105 4.4.4 CAPID2_CFG ...... 105 4.4.5 CAPID3_CFG ...... 106 4.4.6 CAPID4_CFG ...... 106 4.4.7 CAPID5_CFG ...... 107 4.4.8 CAPID6_CFG ...... 107 4.4.9 CAPID7_CFG ...... 107 4.4.10 CAPID8_CFG ...... 107 5DMI Port Register...... 109 5.1 Configuration Registers ...... 109 5.1.1 VID: Vendor ID ...... 109 5.1.2 DID: Device ID ...... 109 5.1.3 PCICMD: PCI Command ...... 109 5.1.4 PCISTS: PCI Status ...... 111 5.1.5 RID: Revision ID ...... 113 5.1.6 CCR: Class Code Register ...... 113 5.1.7 CLSR: Cacheline Size Register...... 113 5.1.8 HDR: Header Type ...... 114 5.1.9 SVID: Subsystem Vendor ID...... 114 5.1.10 SDID: Subsystem Device ID ...... 114 5.1.11 CAPPTR: Capability Pointer ...... 114 5.1.12 INTL: Interrupt Line Register ...... 114 5.1.13 INTPIN: Interrupt Pin Register ...... 115 5.1.14 DMIRCBAR: DMIRCBAR ...... 115 5.1.15 MSICAPID: MSI Capability ID...... 116 5.1.16 MSINXTPTR: MSI Next Pointer ...... 116 5.1.17 MSIMSGCTL: MSI Control ...... 116 5.1.18 MSGADR: MSI Address...... 117 5.1.19 MSGDAT: MSI Data ...... 117 5.1.20 MSGMSK: MSI Mask Bit...... 117 5.1.21 MSIPENDING: MSI Pending Bit ...... 117 5.1.22 PXPCAPID: PCI Express Capability Identity ...... 118 5.1.23 PXPNXTPTR: PCI Express Next Pointer...... 118 5.1.24 PXPCAP: PCI Express Capability ...... 118 5.1.25 DEVCAP: PCI Express Device Capability...... 119 5.1.26 ROOTCON: PCI Express Root Control ...... 119 5.1.27 DEVCAP2: PCI Express Device Capability 2 ...... 121 5.1.28 LNKCAP2: PCI Express Link Capability 2 ...... 122 5.1.29 PMCAP: Power Management Capability ...... 122 5.1.30 PMCSR: Power Management Control and Status Register ...... 123 5.1.31 DEVCTRL: PCI Express Device Control...... 123 5.1.32 DEVSTS: PCI Express Device Status ...... 125 5.1.33 BDF:BAR# for Various MMIO BARs in IIO...... 125 5.1.34 Unimplemented Devices/Functions and Registers...... 126 5.1.35 PCI vs PCIe Device/Function ...... 126 6 PCIe Root Port Registers ...... 127 6.1 PCIe Root Port Configuration Registers ...... 127 6.1.1 VID: Vendor ID ...... 131 6.1.2 DID: Device ID ...... 131 6.1.3 PCICMD: PCI Command ...... 131

Intel® Xeon Phi™ Processor 7 Datasheet - Volume 2, December 2016 6.1.4 PCISTS: PCI Status...... 133 6.1.5 RID: RID ...... 134 6.1.6 CCR: Class Code Register ...... 135 6.1.7 CLSR: Cacheline Size Register ...... 135 6.1.8 HDR: Header Type ...... 135 6.1.9 PBUS: Primary Bus Number Register ...... 136 6.1.10 SECBUS: Secondary Bus Number...... 136 6.1.11 SUBBUS: Subordinate Bus Number Register ...... 136 6.1.12 IOBAS: I/O Base Register ...... 136 6.1.13 IOLIM: I/O Limit Register...... 137 6.1.14 SECSTS: Secondary Status Register ...... 137 6.1.15 MBAS: Memory Base ...... 138 6.1.16 MLIM: Memory Limit ...... 138 6.1.17 PBAS: Prefetchable Memory Base Register ...... 139 6.1.18 PLIM: Prefetchable Memory Limit ...... 139 6.1.19 PBASU: Prefetchable Memory Base (Upper 32 bits) ...... 139 6.1.20 PLIMU: Prefetchable Memory Limit (Upper 32 bits) ...... 140 6.1.21 CAPPTR: Capability Pointer...... 140 6.1.22 INTL: Interrupt Line Register...... 141 6.1.23 INTPIN: Interrupt Pin Register ...... 141 6.1.24 BCTRL: Bridge Control Register ...... 141 6.1.25 SCAPID: Subsystem Capability Identity ...... 143 6.1.26 SNXTPTR: Subsystem ID Next Pointer ...... 143 6.1.27 SVID: Subsystem Vendor ID ...... 143 6.1.28 SSID: Subsystem ID ...... 143 6.1.29 MSICAPID: MSI Capability ID ...... 143 6.1.30 MSINXTPTR: MSI Next Pointer ...... 144 6.1.31 MSIMSGCTL: MSI Control ...... 144 6.1.32 MSGADR: MSI Address ...... 145 6.1.33 MSGDAT: MSI Data...... 145 6.1.34 MSIMSK: MSI Mask Bit ...... 145 6.1.35 MSIPENDING: MSI Pending Bit ...... 145 6.1.36 PXPCAPID: PCI Express Capability Identity ...... 146 6.1.37 PXPNXTPTR: PCI Express Next Pointer ...... 146 6.1.38 PXPCAP: PCI Express Capability ...... 146 6.1.39 DEVCAP: PCI Express Device Capability ...... 146 6.1.40 DEVCTRL: PCI Express Device Control ...... 147 6.1.41 DEVSTS: PCI Express Device Status ...... 148 6.1.42 LNKCAP: PCI Express Link Capabilities...... 149 6.1.43 LNKCON: PCI Express Link Control ...... 151 6.1.44 LNKSTS: PCI Express Link Status...... 152 6.1.45 SLTCAP: PCI Express Slot Capabilities ...... 153 6.1.46 SLTCON: PCI Express Slot Control...... 154 6.1.47 SLTSTS: PCI Express Slot Status ...... 156 6.1.48 ROOTCON: PCI Express Root Control...... 157 6.1.49 ROOTCAP: PCI Express Root Capability ...... 158 6.1.50 ROOTSTS: PCI Express Root Capability ...... 158 6.1.51 DEVCAP2: PCI Express Device Capability 2...... 159 6.1.52 DEVCTRL2: PCI Express Device Control 2...... 160 6.1.53 LNKCAP2: PCI Express Link Capability 2...... 161 6.1.54 LNKCON2: PCI Express Link Control Register 2 ...... 161 6.1.55 LNKSTS2: PCI Express Link Status Register 2 ...... 162 6.1.56 PMCAP: Power Management Capability ...... 163 6.1.57 PMCSR: Power Management Control and Status Register...... 163 6.1.58 XPREUT_HDR_EXT: REUT PCIe Header Extended ...... 164 6.1.59 XPREUT_HDR_CAP: REUT Header Capability ...... 165

8 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.60 XPREUT_HDR_LEF: REUT Header Leaf Capability ...... 165 6.1.61 ACSCAPHDR: Access Control Services Extended Capability Header ...... 165 6.1.62 ACSCAP: Access Control Services Capability Register ...... 166 6.1.63 ACSCTRL: Access Control Services Control Register ...... 166 6.1.64 APICBASE: APIC Base Register...... 167 6.1.65 APICLIMIT: APIC Limit Register ...... 168 6.1.66 ERRCAPHDR: PCI Express Enhanced Capability Header...... 168 6.1.67 UNCERRSTS: Uncorrectable Error Status ...... 168 6.1.68 UNCERRMSK: Uncorrectable Error Mask ...... 169 6.1.69 UNCERRSEV: Uncorrectable Error Severity...... 169 6.1.70 CORERRSTS: Correctable Error Status...... 170 6.1.71 CORERRMSK: Correctable Error Mask...... 170 6.1.72 ERRCAP: Advanced Error Capabilities and Control Register...... 171 6.1.73 HDRLOG0: Header Log 0 ...... 171 6.1.74 HDRLOG1: Header Log 1 ...... 171 6.1.75 HDRLOG2: Header Log 2 ...... 171 6.1.76 HDRLOG3: Header Log 3 ...... 172 6.1.77 RPERRCMD: Root Port Error Command...... 172 6.1.78 RPERRSTS: Root Port Error Status ...... 172 6.1.79 ERRSID: Error Source Identification ...... 173 6.1.80 PERFCTRLSTS_0: Performance Control and Status ...... 173 6.1.81 PERFCTRLSTS_1: Performance Control and Status ...... 175 6.1.82 MISCCTRLSTS_0: Miscellaneous Control and Status ...... 175 6.1.83 MISCCTRLSTS_1: Miscellaneous Control and Status ...... 177 6.1.84 PCIE_BIF_CTRL: PCIe Bifurcation Control ...... 179 6.1.85 ERRINJCAP: PCI Express Error Injection Capability...... 179 6.1.86 ERRINJHDR: PCI Express Error Injection Capability Header ...... 179 6.1.87 ERRINJCON: PCI Express Error Injection Control Register ...... 180 6.1.88 CTOCTRL: Completion Timeout Control...... 181 6.1.89 XPCORERRSTS: XP Correctable Error Status...... 181 6.1.90 XPCORERRMSK: XP Correctable Error Mask...... 181 6.1.91 XPUNCERRSTS: XP Uncorrectable Error Status ...... 182 6.1.92 XPUNCERRMSK: XP Uncorrectable Error Mask ...... 182 6.1.93 XPUNCERRSEV: XP Uncorrectable Error Severity...... 183 6.1.94 XPUNCERRPTR: XP Uncorrectable Error Pointer...... 183 6.1.95 UNCEDMASK: Uncorrectable Error Detect Status Mask...... 183 6.1.96 COREDMASK: Correctable Error Detect Status Mask...... 184 6.1.97 RPEDMASK: Root Port Error Detect Status Mask ...... 184 6.1.98 XPUNCEDMASK: XP Uncorrectable Error Detect Mask ...... 185 6.1.99 XPCORERRDMSK: XP Correctable Detect Error Mask...... 185 6.1.100XPGLBERRSTS: XP Global Error Status ...... 185 6.1.101XPGLBERRPTR: XP Global Error Pointer ...... 186 6.1.102PXP2CAP: Secondary PCI Express Extended Capability Header...... 187 6.1.103LNKCON3: Link Control 3 Register ...... 187 6.1.104LNERRSTS: Lane Error Status Register (16 lanes)...... 188 6.1.105LN0EQ: Lane 0 Equalization Control ...... 188 6.1.106LN1EQ: Lane 1 Equalization Control ...... 190 6.1.107LN2EQ: Lane 2 Equalization Control ...... 191 6.1.108LN3EQ: Lane 3 Equalization Control ...... 192 6.1.109LN4EQ: Lane 4 Equalization Control ...... 193 6.1.110LN5EQ: Lane 5 Equalization Control ...... 194 6.1.111LN6EQ: Lane 6 Equalization Control ...... 195 6.1.112LN7EQ: Lane 7 Equalization Control ...... 196 6.1.113LN8EQ: Lane 8 Equalization Control ...... 197 6.1.114LN9EQ: Lane 9 Equalization Control ...... 198 6.1.115LN10EQ: Lane 10 Equalization Control...... 199

Intel® Xeon Phi™ Processor 9 Datasheet - Volume 2, December 2016 6.1.116LN11EQ: Lane 11 Equalization Control ...... 200 6.1.117LN12EQ: Lane 12 Equalization Control ...... 201 6.1.118LN13EQ: Lane 13 Equalization Control ...... 202 6.1.119LN14EQ: Lane 14 Equalization Control ...... 203 6.1.120LN15EQ: Lane 15 Equalization Control ...... 204 6.1.121LER_CAP: Live Error Recovery Capability ...... 205 6.1.122LER_HDR: Live Error Recovery Capability Header ...... 205 6.1.123LER_CTRLSTS: Live Error Recovery Control and Status ...... 205 6.1.124LER_UNCERRMSK: Live Error Recovery Uncorrectable Error Mask ...... 206 6.1.125LER_XPUNCERRMSK: Live Error Recovery XP Uncorrectable Error Mask ...... 207 6.1.126LER_RPERRMSK: Live Error Recovery Root Port Error Mask...... 207 6.1.127RPPIOERR_CAP: Enhanced RP Error Reporting Capability...... 207 6.1.128RPPIOERR_HDR: Enhanced RP Error Reporting Header...... 208 6.1.129RPPIOERR_HF: Enhanced RP Error Reporting Hard Fail...... 208 6.1.130RPPIOERR_STATUS: Enhanced RP Error Reporting Status...... 209 6.1.131RPPIOERR_MASK: Enhanced RP Error Reporting Mask...... 210 6.1.132RPPIOERR_HDRLOG0: Enhanced RP Error Log Header 0...... 210 6.1.133RPPIOERR_HDRLOG1: Enhanced RP Error Log Header 1...... 211 6.1.134RPPIOERR_HDRLOG2: Enhanced RP Error Log Header 2...... 211 6.1.135RPPIOERR_HDRLOG3: Enhanced RP Error Log Header 3...... 211 6.1.136XPPMDFXMAT0: XP PM DFx Match...... 212 6.1.137XPPMDFXMAT1: XP PM DFx Match...... 212 6.1.138XPPMDFXMSK0: XP PM DFx Mask...... 213 6.1.139XPPMDFXMSK1: XP PM DFx Mask...... 213 6.1.140MCAST_CAP_HDR: Multicast Capability ...... 214 6.1.141MCAST_CAP_EXT: Multicast Header...... 214 6.1.142MCAST_CAP: Multicast Capabilities...... 214 6.1.143MCAST_CTRL: Multicast Control ...... 215 6.1.144MCAST_BASE: Multicast Base Address ...... 215 6.1.145MCAST_OVERLAY_BAR: Multicast Overlay Base Address...... 215 6.1.146XPPMDL0: XP PM Data Low Bits ...... 216 6.1.147XPPMDL1: XP PM Data Low Bits ...... 216 6.1.148XPPMCL0: XP PM Compare Low Bits ...... 216 6.1.149XPPMCL1: XP PM Compare Low Bits ...... 216 6.1.150XPPMDH: XP PM Data High Bits...... 216 6.1.151XPPMCH: XP PM Compare High Bits...... 217 6.1.152XPPMR0: XP PM Response Control...... 217 6.1.153XPPMR1: XP PM Response Control...... 220 6.1.154XPPMEVL0: XP PM Events Low ...... 222 6.1.155XPPMEVL1: XP PM Events Low ...... 223 6.1.156XPPMEVH1: XP PM Events High...... 225 6.1.157XPPMER0: XP PM Resource Events ...... 226 6.1.158XPPMER1: XP PM Resource Events ...... 227 6.1.159PLSR0: Poison Logging/Status 0 ...... 227 6.1.160PLSR1: Poison Logging/Status 1 ...... 228 6.1.161PLSR2: Poison Logging/Status 2 ...... 228 7 Memory Map/Intel® Virtualization Technology for Directed I/O Registers ...... 229 7.1 Memory Map and Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)...... 229 7.2 Configuration Registers ...... 229 7.2.1 VID: Vendor ID ...... 231 7.2.2 DID: Device ID...... 231 7.2.3 PCICMD: PCI Command...... 232 7.2.4 PCISTS: PCI Status...... 232 7.2.5 RID: RID ...... 233 7.2.6 CCR: Class Code Register ...... 233

10 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.2.7 CLSR: Cacheline Size Register...... 233 7.2.8 HDR: Header Type ...... 233 7.2.9 SVID: Subsystem Vendor ID...... 234 7.2.10 SSID: Subsystem ID...... 234 7.2.11 CAPPTR: Capability Pointer ...... 234 7.2.12 INTL: Interrupt Line Register ...... 234 7.2.13 INTPIN: Interrupt Pin Register ...... 234 7.2.14 PXPCAPID: PCI Express Capability Identity ...... 235 7.2.15 PXPNXTPTR: PCI Express Next Pointer...... 235 7.2.16 PXPCAP: PCI Express Capability ...... 235 7.3 Intel VT-d VTBAR Memory Mapped Registers...... 236 7.3.1 VTD0_VERSION: Version Number ...... 237 7.3.2 VTD0_CAP: VT-d Capabilities ...... 238 7.3.3 VTD0_EXT_CAP: Extended VT-d Capability ...... 239 7.3.4 VTD0_GLBCMD: Global Command ...... 239 7.3.5 VTD0_GLBSTS: Global Status ...... 241 7.3.6 VTD0_ROOTENTRYADD: Root Entry Table Address...... 242 7.3.7 VTD0_CTXCMD: Context Command ...... 242 7.3.8 VTD0_FLTSTS: Fault Status ...... 243 7.3.9 VTD0_FLTEVTCTRL: Fault Event Control ...... 244 7.3.10 VTD0_FLTEVTDATA: Fault Event Data ...... 244 7.3.11 VTD0_FLTEVTADDR: Fault Event Lower Address ...... 244 7.3.12 VTD0_FLTEVTUPRADDR: Fault Event Upper Address ...... 245 7.3.13 VTD0_PMEN: Protected Memory Enable...... 245 7.3.14 VTD0_PROT_LOW_MEM_BASE: Protected Memory Low Base ...... 245 7.3.15 VTD0_PROT_LOW_MEM_LIMIT: Protected Memory Low Limit ...... 246 7.3.16 VTD0_PROT_HIGH_MEM_BASE: Protected Memory High Base ...... 246 7.3.17 VTD0_PROT_HIGH_MEM_LIMIT: Protected Memory High Limit...... 246 7.3.18 VTD0_INV_QUEUE_HEAD: Invalidation Queue Header Pointer ...... 247 7.3.19 VTD0_INV_QUEUE_TAIL: Invalidation Queue Tail Pointer...... 247 7.3.20 VTD0_INV_QUEUE_ADD: Invalidation Queue Address ...... 247 7.3.21 VTD0_INV_COMP_STATUS: Invalidation Completion Status...... 247 7.3.22 VTD0_INV_COMP_EVT_CTL: Invalidation Completion Event Control...... 248 7.3.23 VTD0_INV_COMP_EVT_DATA: Invalidation Completion Event Data...... 248 7.3.24 VTD0_INV_COMP_EVT_ADDR: Invalidation Completion Event Lower Address ...... 248 7.3.25 VTD0_INV_COMP_EVT_UPRADDR: Invalidation Completion Event Upper Address...... 249 7.3.26 VTD0_INTR_REMAP_TABLE_BASE: Interrupt Remapping Table Base Address ...... 249 7.3.27 VTD0_FLTREC0_GPA: Fault Record ...... 249 7.3.28 VTD0_FLTREC0_SRC: Fault Record ...... 249 7.3.29 VTD0_FLTREC1_GPA: Fault Record ...... 250 7.3.30 VTD0_FLTREC1_SRC: Fault Record ...... 250 7.3.31 VTD0_FLTREC2_GPA: Fault Record ...... 251 7.3.32 VTD0_FLTREC2_SRC: Fault Record ...... 251 7.3.33 VTD0_FLTREC3_GPA: Fault Record ...... 251 7.3.34 VTD0_FLTREC3_SRC: Fault Record ...... 252 7.3.35 VTD0_FLTREC4_GPA: Fault Record ...... 252 7.3.36 VTD0_FLTREC4_SRC: Fault Record ...... 252 7.3.37 VTD0_FLTREC5_GPA: Fault Record ...... 253 7.3.38 VTD0_FLTREC5_SRC: Fault Record ...... 253 7.3.39 VTD0_FLTREC6_GPA: Fault Record ...... 254 7.3.40 VTD0_FLTREC6_SRC: Fault Record ...... 254 7.3.41 VTD0_FLTREC7_GPA: Fault Record ...... 254 7.3.42 VTD0_FLTREC7_SRC: Fault Record ...... 255 7.3.43 VTD0_INVADDRREG: Invalidate Address ...... 255

Intel® Xeon Phi™ Processor 11 Datasheet - Volume 2, December 2016 7.3.44 VTD0_IOTLBINV: IOTLB Invalidate...... 256 7.3.45 VTD1_VERSION: Version Number ...... 256 7.3.46 VTD1_CAP: Intel VT-d Capabilities ...... 257 7.3.47 VTD1_EXT_CAP: Extended Intel VT-d Capability...... 258 7.3.48 VTD1_GLBCMD: Global Command...... 258 7.3.49 VTD1_GLBSTS: Global Status ...... 260 7.3.50 VTD1_ROOTENTRYADD: Root Entry Table Address ...... 261 7.3.51 VTD1_CTXCMD: Context Command...... 261 7.3.52 VTD1_FLTSTS: Fault Status ...... 262 7.3.53 VTD1_FLTEVTCTRL: Fault Event Control...... 263 7.3.54 VTD1_FLTEVTDATA: Fault Event Data...... 263 7.3.55 VTD1_FLTEVTADDR: Fault Event Lower Address ...... 263 7.3.56 VTD1_FLTEVTUPRADDR: Fault Event Upper Address ...... 264 7.3.57 VTD1_PMEN: Protected Memory Enable ...... 264 7.3.58 VTD1_PROT_LOW_MEM_BASE: Protected Memory Low Base ...... 264 7.3.59 VTD1_PROT_LOW_MEM_LIMIT: Protected Memory Low Limit...... 265 7.3.60 VTD1_PROT_HIGH_MEM_BASE: Protected Memory High Base...... 265 7.3.61 VTD1_PROT_HIGH_MEM_LIMIT: Protected Memory High Limit ...... 265 7.3.62 VTD1_INV_QUEUE_HEAD: Invalidation Queue Header Pointer...... 266 7.3.63 VTD1_INV_QUEUE_TAIL: Invalidation Queue Tail Pointer ...... 266 7.3.64 VTD1_INV_QUEUE_ADD: Invalidation Queue Address ...... 266 7.3.65 VTD1_INV_COMP_STATUS: Invalidation Completion Status ...... 266 7.3.66 VTD1_INV_COMP_EVT_CTL: Invalidation Completion Event Control ...... 267 7.3.67 VTD1_INV_COMP_EVT_DATA: Invalidation Completion Event Data ...... 267 7.3.68 VTD1_INV_COMP_EVT_ADDR: Invalidation Completion Event Lower Address 267 7.3.69 VTD1_INV_COMP_EVT_UPRADDR: Invalidation Completion Event Upper Address ...... 268 7.3.70 VTD1_INTR_REMAP_TABLE_BASE: Interrupt Remapping Table Base Address ...... 268 7.3.71 VTD1_FLTREC0_GPA: Fault Record...... 268 7.3.72 VTD1_FLTREC0_SRC: Fault Record ...... 269 7.3.73 VTD1_FLTREC1_GPA: Fault Record...... 269 7.3.74 VTD1_FLTREC1_SRC: Fault Record ...... 269 7.3.75 VTD1_FLTREC2_GPA: Fault Record...... 270 7.3.76 VTD1_FLTREC2_SRC: Fault Record ...... 270 7.3.77 VTD1_FLTREC3_GPA: Fault Record...... 271 7.3.78 VTD1_FLTREC3_SRC: Fault Record ...... 271 7.3.79 VTD1_FLTREC4_GPA: Fault Record...... 271 7.3.80 VTD1_FLTREC4_SRC: Fault Record ...... 272 7.3.81 VTD1_FLTREC5_GPA: Fault Record...... 272 7.3.82 VTD1_FLTREC5_SRC: Fault Record ...... 272 7.3.83 VTD1_FLTREC6_GPA: Fault Record...... 273 7.3.84 VTD1_FLTREC6_SRC: Fault Record ...... 273 7.3.85 VTD1_FLTREC7_GPA: Fault Record...... 274 7.3.86 VTD1_FLTREC7_SRC: Fault Record ...... 274 7.3.87 VTD1_INVADDRREG: Invalidate Address...... 274 7.3.88 VTD1_IOTLBINV: IOTLB Invalidate...... 275 8RAS Registers...... 277 8.1 RAS Configuration Registers...... 277 8.2 VID: Vendor ID ...... 279 8.3 DID: Device ID...... 280 8.3.1 PCICMD: PCI Command...... 280 8.3.2 PCISTS: PCI Status...... 281 8.3.3 RID: RID ...... 281 8.3.4 CCR: Class Code Register ...... 282 8.3.5 CLSR: Cacheline Size Register ...... 282

12 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 8.3.6 HDR: Header Type ...... 282 8.3.7 SVID: Subsystem Vendor ID...... 282 8.3.8 SDID: Subsystem Device ID ...... 282 8.3.9 CAPPTR: Capability Pointer ...... 283 8.3.10 INTL: Interrupt Line Register ...... 283 8.3.11 INTPIN: Interrupt Pin Register ...... 283 8.3.12 PXPCAPID: PCI Express Capability Identity ...... 283 8.3.13 PXPNXTPTR: PCI Express Next Pointer...... 283 8.3.14 PXPCAP: PCI Express Capability ...... 284 8.3.15 IRPPERRSV: IRP Protocol Error Severity ...... 284 8.3.16 IIOERRSV: IIO Core Error Severity ...... 285 8.3.17 MIERRSV: Miscellaneous Error Severity ...... 286 8.3.18 PCIERRSV: PCIe Error Severity Map...... 287 8.3.19 SYSMAP: System Error Event Map ...... 287 8.3.20 VPPCTL: VPP Control...... 287 8.3.21 VPPSTS: VPP Status ...... 288 8.3.22 VPPFREQ: VPP Frequency Control ...... 288 8.3.23 GCERRST: Global Correctable Error Status...... 289 8.3.24 GCFERRST: Global Correctable First Error Status ...... 290 8.3.25 GCNERRST: Global Correctable Next Error Status ...... 290 8.3.26 GNERRST: Global Non-Fatal Error Status ...... 290 8.3.27 GFERRST: Global Fatal Error Status ...... 291 8.3.28 GERRCTL: Global Error Control...... 292 8.3.29 GSYSST: Global System Event Status ...... 293 8.3.30 GSYSCTL: Global System Event Control...... 293 8.3.31 GFFERRST: Global Fatal First Error Status...... 294 8.3.32 GFNERRST: Global Fatal Next Error Status...... 294 8.3.33 GNFERRST: Global Non-Fatal First Error Status ...... 294 8.3.34 GNNERRST: Global Non-Fatal Next Error Status...... 294 8.3.35 IRPP0ERRST: IRP Protocol Error Status ...... 295 8.3.36 IRPP0ERRCTL: IRP Protocol Error Control...... 295 8.3.37 IRPP0FFERRST: IRP Protocol Fatal First Error Status...... 296 8.3.38 IRPP0FNERRST: IRP Protocol Fatal Next Error Status...... 297 8.3.39 IRPP0FFERRHD0: IRP Protocol Fatal FERR Header Log 0 ...... 298 8.3.40 IRPP0FFERRHD1: IRP Protocol Fatal FERR Header Log 1 ...... 298 8.3.41 IRPP0FFERRHD2: IRP Protocol Fatal FERR Header Log 2 ...... 298 8.3.42 IRPP0FFERRHD3: IRP Protocol Fatal FERR Header Log 3 ...... 298 8.3.43 IRPP0NFERRST: IRP Protocol Non-Fatal First Error Status ...... 298 8.3.44 IRPP0NNERRST: IRP Protocol Non-Fatal Next Error Status ...... 299 8.3.45 IRPP0NFERRHD0: IRP Protocol Non-Fatal FERR Header Log 0 ...... 300 8.3.46 IRPP0NFERRHD1: IRP Protocol Non-Fatal FERR Header Log 1 ...... 300 8.3.47 IRPP0NFERRHD2: IRP Protocol Non-Fatal FERR Header Log 2 ...... 300 8.3.48 IRPP0ERRCNTSEL: IRP Protocol Error Counter Select...... 301 8.3.49 IRPP0ERRCNT: IRP Protocol Error Counter ...... 301 8.3.50 IRPP1ERRST: IRP Protocol Error Status ...... 301 8.3.51 IRPP1ERRCTL: IRP Protocol Error Control...... 302 8.3.52 IRPP1FFERRST: IRP Protocol Fatal First Error Status...... 303 8.3.53 IRPP1FNERRST: IRP Protocol Fatal Next Error Status...... 303 8.3.54 IRPP1FFERRHD0: IRP Protocol Fatal FERR Header Log 0 ...... 304 8.3.55 IRPP1FFERRHD2: IRP Protocol Fatal FERR Header Log 2 ...... 304 8.3.56 IRPP1FFERRHD3: IRP Protocol Fatal FERR Header Log 3 ...... 305 8.3.57 IRPP1NFERRST: IRP Protocol Non-Fatal First Error Status ...... 305 8.3.58 IRPP1NNERRST: IRP Protocol Non-Fatal Next Error Status ...... 305 8.3.59 IRPP1NFERRHD0: IRP Protocol Non-Fatal FERR Header Log 0 ...... 306 8.3.60 IRPP1NFERRHD1: IRP Protocol Non-Fatal FERR Header Log 1 ...... 306 8.3.61 IRPP1NFERRHD2: IRP Protocol Non-Fatal FERR Header Log 2 ...... 307

Intel® Xeon Phi™ Processor 13 Datasheet - Volume 2, December 2016 8.3.62 IRPP1NFERRHD3: IRP Protocol Non-Fatal FERR Header Log 3...... 307 8.3.63 IRPP1ERRCNTSEL: IRP Protocol Error Counter Select ...... 307 8.3.64 IRPP1ERRCNT: IRP Protocol Error Counter...... 307 8.3.65 IIOERRST: IIO Core Error Status ...... 308 8.3.66 IIOERRCTL: IIO Core Error Control...... 308 8.3.67 IIOFFERRST: IIO Core Fatal First Error Status...... 309 8.3.68 IIOFFERRHD_0: IIO Core Fatal First Error Header ...... 309 8.3.69 IIOFFERRHD_1: IIO Core Fatal First Error Header ...... 309 8.3.70 IIOFFERRHD_2: IIO Core Fatal First Error Header ...... 309 8.3.71 IIOFFERRHD_3: IIO Core Fatal First Error Header ...... 310 8.3.72 IIOFNERRST: IIO Core Fatal Next Error Status...... 310 8.3.73 IIONFERRST: IIO Core Non-Fatal First Error Status ...... 310 8.3.74 IIONFERRHD_0: IIO Core Non-Fatal First Error Header ...... 310 8.3.75 IIONFERRHD_1: IIO Core Non-Fatal First Error Header ...... 311 8.3.76 IIONFERRHD_2: IIO Core Non-Fatal First Error Header ...... 311 8.3.77 IIONFERRHD_3: IIO Core Non-Fatal First Error Header ...... 311 8.3.78 IIONNERRST: IIO Core Non-Fatal Next Error Status...... 311 8.3.79 IIOERRCNTSEL: IIO Core Error Counter Selection...... 311 8.3.80 IIOERRCNT: IIO Core Error Counter ...... 312 8.3.81 MIERRST: Miscellaneous Core Error Status ...... 312 8.3.82 MIERRCTL: Miscellaneous Core Error Control ...... 313 8.3.83 MIFFERRST: Miscellaneous Core Fatal First Error Status ...... 313 8.3.84 MIFFERRHD_0: Miscellaneous Core Fatal First Error Header ...... 313 8.3.85 MIFFERRHD_1: Miscellaneous Core Fatal First Error Header ...... 313 8.3.86 MIFFERRHD_2: Miscellaneous Core Fatal First Error Header ...... 314 8.3.87 MIFFERRHD_3: Miscellaneous Core Fatal First Error Header ...... 314 8.3.88 MIFNERRST: Miscellaneous Core Fatal Next Error Status ...... 314 8.3.89 MINFERRST: Miscellaneous Core Non-Fatal First Error Status ...... 314 8.3.90 MINFERRHD_0: Miscellaneous Core Non-Fatal First Error Header...... 315 8.3.91 MINFERRHD_1: Miscellaneous Core Non-Fatal First Error Header...... 315 8.3.92 MINFERRHD_2: Miscellaneous Core Non-Fatal First Error Header...... 315 8.3.93 MINFERRHD_3: Miscellaneous Core Non-Fatal First Error Header...... 315 8.3.94 MINNERRST: Miscellaneous Core Non-Fatal Next Error Status ...... 316 8.3.95 MIERRCNTSEL: Miscellaneous Core Error Counter Selection ...... 316 8.3.96 MIERRCNT: Miscellaneous Core Error Counter...... 316 9 IOxAPIC...... 317 9.1 IOxAPIC Configuration Registers ...... 317 9.1.1 VID: Vendor ID ...... 318 9.1.2 DID: Device ID...... 318 9.1.3 PCICMD: PCI Command...... 318 9.1.4 PCISTS: PCI Status...... 319 9.1.5 RID: RID ...... 320 9.1.6 CCR: Class Code Register ...... 320 9.1.7 CLSR: Cacheline Size Register ...... 320 9.1.8 HDR: Header Type ...... 320 9.1.9 MBAR: Memory BAR for IOxAPIC...... 321 9.1.10 SVID: Subsystem Vendor ID ...... 321 9.1.11 SSID: Subsystem ID ...... 321 9.1.12 CAPPTR: Capability Pointer...... 321 9.1.13 INTL: Interrupt Line Register...... 322 9.1.14 INTPIN: Interrupt Pin Register ...... 322 9.1.15 ABAR: Memory BAR for IOxAPIC ...... 322 9.1.16 PXPCAP: PCI Express Capability ...... 323 9.1.17 IOAPICTETPC: IOxAPIC Table Entry Target Programmable Control...... 323 9.1.18 PMCAP: Power Management Capability ...... 324 9.1.19 PMCSR: Power Management Control and Status Register...... 324

14 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 9.1.20 IOADSELS0: IOxAPIC DSELS Register 0 ...... 325 9.1.21 IOINTSRC0: IO Interrupt Source Register 0 ...... 326 9.1.22 IOINTSRC1: IO Interrupt Source Register 1 ...... 326 9.1.23 IOREMINTCNT: Remote IO Interrupt Count...... 326 9.1.24 IOREMGPECNT: Remote IO GPE Count ...... 327 9.1.25 IOxAPIC MBAR/ABAR Memory Mapped Registers...... 327 9.1.26 INDX: Index ...... 328 9.2 WNDW: Window...... 328 9.2.1 EOI: EOI ...... 328 9.2.2 IOxAPIC Window Registers ...... 329 9.2.3 VER: Version ...... 329 9.2.4 ARBID: Arbitration ID ...... 330 9.2.5 BCFG: Boot Configuration...... 330 9.2.6 RTL0: Redirection Table Low DWORD ...... 331 9.2.7 RTH0: Redirection Table High DWORD...... 332 9.2.8 RTL1: Redirection Table Low DWORD ...... 332 9.2.9 RTH1: Redirection Table High DWORD...... 334 9.2.10 RTH2: Redirection Table High DWORD...... 335 9.2.11 RTL3: Redirection Table Low DWORD ...... 336 9.2.12 RTH3: Redirection Table High DWORD...... 337 9.2.13 RTL4: Redirection Table Low DWORD ...... 338 9.2.14 RTH4: Redirection Table High DWORD...... 339 9.2.15 RTL5: Redirection Table Low DWORD ...... 339 9.2.16 RTH5: Redirection Table High DWORD...... 341 9.2.17 RTL6: Redirection Table Low DWORD ...... 341 9.2.18 RTH6: Redirection Table High DWORD...... 343 9.2.19 RTL7: Redirection Table Low DWORD ...... 343 9.2.20 RTH7: Redirection Table High DWORD...... 345 9.2.21 RTL8: Redirection Table Low DWORD ...... 345 9.2.22 RTH8: Redirection Table High DWORD...... 347 9.2.23 RTL9: Redirection Table Low DWORD ...... 347 9.2.24 RTH9: Redirection Table High DWORD...... 349 9.2.25 RTL10: Redirection Table Low DWORD ...... 349 9.2.26 RTH10: Redirection Table High DWORD...... 351 9.2.27 RTL11: Redirection Table Low DWORD ...... 351 9.2.28 RTH11: Redirection Table High DWORD...... 353 9.2.29 RTL12: Redirection Table Low DWORD ...... 353 9.2.30 RTH12: Redirection Table High DWORD...... 355 9.2.31 RTL13: Redirection Table Low DWORD ...... 355 9.2.32 RTH13: Redirection Table High DWORD...... 357 9.2.33 RTL14: Redirection Table Low DWORD ...... 357 9.2.34 RTH14: Redirection Table High DWORD...... 359 9.2.35 RTL15: Redirection Table Low DWORD ...... 359 9.2.36 RTH15: Redirection Table High DWORD...... 361 9.2.37 RTL16: Redirection Table Low DWORD ...... 361 9.2.38 RTH16: Redirection Table High DWORD...... 363 9.2.39 RTL17: Redirection Table Low DWORD ...... 363 9.2.40 RTH17: Redirection Table High DWORD...... 365 9.2.41 RTL18: Redirection Table Low DWORD ...... 365 9.2.42 RTH18: Redirection Table High DWORD...... 367 9.2.43 RTL19: Redirection Table Low DWORD ...... 367 9.2.44 RTH19: Redirection Table High DWORD...... 369 9.2.45 RTL20: Redirection Table Low DWORD ...... 369 9.2.46 RTH20: Redirection Table High DWORD...... 371 9.2.47 RTL21: Redirection Table Low DWORD ...... 371 9.2.48 RTH21: Redirection Table High DWORD...... 373

Intel® Xeon Phi™ Processor 15 Datasheet - Volume 2, December 2016 9.2.49 RTL22: Redirection Table Low DWORD...... 373 9.2.50 RTH22: Redirection Table High DWORD ...... 375 9.2.51 RTL23: Redirection Table Low DWORD...... 375 9.2.52 RTH23:Redirection Table High DWORD ...... 377 Figures

1-1 Processor Integrated I/O Device Map...... 19 1-2 Processor Uncore Devices Map...... 21 6-1 PCIe Root Port Configuration Register Map Offset 0x00 – 0x1FF ...... 128 6-2 PCIe Root Port Configuration Register Map Offset 0x200 – 0x3FF ...... 129 6-3 PCIe Root Port Configuration Register Map Offset 0x400 - 0x4FF...... 130 7-1 Memory Map and Intel VT-d Configuration Register Map Offset 0x00 - 0x1FF ...... 230 7-2 Memory Map and Intel VT-d Register Map Offset 0x200 - 0x3FF ...... 231 7-3 Intel VT-d Memory Register Map Offset 0x00 - 0x20B ...... 236 7-4 Intel VT-d Memory Register Map Offset 0x1000 - 0x120B...... 237 8-1 RAS Configuration Register Map Offset 0x00 - 0x1FF ...... 278 8-2 RAS Configuration Register Map Offset 0x200 - 0x3FF ...... 279 9-1 IOxAPIC Configuration Register Map Offset 0x00 - 0x2FF ...... 317 9-2 IOxAPIC MMIO Register Map Offset 0x00 - 0x4F ...... 327 9-3 IOxAPIC MMIO Register Map Offset 0x00 - 0x4F ...... 329

Tables

1-1 Functions Specifically Handled by the Processor ...... 23 1-2 Glossary ...... 26 1-3 Register Attribute Definitions...... 28 2-1 Summary of Bus: 2, Device: 23, Function: 4 (CFG) ...... 31 2-2 Summary of Bus: 2, Device: 24, Function: 4 (CFG) ...... 36 3-1 MC0 Register ID/Name Mapping ...... 41 3-2 Physical to Logical Memory channel mapping ...... 43 3-3 Summary of Bus: 2, Device: 10, Function: 0 (CFG) ...... 43 3-4 Summary of Bus: 2, Device: 10, Function: 1 (CFG) ...... 46 3-5 Summary of Bus: 2, Device: 10, Function: 2 (CFG) ...... 55 3-6 Summary of Bus: 2, Device: 8, Function: 0 (CFG) ...... 60 3-7 Summary of Bus: 2, Device: 8, Function: 1 (CFG) ...... 81 4-1 Summary of Bus: 1, Device: 30, Function: 0 (CFG) ...... 89 4-2 Summary of Bus: 1, Device: 30, Function: 1 (CFG) ...... 97 4-3 Summary of Bus: 1, Device: 30, Function: 2 (CFG) ...... 99 4-4 Summary of Bus: 1, Device: 30, Function: 3 (CFG) ...... 103 5-1 BDF BAR# for Various MMIO BARs in IIO ...... 125

16 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Revision History

Document Revision Description Date Number Number

335265 001 • Initial Release December 2016

Intel® Xeon Phi™ Processor 17 Datasheet - Volume 2, December 2016 18 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 1 Registers Overview and Configuration Processor

The Intel® Xeon Phi™ processor (also referred to as “the processor”) in this Datasheet Volume 2 document contains one or more PCI devices within each functional block. The configuration registers for these devices are mapped as devices residing on the PCIBus assigned to the processor socket. CSRs are the basic hardware elements that configure the uncore logic to support various system topologies, memory configuration and densities, and hardware hooks required for RAS operations. Refer to the Intel® Xeon® Processor E5 v3 Product Families Uncore Performance Monitoring Reference Manual for details on Performance Monitoring registers.

Note: Some Default values will vary based on processor type and SKU, and in most cases these are the read only register fields which provide processor support visibility to firmware. Firmware should not rely on these Default values provided in this document, and instead verify these values by reading them with firmware.

1.1 Platform Configuration Structure

The DMI2 physically connects the processor and the PCH. From a configuration stand point the DMI2 is a logical extension of PCI Bus 0. DMI2 and the internal devices in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0.

1.1.1 Processor IIO Devices (CPUBUSNO (0))

The processor IIO contains multiple PCI devices within a single, physical component. The configuration registers for the devices are mapped as devices residing on PCI Bus “CPUBUSNO(0)” where CPUBUSNO(0) is programmable by BIOS.

Figure 1-1. Processor Integrated I/O Device Map

Intel® Xeon Phi™ Processor 19 Datasheet - Volume 2, December 2016 • Device 0: DMI2 Root Port. Logically this appears as a PCI device residing on PCI Bus 0. Device 0 contains the standard PCI header registers, extended PCI configuration registers and DMI2 device specific configuration registers.

PCI Express* Root Port 1a. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express* Specification Revision 3.0. Device 0 contains the standard PCI Express*/PCI configuration registers including PCI Express* Memory Address Mapping registers. It also contains the extended PCI Express* configuration space that include PCI Express* Link status/ control registers and Virtual Channel controls. • Device 1: PCI Express* Root Port 3a, 3b, 3c and 3d. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express* Specification Revision 3.0. Device 1 contains the standard PCI Express*/ PCI configuration registers including PCI Express* Memory Address Mapping registers. It also contains the extended PCI Express* configuration space that include PCI Express* Link status/control registers and Virtual Channel controls. • Device 2: PCI Express* Root Port 2a, 2b, 2c and 2d. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express* Specification Revision 3.0. Device 2 contains the standard PCI Express*/ PCI configuration registers including PCI Express* Memory Address Mapping registers. It also contains the extended PCI Express* configuration space that include PCI Express* error status/control registers and Virtual Channel controls. • Device 5: Integrated I/O Core. This device contains the Standard PCI registers for each of its functions. This device implements three functions; Function 0 contains Memory Mapping, Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) related registers and other system management registers. Function 2 contains I/O RAS registers, Function 4 contains IOAPIC registers.

1.1.2 Processor Uncore Devices (CPUBUSNO (1) & CPUBUSNO (2))

The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number.

20 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Figure 1-2. Processor Uncore Devices Map

• Bus 1, Device 8 - 12: Processor Caching Agent. Device 8 - 11, Functions 0 - 7; Device 12, Functions 0 - 5 contain the CHA Unicast miscellaneous configuration registers. • Bus 1, Device 14 - 18: Processor Caching Agent. Device 14 - 17, Functions 0 - 7; Device 18, Functions 0 - 5 contain the CHA Unicast SAD configuration registers. • Bus 1, Device 20 - 24: Mesh Interconnect. Device 20 - 23, Functions 0 - 7; Device 24, Functions 0 - 5 contain the mesh configuration registers. • Bus 1, Device 29: Processor Caching Agent. Device 29, Functions 0 - 3 contain the CHA Broadcast configuration registers. • Bus 1, Device 30: Processor Power Control Unit. Device 30, Functions 0 - 4 contain the configurable PCU registers. • Bus 2, Device 8 - 11: Memory Controller. Device 8 - 9, Functions 0 - 1; Device 10 - 11, Functions 0 - 2 contain the Memory Controller registers. • Bus 2, Device 8, 9: Memory Controller. Device 8, Functions 2- 4 contain the Memory Controller Channel 0 - 2 registers. Device 9, Functions 2 - 4 contain the Memory Controller Channel 3 - 5 registers. • Bus 2, Device 12: M2PCIE. Device 12, Functions 0 - 1 contain configuration registers for the interface between IIO & the mesh. • Bus 2, Device 12: Mesh Interconnect. Device 12, Function 2 contains the mesh configuration registers. • Bus 2, Device 12: Embedded DRAM Controller (On Package Memory Controller). Device 12, Functions 5 - 6 contain EDC configuration registers. • Bus 2, Device 13: Mesh Interconnect. Device 13, Functions 1, 3 contain the mesh configuration registers.

Intel® Xeon Phi™ Processor 21 Datasheet - Volume 2, December 2016 • Bus 2, Device 14: Mesh Interconnect. Device 14, Functions 1, 3, 5 contain the mesh configuration registers. • Bus 2, Device 15 - 31: Embedded DRAM Controller (On Package Memory Controller). Device 15 - 31, Functions 0 - 2 contain EDC configuration registers. • Bus 2, Device 16 - 17: DDR Physical Layer (DDRIO). Device 16 - 17, Functions - 7 contain DDR Channel 0 - 2 Unicast registers. • Bus 2, Device 18 - 19: DDR Physical Layer (DDRIO). Device 18 - 19, Functions 5 7 contain DDR Channel 3- 5 Unicast registers. • Bus 2, Device 20: DDR Physical Layer (DDRIO). Device 20, Functions 6 - 7 contain DDR Multicast registers. • Bus 2, Device 21: DDR Physical Layer (DDRIO). Device 21, Functions 6 - 7 contain DDR Multicast registers. • Bus 2, Device 23 - 31: OPIO (On Package IO) interface. Device 23 - 31, Function 4 contains OPIO configuration registers. • Bus 2, Device 23 - 31: MCDRAM. Device 23 - 31, Function 6 contains MCDRAM configuration registers.

1.2 Configuration Registers Rules

The processor supports the following configuration register types: • PCI Configuration Registers (CSRs): CSRs are chipset specific registers that are located at PCI defined address space. • Memory-mapped I/O registers: These registers are mapped into the system memory map as MMIO low or MMIO high. They are accessed by any code, typically an OS driver running on the platform. This register space is introduced with the integration of some of the chipset functionality. These MMIO registers are located in the IIO module for the PCIe* segments. • Machine Specific Registers (MSRs) are architectural, located in the core and only accessed by using specific ReadMSR/WriteMSR instructions.

1.2.1 CSR Access

Configuration space registers are accessed via the well known configuration transaction mechanism defined in the PCI specification and uses the “Bus: Device: Function:” number concept to address a specific device's configuration space.

Configuration register accesses can come from various sources: •Local cores •PECI or JTAG

Configuration registers can be read or written in Byte, WORD (16-bit), or DWORD (32- bit) quantities. Accesses larger than a DWORD to PCI Express* configuration space will result in unexpected behavior. All multi-byte numeric fields use “little-endian” ordering (lower addresses contain the least significant parts of the field).

22 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 1.2.1.1 Device Mapping

Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number, Device Number and Function Number. Device configuration is based on the PCI Type 0 configuration conventions.

Table 1-1. Functions Specifically Handled by the Processor (Sheet 1 of 3)

Logic Device ID Bus Device Func Description DMI 7801h-7807h 0 0 0 x4 Link from Processor to PCH

PCI Express* Root Port 1a 7808h 0 0 2 x4 max link width

PCI Express* Root Port 2 780Ah-780Dh 0 2 0-3 x16, x8 or x4 max link width

PCI Express* Root Port 3 780Ah-780Dh 0 1 0-3 x16, x8 or x4 max link width

IIO 7810h 0 5 0 MemoryMap, VT-d & Misc

IIO 7812h 0 5 2 RAS

IIO 7813h 0 5 4 I/O APIC

IIO 7814h 0 5 6 Perf Mon

Uncore 7815h 0 6 1 IIO Debug

Uncore 7815h 0 6 2 IIO Debug

Uncore 7815h 0 6 3 IIO Debug

Uncore 7815h 0 6 4 IIO Debug

Uncore 7815h 0 6 5 IIO Debug

Uncore 7815h 0 6 6 IIO Debug

Uncore 7815h 0 7 1 IIO Debug

Uncore 7815h 0 7 2 IIO Debug

Uncore 7815h 0 7 3 IIO Debug

Uncore 781Ah 0 8 0 Ubox (Non-coherent unit) - Scratchpad and Semaphores

Uncore 781Bh 0 8 1 Ubox (Non-coherent unit) - Scratchpad and Semaphores

Uncore 781Ch 0 8 2 Ubox (Non-coherent unit) - Scratchpad and Semaphores

CHA (Unicast) 782Fh 1 8-11 0-7 CHA Unicast Miscellaneous Configuration Registers

CHA (Unicast) 782Fh 1 12 0-5 CHA Unicast Miscellaneous Configuration Registers

CHA (Unicast) 782Ch 1 14-17 0-7 CHA Unicast System Address Decoder Registers

CHA (Unicast) 782Ch 1 18 0-5 CHA Unicast System Address Decder Registers

CMS (Common Mesh Stop) 781Fh 1 20-23 0-7 Mesh Configuration Registers

CMS 781Fh 1 24 0-5 Mesh Configuration Registers

CHA (Broadcast) 782Ah 1 29 0 CHA Broadcast Configuration Registers

CHA (Broadcast) 782Bh 1 29 1 CHA Broadcast Configuration Registers

CHA (Broadcast) 782Eh 1 29 2 CHA Broadcast Configuration Registers

Intel® Xeon Phi™ Processor 23 Datasheet - Volume 2, December 2016 Table 1-1. Functions Specifically Handled by the Processor (Sheet 2 of 3)

Logic Device ID Bus Device Func Description CHA (Broadcast) 782Dh 1 29 3 CHA Broadcast Configuration Registers

Power Management & 7820h 1 30 0 Power Control Unit Control

Power Management & 7821h 1 30 1 Power Control Unit Control

Power Management & 7822h 1 30 2 Power Control Unit Control

Power Management & 7823h 1 30 3 Power Control Unit Control

Power Management & 7824h 1 30 4 Power Control Unit Control

Memory Controller 0 7840h 2 8 0 Memory Controller 0 Registers

Memory Controller 0 7842h 2 8 1 Memory Controller 0 Registers

Memory Controller 0 7843h 2 8 2-4 Memory Controller 0 Channel 0-2 Registers

Memory Controller 1 7840h 2 9 0 Memory Controller 1 Registers

Memory Controller 1 7842h 2 9 1 Memory Controller 1 Registers

Memory Controller 1 7843h 2 9 2-4 Memory Controller 1 Channel 3-5 Registers

Memory Controller 0/1 7841h 2 10/11 0 Memory Controller 0/1 Registers

Memory Controller 0/1 7844h 2 10/11 1 Memory Controller 0/1 Registers

Memory Controller 0/1 781Fh 2 10/11 2 Memory Controller 0/1 Registers

CMS 7816h 2 12 0 Configuration Registers for the interface between IIO & mesh

CMS 7817h 2 12 1 Configuration Registers for the interface between IIO & mesh

CMS 781Fh 2 12 2 Mesh Configuration Registers

On Package Memory 7832h 2 12 5 Embedded DRAM Controller (EDC) Controller Configuration Registers

On Package Memory 7838h 2 12 6 Embedded DRAM Controller (EDC) Controller Configuration Registers

CMS 781Fh 2 13-14 1,3 Mesh Configuration Registers

CMS 781Fh 2 14 5 Mesh Configuration Registers

On Package Memory 7833h 2 15-22 0 Embedded DRAM Controller (EDC) Controller Configuration Registers

On Package Memory 7839h 2 15-22 1 Embedded DRAM Controller (EDC) Controller Configuration Registers

On Package Memory 781Fh 2 15-22 2 Embedded DRAM Controller (EDC) Controller Configuration Registers

DDR Physical Layer (DDRIO 7848h 2 16 5-7 DDR Channel 0-2 Unicast Registers Unicast)

DDR Physical Layer (DDRIO 7849h 2 17 5-7 DDR Channel 0-2 Unicast Registers Unicast)

DDR Physical Layer (DDRIO 7848h 2 18 5-7 DDR Channel 3-5 Unicast Registers Unicast)

24 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Table 1-1. Functions Specifically Handled by the Processor (Sheet 3 of 3)

Logic Device ID Bus Device Func Description DDR Physical Layer (DDRIO 7849h 2 19 5-7 DDR Channel 3-5 Unicast Registers Unicast)

DDR Physical Layer (DDRIO 7845h 2 20 6 DDR Multicast Registers Multicast)

DDR Physical Layer (DDRIO 7846h 2 20 7 DDR Multicast Registers Multicast)

DDR Physical Layer (DDRIO 7845h 2 21 6 DDR Multicast Registers Multicast)

DDR Physical Layer (DDRIO 7847h 2 21 7 DDR Multicast Registers Multicast)

On Package Memory 7830h 2 23 0 Embedded DRAM Controller (EDC) Controller Configuration Registers

On Package Memory 7836h 2 23 1 Embedded DRAM Controller (EDC) Controller Configuration Registers

On Package Memory 7834h 2 23 2 Embedded DRAM Controller (EDC) Controller Configuration Registers

On-Package IO 783Ah 2 23 4 OPIO Configuration Registers

Multi-Channel DRAM 784Ah 2 23 6 MCDRAM Configuration Registers

On Package Memory 7831h 2 24-31 0 Embedded DRAM Controller (EDC) Controller Configuration Registers

On Package Memory 7837h 2 24-31 1 Embedded DRAM Controller (EDC) Controller Configuration Registers

On Package Memory 7835h 2 24-31 2 Embedded DRAM Controller (EDC) Controller Configuration Registers

On-Package IO 783Bh 2 24-31 4 OPIO Configuration Registers

Multi-Channel DRAM 784Bh 2 24-31 6 MCDRAM Configuration Registers

1.2.1.2 Unimplemented Devices/Functions and Registers

Configuration reads to unimplemented functions and devices will return all ones emulating a master abort response. Note that there is no asynchronous error reporting that happens when a configuration read master aborts. Configuration writes to unimplemented functions and devices will return a normal response.

Software should not attempt or rely on reads or writes to unimplemented registers or register bits. Unimplemented registers should return all zeroes when read. Writes to unimplemented registers are ignored. For configuration writes to these register (require a completion), the completion is returned with a normal completion status (Not master- aborted).

1.2.1.3 Device Hiding

The processor provides a mechanism by which various PCI devices or functions within the unit can be hidden from the host configuration software. This mechanism is needed in cases where a device or function is not used or is not available for use, because it is not serving any meaningful purpose in a given platform configuration.

This mechanism is implemented via the DEVHIDE register:

Intel® Xeon Phi™ Processor 25 Datasheet - Volume 2, December 2016 • Devices that are hidden from host configuration space via the DEVHIDE register are not hidden from the configuration space as seen from the JTAG/SMBus port of an IIO. All PCI devices are always visible via JTAG/SMBus. • Devices that are not used in a given platform configuration can be hidden from host configuration space by BIOS appropriately programming the DEVHIDE register. • The only change DEVHIDE register makes is to abort Type0 configuration accesses to the device space itself.

1.2.2 Memory-Mapped I/O Registers

The PCI standard provides configuration space registers as well as registers which reside in memory-mapped space. For PCI devices, this is typically where the majority of the driver programming occurs and the specific register definitions and characteristics are provided by the device manufacturer. Access to these registers are typically accomplished via CPU reads and writes to non-coherent (UC) or write- combining (WC) space. Reads and writes to memory-mapped registers can be accomplished with 1, 2, 4 or 8 byte transactions.

1.3 Terminology

The table below contains important terms used in this specification. For ease-of-use, numeric entries are listed first, with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.

Table 1-2. Glossary (Sheet 1 of 3)

Word/ Definition Acronym

# A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level.

ASPM Active State Power Management

BMC Baseboard Management Controller

CHA The functional module that includes the CA (Caching Agent) and HA (Home Agent).

CMP Core Multi-Processing refers to a single physical package that utilizes multiple cores for multi-processing capabilities.

CPU-Only Any assertion of the CPU RESET# input signal that does not also assert the PCI RESET signal. Reset The PWRGOOD# signal is not toggled. This capability is not supported by Knights Landing processors.

CSR Control and Status Registers

DDR3 Third generation Double Data Rate synchronous dynamic random access memory (SDRAM) technology.

DDR4 Fourth generation Double Data Rate synchronous dynamic random access memory (SDRAM) technology.

DIMM Dual-in-Line Memory Module. A packaging arrangement of memory devices on a socketable substrate.

DMA Direct Memory Access

DP Dual processors

DRAM Page The DRAM cells selected by the Row Address. (Row)

DSB Data Stream Buffer. Part of the processor core architecture.

TLB Translation Look-Aside Buffer. Part of the processor core architecture.

DTS Digital Thermal Sensor

26 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Table 1-2. Glossary (Sheet 2 of 3)

Word/ Definition Acronym

ECC Error Correcting Code

GPO General Purpose Output

Host This term is used synonymously with processor.

Integrated A memory controller that is integrated in the processor silicon. Memory Controller (IMC)

I/O Input/Output. When used as a qualifier to a transaction type, specifies that transaction targets Intel® architecture-specific I/O space. (for example, I/O read)

IIO Integrated I/O Controller in the processor die providing I/O components.

Inband Communication that is multiplexed on the standard lines of an interface, rather than requiring a dedicated signal.

Intel® 64 Intel® 64 Instruction Set Architecture. The instruction set architecture and programming environment of Intel’s 64-bit processors which is a superset of and compatible with IA-32.

Intel® Intel® QuickData Technology is a platform solution designed to maximize the throughput of QuickData server data traffic across a broader range of configurations and server environments to Technology achieve faster, scalable, and more reliable I/O.

Intel® Processor Virtualization which when used in conjunction with Virtual Machine Monitor Virtualization software enables multiple, robust independent software environments inside a single Technology platform. (Intel® VT)

Integrated A component of the processor package used to enhance the thermal performance of the Heat Spreader package. Component thermal solutions interface with the processor at the IHS surface. (IHS)

Legacy Functional requirements handed down from previous chipsets or PC compatibility requirements from the past.

Link Layer The layer of an interface that handles flow control and often error correction by retry.

LLC Last Level Cache

LRDIMM Load Reduced Dual In-Line Memory Module

LRU Least Recently Used. A term used in conjunction with cache allocation policy.

MCDRAM Multi Channel DRAM. A high band width on package DRAM memory

MMIO Memory Mapped I/O. Any memory access to PCI Express*.

MMCFG Memory Mapped Configuration. A memory transaction that accesses configuration space.

Multi-Core A physical package that contains more than one processor core. Processor

MSR Model Specific Register as the name implies is model specific and may change from processor model number (n) to processor model number (n+1). An MSR is accessed by setting ECX to the register number and executing either the RDMSR or WRMSR instruction. The RDMSR instruction will place the 64 bits of the MSR in the EDX:EAX register pair. The WRMSR writes the contents of the EDX:EAX register pair into the MSR.

PCH Platform Controller Hub

PCU Power Control Unit

PECI Platform Environment Control Interface

Physical A package which contains 1 or more cores that share a common connection to the system Processor bus.

Power-On Also known as Cold Reset - occurs the first time the platform asserts PWRGOOD and Reset RESET_N to the processor.

RAPL Running Average Power Limit is an interface that defines an average power constraint for a given domain and allows the platform to specify its power information via multiple sources (registers and PECI 3.0). The RAPL interface supports multiple usage models for performance and power management features, such as Intel® Turbo Boost Technology.

Intel® Xeon Phi™ Processor 27 Datasheet - Volume 2, December 2016 Table 1-2. Glossary (Sheet 3 of 3)

Word/ Definition Acronym

RASUM Reliability, Availability, Serviceability, Usability, and Manageability, which are all important characteristics of servers.

Rank A group of DRAM chips that fill out the data bus width of the system and are accessed in parallel by each DRAM command.

Ring “Ring” refers to the interface between the processor core and rest of the uncore components.

RDIMM Registered Dual In-line Memory Module

SKU Stock Keeping Unit is a subset of a processor type with specific features, electrical, power and thermal specifications. Not all features are supported on all SKUs. A SKU is based on specific use condition assumption.

SDRAM Synchronous Dynamic Random Access Memory

SEC/DED Single-bit Error Correct / Double-symbol Error Detect

SMBus System Management Bus. Mastered by a system management controller to read and write configuration registers. Signaling and protocol are loosely based on I2C, limited to 100 KHz.

Snooping A means of ensuring cache coherency by monitoring all coherent accesses on a common multi-drop bus to determine if an access is to information resident within a cache. The Cache Agent ensures coherency by initiating snoops on the processor busses with the address of any line that might appear in a cache on that bus.

Socket The Knights Landing processor (core + uncore).

SVID Serial Voltage Identification is a binary pattern output from the processor that tells the voltage regulator the voltage required to operate the processor.

TCC Thermal Control Circuit is a feature of the processor that is used to cool the processor should the processor temperature exceed a predetermined temperature.

TDP Thermal Design Power

Tile A unit in Knights Landing Processor that contains 2 cores, L2 cache, VPU and CHA.

Thread A Logical Processor

Uncore The portion of the processor comprising the IMC, IIO and related components.

UP Uni-processor

Warm Reset Assertion and deassertion of the RESET_N input signal of the CPU where power is maintained to the processor. Does not include “CPU-Only Reset”, or “Power-on reset”.

1.4 Register Terminology

The bits in configuration register descriptions will have an assigned attribute from the following table. Bits without a Sticky attribute are set to their default value by a hard reset.

Note: The table below is a comprehensive list of all possible attributes.

Table 1-3. Register Attribute Definitions (Sheet 1 of 3)

Attribute Description RO Read Only: These bits can only be read by software, writes have no effect. The value of the bits is determined by the hardware only.

RW Read / Write: These bits can be read and written by software.

RC Read Clear Variant: These bits can be read by software, and the act of reading them automatically clears them. HW is responsible for writing these bits, and therefore the -V modifier is implied.

W1S Write 1 to Set: Writing a 1 to these bits will set them to 1. Writing 0 will have no effect. Reading will return indeterminate values.

28 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Table 1-3. Register Attribute Definitions (Sheet 2 of 3)

Attribute Description WO Write Only: These bits can only be written by microcode, reads return indeterminate values. Microcode that wants to ensure this bit was written must read wherever the side- effect takes place.

RW-O Read / Write Once: These bits can be read by software. After reset, these bits can only be written by software once, after which the bits becomes 'Read Only'.

RW-L Read / Write Lock: These bits can be read and written by software. The bits can be made to be 'Read Only' via a separate configuration bit or other logic.

RW-KL Read / Write Lock: These bits can be read and written by software. The bits can be made to be 'Read Only' via a separate configuration bit or other logic. Fields with this attribute also act as the locking agent for other fields.

RW1C Read / Write 1 to Clear: These bits can be read and cleared by software. Writing a '1' to a bit clears it, while writing a '0' to a bit has no effect.

RW0C Read / Write 0 to Clear: These bits can be read and cleared by software. Writing a '0' to a bit clears it while writing a '1' has no effect.

ROS RO Sticky: These bits can only be read by software, writes have no effect. The value of the bits is determined by the hardware only. These bits are only re-initialized to their default value by a PWRGOOD reset.

RW1S Read, Write 1 to Set: These bits can be read. Writing a 1 to a given bit will set it to 1. Writing a 0 to a given bit will have no effect. It is not possible for software to set a bit to “0”. The 1->0 transition can only be performed by hardware. These registers are implicitly - V.

RWS R / W Sticky: These bits can be read and written by software. These bits are only re- initialized to their default value by a PWRGOOD reset.

RW1CS R / W1C Sticky: These bits can be read and cleared by software. Writing a '1' to a bit clears it, while writing a '0' to a bit has no effect. These bits are only re-initialized to their default value by a PWRGOOD reset.

RW-LB Read / Write Lock Bypass: Similar to RWL, these bits can be read and written by software. HW can make these bits “Read Only” via a separate configuration bit or other logic. However, RW-LB is a special case where the locking is controlled by the lock-bypass capability that is controlled by the lock-bypass enable bits. Each lock-bypass enable bit enables a set of config request sources that can bypass the lock. The requests sourced from the corresponding bypass enable bits will be lock-bypassed (that is, RW) while requests sourced from other sources are under lock control (RO). The lock bit and bypass enable bit are generally defined with RWO attributes. Sticky can be used with this attribute (RW-SWB). These bits are only reinitialized to their default values after PWRGOOD. Note that the lock bits may not be sticky, and it is important that they are written to after reset to guarantee that software will not be able to change their values after a reset.

RO-FW Read Only Forced Write: These bits are read only from the perspective of the cores.

RWS-O Read / Write Sticky Once: If a register is both sticky and “once” then the sticky value applies to both the register value and the “once” characteristic. Only a PWRGOOD reset will reset both the value and the “once” so that the register can be written to again.

RW-V / RO-V Read Write Variant / Read Only Variant: These bits may be modified by hardware. Software cannot expect the values to stay unchanged. This is similar to “volatile” in software land.

RWS-V Read / Write Software Variant: These bits can be read or written by software and may be modified by hardware. Software cannot expect the values to stay unchanged. These bits are re-initialized to their default values by a PWRGOOD reset.

RWS-L Read / Write Sticky Lock: If a register is both sticky and locked, then the sticky behavior only applies to the value. The sticky behavior of the lock is determined by the register that controls the lock.

RWS-LV Read / Write Sticky Lock Variant: These bits can be read or written by software and may be modified by hardware. Software cannot expect the values to stay unchanged. These bits are re-initialized to their default values by a PWRGOOD reset. If a register is both sticky and locked, then the sticky behavior only applies to the value. The sticky behavior of the lock is determined by the register that controls the lock.

Intel® Xeon Phi™ Processor 29 Datasheet - Volume 2, December 2016 Table 1-3. Register Attribute Definitions (Sheet 3 of 3)

Attribute Description SMM-RO Read Only in SMM: These bits can only be read by software while in SMM. Writes in SMM have no effect. Attempting to read or write these bits outside of SMM will cause a #GP exception to be raised.

R/SMM-W Read / Write Only in SMM: These bits can be read by software inside or outside of SMM but can only be written by software while in SMM. Attempting to write these bits outside of SMM will cause a #GP exception to be raised.

SMM-RW Read Only in SMM / Write Only in SMM: These bits can only be read and written by software while in SMM. Attempting to write these bits outside of SMM will cause a #GP exception to be raised.

SMM-RW1C Read / Write 1 to Clear in SMM: These bits can be read and cleared by software only while in SMM. Writing a '1' to a bit clears it, while writing a '0' to a bit has no effect.

RSVD-P Reserved - Protected: These bits are reserved for future expansion and their value must not be modified by software. When writing these bits, software must preserve the value read.

RSVD-Z Reserved - Don't Care: These bits are reserved for future expansion and modifying their value has no effect. Software does not need to preserve the value read.

1.5 Notational Conventions

Hexadecimal and Binary Numbers

Base 16 numbers are represented by a string of hexadecimal digits followed by the character H (for example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. Hexadecimal numbers can also be shown using an “x” character (for example 0x2A).

Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for example, 101B). The “B” designation is only used in situations where confusion as to the type of the number might arise.

Base 10 numbers are represented by a string of decimal digits followed by the character D (for example, 23D). The “D” designation is only used in situations where confusion as to the type of the number might arise.

30 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 2 On Package IO (OPIO) Registers

The eDRAM or MCDRAM devices are located inside the Intel® Xeon Phi™ processor package. The OPIO (On Package IO) interface is the external interface to the MCDRAM or eDRAM devices. The Intel® Xeon Phi™ processor EDC version of OPIO supports both MCDRAM and eDRAM in different modes. MCDRAM and eDRAM OPIO are very similar - the main differences being that MCDRAM adds a Response Interface, and requires training to support longer trace lengths between the CPU die and the MCDRAM device.

OPIO configuration register space is located in: • Bus 2, Device 23, Function 4

OPIO0-7 configuration register space is located in: • Bus 2, Device 24-31, Function 4

2.1 Bus: 2, Devices: 23, Function: 4 (CFG)

Table 2-1. Summary of Bus: 2, Device: 23, Function: 4 (CFG)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

0–1h 2 “VID_2_23_4_CFG” on page 31 8086h

2–3h 2 “DID_2_23_4_CFG” on page 32 783Ah

4–5h 2 “PCICMD_2_23_4_CFG” on page 32 0h

6–7h 2 “PCISTS_2_23_4_CFG” on page 33 0h

8–8h 1 “RID_2_23_4_CFG” on page 33 0h

9–Bh 3 “CCR_2_23_4_CFG” on page 34 88000h

C–Ch 1 “CLSR_2_23_4_CFG” on page 34 0h

D–Dh 1 “PLAT_2_23_4_CFG” on page 34 0h

E–Eh 1 “BIST_2_23_4_CFG” on page 35 80h

F–Fh 1 “BIST_2_23_4_CFG” on page 35 0h

34–34h 1 “CAPPTR_2_23_4_CFG” on page 35 0h

3C–3Ch 1 “INTL_2_23_4_CFG” on page 35 0h

3D–3Dh 1 “INTPIN_2_23_4_CFG” on page 35 0h

3E–3Eh 1 “MINGNT_2_23_4_CFG” on page 35 0h

3F–3Fh 1 “MAXLAT_2_23_4_CFG” on page 36 0h

2.1.1 VID_2_23_4_CFG

PCI Vendor ID Register

Intel® Xeon Phi™ Processor 31 Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 4 Offset: 0

Bit Attr Default Description 15:0 RO 8086h Vendor Identification Number (Vendor_Identification_Number) — The value is assigned by PCI-SIG to Intel.

2.1.2 DID_2_23_4_CFG

PCI Device Identification Number

Bus: 2 Device: Function: 4 Offset: 2

Bit Attr Default Description 15:0 RO 783Ah Device_Identification_Number — Device ID values vary from function to function. Please refer to register EDS for the breakdown of DID in function groups and individual assignments for different types of functions for Intel® Xeon Phi™ Processor.

2.1.3 PCICMD_2_23_4_CFG

PCI Command Register

Bus: 2Device: 23Function: 4Offset: 4

Bit Attr Default Description 15:11 RO 0h Reserved (RSVD) — Reserved.

10 RO 0h INTx_Disable — N/A for these devices

9RO0hFast_Back_to_Back_Enable — Not applicable to PCI Express and is hardwired to 0

8RO0hSERR_Enable — This bit has no impact on error reporting from these devices

7RO0hIDSEL_Stepping_Wait_Cycle_Control — Not applicable to internal devices. Hardwired to 0.

6RO0hParity_Error_Response — This bit has no impact on error reporting from these devices

5RO0hVGA_palette_snoop_Enable — Not applicable to internal devices. Hardwired to 0.

4RO0hMemory_Write_and_Invalidate_Enable — Not applicable to internal devices. Hardwired to 0.

3RO0hSpecial_Cycle_Enable — Not applicable. Hardwired to 0.

2RO0hBus_Master_Enable — Hardwired to 0 since these devices don't generate any transactions

1RO0hMemory_Space_Enable — Hardwired to 0 since these devices don't decode any memory BARs

0RO0hIO_Space_Enable — Hardwired to 0 since these devices don't decode any IO BARs

32 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 2.1.4 PCISTS_2_23_4_CFG

PCI Status Register

Bus: 2 Device: Function: 4 Offset: 6

Bit Attr Default Description 15 RO_V 0h Detected_Parity_Error — This bit is set when the device receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.

14 RO 0h Signaled_System_Error — Hardwired to 0

13 RO 0h Received_Master_Abort — Hardwired to 0

12 RO 0h Received_Target_Abort — Hardwired to 0

11 RO 0h Signaled_Target_Abort — Hardwired to 0

10:9 RO 0h DEVSEL_Timing — Not applicable to PCI Express. Hardwired to 0.

8RO0hMaster_Data_Parity_Error — Hardwired to 0

7RO0hFast_Back_to_Back — Not applicable to PCI Express. Hardwired to 0.

6RO0hReserved — Reserved

5RO0hx66MHz_capable — Not applicable to PCI Express. Hardwired to 0.

4RO0hCapabilities_List — This bit indicates the presence of a capabilities list structure. When set to 1, indicates the register at 34h provides an offset into the function.

3RO0hINTx_Status — Reflects the state of the INTA# signal at the input of the enable/ disable circuit. This bit is set by HW to 1 when the INTA# is asserted. This bit is reset by HW to 0 after the interrupt is cleared (independent of the state of the Interrupt Disable bit in the 0.4.0.PCICMD register). Hardwired to 0 on the processor.

2:0 RO 0h Reserved (RSVD) — Reserved.

2.1.5 RID_2_23_4_CFG

“PCIe header Revision ID register”

Bus: 2 Device: Function: 4 Offset: 8

Bit Attr Default Description 7:0 RO_V 0h revision_id — Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in the processor uncore. Implementation Note: Read and write requests from the host to any RID register in processor are handled directly by the NCU.

Intel® Xeon Phi™ Processor 33 Datasheet - Volume 2, December 2016 2.1.6 CCR_2_23_4_CFG

PCIe header Class Code register

Bus: 2 Device: Function: 4Offset: 9

Bit Attr Default Description 23:16 RO_V 8h base_class — The value changes dependent upon the dev-func accessed. Most dev-func will return 8'h08 for this field except for the following dev- func0,func1,... combinations. The following exceptions will return 8'h11. dev-0x8 func-2 dev-0x9 func-2 dev-0xA func-2 dev-0xB func-1,2,5,6 dev-0x10 func-1,6 dev-0x12 func-1,5

15:8 RO_V 80h sub_class — The value changes dependent upon the dev/func accessed. Most dev-func will return 8'h80 for this field except for the following dev- func0,func1,... combinations. The following exceptions will return 8'h01. dev-0x8 func-2 dev-0x9 func-2 dev-0xA func-2 dev-0xB func-1,2,5,6 dev-0x10 func-1,6 dev-0x12 func-1,5

7:0 RO_V 0h register_level_programming_interface — Reserved.

2.1.7 CLSR_2_23_4_CFG

PCI Cache Line Size Register

Bus: 2 Device: Function: 4 Offset: C

Bit Attr Default Description

7:0 RO 0h Cacheline Size (Cacheline_Size) — Size of Cacheline

2.1.8 PLAT_2_23_4_CFG

PCI Latency Timer

Bus: 2 Device: Function: 4 Offset: D

Bit Attr Default Description

7:0 RO 0h Primary_Latency_Timer — Not applicable to PCI-Express. Hardwired to 00h.

2.1.9 HDR_2_23_4_CFG

PCI Header Type

Bus: 2Device: 23Function: 4Offset: E

Bit Attr Default Description 7RO1hMulti_function_Device — This bit defaults to 1b since all these devices are multifunction

6:0 RO 0h configuration_layout — Type 0 header

34 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 2.1.10 BIST_2_23_4_CFG

PCI BIST Register

Bus: 2 Device: Function: 4 Offset: F

Bit Attr Default Description 7:0 RO 0h BIST_Tests — Not supported. Hardwired to 00h

2.1.11 CAPPTR_2_23_4_CFG

PCI Capability Pointer Register

Bus: 2 Device: Function: 4 Offset: 34

Bit Attr Default Description

7:0 RO 0h Capability_Pointer — Points to the first capability structure for the device which is the PCIe capability.

2.1.12 INTL_2_23_4_CFG

PCI Interrupt Line Register

Bus: 2 Device: Function: 4 Offset: 3C

Bit Attr Default Description

7:0 RO 0h Interrupt_Line — N/A for these devices

2.1.13 INTPIN_2_23_4_CFG

PCI Interrupt Pin Register

Bus: 2 Device: Function: 4 Offset: 3D

Bit Attr Default Description

7:0 RO 0h Interrupt_Pin — N/A since these devices do not generate any interrupt on their own

2.1.14 MINGNT_2_23_4_CFG

PCI Min Grant Register

Bus: 2 Device: Function: 4 Offset: 3E

Bit Attr Default Description 7:0 RO 0h MGV — The device does not burst as a PCI compliant master.

Intel® Xeon Phi™ Processor 35 Datasheet - Volume 2, December 2016 2.1.15 MAXLAT_2_23_4_CFG

PCI Max Latency Register

Bus: 2 Device: Function: 4 Offset: 3F

Bit Attr Default Description 7:0 RO 0h MLV — The device has no specific requirements for how often it needs to access the PCI bus.

2.2 Bus: 2, Device: 24, Function: 4 (CFG)

Table 2-2. Summary of Bus: 2, Device: 24, Function: 4 (CFG)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

0–1h 2 “VID_2_24_4_CFG” on page 36 8086h

2–3h 2 “DID_2_24_4_CFG” on page 37 783Bh

4–5h 2 “PCICMD_2_24_4_CFG” on page 37 0h

6–7h 2 “PCISTS_2_24_4_CFG” on page 37 0h

8–8h 1 “RID_2_24_4_CFG” on page 38 0h

9–Bh 3 “CCR_2_24_4_CFG” on page 38 88000h

C–Ch 1 “CLSR_2_24_4_CFG” on page 38 0h

D–Dh 1 “PLAT_2_24_4_CFG” on page 39 0h

E–Eh 1 “HDR_2_24_4_CFG” on page 39 80h

F–Fh 1 “BIST_2_24_4_CFG” on page 39 0h

34–34h 1 “CAPPTR_2_24_4_CFG” on page 39 0h

3C–3Ch 1 “INTL_2_24_4_CFG” on page 39 0h

3D–3Dh 1 “INTPIN_2_24_4_CFG” on page 39 0h

3E–3Eh 1 “MINGNT_2_24_4_CFG” on page 40 0h

2.2.1 VID_2_24_4_CFG

PCI Vendor ID Register

Bus: 2 Device: Function: 4 Offset: 0

Bit Attr Default Description 15:0 RO 8086h Vendor Identification Number (Vendor_Identification_Number) — The value is assigned by PCI-SIG to Intel.

36 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 2.2.2 DID_2_24_4_CFG

PCI Device Identification Number

Bus: 2 Device: Function: 4 Offset: 2

Bit Attr Default Description 15:0 RO 783Bh Device_Identification_Number — Device ID values vary from function to function. Please refer to register EDS for the breakdown of DID in function groups and individual assignments for different types of functions for Intel® Xeon Phi™ Processor.

2.2.3 PCICMD_2_24_4_CFG

PCI Command Register

Bus: 2Device: 24Function: 4Offset: 4

Bit Attr Default Description

15:11 RO 0h Reserved (RSVD) — Reserved.

10 RO 0h INTx_Disable — N/A for these devices

9RO0hFast_Back_to_Back_Enable — Not applicable to PCI Express and is hardwired to 0

8RO0hSERR_Enable — This bit has no impact on error reporting from these devices

7RO0hIDSEL_Stepping_Wait_Cycle_Control — Not applicable to internal devices. Hardwired to 0.

6RO0hParity_Error_Response — This bit has no impact on error reporting from these devices

5RO0hVGA_palette_snoop_Enable — Not applicable to internal devices. Hardwired to 0.

4RO0hMemory_Write_and_Invalidate_Enable — Not applicable to internal devices. Hardwired to 0.

3RO0hSpecial_Cycle_Enable — Not applicable. Hardwired to 0.

2RO0hBus_Master_Enable — Hardwired to 0 since these devices don't generate any transactions

1RO0hMemory_Space_Enable — Hardwired to 0 since these devices don't decode any memory BARs

0RO0hIO_Space_Enable — Hardwired to 0 since these devices don't decode any IO BARs

2.2.4 PCISTS_2_24_4_CFG

PCI Status Register

Bus: 2 Device: Function: 4 Offset: 6

14 RO 0h Signaled_System_Error — Hardwired to 0

13 RO 0h Received_Master_Abort — Hardwired to 0

12 RO 0h Received_Target_Abort — Hardwired to 0

Intel® Xeon Phi™ Processor 37 Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 4 Offset: 6

Bit Attr Default Description 11 RO 0h Signaled_Target_Abort — Hardwired to 0

10:9 RO 0h DEVSEL_Timing — Not applicable to PCI Express. Hardwired to 0.

8RO0hMaster_Data_Parity_Error — Hardwired to 0

7RO0hFast_Back_to_Back — Not applicable to PCI Express. Hardwired to 0.

6RO0hReserved — Reserved

5RO0hx66MHz_capable — Not applicable to PCI Express. Hardwired to 0.

4RO0hCapabilities_List — This bit indicates the presence of a capabilities list structure.

3RO0hINTx_Status — Reflects the state of the INTA# signal at the input of the enable/

2:0 RO 0h Reserved (RSVD) — Reserved.

2.2.5 RID_2_24_4_CFG

“PCIe header Revision ID register”

Bus: Device: Function: 4 Offset: 8

Bit Attr Default Descripti

7:0 RO_V 0h revision_id — Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in the processor uncore. Implementation Note: Read and write requests from the host to any RID register in processor are

2.2.6 CCR_2_24_4_CFG

PCIe header Class Code register

Bus: 2 Device: Function: 4 Offset: 9

7:0 RO_V 0h register_level_programming_interface — Reserved.

2.2.7 CLSR_2_24_4_CFG

PCI Cache Line Size Register

Bus: 2 Device: Function: 4 Offset: C

Bit Attr Default Description

38 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7:0 RO 0h Cacheline Size (Cacheline_Size) — Size of Cacheline

2.2.8 PLAT_2_24_4_CFG

PCI Latency Timer

Bus: Device: Function: 4 Offset: D

Bit Attr Default Descripti

7:0 RO 0h Primary_Latency_Timer — Not applicable to PCI-Express. Hardwired to 00h.

2.2.9 HDR_2_24_4_CFG

PCI Header Type

Bus: 2Device: 24Function: 4Offset: E

Bit Attr Default Description

7RO1hMulti_function_Device — This bit defaults to 1b since all these devices are multifunction

6:0 RO 0h configuration_layout — Type 0 header

2.2.10 BIST_2_24_4_CFG

PCI BIST Register

Bus: 2 Device: Function: 4 Offset: F

Bit Attr Default Description

7:0 RO 0h BIST_Tests — Not supported. Hardwired to 00h

2.2.11 CAPPTR_2_24_4_CFG

PCI Capability Pointer Register

Bus: 2 Device: Function: 4 Offset: 34

Bit Attr Default Description 7:0 RO 0h Capability_Pointer — Points to the first capability structure for the device which is the PCIe capability.

2.2.12 INTL_2_24_4_CFG

PCI Interrupt Line Register

Bus: 2 Device: Function: 4 Offset: 3C

Bit Attr Default Description 7:0 RO 0h Interrupt_Line — N/A for these devices

2.2.13 INTPIN_2_24_4_CFG

PCI Interrupt Pin Register

Intel® Xeon Phi™ Processor 39 Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 4 Offset: 3D

Bit Attr Default Description 7:0 RO 0h Interrupt_Pin — N/A since these devices do not generate any interrupt on their own

2.2.14 MINGNT_2_24_4_CFG

PCI Min Grant Register

Bus: 2 Device: Function: 4 Offset: 3E

Bit Attr Default Description 7:0 RO 0h MGV — The device does not burst as a PCI compliant master.

40 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3 Memory Controller (MC) Registers

The processor implements two Memory Controllers on the processor die. Each memory controller is capable of controlling three DDR4 memory channels. The MC design is derived from the EDC (Near-Memory (MCDRAM) controller) and is a sub-set of EDC in functionality. The main difference from EDC is that the physical interface for MC will be DDR4 IOs. The processor MC will interface with the rest of the unit via the mesh interface (R2Mem -> Ring-to-MC interface). Therefore, the MC agent is broken into three regions: The front-end ring/mesh interface called the “R2Mem”, the core “EDC controller” logic, and three individual “DDR channel controllers/schedulers.”

This chapter describes in detail about the performance monitoring- related registers in the memory controller.

The following table [Table 24: MC0 Register ID/Name Mapping] contains a mapping of the MC0 UCLK and MC0 CH0 register names used in this document corresponding to the legacy Perfmon register names used conventionally on other Intel® processors for convenience of the reader. Please note that the same mapping applies to the rest of MC0 CH1, MC0 CH2, MC1 UCLK, MC1 CH0, MC1 CH1, MC1 CH2 registers.

Table 3-1. MC0 Register ID/Name Mapping (Sheet 1 of 2)

UCLK_PMON_CTR0_LOW_REG MC0_UCLK_MSR_PMON_CTR0_LOW

UCLK_PMON_CTR0_HIGH_REG MC0_UCLK_MSR_PMON_CTR0_HIGH

UCLK_PMON_CTR1_LOW_REG MC0_UCLK_MSR_PMON_CTR1_LOW

UCLK_PMON_CTR1_HIGH_REG MC0_UCLK_MSR_PMON_CTR1_HIGH

UCLK_PMON_CTR2_LOW_REG MC0_UCLK_MSR_PMON_CTR2_LOW

UCLK_PMON_CTR2_HIGH_REG MC0_UCLK_MSR_PMON_CTR2_HIGH

UCLK_PMON_CTR3_LOW_REG MC0_UCLK_MSR_PMON_CTR3_LOW

UCLK_PMON_CTR3_HIGH_REG MC0_UCLK_MSR_PMON_CTR3_HIGH

UCLK_PMON_CTRCTL0_REG MC0_UCLK_MSR_PMON_CTL0

UCLK_PMON_CTRCTL1_REG MC0_UCLK_MSR_PMON_CTL1

UCLK_PMON_CTRCTL2_REG MC0_UCLK_MSR_PMON_CTL2

UCLK_PMON_CTRCTL3_REG MC0_UCLK_MSR_PMON_CTL3

UCLK_PMON_UNIT_CTL_REG MC0_UCLK_MSR_PMON_BOX_CTL

UCLK_PMON_UNIT_STATUS_REG MC0_UCLK_MSR_PMON_BOX_STATUS

UCLK_PMON_TIMESTAMP_LOW_REG MC0_UCLK_MSR_PMON_UCLK_FIXED_LOW

UCLK_PMON_TIMESTAMP_HIGH_REG MC0_UCLK_MSR_PMON_UCLK_FIXED_HIGH

UCLK_PMON_TIMESTAMP_CTL_REG MC0_UCLK_MSR_PMON_UCLK_FIXED_CTL

DCLK_PMON_CTR0_LOW_REG MC0_CH0_MSR_PMON_CTR0_LOW

DCLK_PMON_CTR0_HIGH_REG MC0_CH0_MSR_PMON_CTR0_HIGH

Intel® Xeon Phi™ Processor 41 Datasheet - Volume 2, December 2016 Table 3-1. MC0 Register ID/Name Mapping (Sheet 2 of 2)

DCLK_PMON_CTR1_HIGH_REG MC0_CH0_MSR_PMON_CTR1_HIGH

DCLK_PMON_CTR2_LOW_REG MC0_CH0_MSR_PMON_CTR2_LOW

DCLK_PMON_CTR2_HIGH_REG MC0_CH0_MSR_PMON_CTR2_HIGH

DCLK_PMON_CTR3_LOW_REG MC0_CH0_MSR_PMON_CTR3_LOW

DCLK_PMON_CTR3_HIGH_REG MC0_CH0_MSR_PMON_CTR3_HIGH

DCLK_PMON_CTRCTL0_REG MC0_CH0_MSR_PMON_CTL0

DCLK_PMON_CTRCTL1_REG MC0_CH0_MSR_PMON_CTL1

DCLK_PMON_CTRCTL2_REG MC0_CH0_MSR_PMON_CTL2

DCLK_PMON_CTRCTL3_REG MC0_CH0_MSR_PMON_CTL3

DCLK_PMON_UNIT_CTL_REG MC0_CH0_MSR_PMON_BOX_CTL

DCLK_PMON_UNIT_STATUS_REG MC0_CH0_MSR_PMON_BOX_STATUS

DCLK_PMON_TIMESTAMP_LOW_REG MC0_CH0_MSR_PMON_DCLK_FIXED_LOW

DCLK_PMON_TIMESTAMP_HIGH_REG MC0_CH0_MSR_PMON_DCLK_FIXED_HIGH

DCLK_PMON_TIMESTAMP_CTL_REG MC0_CH0_MSR_PMON_DCLK_FIXED_CTL

MC0 configuration register space is located in: • Bus 2, Device 8, Function 0-4 • Bus 2, Device 10, Function 0-2

MC1 configuration register space is located in: • Bus 2, Device 9, Function 0-4 • Bus 2, Device 11, Function 0-2 Registers in:

Bus 2, Device 8, Function 3 are the same as Bus 2, Device 8, Function 2

Bus 2, Device 8, Function 4 are the same as Bus 2, Device 8, Function 2

MC1 registers are not included in the EDS because they are the same as MC0 registers. In other words, registers in:

Bus 2, Device 9, Function 0 are the same as Bus 2, Device 8, Function 0

Bus 2, Device 9, Function 1 are the same as Bus 2, Device 8, Function 1

Bus 2, Device 9, Function 2 are the same as Bus 2, Device 8, Function 2

Bus 2, Device 9, Function 3 are the same as Bus 2, Device 8, Function 2

Bus2, Device 9, Function 4 are the same as Bus 2, Device 8, Function 2

Bus 2, Device 11, Function 0 are the same as Bus 2, Device 10, Function 0

Bus 2, Device 11, Function 1 are the same as Bus 2, Device 10, Function 1

Bus 2, Device 11, Function 2 are the same as Bus 2, Device 10, Function 2

42 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 The following table depicts the Physical to Logical mapping of the memory DIMM channels.

Table 3-2. Physical to Logical Memory channel mapping

Physical Package Channel Logical Channel Memory Controller 03MC1

14MC1

25MC1

30MC0

41MC0

52MC0

3.1 Bus: 2, Device: 10, Function: 0 (CFG)

Table 3-3. Summary of Bus: 2, Device: 10, Function: 0 (CFG)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

3F–3Fh 1 “MAXLAT_2_10_0_CFG” on page 43 0h

40–43h 4 “PXPCAP_KDMI” on page 43 920010h

100–103h 4 “PXPENHCAP_KDMI” on page 44 0h

208–20Bh 4 “scrb0_cfg” on page 44 0h

20C–20Fh 4 “scrb1_cfg” on page 45 0h

210–213h 4 “scrb2_cfg” on page 45 0h

214–217h 4 “scrb3_cfg” on page 45 0h

218–21Bh 4 “scrb4_cfg” on page 45 0h

21C–21Fh 4 “scrb5_cfg” on page 45 0h

220–223h 4 “scrb6_cfg” on page 46 0h

224–227h 4 “scrb7_cfg” on page 46 0h

3.1.1 MAXLAT_2_10_0_CFG

PCI Max Latency Register

Bus: 2 Device: Function: 0 Offset: 3F

Bit Attr Default Description 7:0 RO 0h MLV — The device has no specific requirements for how often it needs to access the PCI bus.

3.1.2 PXPCAP_KDMI

Intel® Xeon Phi™ Processor 43 Datasheet - Volume 2, December 2016 Not valid for PCIe integrated endpoints Bits 23:20, Attr=RO, Default=9, Device / Port Type. Device type for this device is Root Complex Integrated Endpoint. Bits 19:16, Attr=RO, Default=2, PCI Express Capability structure version number. This device is compliant with version 2 of the PCI Express capability structure version. Bits 15:8, Attr=RO, Default=0, Next Capability Pointer. Set to 0 to indicate there are no more capability structures. Bits 7:0, Attr=RO, Default=10h, Capability ID. Indicates the capability structure is for a PCI Express Capability as assigned by PCI-SIG.

Bus: 2 Device: Function: 0Offset: 40

Bit Attr Default Description 31:0 RO 920010h PXPCAP (pxpcap) — PXPCAP register

3.1.3 PXPENHCAP_KDMI

PCIe header register - read-only register that returns 0x00000000. PXPENHCAP: PCI Express Enhanced Capability Offset 100h Bit 31:20, Attr=RO, Default=0, Next Capability Offset. Pointer to the next capability in the enhanced configuration space. Set to 0 to indicate there are no more capability structures. Bits 19:16, Attr=RO, Default=0, Capability Version. There is no capability at this location. Bits 15:0, Attr=RO, Default=0, Capability ID. There is no capability at this location.

Bus: 2 Device: Function: 0Offset: 100

Bit Attr Default Description

31:0 RO 0h PXPENHCAP (pxpenhcap) — PXPENHCAP register

3.1.4 scrb0_cfg

This register is to control scrub parameters.

Bus: 2 Device: Function: 0Offset: 208

Bit Attr Default Description

31:24 RO 0h Reserved (RSVD) — Reserved.

23:4 RW_V 0h scrb_init_addr_lower20b — Start of patrol scrub address. This translates to system address sys_addr[25:6] = scrb_init_addr_lower20b[19:0]

3RW_V0hscrb_loadaddr — When asserted will cause scrb_strt_addr_lower20b and scrb_strt_addr_upper20b to be loaded into scrub patrol engine.

2RW_V0hscrb_reqtype — When set to 1, scrub patrol engine will become flush engine. When set to 0, scrub patrol engine issues scrub requests.

1RW_V0hscrb_loopcnt — When set to 1, scrub patrol engine will loop forever. When set to 0, scrub patrol engine issue the address in scrub address range only once and stop.

0RW_V0hscrb_en — Enable scrub patrol engine.

44 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3.1.5 scrb1_cfg

This register is to control scrub parameters.

Bus: 2Device: 10Function: 0Offset: 20C

Bit Attr Default Description 31:20 RO 0h Reserved (RSVD) — Reserved.

19:0 RW_V 0h scrb_init_addr_upper20b — Start of patrol scrub address. This translates to system address sys_addr[45:26] = scrb_init_addr_upper20b[19:0].

3.1.6 scrb2_cfg

This register is to control scrub parameters.

Bus: 2Device: 10Function: 0Offset: 210

Bit Attr Default Description 31:20 RO 0h Reserved (RSVD) — Reserved.

19:0 RW_V 0h scrb_max_addr_lower20b — Maximum address of patrol scrub. This translates to system address sys_addr[25:6] = scrb_max_addr_lower20b[19:0]

3.1.7 scrb3_cfg

This register is to control scrub parameters.

Bus: 2 Device: Function: 0Offset: 214

Bit Attr Default Description 31:20 RO 0h Reserved (RSVD) — Reserved.

19:0 RW_V 0h scrb_max_addr_upper20b — Maximum address of patrol scrub address. This translates to system address sys_addr[45:26] = scrb_max_addr_upper20b[19:0].

3.1.8 scrb4_cfg

This register is to control scrub parameters.

Bus: 2 Device: Function: 0Offset: 218

Bit Attr Default Description 31:20 RO 0h Reserved (RSVD) — Reserved.

19:0 RW_V 0h scrb_addr_mask_lower20b — Bits to skip in address range of patrol scrub. This translates to system address sys_addr[25:6] = scrb_mask_addr_lower20b[19:0]

3.1.9 scrb5_cfg

This register is to control scrub parameters.

Intel® Xeon Phi™ Processor 45 Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 0Offset: 21C

Bit Attr Default Description 31:20 RO 0h Reserved (RSVD) — Reserved.

19:0 RW_V 0h scrb_addr_mask_upper20b — Bits to skip in address range of patrol scrub. This translates to system address sys_addr[45:26] = scrb_mask_addr_upper20b[19:0].

3.1.10 scrb6_cfg

This register is to control scrub parameters.

Bus: 2 Device: Function: 0 Offset: 220

Bit Attr Default Description 31:0 RW_V 0h scrb_interval — Number of uclks between each scrub iteration.

3.1.11 scrb7_cfg

This register is to control scrub parameters.

Bus: 2Device: 10Function: 0Offset: 224

Bit Attr Default Description

31:28 RW_V 0h scrb_strideOffset7 — Number of uclks between each scrub iteration.

27:24 RW_V 0h scrb_strideOffset6 — Number of uclks between each scrub iteration.

23:20 RW_V 0h scrb_strideOffset5 — Number of uclks between each scrub iteration.

19:16 RW_V 0h scrb_strideOffset4 — Number of uclks between each scrub iteration.

15:12 RW_V 0h scrb_strideOffset3 — Number of uclks between each scrub iteration.

11:8 RW_V 0h scrb_strideOffset2 — Number of uclks between each scrub iteration.

7:4 RW_V 0h scrb_strideOffset1 — Number of uclks between each scrub iteration.

3:0 RW_V 0h scrb_strideOffset0 — Number of uclks between each scrub iteration.

3.2 Bus: 2, Device: 10, Function: 1 (CFG)

Table 3-4. Summary of Bus: 2, Device: 10, Function: 1 (CFG) (Sheet 1 of 2)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

0–1h 2 “VID_2_10_1_CFG” on page 47 8086h

2–3h 2 “DID_2_10_1_CFG” on page 47 7844h

4–5h 2 “PCICMD_2_10_1_CFG” on page 47 0h

6–7h 2 “PCISTS_2_10_1_CFG” on page 48 10h

8–8h 1 “RID_2_10_1_CFG” on page 49 0h

9–Bh 3 “CCR_2_10_1_CFG” on page 49 88000h

C–Ch 1 “CLSR_2_10_1_CFG” on page 49 0h

46 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Table 3-4. Summary of Bus: 2, Device: 10, Function: 1 (CFG) (Sheet 2 of 2)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

D–Dh 1 “PLAT_2_10_1_CFG” on page 49 0h

E–Eh 1 “HDR_2_10_1_CFG” on page 49 80h

F–Fh 1 “BIST_2_10_1_CFG” on page 50 0h

2C–2Fh 4 “SVID_MCXKDRWDBU_CFG” on page 50 8086h

34–34h 1 “CAPPTR_2_10_1_CFG” on page 50 40h

3C–3Ch 1 “INTL_2_10_1_CFG” on page 50 0h

3D–3Dh 1 “INTPIN_2_10_1_CFG” on page 50 0h

3E–3Eh 1 “MINGNT_2_10_1_CFG” on page 51 0h

3F–3Fh 1 “MAXLAT_2_10_1_CFG” on page 51 0h

40–43h 4 “PXPCAP_KDRWDBU” on page 51 920010h

100–103h 4 “PXPENHCAP_KDRWDBU” on page 51 0h

300–303h 4 “devtag_cntl_0” on page 52 3Fh

304–307h 4 “devtag_cntl_1” on page 52 3Fh

308–30Bh 4 “devtag_cntl_2” on page 53 3Fh

624–627h 4 “mcmtr_cfg” on page 54 4h

3.2.1 VID_2_10_1_CFG

PCI Vendor ID Register

Bus: 2 Device: Function: 1 Offset: 0

Bit Attr Default Description 15:0 RO 8086h Vendor Identification Number (Vendor_Identification_Number) — The value is assigned by PCI-SIG to Intel.

3.2.2 DID_2_10_1_CFG

PCI Device Identification Number

Bus: 2 Device: Function: 1 Offset: 2

Bit Attr Default Description 15:0 RO 7844h Device_Identification_Number — Device ID values vary from function to function. Please refer to register EDS for the breakdown of DID in function groups and individual assignments for different types of functions for Intel® Xeon Phi™ Processor.

3.2.3 PCICMD_2_10_1_CFG

PCI Command Register

Intel® Xeon Phi™ Processor 47 Datasheet - Volume 2, December 2016 Bus: 2Device: 10Function: 1Offset: 4

Bit Attr Default Description 15:11 RO 0h Reserved (RSVD) — Reserved.

10 RO 0h INTx_Disable — N/A for these devices

9RO0hFast_Back_to_Back_Enable — Not applicable to PCI Express and is hardwired to 0

8RO0hSERR_Enable — This bit has no impact on error reporting from these devices

7RO0hIDSEL_Stepping_Wait_Cycle_Control — Not applicable to internal devices. Hardwired to 0.

6RO0hParity_Error_Response — This bit has no impact on error reporting from these devices

5RO0hVGA_palette_snoop_Enable — Not applicable to internal devices. Hardwired to 0.

4RO0hMemory_Write_and_Invalidate_Enable — Not applicable to internal devices. Hardwired to 0.

3RO0hSpecial_Cycle_Enable — Not applicable. Hardwired to 0.

2RO0hBus_Master_Enable — Hardwired to 0 since these devices don't generate any transactions

1RO0hMemory_Space_Enable — Hardwired to 0 since these devices don't decode any memory BARs

0RO0hIO_Space_Enable — Hardwired to 0 since these devices don't decode any IO BARs

3.2.4 PCISTS_2_10_1_CFG

PCI Status Register

Bus: 2 Device: Function: 1 Offset: 6

Bit Attr Default Description

15 RO_V 0h Detected_Parity_Error — This bit is set when the device receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.

14 RO 0h Signaled_System_Error — Hardwired to 0

13 RO 0h Received_Master_Abort — Hardwired to 0

12 RO 0h Received_Target_Abort — Hardwired to 0

11 RO 0h Signaled_Target_Abort — Hardwired to 0

10:9 RO 0h DEVSEL_Timing — Not applicable to PCI Express. Hardwired to 0.

8RO0hMaster_Data_Parity_Error — Hardwired to 0

7RO0hFast_Back_to_Back — Not applicable to PCI Express. Hardwired to 0.

6RO0hReserved — Reserved

5RO0hx66MHz_capable — Not applicable to PCI Express. Hardwired to 0.

4RO1hCapabilities_List — This bit indicates the presence of a capabilities list structure. When set to 1, indicates the register at 34h provides an offset into the function.

48 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3.2.5 RID_2_10_1_CFG

“PCIe header Revision ID register”

Bus: 2 Device: Function: 1 Offset: 8

3.2.6 CCR_2_10_1_CFG

PCIe header Class Code register

Bus: 2 Device: Function: 1 Offset: 9

Bit Attr Default Description

23:16 RO_V 8h base_class — The value changes dependent upon the dev-func accessed. Most dev-func will return 8'h08 for this field except for the following dev- func0,func1,... combinations. The following exceptions will return 8'h11. dev-0x8 func-2 dev-0x9 func-2 dev-0xA func-2 dev-0xB func-1,2,5,6 dev-0x10 func-1,6 dev-0x12 func-1,5

7:0 RO_V 0h register_level_programming_interface — Reserved.

3.2.7 CLSR_2_10_1_CFG

PCI Cache Line Size Register

Bus: Device: Function: 1 Offset: C

Bit Attr Default Descripti

7:0 RO 0h Cacheline Size (Cacheline_Size) — Size of Cacheline

3.2.8 PLAT_2_10_1_CFG

PCI Latency Timer

Bus: 2 Device: Function: 1 Offset: D

Bit Attr Default Description 7:0 RO 0h Primary_Latency_Timer — Not applicable to PCI-Express. Hardwired to 00h.

3.2.9 HDR_2_10_1_CFG

PCI Header Type

Intel® Xeon Phi™ Processor 49 Datasheet - Volume 2, December 2016 Bus: 2Device: 10Function: 1Offset: E

Bit Attr Default Description 7RO1hMulti_function_Device — This bit defaults to 1b since all these devices are multifunction

6:0 RO 0h configuration_layout — Type 0 header

3.2.10 BIST_2_10_1_CFG

PCI BIST Register

Bus: 2 Device: Function: 1 Offset: F

Bit Attr Default Description 7:0 RO 0h BIST_Tests — Not supported. Hardwired to 00h

3.2.11 SVID_MCXKDRWDBU_CFG

PCI Subsystem Vendor ID Register

Bus: 2Device: 10Function: 1Offset: 2C

Bit Attr Default Description 31:16 RW_OV 0h SDID — The default value specifies Intel but can be set to any value once after reset.

15:0 RW_OV 8086h Subsystem_Vendor_Identification_Number (SVID) — The default value specifies Intel but can be set to any value once after reset.

3.2.12 CAPPTR_2_10_1_CFG

PCI Capability Pointer Register

Bus: Device: Function: 1 Offset: 34

Bit Attr Default Descripti

7:0 RO 40h Capability_Pointer — Points to the first capability structure for the device which is the PCIe capability.

3.2.13 INTL_2_10_1_CFG

PCI Interrupt Line Register

Bus: 2 Device: Function: 1 Offset: 3C

Bit Attr Default Description 7:0 RO 0h Interrupt_Line — N/A for these devices

3.2.14 INTPIN_2_10_1_CFG

PCI Interrupt Pin Register

50 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 1 Offset: 3D

Bit Attr Default Description 7:0 RO 0h Interrupt_Pin — N/A since these devices do not generate any interrupt on their own

3.2.15 MINGNT_2_10_1_CFG

PCI Min Grant Register

Bus: 2 Device: Function: 1 Offset: 3E

Bit Attr Default Description 7:0 RO 0h MGV — The device does not burst as a PCI compliant master.

3.2.16 MAXLAT_2_10_1_CFG

PCI Max Latency Register

Bus: 2 Device: Function: 1 Offset: 3F

Bit Attr Default Description 7:0 RO 0h MLV — The device has no specific requirements for how often it needs to access the PCI bus.

3.2.17 PXPCAP_KDRWDBU

PCIe header register - read-only register that returns 0x00920010. PXPCAP: PCI Express Capability Offset 40h Bits 31:30, Attr=RSVD, Default=0, Reserved Bits 29:25, Attr=RO, Default=0, Interrupt Message Number, Not valid for this device since this device does not generate interrupts. Bits 24, Attr=RO, Default=0, Slot Implemented. Not valid for PCIe integrated endpoints Bits 23:20, Attr=RO, Default=9, Device / Port Type. Device type for this device is Root Complex Integrated Endpoint. Bits 19:16, Attr=RO, Default=2, PCI Express Capability structure version number. This device is compliant with version 2 of the PCI Express capability structure version. Bits 15:8,

Attr=RO, Default=0, Next Capability Pointer. Set to 0 to indicate there are no more capability structures. Bits 7:0, Attr=RO, Default=10h, Capability ID. Indicates the capability structure is for a PCI Express Capability as assigned by PCI-SIG.

Bus: 2 Device: Function: 1Offset: 40

Bit Attr Default Description 31:0 RO 920010h PXPCAP (pxpcap) — PXPCAP register

3.2.18 PXPENHCAP_KDRWDBU

Intel® Xeon Phi™ Processor 51 Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 1Offset: 100

Bit Attr Default Description 31:0 RO 0h PXPENHCAP (pxpenhcap) — PXPENHCAP register

3.2.19 devtag_cntl_0

Usage model - When the number of correctable errors (CORRERRCNT_x) from a particular rank exceeds the corresponding threshold (CORRERRTHRSHLD_y), hardware will generate a SMI interrupt and log (and preserve) the failing device in the FailDevice field. SMM software will read the failing device on the particular rank.

Software then set the EN bit to enable substitution of the failing device/rank with the parity from the rest of the devices inline. For independent channel configuration, each rank can tag once. Up to 8 ranks can be tagged. For lock-step channel configuration, only one x8 device can be tagged per rank-pair. SMM software must identify which channel should be tagged for this rank and only set the valid bit for the channel from the channel-pair. There is no hardware logic to report incorrect programming error.

Unpredictable error and/or silent data corruption will be the consequence of such programming error. If the rank-sparing is enabled, it is recommend to prioritize the rank-sparing before triggering the device tagging due to the nature of the device tagging would drop the correction capability and any subsequent ECC error from this rank would cause uncorrectable error. In Intel® Xeon Phi™ Processor this is locked by devtag_lck.devtag_lck. If the lock bit is 1 this register is locked.

Bus: 2 Device: Function: 1Offset: 300

Bit Attr Default Description

31:8 RO 0h Reserved (RSVD) — Reserved.

7RW_LV0hen — Device tagging enable for this rank. Once set, the parity device of the rank is used for the replacement device content. After tagging, the rank will no longer have the “correction” capability. ECC error “detection” capability will not degrade after setting this bit. Warning: For lock-step channel configuration, only one x8 device can be tagged per rank- pair. SMM software must identify which channel should be tagged for this rank device. The DEVTAG_CNTL_x.EN on the other channel of the corresponding rank must not be set. Must never be enable prior using IOSAV and only set the corresponding DEVTAG_CNTL_x.EN bit for the channel contains the fail

6RO0hReserved (RSVD) — Reserved.

5:0 RW_LV 3Fh faildevice — When the corresponding rank's CORRESRRCNT is greater than its CORERRTHRESHLD, the hardware will capture the fail device ID of the rank in the FailDevice field. Subsequent correctable error will not change this field until the field is cleared. Valid Range is 0-17 to indicate which x4 device (independent channel) or x8 device (lock-step mode) had failed. If the value is equal or greater than 24, the field indicates no device failure had occurred on this rank.

3.2.20 devtag_cntl_1

52 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 only one x8 device can be tagged per rank-pair. SMM software must identify which channel should be tagged for this rank and only set the valid bit for the channel from the channel-pair. There is no hardware logic to report incorrect programming error.

Bus: 2 Device: Function: 1Offset: 304

Bit Attr Default Description 31:8 RO 0h Reserved (RSVD) — Reserved.

7RW_LV0hen — Device tagging enable for this rank. Once set, the parity device of the rank is used for the replacement device content. After tagging, the rank will no longer have the “correction” capability. ECC error “detection” capability will not degrade after setting this bit. Warning: For lock-step channel configuration, only one x8 device can be tagged per rank- pair. SMM software must identify which channel should be tagged for this rank and only set the corresponding DEVTAG_CNTL_x.EN bit for the channel contains the fail device. The DEVTAG_CNTL_x.EN on the other channel of the corresponding rank must not be set. Must never be enable prior using IOSAV

6RO0hReserved (RSVD) — Reserved.

3.2.21 devtag_cntl_2

Bus: 2 Device: Function: 1Offset: 308

Bit Attr Default Description

Intel® Xeon Phi™ Processor 53 Datasheet - Volume 2, December 2016 31:8 RO 0h Reserved (RSVD) — Reserved.

7RW_LV0hen — Device tagging enable for this rank. Once set, the parity device of the rank is used for the replacement device content. After tagging, the rank will no longer have the “correction” capability. ECC error “detection” capability will not degrade after setting this bit. Warning: For lock-step channel configuration, only one x8 device can be tagged per rank- pair. SMM software must identify which channel should be tagged for this rank and only set the corresponding DEVTAG_CNTL_x.EN bit for the channel contains the fail device. The DEVTAG_CNTL_x.EN on the other channel of the corresponding rank must not be set. Must never be enable prior using IOSAV

6RO0hReserved (RSVD) — Reserved.

3.2.22 mcmtr_cfg

Bus: 2 Device: Function: 1Offset: 624

Bit Attr Default Description

31:18 RO 0h Reserved (RSVD) — Reserved.

17:16 RW_LB 0h pass76 — 00: do not alter ChnAdd calculation 01: replace ChnAdd[6] with SysAdd[6] 10: Reserved 11: replace ChnAdd[7:6] with SysAdd[7:6]

15 RW_LB 0h cpgc_link_train — CPGC in VMSE link training mode, where MXB uses column bits 7:3 as buffer ID

14 RW_LB 0h ddr4 — DDR4 test development vehicle mode

13:12 RW_LB 0h imc_mode — Memory mode: 00: Native DDR3 01: Reserved 10: VMSE 1:1 Subchannel Lockstep Mode 11: VMSE 2:1 Performance Mode

11:10 RW_LB 0h trng_mode — 00: reserved 01: Native CPGC Mode and Setting to be used post VMSE CMD training (including EV). (mcmtr.normal must be zero for this mode) 10: CPGC VMSE CMD training mode - Setting till VMSE CMD (coarse/fine) bus is trained (mcmtr.normal must be zero for this mode) 11: Normal Mode (mcmtr.normal is a don't care for this mode)

9RSVD-P0hReserved (RSVD-P) — Reserved - protected.

8RW_LB0hnormal — 0: Training mode 1: Normal Mode

7RO0hReserved (RSVD) — Reserved.

6RW_LB0hscrmbl_en — Data Scramble enable.

5RO0hsp_dir_en — Enable spare directory in EX SCLS mode

4RO0hscls_en — Use VMSE subchannel lock-step mode if set; otherwise, independent channel mode. Note: DIS_LOCKSTEP fuse will force override this bit to zero.

54 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 1Offset: 624

Bit Attr Default Description

3RW_LB0hdir_en — If the directory disable fuse is set to directory disable state, this register bit is set to Read-Only (RO) with 0 value, that is, directory is disabled. When this bit is set to zero, MC ECC code will use the non-directory CRC-16. If the directory disable fuse is not blown, that is, directory is not disabled, the DIR_EN bit can be set by BIOS, MC ECC will use CRC-15 in the first 32B codeword to yield one directory bit. It is important to know that changing this bit will require BIOS to re-initialize the memory.

2RW_LB1hecc_en — ECC enable. Note: DIS_ECC fuse will force override this bit to 0.

1RW_LB0hls_en — Use lock-step channel mode if set; otherwise, independent channel mode. Note: DIS_LOCKSTEP fuse will force override this bit to zero.

0RW_LB0hclose_pg — Use close page address mapping if set; otherwise, open page.

3.3 Bus: 2, Device: 10, Function: 2 (CFG)

Table 3-5. Summary of Bus: 2, Device: 10, Function: 2 (CFG)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

0–1h 2 “VID_2_10_2_CFG” on page 56 8086h

2–3h 2 “DID_2_10_2_CFG” on page 56 781Fh

4–5h 2 “PCICMD_2_10_2_CFG” on page 56 0h

6–7h 2 “PCISTS_2_10_2_CFG” on page 56 0h

8–8h 1 “RID_2_10_2_CFG” on page 57 0h

9–Bh 3 “CCR_2_10_2_CFG” on page 57 88000h

C–Ch 1 “CLSR_2_10_2_CFG” on page 58 0h

D–Dh 1 “PLAT_2_10_2_CFG” on page 58 0h

E–Eh 1 “HDR_2_10_2_CFG” on page 58 80h

F–Fh 1 “BIST_2_10_2_CFG” on page 58 0h

2C–2Dh 2 “SVID” on page 59 8086h

2E–2Fh 2 “SDID” on page 59 0h

34–34h 1 “CAPPTR_2_10_2_CFG” on page 59 0h

3C–3Ch 1 “INTL_2_10_2_CFG” on page 59 0h

3D–3Dh 1 “INTPIN_2_10_2_CFG” on page 59 0h

3E–3Eh 1 “MINGNT_2_10_2_CFG” on page 59 0h

3F–3Fh 1 “MAXLAT_2_10_2_CFG” on page 60 0h

90–93h 4 “visaaddr” on page 60 0h

94–97h 4 “visadata” on page 60 0h

Intel® Xeon Phi™ Processor 55 Datasheet - Volume 2, December 2016 3.3.1 VID_2_10_2_CFG

PCI Vendor ID Register

Bus: 2 Device: Function: 2 Offset: 0

Bit Attr Default Description 15:0 RO 8086h Vendor Identification Number (Vendor_Identification_Number) — The value is assigned by PCI-SIG to Intel.

3.3.2 DID_2_10_2_CFG

PCI Device Identification Number

Bus: 2 Device: Function: 2 Offset: 2

Bit Attr Default Description

15:0 RO 781Fh Device_Identification_Number — Device ID values vary from function to function. Please refer to register EDS for the breakdown of DID in function groups and individual assignments for different types of functions for Intel® Xeon Phi™ Processor.

3.3.3 PCICMD_2_10_2_CFG

PCI Command Register

Bus: 2Device: 10Function: 2Offset: 4

Bit Attr Default Description

15:11 RO 0h Reserved (RSVD) — Reserved. 10 RO 0h INTx_Disable — N/A for these devices

9RO0hFast_Back_to_Back_Enable — Not applicable to PCI Express and is hardwired to 0

8RO0hSERR_Enable — This bit has no impact on error reporting from these devices

7RO0hIDSEL_Stepping_Wait_Cycle_Control — Not applicable to internal devices. Hardwired to 0.

6RO0hParity_Error_Response — This bit has no impact on error reporting from these devices

5RO0hVGA_palette_snoop_Enable — Not applicable to internal devices. Hardwired to 0.

4RO0hMemory_Write_and_Invalidate_Enable — Not applicable to internal devices. Hardwired to 0.

3RO0hSpecial_Cycle_Enable — Not applicable. Hardwired to 0.

2RO0hBus_Master_Enable — Hardwired to 0 since these devices don't generate any transactions

1RO0hMemory_Space_Enable — Hardwired to 0 since these devices don't decode any memory BARs

0RO0hIO_Space_Enable — Hardwired to 0 since these devices don't decode any IO BARs

3.3.4 PCISTS_2_10_2_CFG

PCI Status Register

56 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 2 Offset: 6

14 RO 0h Signaled_System_Error — Hardwired to 0

13 RO 0h Received_Master_Abort — Hardwired to 0

12 RO 0h Received_Target_Abort — Hardwired to 0

11 RO 0h Signaled_Target_Abort — Hardwired to 0

10:9 RO 0h DEVSEL_Timing — Not applicable to PCI Express. Hardwired to 0.

8RO0hMaster_Data_Parity_Error — Hardwired to 0

7RO0hFast_Back_to_Back — Not applicable to PCI Express. Hardwired to 0.

6RO0hReserved — Reserved

5RO0hx66MHz_capable — Not applicable to PCI Express. Hardwired to 0.

4RO0hCapabilities_List — This bit indicates the presence of a capabilities list structure. When set to 1, indicates the register at 34h provides an offset into the function.

2:0 RO 0h Reserved (RSVD) — Reserved.

3.3.5 RID_2_10_2_CFG

“PCIe header Revision ID register”

Bus: 2 Device: Function: 2 Offset: 8

Bit Attr Default Description

3.3.6 CCR_2_10_2_CFG

PCIe header Class Code register

Intel® Xeon Phi™ Processor 57 Datasheet - Volume 2, December 2016 Bus: 2 Device: Function: 2 Offset: 9

7:0 RO_V 0h register_level_programming_interface — Reserved.

3.3.7 CLSR_2_10_2_CFG

PCI Cache Line Size Register

Bus: 2 Device: Function: 2 Offset: C

Bit Attr Default Description 7:0 RO 0h Cacheline Size (Cacheline_Size) — Size of Cacheline

3.3.8 PLAT_2_10_2_CFG

PCI Latency Timer

Bus: Device: Function: 2 Offset: D

Bit Attr Default Descripti

7:0 RO 0h Primary_Latency_Timer — Not applicable to PCI-Express. Hardwired to 00h.

3.3.9 HDR_2_10_2_CFG

PCI Header Type

Bus: 2Device: 10Function: 2Offset: E

Bit Attr Default Description 7RO1hMulti_function_Device — This bit defaults to 1b since all these devices are multifunction

6:0 RO 0h configuration_layout — Type 0 header

3.3.10 BIST_2_10_2_CFG

PCI BIST Register

Bus: 2 Device: Function: 2 Offset: F

Bit Attr Default Description 7:0 RO 0h BIST_Tests — Not supported. Hardwired to 00h

58 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3.3.11 SVID

PCI Subsystem Vendor ID Register

Bus: 2 Device: Function: 2 Offset: 2C

Bit Attr Default Description 15:0 RW_O 8086h Subsystem_Vendor_Identification_Number — The default value specifies Intel but can be set to any value once after reset.

3.3.12 SDID

PCI Subsystem device ID Register

Bus: 2 Device: Function: 2 Offset: 2E

Bit Attr Default Description

15:0 RW_O 0h Subsystem_Device_Identification_Number — Assigned by the subsystem vendor to uniquely identify the subsystem

3.3.13 CAPPTR_2_10_2_CFG

PCI Capability Pointer Register

Bus: 2 Device: Function: 2 Offset: 34

Bit Attr Default Description 7:0 RO 0h Capability_Pointer — Points to the first capability structure for the device which is the PCIe capability.

3.3.14 INTL_2_10_2_CFG

PCI Interrupt Line Register

Bus: 2 Device: Function: 2 Offset: 3C

Bit Attr Default Description

7:0 RO 0h Interrupt_Line — N/A for these devices

3.3.15 INTPIN_2_10_2_CFG

PCI Interrupt Pin Register

Bus: 2 Device: Function: 2 Offset: 3D

Bit Attr Default Description 7:0 RO 0h Interrupt_Pin — N/A since these devices do not generate any interrupt on their own

3.3.16 MINGNT_2_10_2_CFG

PCI Min Grant Register

Bus: 2 Device: Function: 2 Offset: 3E

Intel® Xeon Phi™ Processor 59 Datasheet - Volume 2, December 2016 Bit Attr Default Description 7:0 RO 0h MGV — The device does not burst as a PCI compliant master.

3.3.17 MAXLAT_2_10_2_CFG

PCI Max Latency Register

Bus: 2 Device: Function: 2 Offset: 3F

Bit Attr Default Description 7:0 RO 0h MLV — The device has no specific requirements for how often it needs to access the PCI bus.

3.3.18 visaaddr

Bus: 2Device: 10Function: 2Offset: 90

Bit Attr Default Description 31:16 RO 0h Reserved (RSVD) — Reserved.

15:2 RWS_L 0h csr_visa_addr — VISA address for the TGR VISA MUX.

1:0 RO 0h Reserved (RSVD) — Reserved.

3.3.19 visadata

Bus: 2 Device: 10 Function: 2Offset: 94

Bit Attr Default Description 31:0 RWS_L 0h csr_visa_data — VISA data from VISA MUX to CMS.

3.4 Bus: 2, Device: 8, Function: 0 (CFG)

Table 3-6. Summary of Bus: 2, Device: 8, Function: 0 (CFG) (Sheet 1 of 3)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

0–1h 2 “VID_2_8_0_CFG” on page 62 8086h

2–3h 2 “DID_2_8_0_CFG” on page 62 7840h

4–5h 2 “PCICMD_2_8_0_CFG” on page 62 0h

6–7h 2 “PCISTS_2_8_0_CFG” on page 63 10h

8–8h 1 “RID_2_8_0_CFG” on page 64 0h

9–Bh 3 “CCR_2_8_0_CFG” on page 64 88000h

C–Ch 1 “CLSR_2_8_0_CFG” on page 64 0h

D–Dh 1 “PLAT_2_8_0_CFG” on page 64 0h

E–Eh 1 “HDR_2_8_0_CFG” on page 64 80h

60 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Table 3-6. Summary of Bus: 2, Device: 8, Function: 0 (CFG) (Sheet 2 of 3)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

F–Fh 1 “BIST_2_8_0_CFG” on page 65 0h

2C–2Fh 4 “SVID_MCXKDMC_CFG” on page 65 8086h

34–34h 1 “CAPPTR_2_8_0_CFG” on page 65 40h

3C–3Ch 1 “INTL_2_8_0_CFG” on page 65 0h

3D–3Dh 1 “INTPIN_2_8_0_CFG” on page 65 0h

3E–3Eh 1 “MINGNT_2_8_0_CFG” on page 66 0h

3F–3Fh 1 “MAXLAT_2_8_0_CFG” on page 66 0h

40–43h 4 “PXPCAP_KDMC” on page 66 920010h

98–9Bh 4 “mcdecs_chicken_bits_CFG” on page 66 CC0h

A0–A3h 4 “CREDIT_CONTROL_REG” on page 67 0h

100–103h 4 “PXPENHCAP_KDMC” on page 67 0h

1D4–1D7h 4 “rsp_func_mcctrl_err_inj_CFG” on page 67 4h

1D8–1DBh 4 “ddr_trace_throttle_ctl_CFG” on page 68 FFFh

1DC–1DFh 4 “mcwdb_chkn_bit_CFG” on page 68 1h

1E0–1E3h 4 “rsp_func_crc_err_inj_dev0_xor_msk_CFG” on page 69 0h

1E4–1E7h 4 “rsp_func_crc_err_inj_dev1_xor_msk_CFG” on page 69 0h

1E8–1EBh 4 “rsp_func_crc_err_inj_extra_CFG” on page 69 3C000000h

24C–24Fh 4 “dft_rdret_control_CFG” on page 70 0h

250–253h 4 “demand_scrub_cfg” on page 71 3h

280–283h 4 “x4modesel_CFG” on page 72 0h

400–403h 4 “mc_tad0_limit_lo_CFG” on page 72 69h

404–407h 4 “mc_tad0_offset_lo_CFG” on page 72 10h

408–40Bh 4 “mc_tad0_limit_offset_hi_CFG” on page 72 10000h

500–503h 4 “mc_tad1_limit_lo_CFG” on page 73 0h

504–507h 4 “mc_tad1_offset_lo_CFG” on page 73 10h

508–50Bh 4 “mc_tad1_limit_offset_hi_CFG” on page 73 0h

600–603h 4 “mc_tad2_limit_lo_CFG” on page 73 0h

604–607h 4 “mc_tad2_offset_lo_CFG” on page 74 10h

608–60Bh 4 “mc_tad2_limit_offset_hi_CFG” on page 74 0h

700–703h 4 “mc_tad3_limit_lo_CFG” on page 74 0h

704–707h 4 “mc_tad3_offset_lo_CFG” on page 74 10h

708–70Bh 4 “mc_tad3_limit_offset_hi_CFG” on page 75 0h

800–803h 4 “mc_tad4_limit_lo_CFG” on page 75 0h

804–807h 4 “mc_tad4_offset_lo_CFG” on page 75 10h

808–80Bh 4 “mc_tad4_limit_offset_hi_CFG” on page 75 0h

900–903h 4 “mc_tad5_limit_lo_CFG” on page 75 0h

Intel® Xeon Phi™ Processor 61 Datasheet - Volume 2, December 2016 Table 3-6. Summary of Bus: 2, Device: 8, Function: 0 (CFG) (Sheet 3 of 3)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

904–907h 4 “mc_tad5_offset_lo_CFG” on page 76 10h

908–90Bh 4 “mc_tad5_limit_offset_hi_CFG” on page 76 0h

A00–A03h 4 “mc_tad6_limit_lo_CFG” on page 76 0h

A04–A07h 4 “mc_tad6_offset_lo_CFG” on page 76 10h

A08–A0Bh 4 “mc_tad6_limit_offset_hi_CFG” on page 77 0h

B00–B03h 4 “mc_tad7_limit_lo_CFG” on page 77 0h

B04–B07h 4 “mc_tad7_offset_lo_CFG” on page 77 10h

B08–B0Bh 4 “mc_tad7_limit_offset_hi_CFG” on page 77 0h

C00–C03h 4 “mc_tag_mask_lo_CFG” on page 78 100000h

C04–C07h 4 “mc_tag_mask_hi_CFG” on page 78 0h

C80–C83h 4 “controller_throttle_reg” on page 78 FFFFFFFFh

D00–D03h 4 “errinj_addr_lo_reg” on page 78 0h

D04–D07h 4 “errinj_addr_hi_reg” on page 78 0h

D08–D0Bh 4 “errinj_mask_lo_reg” on page 79 0h

D0C–D0Fh 4 “errinj_mask_hi_reg” on page 79 0h

D10–D13h 4 “errinj_lfsr_reg” on page 79 0h

D14–D17h 4 “errinj_limit_reg” on page 80 0h

3.4.1 VID_2_8_0_CFG

PCI Vendor ID Register

Bus: 2 Device: 8 Function: 0 Offset: 0

Bit Attr Default Description

15:0 RO 8086h Vendor Identification Number (Vendor_Identification_Number) — The value is assigned by PCI-SIG to Intel.

3.4.2 DID_2_8_0_CFG

PCI Device Identification Number

Bus: 2 Device: 8 Function: 0 Offset: 2 Bit Attr Default Description

15:0 RO 7840h Device_Identification_Number — Device ID values vary from function to function. Please refer to register EDS for the breakdown of DID in function groups and individual assignments for different types of functions for Intel® Xeon Phi™ Processor.

3.4.3 PCICMD_2_8_0_CFG

PCI Command Register

62 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2Device: 8Function: 0Offset: 4

Bit Attr Default Description 15:11 RO 0h Reserved (RSVD) — Reserved.

10 RO 0h INTx_Disable — N/A for these devices

9RO0hFast_Back_to_Back_Enable — Not applicable to PCI Express and is hardwired to 0

8RO0hSERR_Enable — This bit has no impact on error reporting from these devices

7RO0hIDSEL_Stepping_Wait_Cycle_Control — Not applicable to internal devices. Hardwired to 0.

6RO0hParity_Error_Response — This bit has no impact on error reporting from these devices

5RO0hVGA_palette_snoop_Enable — Not applicable to internal devices. Hardwired to 0.

4RO0hMemory_Write_and_Invalidate_Enable — Not applicable to internal devices. Hardwired to 0.

3RO0hSpecial_Cycle_Enable — Not applicable. Hardwired to 0.

2RO0hBus_Master_Enable — Hardwired to 0 since these devices don't generate any transactions

1RO0hMemory_Space_Enable — Hardwired to 0 since these devices don't decode any memory BARs

0RO0hIO_Space_Enable — Hardwired to 0 since these devices don't decode any IO BARs

3.4.4 PCISTS_2_8_0_CFG

PCI Status Register

Bus: 2 Device: 8 Function: 0 Offset: 6

Bit Attr Default Description

14 RO 0h Signaled_System_Error — Hardwired to 0

13 RO 0h Received_Master_Abort — Hardwired to 0

12 RO 0h Received_Target_Abort — Hardwired to 0

11 RO 0h Signaled_Target_Abort — Hardwired to 0

10:9 RO 0h DEVSEL_Timing — Not applicable to PCI Express. Hardwired to 0.

8RO0hMaster_Data_Parity_Error — Hardwired to 0

7RO0hFast_Back_to_Back — Not applicable to PCI Express. Hardwired to 0.

6RO0hReserved — Reserved

5RO0hx66MHz_capable — Not applicable to PCI Express. Hardwired to 0.

4RO1hCapabilities_List — This bit indicates the presence of a capabilities list structure. When set to 1, indicates the register at 34h provides an offset into the function.

2:0 RO 0h Reserved (RSVD) — Reserved.

Intel® Xeon Phi™ Processor 63 Datasheet - Volume 2, December 2016 3.4.5 RID_2_8_0_CFG

“PCIe header Revision ID register”

Bus: 2 Device: 8 Function: 0 Offset: 8

3.4.6 CCR_2_8_0_CFG

PCIe header Class Code register

Bus: 2 Device: 8 Function: 0Offset: 9

Bit Attr Default Description

23:16 RO_V 8h base_class — The value changes dependent upon the dev-func accessed. Most dev-func will return 8'h08 for this field except for the following dev- func0,func1,... combinations. The following exceptions will return 8'h11. dev-0x9 func-2 dev-0xA func-2 dev-0xB func-1,2,5,6 dev-0x dev-0x8 func-2 10 func-1,6 dev-0x12 func-1,5

7:0 RO_V 0h register_level_programming_interface — Reserved.

3.4.7 CLSR_2_8_0_CFG

PCI Cache Line Size Register

Bus: 2 Device: 8 Function: 0 Offset: C

Bit Attr Default Description 7:0 RO 0h Cacheline Size (Cacheline_Size) — Size of Cacheline

3.4.8 PLAT_2_8_0_CFG

PCI Latency Timer

Bus: 2 Device: 8 Function: 0 Offset: D

Bit Attr Default Description 7:0 RO 0h Primary_Latency_Timer — Not applicable to PCI-Express. Hardwired to 00h.

3.4.9 HDR_2_8_0_CFG

PCI Header Type

64 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2Device: 8Function: 0Offset: E

Bit Attr Default Description 7RO1hMulti_function_Device — This bit defaults to 1b since all these devices are multifunction

6:0 RO 0h configuration_layout — Type 0 header

3.4.10 BIST_2_8_0_CFG

PCI BIST Register

Bus: Device: Function: 0 Offset: F

Bit Attr Default Descripti

7:0 RO 0h BIST_Tests — Not supported. Hardwired to 00h

3.4.11 SVID_MCXKDMC_CFG

PCI Subsystem Vendor ID Register

Bus: 2Device: 8Function: 0Offset: 2C

Bit Attr Default Description

31:16 RW_OV 0h SDID — The default value specifies Intel but can be set to any value once after reset.

15:0 RW_OV 8086h Subsystem_Vendor_Identification_Number (SVID) — The default value specifies Intel but can be set to any value once after reset.

3.4.12 CAPPTR_2_8_0_CFG

PCI Capability Pointer Register

Bus: 2 Device: 8 Function: 0 Offset: 34

Bit Attr Default Description

7:0 RO 40h Capability_Pointer — Points to the first capability structure for the device which is the PCIe capability.

3.4.13 INTL_2_8_0_CFG

PCI Interrupt Line Register

Bus: Device: Function: 0 Offset: 3C

Bit Attr Default Descripti

7:0 RO 0h Interrupt_Line — N/A for these devices

3.4.14 INTPIN_2_8_0_CFG

PCI Interrupt Pin Register

Intel® Xeon Phi™ Processor 65 Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 0 Offset: 3D

Bit Attr Default Description 7:0 RO 0h Interrupt_Pin — N/A since these devices do not generate any interrupt on their own

3.4.15 MINGNT_2_8_0_CFG

PCI Min Grant Register

Bus: 2 Device: 8 Function: 0 Offset: 3E

Bit Attr Default Description 7:0 RO 0h MGV — The device does not burst as a PCI compliant master.

3.4.16 MAXLAT_2_8_0_CFG

PCI Max Latency Register

Bus: 2 Device: 8 Function: 0 Offset: 3F

Bit Attr Default Description 7:0 RO 0h MLV — The device has no specific requirements for how often it needs to access the PCI bus.

3.4.17 PXPCAP_KDMC

Bus: 2 Device: 8 Function: 0Offset: 40

Bit Attr Default Description 31:0 RO 920010h PXPCAP (pxpcap) — PXPCAP register

3.4.18 mcdecs_chicken_bits_CFG

MCDECS_CHICKEN_BITS

66 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 0Offset: 98

Bit Attr Default Description 31:15 RW_LB 0h DSM_RSVD — Reserved Unused

14 RW_LB 0h early_vpq_tkn_rtn_na — This bit is NA in MC

13:6 RWS_LB 33h poolSize — This bit specifies number of SWPQ tokens for posted/Fill/victim/I2E (allowing that many more posted writes).

5RWS_LB0hblockTokenReservation — not applicable in MC

4RW_LB0hmemInit_scrbAllocAsWr — causes scrub engine to allocate as write for use with force_Istate_writes to perform memory initialization with valid ecc/scramble/clstate

3RW_LB0hforce_Istate_writes — Reserved Unused

2 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

1 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

0 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

3.4.19 CREDIT_CONTROL_REG

This register controls the credit values for DDRMC.

Bus: 2Device: 8Function: 0Offset: A0

Bit Attr Default Description 31:24 RO 0h Reserved (RSVD) — Reserved.

23:16 RW_LB 0h Snoop Credits per CHA (cr_snoop_credits_per_cha) — Snoop Credits per CHA

15:8 RW_LB 0h Write Credits per DDRMC (cr_write_credits_per_ddrmc) — Write Credits per DDRMC

7:0 RW_LB 0h Read Credits per DDRMC (cr_read_credits_per_ddrmc) — Read Credits per DDRMC

3.4.20 PXPENHCAP_KDMC

Bus: 2 Device: 8 Function: 0Offset: 100

Bit Attr Default Description 31:0 RO 0h PXPENHCAP (pxpenhcap) — PXPENHCAP register

3.4.21 rsp_func_mcctrl_err_inj_CFG

Error Injection Response Function This register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK

(MSR). The referenced Used Trigger-0/Use Trigger-1/Use Trigger-2 are being mapped as the followings: 01 - Use Trigger-0 from MCGLBRSPCNTL.GlbRsp0 10 - Use

Intel® Xeon Phi™ Processor 67 Datasheet - Volume 2, December 2016 Trigger-1 from MCGLBRSPCNTL.GlbRsp1 11 - Use Trigger-2 from MCGLBRSPCNTL.GlbRsp2 Please refer to Intel® Xeon® E5 v3 Product Family DFx related MAS document for further detail. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

Bus: 2 Device: 8 Function: 0Offset: 1D4

Bit Attr Default Description 31:16 RO 0h Reserved (RSVD) — Reserved.

15:14 RW_LV 0h rd_retry_inj_sel — Read Retry Error Injection Selection: 00-Don't Inject, 01-Use Trigger-0, 10-Use Trigger-1, 11-Use Trigger-2

13:12 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

11:10 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

9:8 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

7:4 RO 0h Reserved (RSVD) — Reserved.

3:2 RSVD-P 1h Reserved (RSVD-P) — Reserved - protected.

1:0 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

3.4.22 ddr_trace_throttle_ctl_CFG

DDR trace debug throttle control. Use this CSR to control the rate at which commands are sent to the WDB which is being used as a FIFO to prevent overflows.

Bus: 2 Device: 8 Function: 0Offset: 1D8

Bit Attr Default Description

31:15 RO 0h Reserved (RSVD) — Reserved.

14 RO_V 0h write_overflow — Data tracing write FIFO has lost sample data

13 RO_V 0h read_overflow — Data tracing read FIFO has lost sample data

12 RW_V 0h pwm_mode — Use PWM with period of read_fifo_thresh+1 and a stall duty cycle of write_fifo_thresh

11:6 RW_V 3Fh write_fifo_thresh — When the write data FIFO has more than write_fifo_thresh entires, stall the scheduler. To disable this function, set write_fifo_thresh to a value greater than decimal 39

5:0 RW_V 3Fh read_fifo_thresh — When the read data FIFO has more than read_fifo_thresh entires, stall the scheduler. To disable this function, set read_fifo_thresh to a value greater than decimal 39

3.4.23 mcwdb_chkn_bit_CFG

generated by critter 20_2_0x0f4

Bus: 2 Device: 8 Function: 0Offset: 1DC

Bit Attr Default Description 31:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB1hdis_ddrio_earlywdata — Disable sending write data early to DDRIO for anti cross talk logic; If 0, data will be sent early one Dclock so DDRIO has time to do cross talk cancellation logic. If set to 1, write data will be sent with normal timing and DDRIO will have no time to do cross talk cancellation logic.

68 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3.4.24 rsp_func_crc_err_inj_dev0_xor_msk_CFG

Error Injection Response Function on Address Match Write Data Error Injection. Associating registers: RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_CRC_ERR_INJ_EXTRA.CRC_ERR_INJ_DEV0_5_BITS and

CRC_ERR_INJ_DEV1_5_BITS In addition to LT lock, this register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK

(MSR). In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

Bus: Device: Function: 0 Offset: 1E0

Bit Attr Default Descripti

31:0 RW_LV 0h dev0_xor_msk — device 0 data inversion mask for error injection. Eight 4-bit values specify which bits of the nibble are inverted on each data cycle of a BL8 write. Bits 3:0 correspond to the first data cycle. In addition to LT lock, this register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND 3.4.25 rsp_func_crc_err_inj_dev1_xor_msk_CFG

CRC_ERR_INJ_DEV1_5_BITS In addition to LT lock, this register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK

(MSR). In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

Bus: 2 Device: 8 Function: 0 Offset: 1E4

Bit Attr Default Description

31:0 RW_LV 0h dev1_xor_msk — device 1 data inversion mask for error injection. Eight 4-bit values specify which bits of the nibble are inverted on each data cycle of a BL8 write. Bits 3:0 correspond to the first data cycle. In addition to LT lock, this register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK (MSR).

3.4.26 rsp_func_crc_err_inj_extra_CFG

Error Injection Response Function In addition to LT lock, this register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK

(MSR). In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

Intel® Xeon Phi™ Processor 69 Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 0Offset: 1E8

Bit Attr Default Description 31:30 RO 0h Reserved (RSVD) — Reserved.

29:28 RW_LV 3h crc_err_inj_chunk_dev1 — Error Injection Response Function on Address Match Write Data Error Injection. Associating registers: RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_ADDR_MATCH_LO&HI, These bits control whether the injection is performed on the upper or lower 64 chunk per Dclk. This is to allow device targeting for DDDC. 11: Default, same injection on both chunks 01: Inject only on lower chunk 10: Inject only on upper chunk 00: Reserved, will disable injection

27:26 RW_LV 3h crc_err_inj_chunk_dev0 — Error Injection Response Function on Address Match Write Data Error Injection. Associating registers: RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_ADDR_MATCH_LO&HI, These bits control whether the injection is performed on the upper or lower 64 chunk per Dclk. This is to allow device targeting for DDDC. 11: Default, same injection on both chunks 01: Inject only on lower chunk 10: Inject only on upper chunk 00: Reserved, will disable injection

25:24 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

23:18 RO 0h Reserved (RSVD) — Reserved.

17:16 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

15:13 RO 0h Reserved (RSVD) — Reserved.

12:8 RW_LV 0h crc_err_inj_dev1_5_bits — Error Injection Response Function on Address Match Write Data Error Injection. Associating registers: RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_CRC_ERR_INJ_DEV0_XOR_MSK and RSP_FUNC_CRC_ERR_INJ_DEV1_XOR_MSK Selects nibble of data bus for device 1 error injection. 0x0 selects DQ[3:0], 0x1 selects DQ[7:4], 0x17 selects ECC[7:4] and so forth. 0x18 - 0x31 are reserved. In addition to LT lock, this register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK (MSR).

7:5 RO 0h Reserved (RSVD) — Reserved.

4:0 RW_LV 0h crc_err_inj_dev0_5_bits — Error Injection Response Function on Address Match Write Data Error Injection. Associating registers: RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_ADDR_MATCH_LO&HI, RSP_FUNC_CRC_ERR_INJ_DEV0_XOR_MSK and RSP_FUNC_CRC_ERR_INJ_DEV1_XOR_MSK Selects nibble of data bus for error injection. 0x0 selects DQ[3:0], 0x1 selects DQ[7:4], 0x17 selects ECC[7:4] and so forth. 0x18 - 0x31 are reserved. In addition to LT lock, this register is locked by EPMCMAIN_DFX_LCK_CNTL.RSPLCK (uCR) AND MC_ERR_INJ_LCK.MC_ERR_INJ_LCK (MSR).

3.4.27 dft_rdret_control_CFG

controls DFT features for DDR data return path

70 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 0Offset: 24C

Bit Attr Default Description 31:15 RO 0h Reserved (RSVD) — Reserved.

14:10 RW_V 0h lfsr_seed — 00000 0x544a31c34562d8bd 00001 0xa731a0883bfe067c 00010 0x3538e4a7139fae94 00011 0xba07a1e9f08c03f6 00100 0x788af32dcfe2a68d 00101 0x4adbaba47e5c251f 00110 0x34eed8ff12ad115c 00111 0xfcc3d08a5b7cda8d 01000 0xf2ae1efd13815494 01001 0xa570857f1675a8a2 01010 0x13d5110591290d2f 01011 0x6789118327be202f 01100 0x7a391ddb84826998 01101 0xa54f30c8affc3169 10011 0xebbddca22a728039 10100 0x710151796a9f8981 10101 0x3512be901c6ae21d 10110 0xe2365ec374e91f47 10111 0x6a6f5c5c7cb74da8 11000 0x084d8ce28bff7215 11001 0x21aef5d1ded4cef2 11010 0xb9f9f2bd1692f3a4 11011 0x62bed2d667121de9 11100 0x8000000000000000 11101 0xffffffffffffffff 11110 0xaaaaaaaaaaaaaaaa 11111 0x5555555555555555 01110 0xd67b1c052b5af39e 01111 0xca46737a38285c24 10000 0x257c40d8e0a5c571 10001 0xe17f9ca88c1ccee5 10010 0xa70f03dd9d03a7de

9:8 RW_V 0h mode — 00= rdret_dft is disabled 01= rdret_dft is enabled with LFSR clocked on free running qclk. 10= rdret_dft is enabled with lfsr clocked on sample DDR. 11= rdret_dft is enabled with lfsr not clocked.

7:0 RW_V 0h ecc_bits — These bits will replace ecc bits coming back from pads when mode bits in this register are non_zero

3.4.28 demand_scrub_cfg

Bus: 2Device: 8Function: 0Offset: 250

Bit Attr Default Description 31:3 RO 0h Reserved (RSVD) — Reserved.

2RW_LB0hmeminit_credit_adjust — Reserved.

1RW_LB1hpatrol_writeback_en — Reserved.

0RW_LB1hdemand_scrub_en — Reserved.

Intel® Xeon Phi™ Processor 71 Datasheet - Volume 2, December 2016 3.4.29 x4modesel_CFG

x4ModelSel - MCDP x4 Mode Select

Bus: 2Device: 8Function: 0Offset: 280

Bit Attr Default Description 31:3 RO 0h Reserved (RSVD) — Reserved.

2RW_V0hdimm2_mode — Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM2 DQS select.

1RW_V0hdimm1_mode — Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM1 DQS select.

0RW_V0hdimm0_mode — Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM0 DQS select.

3.4.30 mc_tad0_limit_lo_CFG

TAD Decoder Range Limit value (lower half)

Bus: 2Device: 8Function: 0Offset: 400

Bit Attr Default Description

31:6 RW_LB 1h limit_lo — Bits 31:0 of TAD RANGE limit

5:3 RW_LB 5h edcIntlv — typedef enum bit[2:0] {edc8way, edc6way, edc4way, edc3way, edc2way, edc1way} edcIntlvT;

2:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB1henable — node enable;

3.4.31 mc_tad0_offset_lo_CFG

TAD Decoder Range Offset value (lower half)

Bus: 2Device: 8Function: 0Offset: 404

Bit Attr Default Description

31:6 RW_LB 0h offset_lo — Bits 31:0 of TAD OFFSET

5RO0hReserved (RSVD) — Reserved.

4:2 RW_LB 4h tadMode — Interleave Mode: 0 = quad, 1 = hemi, 2 = snc4, 3 = snc2, 4 = all2all

1RO0hReserved (RSVD) — Reserved.

0RW_LB0hmod3_mode — mod3_mode to select between target address generation

3.4.32 mc_tad0_limit_offset_hi_CFG

TAD Decoder Range Limit and Offset value (upper portion)

Bus: 2Device: 8Function: 0Offset: 408

Bit Attr Default Description 31:16 RW_LB 1h limit_hi — Bits 47:32 of TAD LIMIT

15:0 RW_LB 0h offset_hi — Bits 47:32 of TAD OFFSET

72 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3.4.33 mc_tad1_limit_lo_CFG

TAD Decoder Range Limit value (lower half)

Bus: 2Device: 8Function: 0Offset: 500

Bit Attr Default Description 31:6 RW_LB 0h limit_lo — Bits 31:0 of TAD RANGE limit

5:3 RW_LB 0h edcIntlv — typedef enum bit[2:0] {edc8way, edc6way, edc4way, edc3way, edc2way, edc1way} edcIntlvT;

2:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB0henable — node enable;

3.4.34 mc_tad1_offset_lo_CFG

TAD Decoder Range Offset value (lower half)

Bus: 2Device: 8 Function: 0 Offset: 504

Bit Attr Default Descripti

31:6 RW_LB 0h offset_lo — Bits 31:0 of TAD OFFSET

5RO0hReserved (RSVD) — Reserved.

4:2 RW_LB 4h tadMode — Interleave Mode: 0 = quad, 1 = hemi, 2 = snc4, 3 = snc2, 4 = all2all

1RO0hReserved (RSVD) — Reserved.

0 RW_LB 0h mod3_mode — mod3_mode to select between target address generation

3.4.35 mc_tad1_limit_offset_hi_CFG

TAD Decoder Range Limit and Offset value (upper portion)

Bus: 2Device: 8Function: 0Offset: 508

Bit Attr Default Description

31:16 RW_LB 0h limit_hi — Bits 47:32 of TAD LIMIT

15:0 RW_LB 0h offset_hi — Bits 47:32 of TAD OFFSET

3.4.36 mc_tad2_limit_lo_CFG

TAD Decoder Range Limit value (lower half)

Bus: 2Device: 8Function: 0Offset: 600

Bit Attr Default Description 31:6 RW_LB 0h limit_lo — Bits 31:0 of TAD RANGE limit

5:3 RW_LB 0h edcIntlv — typedef enum bit[2:0] {edc8way, edc6way, edc4way, edc3way, edc2way, edc1way} edcIntlvT;

2:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB0henable — node enable;

Intel® Xeon Phi™ Processor 73 Datasheet - Volume 2, December 2016 3.4.37 mc_tad2_offset_lo_CFG

TAD Decoder Range Offset value (lower half)

Bus: 2Device: 8Function: 0Offset: 604

Bit Attr Default Description 31:6 RW_LB 0h offset_lo — Bits 31:0 of TAD OFFSET

5RO0hReserved (RSVD) — Reserved.

4:2 RW_LB 4h tadMode — Interleave Mode: 0 = quad, 1 = hemi, 2 = snc4, 3 = snc2, 4 = all2all

1RO0hReserved (RSVD) — Reserved.

0RW_LB0hmod3_mode — mod3_mode to select between target address generation

3.4.38 mc_tad2_limit_offset_hi_CFG

TAD Decoder Range Limit and Offset value (upper portion)

Bus: 2Device: 8Function: 0Offset: 608

Bit Attr Default Description

31:16 RW_LB 0h limit_hi — Bits 47:32 of TAD LIMIT

15:0 RW_LB 0h offset_hi — Bits 47:32 of TAD OFFSET

3.4.39 mc_tad3_limit_lo_CFG

TAD Decoder Range Limit value (lower half)

Bus: 2Device: 8Function: 0Offset: 700

Bit Attr Default Description

31:6 RW_LB 0h limit_lo — Bits 31:0 of TAD RANGE limit

5:3 RW_LB 0h edcIntlv — typedef enum bit[2:0] {edc8way, edc6way, edc4way, edc3way, edc2way, edc1way} edcIntlvT;

2:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB0henable — node enable;

3.4.40 mc_tad3_offset_lo_CFG

TAD Decoder Range Offset value (lower half)

Bus: 2Device: 8Function: 0Offset: 704

Bit Attr Default Description 31:6 RW_LB 0h offset_lo — Bits 31:0 of TAD OFFSET

5RO0hReserved (RSVD) — Reserved.

4:2 RW_LB 4h tadMode — Interleave Mode: 0 = quad, 1 = hemi, 2 = snc4, 3 = snc2, 4 = all2all

1RO0hReserved (RSVD) — Reserved.

0RW_LB0hmod3_mode — mod3_mode to select between target address generation

74 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3.4.41 mc_tad3_limit_offset_hi_CFG

TAD Decoder Range Limit and Offset value (upper portion)

Bus: 2Device: 8Function: 0Offset: 708

Bit Attr Default Description 31:16 RW_LB 0h limit_hi — Bits 47:32 of TAD LIMIT

15:0 RW_LB 0h offset_hi — Bits 47:32 of TAD OFFSET

3.4.42 mc_tad4_limit_lo_CFG

TAD Decoder Range Limit value (lower half)

Bus: 2Device: 8Function: 0Offset: 800

Bit Attr Default Description

31:6 RW_LB 0h limit_lo — Bits 31:0 of TAD RANGE limit

5:3 RW_LB 0h edcIntlv — typedef enum bit[2:0] {edc8way, edc6way, edc4way, edc3way, edc2way, edc1way} edcIntlvT;

2:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB0henable — node enable;

3.4.43 mc_tad4_offset_lo_CFG

TAD Decoder Range Offset value (lower half)

Bus: 2Device: 8Function: 0Offset: 804

Bit Attr Default Description 31:6 RW_LB 0h offset_lo — Bits 31:0 of TAD OFFSET

5RO0hReserved (RSVD) — Reserved.

4:2 RW_LB 4h tadMode — Interleave Mode: 0 = quad, 1 = hemi, 2 = snc4, 3 = snc2, 4 = all2all

1RO0hReserved (RSVD) — Reserved.

0RW_LB0hmod3_mode — mod3_mode to select between target address generation

3.4.44 mc_tad4_limit_offset_hi_CFG

TAD Decoder Range Limit and Offset value (upper portion)

Bus: 2Device: 8Function: 0Offset: 808

Bit Attr Default Description 31:16 RW_LB 0h limit_hi — Bits 47:32 of TAD LIMIT

15:0 RW_LB 0h offset_hi — Bits 47:32 of TAD OFFSET

3.4.45 mc_tad5_limit_lo_CFG

TAD Decoder Range Limit value (lower half)

Intel® Xeon Phi™ Processor 75 Datasheet - Volume 2, December 2016 Bus: 2Device: 8Function: 0Offset: 900

Bit Attr Default Description 31:6 RW_LB 0h limit_lo — Bits 31:0 of TAD RANGE limit

5:3 RW_LB 0h edcIntlv — typedef enum bit[2:0] {edc8way, edc6way, edc4way, edc3way, edc2way, edc1way} edcIntlvT;

2:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB0henable — node enable;

3.4.46 mc_tad5_offset_lo_CFG

TAD Decoder Range Offset value (lower half)

Bus: 2Device: 8Function: 0Offset: 904

Bit Attr Default Description

31:6 RW_LB 0h offset_lo — Bits 31:0 of TAD OFFSET

5RO0hReserved (RSVD) — Reserved.

4:2 RW_LB 4h tadMode — Interleave Mode: 0 = quad, 1 = hemi, 2 = snc4, 3 = snc2, 4 = all2all

1RO0hReserved (RSVD) — Reserved.

0RW_LB0hmod3_mode — mod3_mode to select between target address generation

3.4.47 mc_tad5_limit_offset_hi_CFG

TAD Decoder Range Limit and Offset value (upper portion)

Bus: 2Device: 8Function: 0Offset: 908

Bit Attr Default Description 31:16 RW_LB 0h limit_hi — Bits 47:32 of TAD LIMIT

15:0 RW_LB 0h offset_hi — Bits 47:32 of TAD OFFSET

3.4.48 mc_tad6_limit_lo_CFG

TAD Decoder Range Limit value (lower half)

Bus: 2Device: 8Function: 0Offset: A00

Bit Attr Default Description 31:6 RW_LB 0h limit_lo — Bits 31:0 of TAD RANGE limit

5:3 RW_LB 0h edcIntlv — typedef enum bit[2:0] {edc8way, edc6way, edc4way, edc3way, edc2way, edc1way} edcIntlvT;

2:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB0henable — node enable;

3.4.49 mc_tad6_offset_lo_CFG

TAD Decoder Range Offset value (lower half)

76 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2Device: 8Function: 0Offset: A04

Bit Attr Default Description 31:6 RW_LB 0h offset_lo — Bits 31:0 of TAD OFFSET

5RO0hReserved (RSVD) — Reserved.

4:2 RW_LB 4h tadMode — Interleave Mode: 0 = quad, 1 = hemi, 2 = snc4, 3 = snc2, 4 = all2all

1RO0hReserved (RSVD) — Reserved.

0RW_LB0hmod3_mode — mod3_mode to select between target address generation

3.4.50 mc_tad6_limit_offset_hi_CFG

TAD Decoder Range Limit and Offset value (upper portion)

Bus: 2Device: 8Function: 0Offset: A08

Bit Attr Default Description

31:16 RW_LB 0h limit_hi — Bits 47:32 of TAD LIMIT

15:0 RW_LB 0h offset_hi — Bits 47:32 of TAD OFFSET

3.4.51 mc_tad7_limit_lo_CFG

TAD Decoder Range Limit value (lower half)

Bus: 2Device: 8Function: 0Offset: B00

Bit Attr Default Description 31:6 RW_LB 0h limit_lo — Bits 31:0 of TAD RANGE limit

5:3 RW_LB 0h edcIntlv — typedef enum bit[2:0] {edc8way, edc6way, edc4way, edc3way, edc2way, edc1way} edcIntlvT;

2:1 RO 0h Reserved (RSVD) — Reserved.

0RW_LB0henable — node enable;

3.4.52 mc_tad7_offset_lo_CFG

TAD Decoder Range Offset value (lower half)

Bus: 2Device: 8Function: 0Offset: B04

Bit Attr Default Description 31:6 RW_LB 0h offset_lo — Bits 31:0 of TAD OFFSET

5RO0hReserved (RSVD) — Reserved.

4:2 RW_LB 4h tadMode — Interleave Mode: 0 = quad, 1 = hemi, 2 = snc4, 3 = snc2, 4 = all2all

1RO0hReserved (RSVD) — Reserved.

0RW_LB0hmod3_mode — mod3_mode to select between target address generation

3.4.53 mc_tad7_limit_offset_hi_CFG

TAD Decoder Range Limit and Offset value (upper portion)

Intel® Xeon Phi™ Processor 77 Datasheet - Volume 2, December 2016 Bus: 2Device: 8Function: 0Offset: B08

Bit Attr Default Description 31:16 RW_LB 0h limit_hi — Bits 47:32 of TAD LIMIT

15:0 RW_LB 0h offset_hi — Bits 47:32 of TAD OFFSET

3.4.54 mc_tag_mask_lo_CFG

Tag Mask

Bus: 2Device: 8Function: 0Offset: C00

Bit Attr Default Description 31:6 RW_LB 4000h mask_lo —

5:0 RO 0h Reserved (RSVD) — Reserved.

3.4.55 mc_tag_mask_hi_CFG

Tag Mask

Bus: 2Device: 8Function: 0Offset: C04

Bit Attr Default Description 31:16 RO 0h Reserved (RSVD) — Reserved.

15:0 RW_LB 0h mask_hi —

3.4.56 controller_throttle_reg

Controller throttle register.

Bus: 2 Device: 8 Function: 0 Offset: C80

Bit Attr Default Description 31:0 RW_LB FFFFFFFFh cr_controller_throttle_register — Used to control throttle in the controller (kdmc).

3.4.57 errinj_addr_lo_reg

Error Injection register.

Bus: 2 Device: 8 Function: 0 Offset: D00

Bit Attr Default Description 31:0 RW_LV 0h errinj_addr_lo — Error Injection Address. sys_addr[45:6] = {errInj_addr_hi[7:0],errInj_addr_lo[31:0]}. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

3.4.58 errinj_addr_hi_reg

Error Injection register.

78 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 0Offset: D04

Bit Attr Default Description 31:18 RO 0h Reserved (RSVD) — Reserved.

17:16 RW_LV 0h errinj_target_ph — Error Injection Phase. Select which data phase to inject error at targeted address. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

15:9 RO 0h Reserved (RSVD) — Reserved.

8RW_LV0herrinj_target_en — Error Injection for targeted address enable bit. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

7:0 RW_LV 0h errinj_addr_hi — Error Injection Address. sys_addr[45:6] = {errInj_addr_hi[7:0],errInj_addr_lo[31:0]}. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

3.4.59 errinj_mask_lo_reg

Error Injection register.

Bus: 2 Device: 8 Function: 0 Offset: D08

Bit Attr Default Description

31:0 RW_LV 0h errinj_mask_lo — Error Injection Address Mask. errInj_mask[45:6] = {errInj_mask_hi[7:0],errInj_mask_lo[31:0]}. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

3.4.60 errinj_mask_hi_reg

Error Injection register.

Bus: 2 Device: 8 Function: 0Offset: D0C

Bit Attr Default Description

31:8 RO 0h Reserved (RSVD) — Reserved.

7:0 RW_LV 0h errinj_mask_hi — Error Injection Address Mask. errInj_mask[45:6] = {errInj_mask_hi[7:0],errInj_mask_lo[31:0]}. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

3.4.61 errinj_lfsr_reg

Error Injection lfsr register. By programming the register, user can inject error at 'randomly'

Intel® Xeon Phi™ Processor 79 Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 0Offset: D10

Bit Attr Default Description 31 RW_LV 0h errinj_random_en — Error Injection for targeted address enable bit. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

30 RO 0h Reserved (RSVD) — Reserved.

29:28 RW_LV 0h errinj_random_ph — Error Injection Phase. Select which data phase to inject error at targeted address In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

27:21 RO 0h Reserved (RSVD) — Reserved.

20 RW_LV 0h errinj_lfsrload — Error Injection Phase. Select which data phase to inject error at targeted address. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

19:18 RO 0h Reserved (RSVD) — Reserved.

17:0 RW_LV 0h errinj_lfsrseed — Error Injection Phase. Select which data phase to inject error at targeted address. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

3.4.62 errinj_limit_reg

Error Injection limit register. Restrict the number of errors injected. If en_errInj_cntr is set to 0, then there is no limit on the number of errors injected. If en_errInj_ctnr is set to 0, then after the errInj_cntr hits errInj_err_limit we stops injecting error.

Bus: 2 Device: 8 Function: 0Offset: D14

Bit Attr Default Description

31:16 RO 0h Reserved (RSVD) — Reserved.

15:8 RW_LV 0h errinj_err_limit — Enable Error Injection counter limit. In Intel® Xeon Phi™ Processor, this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

7:3 RO 0h Reserved (RSVD) — Reserved.

2RW_LV0herrinj_hit_err_limit — error injection has hit the limit set by errInj_err_limit. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

1RW_LV0hclear_errinj_cntr — Clear Error Injection counter. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

0RW_LV0hen_errinj_cntr — Enable Error Injection counter. The counter will increment if an error were injected to a specific address. In Intel® Xeon Phi™ Processor this is locked by mc_err_inj_lck.mc_err_inj_lck. If the lock bit is 1 this register is locked.

3.5 Bus: 2, Device: 8, Function: 1 (CFG)

80 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Table 3-7. Summary of Bus: 2, Device: 8, Function: 1 (CFG)

Offset Size Register Name (Register Symbol) Default (Bytes) Value

0–1h 2 “VID_2_8_1_CFG” on page 81 8086h

2–3h 2 “DID_2_8_1_CFG” on page 81 7842h

4–5h 2 “PCICMD_2_8_1_CFG” on page 82 0h

6–7h 2 “PCISTS_2_8_1_CFG” on page 82 10h

8–8h 1 “RID_2_8_1_CFG” on page 83 0h

9–Bh 3 “CCR_2_8_1_CFG” on page 83 88000h

C–Ch 1 “CLSR_2_8_1_CFG” on page 84 0h

D–Dh 1 “PLAT_2_8_1_CFG” on page 84 0h

E–Eh 1 “HDR_2_8_1_CFG” on page 84 80h

F–Fh 1 “BIST_2_8_1_CFG” on page 84 0h

2C–2Fh 4 “SVID_MCXKDMISC_CFG” on page 84 8086h

34–34h 1 “CAPPTR_2_8_1_CFG” on page 84 40h

3C–3Ch 1 “INTL_2_8_1_CFG” on page 85 0h

3D–3Dh 1 “INTPIN_2_8_1_CFG” on page 85 0h

3E–3Eh 1 “MINGNT_2_8_1_CFG” on page 85 0h

3F–3Fh 1 “MAXLAT_2_8_1_CFG” on page 85 0h

40–43h 4 “PXPCAP_KDMISC” on page 85 920010h

100–103h 4 “PXPENHCAP_KDMISC” on page 86 0h

200–203h 4 “mc_init_state_g” on page 86 102h

210–213h 4 “rcomp_timer” on page 87 700h

214–217h 4 “dly_pma_cmp_done_timer” on page 87 1C20h

890–893h 4 “mh_min_asrt_cntr_cfg” on page 87 0h

89C–89Fh 4 “mh_chn_astn_cfg” on page 88 8h

3.5.1 VID_2_8_1_CFG

PCI Vendor ID Register

Bus: 2 Device: 8 Function: 1 Offset: 0

Bit Attr Default Description 15:0 RO 8086h Vendor Identification Number (Vendor_Identification_Number) — The value is assigned by PCI-SIG to Intel.

3.5.2 DID_2_8_1_CFG

PCI Device Identification Number

Intel® Xeon Phi™ Processor 81 Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 1 Offset: 2

Bit Attr Default Description 15:0 RO 7842h Device_Identification_Number — Device ID values vary from function to function. Please refer to register EDS for the breakdown of DID in function groups and individual assignments for different types of functions for Intel® Xeon Phi™ Processor.

3.5.3 PCICMD_2_8_1_CFG

PCI Command Register

Bus: 2Device: 8Function: 1Offset: 4

Bit Attr Default Description 15:11 RO 0h Reserved (RSVD) — Reserved.

10 RO 0h INTx_Disable — N/A for these devices

9RO0hFast_Back_to_Back_Enable — Not applicable to PCI Express and is hardwired to 0

8RO0hSERR_Enable — This bit has no impact on error reporting from these devices

7RO0hIDSEL_Stepping_Wait_Cycle_Control — Not applicable to internal devices. Hardwired to 0.

6RO0hParity_Error_Response — This bit has no impact on error reporting from these devices

5RO0hVGA_palette_snoop_Enable — Not applicable to internal devices. Hardwired to 0.

4RO0hMemory_Write_and_Invalidate_Enable — Not applicable to internal devices. Hardwired to 0.

3RO0hSpecial_Cycle_Enable — Not applicable. Hardwired to 0.

2RO0hBus_Master_Enable — Hardwired to 0 since these devices don't generate any transactions

1RO0hMemory_Space_Enable — Hardwired to 0 since these devices don't decode any memory BARs

0RO0hIO_Space_Enable — Hardwired to 0 since these devices don't decode any IO BARs

3.5.4 PCISTS_2_8_1_CFG

PCI Status Register

Bus: 2 Device: 8 Function: 1 Offset: 6

14 RO 0h Signaled_System_Error — Hardwired to 0

13 RO 0h Received_Master_Abort — Hardwired to 0

12 RO 0h Received_Target_Abort — Hardwired to 0

11 RO 0h Signaled_Target_Abort — Hardwired to 0

10:9 RO 0h DEVSEL_Timing — Not applicable to PCI Express. Hardwired to 0.

82 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 1 Offset: 6

Bit Attr Default Description 8RO0hMaster_Data_Parity_Error — Hardwired to 0

7RO0hFast_Back_to_Back — Not applicable to PCI Express. Hardwired to 0.

6RO0hReserved — Reserved

5RO0hx66MHz_capable — Not applicable to PCI Express. Hardwired to 0.

4RO1hCapabilities_List — This bit indicates the presence of a capabilities list structure. When set to 1, indicates the register at 34h provides an offset into the function.4

2:0 RO 0h Reserved (RSVD) — Reserved.

3.5.5 RID_2_8_1_CFG

“PCIe header Revision ID register”

Bus: Device: Function: 1 Offset: 8

Bit Attr Default Descripti

PCIe header Class Code register

Bus: 2 Device: 8 Function: 1 Offset: 9

Bit Attr Default Description

7:0 RO_V 0h register_level_programming_interface — Reserved.

Intel® Xeon Phi™ Processor 83 Datasheet - Volume 2, December 2016 3.5.7 CLSR_2_8_1_CFG

PCI Cache Line Size Register

Bus: 2 Device: 8 Function: 1 Offset: C

Bit Attr Default Description 7:0 RO 0h Cacheline Size (Cacheline_Size) — Size of Cacheline

3.5.8 PLAT_2_8_1_CFG

PCI Latency Timer

Bus: 2 Device: 8 Function: 1 Offset: D

Bit Attr Default Description 7:0 RO 0h Primary_Latency_Timer — Not applicable to PCI-Express. Hardwired to 00h.

3.5.9 HDR_2_8_1_CFG

PCI Header Type

Bus: 2Device: 8Function: 1Offset: E

Bit Attr Default Description

7RO1hMulti_function_Device — This bit defaults to 1b since all these devices are multifunction

6:0 RO 0h configuration_layout — Type 0 header

3.5.10 BIST_2_8_1_CFG

PCI BIST Register

Bus: 2 Device: 8 Function: 1 Offset: F

Bit Attr Default Description

7:0 RO 0h BIST_Tests — Not supported. Hardwired to 00h

3.5.11 SVID_MCXKDMISC_CFG

PCI Subsystem Vendor ID Register

Bus: 2Device: 8Function: 1Offset: 2C

Bit Attr Default Description 31:16 RW_OV 0h SDID — The default value specifies Intel but can be set to any value once after reset.

15:0 RW_OV 8086h Subsystem_Vendor_Identification_Number (SVID) — The default value specifies Intel but can be set to any value once after reset.

3.5.12 CAPPTR_2_8_1_CFG

PCI Capability Pointer Register

84 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 2 Device: 8 Function: 1 Offset: 34

Bit Attr Default Description 7:0 RO 40h Capability_Pointer — Points to the first capability structure for the device which is the PCIe capability.

3.5.13 INTL_2_8_1_CFG

PCI Interrupt Line Register

Bus: 2 Device: 8 Function: 1 Offset: 3C

Bit Attr Default Description 7:0 RO 0h Interrupt_Line — N/A for these devices

3.5.14 INTPIN_2_8_1_CFG

PCI Interrupt Pin Register

Bus: 2 Device: 8 Function: 1 Offset: 3D

Bit Attr Default Description

7:0 RO 0h Interrupt_Pin — N/A since these devices do not generate any interrupt on their own

3.5.15 MINGNT_2_8_1_CFG

PCI Min Grant Register

Bus: 2 Device: 8 Function: 1 Offset: 3E

Bit Attr Default Description 7:0 RO 0h MGV — The device does not burst as a PCI compliant master.

3.5.16 MAXLAT_2_8_1_CFG

PCI Max Latency Register

Bus: 2 Device: 8 Function: 1 Offset: 3F

Bit Attr Default Description 7:0 RO 0h MLV — The device has no specific requirements for how often it needs to access the PCI bus.

3.5.17 PXPCAP_KDMISC

Intel® Xeon Phi™ Processor 85 Datasheet - Volume 2, December 2016 Attr=RO, Default=0, Next Capability Pointer. Set to 0 to indicate there are no more capability structures. Bits 7:0, Attr=RO, Default=10h, Capability ID. Indicates the capability structure is for a PCI Express Capability as assigned by PCI-SIG.

Bus: 2 Device: 8 Function: 1Offset: 40

Bit Attr Default Description 31:0 RO 920010h PXPCAP (pxpcap) — PXPCAP register

3.5.18 PXPENHCAP_KDMISC

Bus: 2 Device: 8 Function: 1Offset: 100

Bit Attr Default Description

31:0 RO 0h PXPENHCAP (pxpenhcap) — PXPENHCAP register

3.5.19 mc_init_state_g

This register defines the high-level behavior in CPGC mode. It defines the DDR reset pin value, DCLK enable, refresh enable and bits indicating the MRC status T.

Bus: 2 Device: 8 Function: 1Offset: 200

Bit Attr Default Description

31:13 RO 0h Reserved (RSVD) — Reserved.

12:9 RWS_LV 0h cs_oe_en — Reserved.

8RWS_LV1hsafe_sr — This bit indicates if it is safe to keep the MC in SR during MC-reset. If it is clear when reset occurs, it means that the reset is without warning and the DDR-reset should be asserted. If set when reset occurs, it indicates that DDR is already in SR and it can keep it this way. This bit can also indicate MRC if reset without warning has occurred, and if it has, cold-reset flow should be selected Note to MRC BIOS: clear this bit at MRC entry. Note to PCODE: set this bit during reset-warn flow after In_SR assertion.

7RW_LV0hmrc_done — Reserved.

6:4 RO 0h Reserved (RSVD) — Reserved.

3RW_LV0hrefresh_enable — Refresh enable If cold reset, this bit should be set by BIOS after Initializing the refresh timing parameters Running DDR through reset and init sequence If warm reset or S3 exit, this bit should be set immediately after SR exit 2RW_LV0hdclk_enable — DCLK Enable (for all channels)

1RW_LV1hddr_reset — DDR reset for all DIMMs from all channels within this socket. No IMC/ DDRIO logic is reset by asserting this register. It is important to note that this bit is negative logic! that is, writing 0 to induce a reset and write 1 for not reset.

0RO0hReserved (RSVD) — Reserved.

86 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 3.5.20 rcomp_timer

Defines the time from IO starting to run RCOMP evaluation until RCOMP results are ready. This counter is added in order to keep determinism of the process if operated in different modes The register also indicates that first RCOMP has been done - required by BIOS.

Bus: 2 Device: 8 Function: 1Offset: 210

Bit Attr Default Description 31 RW_LB 0h rcomp_in_progress — set on start condition, cleared when MC generates compUpdate signals (after DDRIO generated a compDone indicator)

30 RW_LB 0h rcomp — RCOMP start via message channel control for BIOS. RCOMP start only triggered when the register bit output is changing from 0 -> 1 MC will not be responsible for clearing this bit. MC already provides feedback to bias when Rcomp is done via first_rcomp_done bit field.

29:19 RO 0h Reserved (RSVD) — Reserved.

18 RW_LB 0h frc_rcomp_cmp_ack — Force rcomp completion ack (force a compDone as if from DDRIO)

17 RW_LB 0h dis_rcomp — gate off compStart to DDRIO

16 RW_LB 0h first_rcomp_done — This is a status bit that indicates the first RCOMP has been completed. It is cleared on reset, and set by MC HW when the first RCOMP is completed. BIOS should wait until this bit is set before executing any DDR command Locked by the inverted output of MCMAIN.PSMI_QSC_CNTL.FORCERW

15:0 RW_LB 700h count — DCLK cycle count that MC needs to wait from the point it has triggered RCOMP evaluation until it can trigger the load to registers, a non-zero value will force compUpdates, a zero value will let MC schedule compUpdates naturally as it detects TX not driven for cmd and dq/dqs

3.5.21 dly_pma_cmp_done_timer

Bus: 2Device: 8Function: 1Offset: 214

Bit Attr Default Description

31:13 RO 0h Reserved (RSVD) — Reserved.

12:0 RW_V 1C20h dly_pma_cmp_done_timer — Delay reporting pma rcomp done to PMA

3.5.22 mh_min_asrt_cntr_cfg

MEMHOT# Minimum Assertion Time Current Count in number of CNTR_500_NANOSEC.

Bus: 2 Device: 8 Function: 1Offset: 890

Bit Attr Default Description 31:12 RO 0h Reserved (RSVD) — Reserved.

11:0 RO_V 0h mh_min_asrtn_cntr — MEMHOT# Minimum Assertion Time Current Count in number of CNTR_500_NANOSEC (decrement by 1 every CNTR_500_NANOSEC). When the counter is zero, the counter is remain at zero and it is only loaded with MH_MIN_ASRTN only when MH_DUTY_CYC_PRD_CNTR is reloaded. Not affected by the PSMI quiescence. PSMI quiescence must wait until MH_MIN_ASRTN_CNTR has decremented to zero.

Intel® Xeon Phi™ Processor 87 Datasheet - Volume 2, December 2016 3.5.23 mh_chn_astn_cfg

MemHot# Channel Association bits and Channel IDs within MEMHOT domain.

Bus: 2 Device: 8 Function: 1Offset: 89C

Bit Attr Default Description 31:4 RO 0h Reserved (RSVD) — Reserved.

3:0 RO 8h mh_chn_astn — MemHot# Channel Association bit 3: is valid bit. Note: Valid bit means the association is valid and it does not implies the channel is populated or exist. bit 2-0: 1st channel ID within this MEMHOT domain Note: This register is hardcoded in design. It is read-accessible by firmware. Design must make sure this register is not removed by downstream tools.

88 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 4 Power Control Unit (PCU) Registers

The processors Power Control Unit (PCU) is a dedicated controller that provides power and thermal management for the processor. The PCU implements a PECI interface for out-of-band management. The PCU consists of a dedicated microcontroller, ROM and RAM for pcode (PCU microcode), HW state machines; I/O registers for interfacing to the microcontroller and interfaces to the hardware units in the processor.

PCU configuration register space is located in: • Bus 1, Device 30, Function 0-6

4.1 Bus: 1, Device: 30, Function: 0 (CFG)

Table 4-1. Summary of Bus: 1, Device: 30, Function: 0 (CFG)

Offset Size Register Name (Register Symbol) Default Value (Bytes)

11C–11Fh 4 “SMB_TSOD_POLL_RATE_CNTR_1” on page 92 0h

120–123h 4 “SMB0_PERIOD_CFG” on page 92 445C2AF8h

124–127h 4 “SMB1_PERIOD_CFG” on page 93 445C2AF8h

128–12Bh 4 “SMB0_TLOW_TIMEOUT_CNTR” on page 93 0h

12C–12Fh 4 “SMB1_TLOW_TIMEOUT_CNTR” on page 93 0h

130–133h 4 “SMB_PERIOD_CNTR” on page 94 0h

134–137h 4 “SMB0_TSOD_POLL_RATE” on page 94 7D0h

138–13Bh 4 “SMB1_TSOD_POLL_RATE” on page 94 7D0h

140–143h 4 “SMB1_TLOW_TIMEOUT_CNTR” on page 93 0h

144–147h 4 “SMB0_TSOD_SAMPLE_4_7” on page 95 0h

148–14Bh 4 “SMB1_TSOD_SAMPLE_0_3” on page 96 0h

14C–14Fh 4 “SMB1_TSOD_SAMPLE_4_7” on page 96 0h

4.1.1 SMB_TSOD_POLL_RATE_CNTR_0

TSOD poll rate counter

Bus: 1 Device: Function: 0Offset: 10C

Bit Attr Default Description 31:18 RO 0h Reserved (RSVD) — Reserved.

17:0 RO_V 0h TSOD poll rate counter (SMB_TSOD_POLL_RATE_CNTR) — TSOD poll rate counter. When it is decremented to zero, reset to zero or written to zero, SMB_TSOD_POLL_RATE value is loaded into this counter and appear the updated value in the next FCLK.

Intel® Xeon Phi™ Processor 89 Datasheet - Volume 2, December 2016 4.1.2 SMB_STAT_1

This register provides the interface to the SMBus/I2C (SCL and SDA signals) that is used to access the Serial Presence Detect EEPROM or Thermal Sensor on DIMM (TSOD) that defines the technology, configuration, and speed of the DIMMs controlled by PCU. All bits represents status for SMBus-1

Bus: 1 Device: Function: 0 Offset: 110

Bit Attr Default Description 31 RO_V 0h SMBus Read Data Valid (SMB_RDO) — This bit is set by PCU (Read Data Valid Status) when the Data field of this register receives read data from the SPD/TSOD after completion of an SMBus read command. It is cleared by PCU when a subsequent SMBus read command is issued.

30 RO_V 0h Write Operation Done (SMB_WOD) — This bit is set by PCU when a SMBus Write command has been completed on the SMBus. It is cleared by PCU when a subsequent SMBus Write command is issued.

29 RO_V 0h SMBus Error (SMB_SBE) — This bit is set by PCU if an SMBus transaction (including the TSOD polling or message channel initiated SMBus access) that does not complete successfully (non-Ack has been received from slave at expected Ack slot of the transfer). If a slave device is asserting clock stretching, PCU does not have logic to detect this condition to set the SBE bit directly; however, the SMBus master will detect the error at the corresponding transaction's expected ACK slot.

28 ROS_V 0h SMBus busy state (SMB_BUSY) — SMBus Busy state. This bit is set by PCU while an SMBus/I2C command (including TSOD command issued from PCU hardware) is executing. Any transaction that is completed normally or gracefully will clear this bit automatically. By setting the SMB_SOFT_RST will also clear this bit. This register bit is sticky across reset so any surprise reset during pending SMBus operation will sustain the bit assertion across surprised warm-reset. BIOS reset handler can read this bit before issuing any SMBus transaction to determine whether a slave device may need special care to force the slave to idle state (e.g. via clock override toggling (SMB_CKOVRD) and/or via induced time-out by asserting SMB_CKOVRD for 25- 35ms).

27 RO 0h Reserved (RSVD) — Reserved.

26:24 RO_V 7h TSOD slave address (TSOD_SA) — This field captures the last issued TSOD slave address. Since this field only captures the TSOD polling slave address. During SMB error handling, software should check the hung SMB_TSOD_POLL_EN state before disabling the SMB_TSOD_POLL_EN in order to qualify whether this field is valid.

23:16 RO 0h Reserved (RSVD) — Reserved.

15:0 RO_V 0h SMbus read data (SMB_RDATA) — Read DataHolds data read from SMBus Read commands. Since TSOD/EEPROM are I2C devices and the byte order is MSByte first in a word read, reading of I2C using word read should return SMB_RDATA[15:8]=I2C_MSB and SMB_RDATA[7:0]=I2C_LSB. If reading of I2C using byte read, the SMB_RDATA[15:8]=dont care; SMB_RDATA[7:0]=read_byte. If we have a SMB slave connected on the bus, reading of the SMBus slave using word read should return SMB_RDATA[15:8]=SMB_LSB and SMB_RDATA[7:0]=SMB_MSB. If the software is not sure whether the target is I2C or SMBus slave, please use byte access.

4.1.3 SMBCMD_1

A write to this register initiates a DIMM EEPROM access through the SMBus/I2C.

90 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 0 Offset: 114

Bit Attr Default Description 31 RW_V 0h SMbus command trigger (SMB_CMD_TRIGGER) — CMD trigger: After setting this bit to 1, the SMBus master will issue the SMBus command using the other fields written in SMBCMD_[0:1] and SMBCntl_[0:1]. Note: the '-V' in the attribute implies the hardware will reset this bit when the SMBus command is being started.

30 RWS 0h SMbus pointer select (SMB_PNTR_SEL) — Pointer Selection: SMBus/I2C present pointer based access enable when set; otherwise, use random access protocol. Hardware based TSOD polling will also use this bit to enable the pointer word read. Important Note: The processor hardware based TSOD polling can be configured with pointer based access. If software manually issue SMBus transaction to other address, that is, changing the pointer in the slave device, it is software's responsibility to restore the pointer in each TSOD before returning to hardware based TSOD polling while keeping the SMB_PNTR_SEL=1.

29 RWS 0h SMbus word access (SMB_WORD_ACCESS) — word access: SMBus/I2C word (2B) access when set; otherwise, it is a byte access.

28 RWS 0h SMBus write pointer (SMB_WRT_PNTR) — Bit[28:27]=00: SMBus Read Bit[28:27]=01: SMBus Write Bit[28:27]=10: illegal combination Bit[28:27]=11: Write to pointer register SMBus/I2C* pointer update (byte). bit 30, and 29 are ignored. Note: SMBCntl_[0:1][26] will NOT disable WrtPntr update command.

27 RWS 0h SMbus write command (SMB_WRT_CMD) — When '0', it's a read command When '1', it's a write command

26:24 RWS 0h SMBus Slave Address (SMB_SA) — Slave Address: This field identifies the DIMM SPD/ TSOD to be accessed.

23:16 RWS 0h SMbus Bus Transaction Address (SMB_BA) — Bus Txn Address: This field identifies the bus transaction address to be accessed. Note: in WORD access, 23:16 specifies 2B access address. In Byte access, 23:16 specified 1B access address.

15:0 RWS 0h SMbus write data (SMB_WDATA) — Write Data: Holds data to be written by SPDW commands. Since TSOD/EEPROM are I2C devices and the byte order is MSByte first in a word write, writing of I2C using word write should use SMB_WDATA[15:8]=I2C_MSB and SMB_WDATA[7:0]=I2C_LSB. If writing of I2C using byte write, the SMB_WDATA[15:8]=dont care; SMB_WDATA[7:0]=write_byte. If we have a SMB slave connected on the bus, writing of the SMBus slave using word write should use SMB_WDATA[15:8]=SMB_LSB and SMB_WDATA[7:0]=SMB_MSB. It is software responsibility to figure out the byte order of the slave access.

4.1.4 SMBCNTL_1

SMBus operation control register

Bus: 1 Device: Function: 0Offset: 118

Bit Attr Default Description 31:28 RWS Ah Device Type Identifier (SMB_DTI) — Device Type Identifier: This field specifies the device type identifier. Only devices with this device-type will respond to commands. '0011' specifies TSOD. '1010' specifies EEPROM's. '0110' specifies a write-protect operation for an EEPROM. Other identifiers can be specified to target non-EEPROM devices on the SMBus. Note: PCU based hardware TSOD polling uses hardcoded DTI. Changing this field has no effect on the hardware based TSOD polling.

Intel® Xeon Phi™ Processor 91 Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 0Offset: 118

Bit Attr Default Description 27 RWS_V 1h clock override (SMB_CKOVRD) — Clock Override '0' = Clock signal is driven low, overriding writing a '1' to CMD. '1' = Clock signal is released high, allowing normal operation of CMD. Toggling this bit can be used to 'budge' the port out of a 'stuck' state. Software can write this bit to 0 and the SMB_SOFT_RST to 1 to force hung SMBus controller and the SMB slaves to idle state without using power good reset or warm reset. Note: software need to set the SMB_CKOVRD back to 1 after 35ms in order to force slave devices to time-out in case there is any pending transaction. The corresponding SMB_STAT_x.SMB_SBE error status bit may be set if there was such pending transaction time-out (non-graceful termination). If the pending transaction was a write operation, the slave device content may be corrupted by this clock override operation. A subsequent SMB command will automatically cleared the SMB_SBE. PCU added SMBus time-out control timer. When the time-out control timer expired, the SMB_CKOVRD# will “de-assert”, that is, return to 1 value.

26 RW_LB 1h Disable SMBus Write (SMB_DIS_WRT) — Writing a '0' to this bit enables CMD to be set to 1; Writing a 1 to force CMD bit to be always 0, that is, disabling SMBus write. This bit can only be written in SMMode. SMBus Read is not affected. I2C Write Pointer Update Command is not affected. Important Note to BIOS: Since BIOS is the source to update SMBCNTL_x register initially after reset, it is important to determine whether the SMBus can have write capability before writing any upper bits (bit24-31) via byte-enable config write (or writing any bit within this register via 32b config write) within the SMBCNTL register.

25:24 RO 0h Reserved (RSVD) — Reserved.

23 RW 0h SMbus error recovery enable (SMB_SBE_EN) — SMBus error recovery enable if set.

22 RW 0h smb_sbe_smi_en (SMB_SBE_SMI_EN) — Enable SMI generation when SMB_SBE is 0 1. 21 RW 0h smb_sbe_err0_en (SMB_SBE_ERR0_EN) — Enable ERR0 assertion when SMB_SBE is 0 . 20:11 RO 0h Reserved (RSVD) — Reserved.

9RW_V0hstart_tsod_poll (START_TSOD_POLL) — This bit starts the reading of all enabled devices Note that the hardware will reset this bit when the SMBus polling has started.

4.1.5 SMB_TSOD_POLL_RATE_CNTR_1

TSOD poll rate counter

Bus: 1 Device: Function: 0Offset: 11C

Bit Attr Default Description 31:18 RO 0h Reserved (RSVD) — Reserved.

4.1.6 SMB0_PERIOD_CFG

SMBus-0 Clock Period Configuration

92 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 0Offset: 120

Bit Attr Default Description 31:16 RWS 445Ch smb0_tlow_timeout (SMB0_TLOW_TIMEOUT) — Upper 16b of the 18b SMBus Time-Out Timer Configuration in unit of SPDTOP_500NS_CFG.CNFG_500_NANOSEC. The lower 2b of the 18b counter config is always 00. Assuming the CNFG_500_NANOSEC is set at 500ns: For 35ms time out, please configure this register to 445C For 65ms time out, please configure this register to 7EF4

15:0 RWS_O 2AF8h smb0_clk_prd (SMB0_CLK_PRD) — This field specifies both SMBus Clock in number of FCLK. Note: In order to generate a 50% duty cycle SCL, half of the SMB_CLK_PRD is used to generate SCL high. SCL must stay low for at least another half of the SMB_CLK_PRD before pulling high. It is recommend to program an even value in this field since the hardware is simply doing a right shift for the divided by 2 operation. Note the 100KHz SMB_CLK_PRD default value is calculated based on 1.1Ghz FCLK.

4.1.7 SMB1_PERIOD_CFG

SMBus-1 Clock Period Configuration

Bus: 1 Device: Function: 0 Offset: 124

Bit Attr Default Description

31:16 RWS 445Ch smb1_tlow_timeout (SMB1_TLOW_TIMEOUT) — Upper 16b of the 18b SMBus Time-Out Timer Configuration in unit of SPDTOP_500NS_CFG.CNFG_500_NANOSEC. The lower 2b of the 18b counter config is always 00. Assuming the CNFG_500_NANOSEC is set at 500ns: For 35ms time out, please configure this register to 445C For 65ms time out, please configure this register to 7EF4

15:0 RWS_O 2AF8h smb1_clk_prd (SMB1_CLK_PRD) — This field specifies both SMBus Clock in number of FCLK. Note: In order to generate a 50% duty cycle SCL, half of the SMB_CLK_PRD is used to generate SCL high. SCL must stay low for at least another half of the SMB_CLK_PRD before pulling high. It is recommend to program an even value in this field since the hardware is simply doing a right shift for the divided by 2 operation. Note the 100KHz SMB_CLK_PRD default value is calculated based on 1.1Ghz FCLK.

4.1.8 SMB0_TLOW_TIMEOUT_CNTR

SMBus Clock Low Timeout Counter

Bus: 1Device: 30Function: 0Offset: 128

Bit Attr Default Description 31:18 RO 0h Reserved (RSVD) — Reserved.

17:0 RO_V 0h smb0_tlow_timeout_cntr (SMB0_TLOW_TIMEOUT_CNTR) — SMBus 0 Time-out Timer Counter (18b)

4.1.9 SMB1_TLOW_TIMEOUT_CNTR

SMBus Clock Low Timeout Counter

Bus: 1Device: 30Function: 0Offset: 12C

Bit Attr Default Description 31:18 RO 0h Reserved (RSVD) — Reserved.

17:0 RO_V 0h smb1_tlow_timeout_cntr (SMB1_TLOW_TIMEOUT_CNTR) — SMBus 1 Time-out Timer Counter (18b)

Intel® Xeon Phi™ Processor 93 Datasheet - Volume 2, December 2016 4.1.10 SMB_PERIOD_CNTR

SMBus Clock Period Counter

Bus: 1 Device: Function: 0 Offset: 130

Bit Attr Default Description 31:16 RO_V 0h smb1_clk_prd_cntr (SMB1_CLK_PRD_CNTR) — SMBus #1 Clock Period Counter. This field is the current SMBus Clock Period Counter Value. PSMI wipe will clear the counter.

15:0 RO_V 0h smb0_clk_prd_cntr (SMB0_CLK_PRD_CNTR) — SMBus #0 Clock Period Counter. This field is the current SMBus Clock Period Counter Value. PSMI wipe will clear the counter.

4.1.11 SMB0_TSOD_POLL_RATE

SMBus-0 TSOD POLL RATE

Bus: 1 Device: Function: 0Offset: 134

Bit Attr Default Description

31:18 RO 0h Reserved (RSVD) — Reserved.

17:0 RWS 7D0h smb_tsod_poll_rate (SMB_TSOD_POLL_RATE) — TSOD poll rate configuration between consecutive TSOD accesses to the TSOD devices on the same SMBus segment. This field specifies the TSOD poll rate in number of 500ns per CNFG_500_NANOSEC register field definition.

4.1.12 SMB1_TSOD_POLL_RATE

SMBus-1 TSOD POLL RATE

Bus: 1 Device: Function: 0Offset: 138

Bit Attr Default Description 31:18 RO 0h Reserved (RSVD) — Reserved.

4.1.13 SMB0_TSOD_SAMPLE_0_3

The register stores the temperature values (and valid bits) read from TSOD attached to SMB0. It enables CLTT. THIS REGISTER IS DUPLICATED IN THE PCU IOREG SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Bus: 1 Device: Function: 0 Offset: 140

Bit Attr Default Description 31 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_3) — PCU CLTT TSOD temperature valid bit for SMB0 Slot #3. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

30:24 RO_V 0h tsod_sample (TSOD_SAMPLE_3) — PCU CLTT logic extracted SMB0 Slot #3 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

94 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 0 Offset: 140

Bit Attr Default Description 23 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_2) — PCU CLTT TSOD temperature valid bit for SMB0 Slot #2. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

22:16 RO_V 0h tsod_sample (TSOD_SAMPLE_2) — PCU CLTT logic extracted SMB0 Slot #2 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

15 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_1) — PCU CLTT TSOD temperature valid bit for SMB0 Slot #1. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

14:8 RO_V 0h tsod_sample (TSOD_SAMPLE_1) — PCU CLTT logic extracted SMB0 Slot #1 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

7RO_V0h tsod_sample_val (TSOD_SAMPLE_VAL_0) — PCU CLTT TSOD temperature valid bit for SMB0 Slot #0. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

6:0 RO_V 0h tsod_sample (TSOD_SAMPLE_0) — PCU CLTT logic extracted SMB0 Slot #0 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

4.1.14 SMB0_TSOD_SAMPLE_4_7

The register stores the temperature values (and valid bits) read from TSOD attached to SMB0. It enables CLTT. THIS REGISTER IS DUPLICATED IN THE PCU IOREG SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Bus: 1 Device: Function: 0Offset: 144

Bit Attr Default Description

31 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_7) — PCU CLTT TSOD temperature valid bit for SMB0 Slot #7. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

30:24 RO_V 0h tsod_sample (TSOD_SAMPLE_7) — PCU CLTT logic extracted SMB0 Slot #7 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

23 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_6) — PCU CLTT TSOD temperature valid bit for SMB0 Slot #6. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

22:16 RO_V 0h tsod_sample (TSOD_SAMPLE_6) — PCU CLTT logic extracted SMB0 Slot #6 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

15 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_5) — PCU CLTT TSOD temperature valid bit for SMB0 Slot #5. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

14:8 RO_V 0h tsod_sample (TSOD_SAMPLE_5) — PCU CLTT logic extracted SMB0 Slot #5 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

Intel® Xeon Phi™ Processor 95 Datasheet - Volume 2, December 2016 7RO_V0htsod_sample_val (TSOD_SAMPLE_VAL_4) — PCU CLTT TSOD temperature valid bit for SMB0 Slot #4. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

6:0 RO_V 0h tsod_sample (TSOD_SAMPLE_4) — PCU CLTT logic extracted SMB0 Slot #4 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

4.1.15 SMB1_TSOD_SAMPLE_0_3

The register stores the temperature values (and valid bits) read from TSOD attached to SMB1. It enables CLTT. THIS REGISTER IS DUPLICATED IN THE PCU IOREG SPACE, CHANGES MUST BE MADE IN BOTH PLACES

Bus: 1 Device: Function: 0 Offset: 148

Bit Attr Default Description 31 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_3) — PCU CLTT TSOD temperature valid bit for SMB1 Slot #3. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

30:24 RO_V 0h tsod_sample (TSOD_SAMPLE_3) — PCU CLTT logic extracted SMB1 Slot #3 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

23 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_2) — PCU CLTT TSOD temperature valid bit for SMB1 Slot #2. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

22:16 RO_V 0h tsod_sample (TSOD_SAMPLE_2) — PCU CLTT logic extracted SMB1 Slot #2 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

15 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_1) — PCU CLTT TSOD temperature valid bit for SMB1 Slot #1. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

14:8 RO_V 0h tsod_sample (TSOD_SAMPLE_1) — PCU CLTT logic extracted SMB1 Slot #1 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

7RO_V0htsod_sample_val (TSOD_SAMPLE_VAL_0) — PCU CLTT TSOD temperature valid bit for SMB1 Slot #0. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

6:0 RO_V 0h tsod_sample (TSOD_SAMPLE_0) — PCU CLTT logic extracted SMB1 Slot #0 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

4.1.16 SMB1_TSOD_SAMPLE_4_7

The register stores the temperature values (and valid bits) read from TSOD attached to SMB1. It enables CLTT. THIS REGISTER IS DUPLICATED IN THE PCU IOREG SPACE, CHANGES MUST BE MADE IN BOTH PLACES

96 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 0 Offset: 14C

Bit Attr Default Description 31 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_7) — PCU CLTT TSOD temperature valid bit for SMB1 Slot #7. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

30:24 RO_V 0h tsod_sample (TSOD_SAMPLE_7) — PCU CLTT logic extracted SMB1 Slot #7 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

23 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_6) — PCU CLTT TSOD temperature valid bit for SMB1 Slot #6. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

22:16 RO_V 0h tsod_sample (TSOD_SAMPLE_6) — PCU CLTT logic extracted SMB1 Slot #6 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

15 RO_V 0h tsod_sample_val (TSOD_SAMPLE_VAL_5) — PCU CLTT TSOD temperature valid bit for SMB1 Slot #5. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

14:8 RO_V 0h tsod_sample (TSOD_SAMPLE_5) — PCU CLTT logic extracted SMB1 Slot #5 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

7RO_V0htsod_sample_val (TSOD_SAMPLE_VAL_4) — PCU CLTT TSOD temperature valid bit for SMB1 Slot #4. This bit is set by PCU when the corresponding TSOD_SAMPLE has been updated. This bit is cleared in the next DCLK after read to this register; however, if read and the PCU update (setting this bit) occur at the same cycle, the PCU set operation will dominate, that is, the bit is remaining as set in the next DCLK.

6:0 RO_V 0h tsod_sample (TSOD_SAMPLE_4) — PCU CLTT logic extracted SMB1 Slot #4 TSOD temperature (truncated TSOD reading, integer range from 0 to +127C) and update this byte.

4.2 Bus: 1, Device: 30, Function: 1 (CFG)

Table 4-2. Summary of Bus: 1, Device: 30, Function: 1 (CFG)

Offset Size Register Name (Register Symbol) Default Value (Bytes)

68–6Fh 8 “SSKPD_CFG” on page 97 0h

74–77h 4 “C2C3TT_CFG” on page 98 32h

A4–A7h 4 “CSR_DESIRED_CORES_CFG” on page 98 0h

A8–ABh 4 “CSR_DESIRED_CORES_CFG_1” on page 98 0h

4.2.1 SSKPD_CFG

This register holds 64 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers.

Intel® Xeon Phi™ Processor 97 Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 1 Offset: 68

Bit Attr Default Description 63:0 RWS 0h Scratchpad Data (SKPD) — 4 WORDs of data storage.

4.2.2 C2C3TT_CFG

This register contains the initial snoop timer (pop-down) value. BIOS can update this value during run-time. PCODE will sample this register at slow loop. If the value has changed since the previous sample and in addition there is no valid Hysteresis parameter (HYS) from a previous PM_DMD or PM_RSP message, then PCODE will configure IMPH_CR_SNP_RELOAD[LIM] with this value.

Bus: 1Device: 30Function: 1Offset: 74

Bit Attr Default Description

31:12 RO 0h Reserved (RSVD) — Reserved.

11:0 RW 32h Pop Down Initialization Value (PPDN_INIT) — Value

4.2.3 CSR_DESIRED_CORES_CFG

Bus: 1 Device: Function: 1 Offset: A4

Bit Attr Default Description

31:0 RWS_L 0h Cores Off Mask (CORE_OFF_MASK) — BIOS will set this bit to request that the matching tile should not be activated coming out of reset.

The default value of this registers means that all tiles are enabled.

Restrictions: At least one tile needs to be left active. Otherwise, FW will ignore the setting altogether. 4.2.4 CSR_DESIRED_CORES_CFG_1

Intel® Xeon Phi™ Processor: Number of Tiles BIOS wants to exist on the next reset. A processor reset must be used for this register to take effect. Note, programming this register to a value higher than the product has tiles should not be done. FW uses the information in this register, along with FUSE_LLC_SLICE_IA_CORE_DIS and FUSE_HT_DIS to update RESOLVED_CORES_MASK[core_mask] and RESOLVED_CORES_MASK[thread_mask]. This register is reset only by PWRGOOD.

98 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 1Offset: A8

Bit Attr Default Description 31 RWS_KL 0h Lock (LOCK) — Lock: once written to a '1', changes to this register cannot be done. Cleared only by a power-on reset

30 RWS_L 0h SMT Disable (SMT_DISABLE) — Disable simultaneous multi-threading in all tiles if this bit is set to '1'.

29:6 RWS_L 0h Reserved (RSVD) — Reserved

5:0 RWS_L 0h Cores Off Mask (CORE_OFF_MASK) — BIOS will set this bit to request that the matching tile should not be activated coming out of reset. The default value of this registers means that all tiles are enabled. Restrictions: At least one tile needs to be left active. Otherwise, FW will ignore the setting altogether.

4.3 Bus: 1, Device: 30, Function: 2 (CFG)

Table 4-3. Summary of Bus: 1, Device: 30, Function: 2 (CFG)

Offset Size Register Name (Register Symbol) Default Value (Bytes)

0–1h 2 “VID_1_30_2_CFG” on page 99 8086h

2–3h 2 “DID_1_30_2_CFG” on page 99 7822h

4–5h 2 “PCICMD_1_30_2_CFG” on page 100 0h

80–87h 8 “PACKAGE_POWER_SKU_CFG” on page 100 12024000600118h

88–8Bh 4 “PACKAGE_RAPL_PERF_STATUS” on page 101 0h

8C–8Fh 4 “PACKAGE_POWER_SKU_UNIT_CFG” on page 101 A0E03h

90–93h 4 “PACKAGE_ENERGY_STATUS_CFG” on page 102 0h

C8–CBh 4 “PACKAGE_TEMPERATURE_CFG” on page 102 0h

CC–CFh 4 “PP0_TEMPERATURE_CFG” on page 102 0h

D8–DBh 4 “DRAM_RAPL_PERF_STATUS_CFG” on page 102 0h

E0–E3h 4 “PACKAGE_THERM_MARGIN_CFG” on page 102 0h

E4–E7h 4 “TEMPERATURE_TARGET_CFG” on page 103 0h

4.3.1 VID_1_30_2_CFG

PCI Vendor ID Register

Bus: 1 Device: Function: 2 Offset: 0

Bit Attr Default Description 15:0 RO 8086h Vendor Identification Number (Vendor_Identification_Number) — The value is assigned by PCI-SIG to Intel.

4.3.2 DID_1_30_2_CFG

PCI Device Identification Number

Intel® Xeon Phi™ Processor 99 Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 2 Offset: 2

Bit Attr Default Description 15:0 RO 7822h Device_Identification_Number — Device ID values vary from function to function. Please refer to register EDS for the breakdown of DID in function groups and individual assignments for different types of functions for Intel® Xeon Phi™ Processor.

4.3.3 PCICMD_1_30_2_CFG

PCI Command Register

Bus: 1Device: 30Function: 2Offset: 4

Bit Attr Default Description 15:11 RO 0h Reserved (RSVD) — Reserved.

10 RO 0h INTx_Disable — N/A for these devices

9RO0hFast_Back_to_Back_Enable — Not applicable to PCI Express and is hardwired to 0

8RO0hSERR_Enable — This bit has no impact on error reporting from these devices

7RO0hIDSEL_Stepping_Wait_Cycle_Control — Not applicable to internal devices. Hardwired to 0.

6RO0hParity_Error_Response — This bit has no impact on error reporting from these devices

5RO0hVGA_palette_snoop_Enable — Not applicable to internal devices. Hardwired to 0.

4RO0hMemory_Write_and_Invalidate_Enable — Not applicable to internal devices. Hardwired to 0.

3RO0hSpecial_Cycle_Enable — Not applicable. Hardwired to 0.

2RO0hBus_Master_Enable — Hardwired to 0 since these devices don't generate any transactions

1RO0hMemory_Space_Enable — Hardwired to 0 since these devices don't decode any memory BARs

0RO0hIO_Space_Enable — Hardwired to 0 since these devices don't decode any IO BARs

4.3.4 PACKAGE_POWER_SKU_CFG

Defines allowed SKU power and timing parameters.

Bus: 1 Device: Function: 2Offset: 80

Bit Attr Default Description 63:55 RO 0h Reserved (RSVD) — Reserved.

54:48 ROS_V 12h Maximal Time Window (PKG_MAX_WIN) — The maximal time window allowed for the SKU. Higher values will be clamped to this value. x = PKG_MAX_WIN[54:53] y = PKG_MAX_WIN[52:48] The timing interval window is Floating Point number given by 1.x * power(2,y). The unit of measurement is defined in PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT].

47 RO 0h Reserved (RSVD) — Reserved.

46:32 ROS_V 240h Maximal Package Power (PKG_MAX_PWR) — The maximal package power setting allowed for the SKU. Higher values will be clamped to this value. The maximum setting is typical (not guaranteed). The units for this value are defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT].

31 RO 0h Reserved (RSVD) — Reserved.

100 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 1 Device: Function: 2Offset: 80

Bit Attr Default Description

30:16 ROS_V 60h Minimal Package Power (PKG_MIN_PWR) — The minimal package power setting allowed for this part. Lower values will be clamped to this value. The minimum setting is typical (not guaranteed). The units for this value are defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT].

15 RO 0h Reserved (RSVD) — Reserved.

14:0 RSVD-P 118h Reserved (RSVD-P) — Reserved - protected.

4.3.5 PACKAGE_RAPL_PERF_STATUS

This register is used by Pcode to report Package Power limit violations in the Platform PBM. Provides information on the performance impact of the RAPL power limit.

Provides the total time for which PACKAGE was throttled because of the RAPL power limit. Throttling here is defined as going below O.S requested P-state. Total time = Reg value * 1s *1 /2^(time unit) Usage model: Enables the O.S/Driver to learn about PACKAGE throttling as a result of RAPL limit Can be used by other S/W components that control the PACKAGE power This register is mapped as an MSR with the name Package_Perf_Status

Bus: 1 Device: Function: 2 Offset: 88

Bit Attr Default Description

31:0 RO_V 0h Power Limit Throttle Counter (PWR_LIMIT_THROTTLE_CTR) — Reports the number of times the Power limiting algorithm had to clip the power limit due to hitting the lowest power state available. Accumulated PACKAGE throttled time

4.3.6 PACKAGE_POWER_SKU_UNIT_CFG

Defines units for calculating SKU power and timing parameters.

Bus: 1 Device: Function: 2Offset: 8C

Bit Attr Default Description

31:20 RO 0h Reserved (RSVD) — Reserved.

19:16 RO_V Ah Time Unit (TIME_UNIT) — Time Units used for power control registers. The actual unit value is calculated by 1 s / Power(2,TIME_UNIT). The default value of Ah corresponds to 976 usec.

15:13 RO 0h Reserved (RSVD) — Reserved.

12:8 RO_V Eh Energy Units (ENERGY_UNIT) — Energy Units used for power control registers. The actual unit value is calculated by 1 J / Power(2,ENERGY_UNIT). The default value of 14 corresponds to Ux.14 number.

7:4 RO 0h Reserved (RSVD) — Reserved.

3:0 RO_V 3h Power Units (PWR_UNIT) — Power Units used for power control registers. The actual unit value is calculated by 1 W / Power(2,PWR_UNIT). The default value of 0011b corresponds to 1/8 W.

Intel® Xeon Phi™ Processor 101 Datasheet - Volume 2, December 2016 4.3.7 PACKAGE_ENERGY_STATUS_CFG

Package energy consumed by the entire CPU (including IA, Integrated Graphics and Uncore). The counter will wrap around and continue counting when it reaches its limit. The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT].

Bus: 1 Device: Function: 2Offset: 90

Bit Attr Default Description 31:0 RO_V 0h Energy Value (DATA) — Energy Value

4.3.8 PACKAGE_TEMPERATURE_CFG

Package temperature in degrees (C). This field is updated by FW.

Bus: 1Device: 30Function: 2Offset: C8

Bit Attr Default Description

31:8 RO 0h Reserved (RSVD) — Reserved.

7:0 RO_V 0h Temperature (DATA) — Package temperature in degrees (C).

4.3.9 PP0_TEMPERATURE_CFG

PP0 temperature in degrees (C). This field is updated by FW.

Bus: 1Device: 30Function: 2Offset: CC

Bit Attr Default Description 31:8 RO 0h Reserved (RSVD) — Reserved.

7:0 RO_V 0h Temperature (DATA) — Temperature in degrees (C).

4.3.10 DRAM_RAPL_PERF_STATUS_CFG

This register is used by Pcode to report DRAM Plane Power limit violations in the Platform PBM. Provides information on the performance impact of the RAPL power limit. Provides the total time for which DRAM was throttled because of the RAPL power limit. Total time = Reg Value *1 s * 1/ (2^time_unit) Usage model: Enables the OS/ Driver to learn about DRAM throttling as a result of RAPL limit Can be used by other S/W components that control the DRAM power This register is mapped as an MSR with the name DRAM_RAPL_PERF_STATUS

Bus: 1 Device: Function: 2 Offset: D8

Bit Attr Default Description 31:0 RO_V 0h Power Limit Throttle Counter (PWR_LIMIT_THROTTLE_CTR) — Reports the number of times the Power limiting algorithm had to clip the power limit due to hitting the lowest power state available. Accumulated DRAM throttled time

4.3.11 PACKAGE_THERM_MARGIN_CFG

DTS2.0 Thermal Margin. This CSR is a mirror of MSR (1A1h) PACKAGE_THERM_MARGIN. Refer to this MSR for field descriptions.

102 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: 1Device: 30Function: 2Offset: E0

Bit Attr Default Description 31:16 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

15:0 RO_V 0h Thermal margin (THERM_MARGIN) — Thermal margin in 8.8 format

4.3.12 TEMPERATURE_TARGET_CFG

Legacy register holding temperature related constants for Platform use.

Bus: 1 Device: Function: 2Offset: E4

Bit Attr Default Description 31:28 RO 0h Reserved (RSVD) — Reserved.

27:24 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

23:16 RO_V 0h Thermal Monitor Reference Temperature (REF_TEMP) — This field indicates the maximum junction temperature, also referred to as the Throttle Temperature, TCC Activation Temperature or Prochot Temperature. This is the temperature at which the Adaptive Thermal Monitor is activated.

15:8 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

7:0 RO 0h Reserved (RSVD) — Reserved.

4.4 Bus: 1, Device: 30, Function: 3 (CFG)

Table 4-4. Summary of Bus: 1, Device: 30, Function: 3 (CFG)

Offset Size Register Name (Register Symbol) Default Value (Bytes)

80–83h 4 “CAP_HDR_CFG” on page 103 1280009h

84–87h 4 “CAPID0_CFG” on page 104 0h

88–8Bh 4 “CAPID1_CFG” on page 105 0h

8C–8Fh 4 “CAPID2_CFG” on page 105 0h

90–93h 4 “CAPID3_CFG” on page 106 0h

94–97h 4 “CAPID4_CFG” on page 106 0h

98–9Bh 4 “CAPID5_CFG” on page 107 0h

9C–9Fh 4 “CAPID6_CFG” on page 107 0h

A0–A3h 4 “CAPID7_CFG” on page 107 0h

A4–A7h 4 “CAPID8_CFG” on page 107 0h

4.4.1 CAP_HDR_CFG

This register is a Capability Header.It enumerates the CAPID registers available, and points to the next CAP_PTR.

Intel® Xeon Phi™ Processor 103 Datasheet - Volume 2, December 2016 Bus: 1Device: 30Function: 3Offset: 80

Bit Attr Default Description 31:28 RO 0h Reserved (RSVD) — Reserved.

27:24 RO_FW 1h CAPID_Version — This field has the value 0001b to identify the first revision of the CAPID register definition.

23:16 RO_FW 28h CAPID_Length — This field indicates the structure length including the header in Bytes.

15:8 RO_FW 0h Next_Cap_Ptr — This field is hardwired to 00h indicating the end of the capabilities linked list.

7:0 RO_FW 9h CAP_ID — This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers.

4.4.2 CAPID0_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Bus: 1 Device: Function: 3Offset: 84

Bit Attr Default Description 31:30 RO 0h Reserved (RSVD) — Reserved.

29 RO_FW 0h PECI_EN — PECI to the Processor

28 RO 0h Reserved (RSVD) — Reserved.

27 RO_FW 0h RSVD_27 — Reserved for future use.

26:25 RO 0h Reserved (RSVD) — Reserved.

24 RO_FW 0h RSVD_24 — Reserved for future use.

23 RO_FW 0h AES_DIS — AES disabled

22 RO_FW 0h TSC_DEADLINE_DIS — APIC timer last tick relative mode: Support for TSC Deadline disabled

21:19 RO 0h Reserved (RSVD) — Reserved.

18 RO_FW 0h CARD_MODE — Card Mode. 0:Self_Boot, 1:Card_Mode

17 RO_FW 0h HFI_INTERCONNECT_EN — 1: Fabric component integrated on the package

16:15 RO_FW 0h MCDRAM_SIZE — Size per EDC controller 00: 512 MB 01: 1 GB 10: 2 GB 11: 4 GB

14 RO_FW 0h RSVD_14 — Reserved for future use

13 RO_FW 0h RSVD_13 — Reserved for future use

12 RO_FW 0h HT_DIS — Disable Multi threading (redefined for Intel® Xeon Phi™ Processor). This implies either we have 1 thread per core or 4 threads per core

11 RO_FW 0h FORM_FACTOR_TYPE — LGA or BGA Package. 0: LGA, 1: BGA

10:9 RO_FW 0h MAX_OPIO_LINK_SPEED — Maximum encoded OPIO link speed for the part.Endcoding 11 - 8.0 GT/s; 10 - 7.2 GT/s; 01 - 6.4 GT/s; 00 - 3.6 GT/s;

8RO_FW0hPRG_TDP_LIM_EN — TURBO_POWER_LIMIT MSRs usage enabled

7:0 RO_FW 0h ENABLED_EDC_MASK — Bit mask for which EDCs are fuse enabled. BIOS should use pop count of this value to determine # of fuse enabled EDC controllers.

104 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 4.4.3 CAPID1_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Bus: 1 Device: Function: 3Offset: 88

Bit Attr Default Description 31:30 RO 0h Reserved (RSVD) — Reserved.

29:26 RO_FW 0h DMFC — This field encodes the maximum allowed MC frequency. Any attempt to write an unsupported value will be ignored. 0000: MC capable of DDR3 2400 MHz (2400 is the upper limit) 0001: MC capable of up to DDR3 2133 MHz 0010: MC capable of up to DDR3 1867 MHz 0011: MC capable of up to DDR3 1600 MHz

25:23 RO 0h Reserved (RSVD) — Reserved.

22 RO_FW 0h RSVD_22 — Reserved for future use.

21 RO_FW 0h RSVD_21 — Reserved for future use.

20 RO_FW 0h RSVD_20 — Reserved for future use.

19 RO_FW 0h RSVD_19 — Reserved for future use.

18 RO_FW 0h RSVD_18 — Reserved for future use.

17 RO_FW 0h RSVD_17 — Reserved for future use.

16 RO_FW 0h RSVD_16 — Reserved for future use.

15 RO_FW 0h RSVD_15 — Reserved for future use.

14 RO_FW 0h RSVD_14 — Reserved for future use.

13 RO_FW 0h RSVD_13 — Reserved for future use.

12 RO_FW 0h RSVD_12 — Reserved for future use.

11 RO_FW 0h RSVD_11 — Reserved for future use.

10 RO_FW 0h RSVD_10 — Reserved for future use.

9:8 RO 0h Reserved (RSVD) — Reserved.

7RO_FW0hX2APIC_EN — Enable Extended APIC support. When set enables the support of x2APIC (Extended APIC) in the core and uncore.

6RO0hReserved (RSVD) — Reserved.

5RO_FW0hPWRBITS_DIS — 0bPower features activated during reset 1bPower features (especially clock gating) are not activated

4RO_FW0hGV3_DIS — GV3 disabled. Does not allow for the writing of the IA32_PERF_CONTROL register in order to change ratios

3:0 RO_FW 0h DMFC_EDC — This field encodes the maximum allowed EDC frequency. Any attempt to write an unsupported value will be ignored. 0000: EDC capable of MCDRAM 500 MHz (500MHz is the upper limit) 0001: EDC capable of up to MCDRAM 450 MHz 0010: EDC capable of up to MCDRAM 400 MHz 0011: EDC capable of up to MCDRAM 225 MHz

4.4.4 CAPID2_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Bus: 1Device: 30Function: 3Offset: 8C

Bit Attr Default Description

31:23 RO 0h Reserved (RSVD) — Reserved.

Intel® Xeon Phi™ Processor 105 Datasheet - Volume 2, December 2016 22 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

21:20 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

19 RO_FW 0h PCIE_DISNTB — NTB support disabled

18:16 RO 0h Reserved (RSVD) — Reserved.

15 RO_FW 0h PCIE_DISPCIEG3 — PCIe Gen 3 disabled

14 RO_FW 0h PCIE_DISDMA — NOT relevant for Intel® Xeon Phi™ Processor

13 RO_FW 0h PCIE_DISDMI — DMI interface disabled - Not relevant for Intel® Xeon Phi™ Processor

12:3 RO_FW 0h PCIE_DISXPDEV — Specific PCIe port disabled (example: 2x20 (EP), 1x20(EN2), 2x20 (EN1) speed supported here)

2:1 RO_FW 0h PCIE_DISx16 — PCIe x16 ports disabled (limit to x8's only)

0RO0hReserved (RSVD) — Reserved.

4.4.5 CAPID3_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Bus: 1Device: 30Function: 3Offset: 90

Bit Attr Default Description 31 RSVD-P 0h Reserved (RSVD-P) — Reserved - protected.

30 RO 0h Reserved (RSVD) — Reserved.

29:24 RO_FW 0h MC2GDFuse — NOT relevant for Intel® Xeon Phi™ Processor.

23 RO 0h Reserved (RSVD) — Reserved.

22 RO_FW 0h DISABLE_SMBUS_WRT — SMBUS write capability disabled. When set, SMBus write is disabled. Intel® Xeon Phi™ Processor - this bit is used by SMbus h/w in PCU

21:16 RO 0h Reserved (RSVD) — Reserved.

15 RO_FW 0h DISABLE_CLTT — CLTT disabled. When set, CLTT support is disabled. Intel® Xeon Phi™ Processor - this bit is used by SMbus h/w in PCU

14:6 RO 0h Reserved (RSVD) — Reserved.

5:0 RO_FW 0h CHN_DISABLE — Channel disabled. When set, the corresponding channel is disabled.

4.4.6 CAPID4_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Bus: 1Device: 30Function: 3Offset: 94

Bit Attr Default Description 31 RO_FW 0h DRAM Power Meter disabled (DRAM_POWER_METER_DISABLE) —

30 RO_FW 0h Disable DRAM RAPL (DRAM_RAPL_DISABLE) — DRAM RAPL disabled

29 RO_FW 0h RSVD_29 — Reserved for future use

28:27 RO 0h Reserved (RSVD) — Reserved.

106 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 26 RO_FW 0h EET_ENABLE — Energy efficient turbo enable

25:21 RO 0h Reserved (RSVD) — Reserved.

20 RO_FW 0h SMM_CODE_CHK_DIS — Code access check disabled

19:6 RO 0h Reserved (RSVD) — Reserved.

5:4 RO_FW 0h PROD_TYPE — Product type 00: MIC - Intel® Xeon Phi™ Processor

3RO0hReserved (RSVD) — Reserved.

2RO_FW0hFIT_BOOT_DIS — FIT boot disabled

1RO0hReserved (RSVD) — Reserved.

0RO_FW0hERROR_SPOOFING_DIS — Error spoofing disabled

4.4.7 CAPID5_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Bus: 1 Device: Function: 3Offset: 98

Bit Attr Default Description

31:0 RO_FW 0h SPARE — Spare for Intel® Xeon Phi™ Processor use

4.4.8 CAPID6_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Bus: 1Device: 30Function: 3Offset: 9C

Bit Attr Default Description

31:28 RO 0h Reserved (RSVD) — Reserved.

27:6 RO_FW 0h SPARE — Spare bits reserved for future use

5:0 RO 0h Reserved (RSVD) — Reserved.

4.4.9 CAPID7_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Bus: Device: Function: 3Offset: A0

Bit Attr Default Description

31:0 RO_FW 0h TILE_EN —

4.4.10 CAPID8_CFG

This register is a Capability Register used to expose feature support to BIOS for SKU differentiation.

Intel® Xeon Phi™ Processor 107 Datasheet - Volume 2, December 2016 Bus: 1Device: 30Function: 3Offset: A4

Bit Attr Default Description 31:29 RO 0h Reserved (RSVD) — Reserved.

28:6 RO_FW 0h SPARE — Spare bits reserved for future use

5:0 RO_FW 0h TILE_EN —

108 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 5 DMI Port Register

The DMI Port is controlled through a set of configuration registers and registers located in memory mapped space at DMIRCBAR.

5.1 Configuration Registers

5.1.1 VID: Vendor ID

Bus: RootBus0Device: 0Function: 0Offset: 0hMode: DMI

Bit Attr Default Description

15:0 RO 8086h Vendor_Identification_Number The value is assigned by PCI-SIG to Intel.

5.1.2 DID: Device ID

Bus: RootBus0Device: 0Function: 0Offset: 2hMode: DMI

Bit Attr Default Description

15:0 RO - Device_Identification_Number Please refer to the Figure 6-1, “PCIe Root Port Configuration Register Map Offset 0x00 – 0x1FF” on page 128 for the DID value

5.1.3 PCICMD: PCI Command

Bus: RootBus0Device: 0Function: 0Offset: 4hMode: DMI

Bit Attr Default Description

15:11 RV 00h Reserved

Interrupt_Disable INTx Interrupt Disable Controls the ability of the PCI-Express port to generate INTx messages on its own behalf. This bit does not affect the ability of the Root Port to forward interrupt messages received from the PCI-Express port, to the internal I/OxAPIC block. However, this bit controls the internal generation of legacy INTx interrupts for PCI-Express RAS events or for INTx interrupts due to HP/PM events or for BW change notification. 1: Internal INTx Legacy Interrupt generation is disabled 10 RW 0b 0: Internal INTx Legacy Interrupt generation is enabled Notes: Notes: • When this bit is set to 1, this does NOT mean that MSI is enabled. It just means that INTx is disabled. The selection of whether MSI or INTx is chosen for generation an interrupt is achieved via the MSI enable bit in MSICTRL of this device/function. • If a root port had previously generated an Assert_INTx interrupt when this bit transitions from 0 to 1, then the root port generates a Deassert_INTx message to indicate the interrupt is deasserted.

Fast_Back_To_Back_Enable 9RO0b Not applicable to DMI or PCI Express and is hardwired to 0

Intel® Xeon Phi™ Processor 109 Datasheet - Volume 2, December 2016 Bus: RootBus0Device: 0Function: 0Offset: 4hMode: DMI

Bit Attr Default Description

SERRE SERR Reporting Enable For PCI Express/DMI ports, this field enables notifying the internal IIO core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the port. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message and so forth). Note this bit also controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL messages received from the port to the internal IIO core error logic. 8RW0b1: Fatal and Non-fatal error message generation and Fatal and Non-fatal error message forwarding is enabled 0: Fatal and Non-fatal error message generation and Fatal and Non-fatal error message forwarding is disabled Refer to PCI Express Base Specification, Revision 2.0 and RAS Chapter for details of how this bit is used in conjunction with other control bits like the ones in the Root Control register for forwarding errors detected on the PCI Express interface to the IIO core error logic.

IDSEL_Stepping_Wait_Cycle_Control 7RO0b Not applicable to internal IIO devices. Hardwired to 0.

PERRE Parity Error Reporting Enable 6RW0bFor PCI Express ports, IIO ignores this bit and always does parity checking and signaling for data/address of transactions both to and from root port. This bit though affects the setting of bit 8 in the PCISTS register.

VGA_Palette_Snoop_Enable 5RO0b Not applicable to internal IIO devices. Hardwired to 0.

MWIE 4RO0bMemory Write and Invalidate Enable Not applicable to internal IIO devices. Hardwired to 0.

SCE 3RO0bSpecial Cycle Enable Not applicable to DMI/PCI Express devices. Hardwired to 0

BME Bus Master Enable Controls the ability of the PCI Express port in generating and also in forwarding memory (including MSI writes) or I/O transactions (and not messages) or configuration transactions from the secondary side to the primary side. 1: Enables the PCI Express port to a) generate MSI writes internally for AER/HP/PM events (note: there are several other RP MSI related control/enable bits. See the RAS Chapter and PCI Express Base Specification, Revision 2.0 for complete details) and also to b) forward memory (including MSI writes from devices south of the RP), config or I/O read/write requests from secondary to primary side 2RO RW-L0b0: The Bus Master is disabled. When this bit is 0, IIO root ports will a) treat upstream PCI Express memory writes/reads, IO writes/reads, and configuration reads and writes as unsupported requests (and follow the rules for handling unsupported requests). This behavior is also true towards transactions that are already pending in the IIO root port's internal queues when the BME bit is turned off. Mask the root port from generating MSI writes internally for AER/HP/PM events at the root port. Need to remove specifics, this generically enables inbound requests. Bit is locked in DMI mode. Note: Read-only in DMI Mode, since the DMI is not a P2P bridge. Hardware should not use this bit to determine if it can forward requests from DMI to the system.

110 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus0Device: 0Function: 0Offset: 4hMode: DMI

Bit Attr Default Description

MSE Memory Space Enable 1: Enables a PCI Express port's memory range registers, with the exception of the I/ OxAPIC range register ('APICBASE: APIC Base Register (APICBASE)' and 'APICLIMIT: APIC Limit Register (APICLIMIT)'), to be decoded as valid target addresses for transactions from primary side. 0: Disables a PCI Express port's memory range registers, with the exception of the I/ OxAPIC range register ('APICBASE: APIC Base Register (APICBASE)' and 'APICLIMIT: 1RO0bAPIC Limit Register (APICLIMIT)'), to be decoded as valid target addresses for transactions from primary side. Notes: • Note that the I/OxAPIC address range of a root port has its own enable bit. • Note this bit is not ever used by hardware to decode transactions from the secondary side of the root port. • This bit is hardwired to 0 in DMI Mode, since the DMI is not a P2P bridge and does not claim any memory resource on its own. Hardware should not use this bit to determine if it can forward memory requests to DMI while in DMI mode.

IOSE I/O Space Enable 1: Enables the I/O address range, defined in the IOBASE and IOLIM registers of the PCI- to-PCI bridge header, for target decode from primary side 0: Disables the I/O address range, defined in the IOBASE and IOLIM registers of the PCI- 0RO0bto-PCI bridge header, for target decode from primary side Notes: • Note this bit is not ever used by hardware to decode transactions from the secondary side of the root port. • This bit is hardwired to 0 in DMI Mode, since the DMI is not a P2P bridge and does not claim any IO resource on its own. Hardware should not use this bit to determine if it can forward memory requests to DMI while in DMI mode.

5.1.4 PCISTS:PCI Status

Bus: RootBus0Device: 0Function: 0Offset: 6hMode: DMI

Bit Attr Default Description

DPE Detected Parity Error 15 RW1C 0b (Set on reception of a packet with poison bit set.) Need to copy the spec definitions. See PCIe specification.

SSE Signaled System Error 1: The root port (or DMI port in DMI mode) reported fatal/non-fatal (and not correctable) errors it detected on its PCI Express (or DMI) interface to the IIO core error logic (which might eventually escalate the error through the ERR[2:0] pins or message to CPU core or message to PCH). Note that the SERRE bit in the PCICMD register must be set for a device to report the error the IIO core error logic. Software clears this bit by writing a '1' to it. 14 RW1C 0b This bit is also set (when SERR enable bit is set) when a FATAL/NON-FATAL message is forwarded to the IIO core error logic. Note that IIO internal 'core' errors (like parity error in the internal queues) are not reported via this bit. 0: The root port (or DMI port) did not report a fatal/non- fatal error (Set if the root port forwards an error message internally or generates an error message internally.) Copy spec definition here See PCIe specification.

Intel® Xeon Phi™ Processor 111 Datasheet - Volume 2, December 2016 Bus: RootBus0Device: 0Function: 0Offset: 6hMode: DMI

Bit Attr Default Description

RMA Received Master Abort This bit is set when a root port experiences a master abort condition on a transaction it mastered on the primary interface (uncore internal bus). Note that certain errors might be detected right at the PCI Express interface and those transactions might not 'propagate' to the primary interface before the error is detected (e.g. accesses to memory above TOCM in cases where the PCIE interface logic itself might have visibility into TOCM). Such errors do not cause this bit to be set, and are 13 RW1C 0b reported via the PCI Express interface error bits (secondary status register). Conditions that cause bit 13 to be set, include: • Device receives a completion on the primary interface (internal bus of uncore) with Unsupported Request or master abort completion Status. This includes UR status received on the primary side of a PCI Express port on peer-to-peer completions also. • Other master abort conditions detected on the IIO internal bus amongst those listed in the Chapter 5, 'Inbound Address Decoding,' chapter.

RTA Received Target Abort • This bit is set when a device experiences a completer abort condition on a transaction it mastered on the primary interface (uncore internal bus). Note that certain errors might be detected right at the PCI Express interface and those transactions might not 'propagate' to the primary interface before the error is detected (e.g. accesses to memory above VTBAR). Such errors do not cause this 12 RW1C 0b bit to be set, and are reported via the PCI Express interface error bits (secondary status register). Conditions that cause bit 12 to be set, include: • Device receives a completion on the primary interface (internal bus of uncore) with completer abort completion Status. This includes CA status received on the primary side of a PCI Express port on peer-to-peer completions also. • Other completer abort conditions detected on the uncore internal bus amongst those listed in the Chapter 5, 'Inbound Address Decoding,' chapter.

STA Signaled Target Abort 11 RW1C 0b This bit is set when a root port signals a completer abort completion status on the primary side (internal bus of uncore). This condition includes a PCI Express port forwarding a completer abort status received on a completion from the secondary

DEVSEL_Timing 10:9 RO 0h Not applicable to DMI. Hardwired to 0.

MDPE Master Data Parity Error 8RW1C0bThis bit is set by a root port if the Parity Error Response bit in the PCI Command register is set and it either receives a completion with poisoned data from the primary side or it forwards a packet with data (including MSI writes) to the primary side with poison.

Fast_Back_To_Back 7RO0b Not applicable to DMI or PCI Express. Hardwired to 0.

6 RV 0b Reserved

pci66MHz_capable 5RO0b Not applicable to DMI or PCI Express. Hardwired to 0.

Capabilities_List 4RO1bThis bit indicates the presence of a capabilities list structure.

112 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus0Device: 0Function: 0Offset: 6hMode: DMI

Bit Attr Default Description

INTx_Status This Read-only bit reflects the state of the interrupt in the PCI-Express Root Port. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, will this device generate INTx interrupt. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit.This bit does not get set for interrupts forwarded 3RO-V0b to the root port from downstream devices in the hierarchy. When MSI are enabled, Interrupt status should not be set. The intx status bit should be deasserted when all the relevant events (RAS errors/HP/ link change status/PM) internal to the port using legacy interrupts are cleared by software.

2:0 RV 0h Reserved

5.1.5 RID: Revision ID

Bus: RootBus0Device: 0Function: 0Offset: 8hMode: DMI

Bit Attr Default Description

Revision_ID 7:0 RO-V 00h Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to this register.

5.1.6 CCR: Class Code Register

Bus: RootBus0Device: 0Function: 0Offset: 9hMode: DMI

Bit Attr Default Description

Base_Class 23:16 RO 06h For Device#0 this field is hardwired to 06h, indicating it is a 'Bridge Device'.

Sub_Class 15:8 RO 00h In DMI mode, this field defaults to 00h to indicate a 'host bridge' In PCIe mode, this field defaults to 04h to indicate a 'PCI to PCI bridge'.

Interface 7:0 RO 00h This field is hardwired to 00h for PCI Express/DMI ports.

5.1.7 CLSR:Cacheline Size Register

Bus: RootBus0Device: 0Function: 0Offset: ChMode: DMI

Bit Attr Default Description

Cacheline_Size 7:0 RW 00h This register is set as RW for compatibility reasons only. Cacheline size is 64B. IIO ignores this setting.

For Intel® Xeon Phi™ Processor, this is a multifunction device.

Intel® Xeon Phi™ Processor 113 Datasheet - Volume 2, December 2016 5.1.8 HDR: Header Type

Bus: RootBus0Device: 0Function: 0Offset: EhMode: DMI

Bit Attr Default Description

7 RO 0b Multi_function_Device Set to 0b since the DMI port is a single function device

6:0 RO-V 00h Configuration_Layout This field identifies the format of the configuration header layout. In DMI mode, default is 00h indicating a conventional type PCI header. In PCIe mode, default is 01h indicating a bridge type PCI header.

5.1.9 SVID: Subsystem Vendor ID

Bus: RootBus0Device: 0Function: 0Offset: 2ChMode: DMI

Bit Attr Default Description

Subsystem_Vendor_ID 15:0 RW-O 8086h The default value specifies Intel but can be set to any value once after reset.

5.1.10 SDID: Subsystem Device ID

Bus: RootBus0Device: 0Function: 0Offset: 2EhMode: DMI

Bit Attr Default Description

Subsystem_Device_ID 15:0 RW-O 0000h The default value specifies Intel but can be set to any value once after reset.

5.1.11 CAPPTR:Capability Pointer

Bus: RootBus0Device: 0Function: 0Offset: 34hMode: DMI

Bit Attr Default Description

7:0 RO-V 90h Capability_Pointer Points to the first capability structure for the device. In DMI mode, it points to the PCIe capability. The MSI capability is available, but is not currently being used by software, therefore it is skipped over. In PCIe mode, it points to the SVID/SDID capability.

5.1.12 INTL: Interrupt Line Register

Bus: RootBus0Device: 0Function: 0Offset: 3ChMode: DMI

Bit Attr Default Description

Interrupt_Line 7:0 RO 00h This is RW only for compatibility reasons. IIO hardware does not use it for any reason.

114 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 5.1.13 INTPIN: Interrupt Pin Register

Bus: RootBus0Device: 0Function: 0Offset: 3DhMode: DMI

Bit Attr Default Description

7:0 RW-O 01h INTP The only allowed values in this register are 00h and 01h. BIOS will leave the register at its default value unless it chooses to fully defeature INTx generation from a root port. For the latter scenario, BIOS will write a value of 00h before OS takes control. OS when it reads this register to be 00h understands that the root port does not generate any INTx interrupt. This helps simplify some of the BIOS ACPI tables relating to interrupts, when INTx interrupt generation from a root port is not enabled in the platform. Note that when BIOS writes a value of 00h in this register, that in itself does not disable INTx generation in hardware. Disabling INTx generation in hardware has to be achieved through the INTx Disable bit in the PCICMD register. Also, reader is referred to the MSI enable bit in MSICTRL for a description of how software selects MSI vs. INTx interrupt for the system interrupt method. IIO hardware does not use this bit for anything. For DMI mode operation, it is not applicable, since Device#0 does not generate any INTx interrupts on its own while in DMI mode.

IOxAPIC may be using this to swizzle the interrupts.

5.1.14 DMIRCBAR: DMIRCBAR

Bus: RootBus0Device: 0Function: 0Offset: 50hMode: DMI

Bit Attr Default Description

DMIRCBAR This field corresponds to bits 32 to 12 of the base address DMI Root Complex register space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 64GB of addressable memory space. System Software uses this base address to program the DMI 31:12 RW-LB 00000h Root Complex register set. All the Bits in this register are locked in LT mode. Note that this register is kept around on Device#0 even if that port is operating as PCIe port, to provide flexibility of using the VCs in PCIe mode as well. Nobody is asking for this capability right now but maintaining that flexibility.

11:1 RV 000h Reserved

DMIRCBAREN 0: DMIRCBAR is disabled and does not claim any memory 1: DMIRCBAR memory mapped accesses are claimed and decoded Notes: • Accesses to registers pointed to by the DMIRCBAR, via message channel or JTAG mini-port 0RW-LB0b are not gated by this enable bit that is, accesses these registers are honored regardless of the setting of this bit. • BIOS sets this bit only when it wishes to update the registers in the DMIRCBAR. It must clear this bit when it has finished changing values. This is required to ensure that the registers cannot be changed during an LT lock. This bit is protected by LT mode, but the registers in DMIRCBAR are not protected except by this bit.

Intel® Xeon Phi™ Processor 115 Datasheet - Volume 2, December 2016 5.1.15 MSICAPID: MSI Capability ID

Bus: RootBus0Device: 0Function: 0Offset: 60hMode: DMI

Bit Attr Default Description

Capability_ID 7:0 RO 05h Assigned by PCI-SIG for MSI (root ports).

5.1.16 MSINXTPTR: MSI Next Pointer

Bus: RootBus0Device: 0Function: 0Offset: 61hMode: DMI

Bit Attr Default Description

Next_Ptr 7:0 RW-O 90h This field is set to 90h for the next capability list (PCI Express capability structure) in the chain.

5.1.17 MSIMSGCTL: MSI Control

Bus: RootBus0Device: 0Function: 0Offset: 62hMode: DMI

Bit Attr Default Description

15:9 RV 0 Reserved

PVMC 8RO1bPer-vector masking capable This bit indicates that PCI Express ports support MSI per- vector masking.

B64AC Bus 64-bit Address Capable 7RO0b This field is hardwired to 0h since the message addresses are only 32-bit addresses (e.g. FEEx_xxxxh).

MME Multiple Message Enable Applicable only to PCI Express ports. Software writes to this field to indicate the number of 6:4 RW 000b allocated messages which is aligned to a power of two. When MSI is enabled, the software will allocate at least one message to the device. A value of 000 indicates 1 message. Any value greater than or equal to 001 indicates a message of 2. See MSIDR for discussion on how the interrupts are distributed amongst the various sources of interrupt based on the number of messages allocated by software for the PCI Express ports.

MMC 3:1 RO 001b Multiple Message Capable IIO Root Ports support two messages for all their internal events.

MSIEN MSI Enable Software sets this bit to select INTx style interrupt or MSI interrupt for root port generated interrupts. 0RW0b0: INTx interrupt mechanism is used for root port interrupts, provided the override bits in MISCCTRLSTS allow it 1: MSI interrupt mechanism is used for root port interrupts, provided the override bits in MISCCTRLSTS allow it Note there bits 4:2 and bit 2 MISCCTRLSTS can disable both MSI and INTx interrupt from being generated on root port interrupt events.

116 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 5.1.18 MSGADR: MSI Address

Bus: RootBus0Device: 0Function: 0Offset: 64hMode: DMI

Bit Attr Default Description

Address_MSB 31:20 RW 000h This field specifies the 12 most significant bits of the 32-bit MSI address.

Address_ID 19:2 RW 00000h Refer to the Interrupt Chapter for details of how this field is interpreted by IIO hardware. The definition of this field depends on whether interrupt remapping is enabled or disabled.

1:0 RO 0h Reserved

5.1.19 MSGDAT: MSI Data

Bus: RootBus0Device: 0Function: 0Offset: 68hMode: DMI

Bit Attr Default Description

31:16 RO 0000h Reserved

Data 15:0 RW 0000h Refer to the Interrupt Chapter for details of how this field is interpreted by IIO hardware. The definition of this field depends on whether interrupt remapping is enabled or disabled.

5.1.20 MSGMSK: MSI Mask Bit

Bus: RootBus0Device: 0Function: 0Offset: 6ChMode: DMI

Bit Attr Default Description

31:2 RV 0 Reserved

Mask_Bits Relevant only when MSI is enabled and used for interrupts generated by the root port. For each 1:0 RW 0h Mask bit that is set, the PCI Express port is prohibited from sending the associated message. When only one message is allocated to the root port by software, only mask bit 0 is relevant and used by hardware.

5.1.21 MSIPENDING: MSI Pending Bit

Bus: RootBus0Device: 0Function: 0Offset: 70hMode: DMI

Bit Attr Default Description

31:2 RV 0 Reserved

Intel® Xeon Phi™ Processor 117 Datasheet - Volume 2, December 2016 Bus: RootBus0Device: 0Function: 0Offset: 70hMode: DMI

Bit Attr Default Description

Pending_Bits Relevant only when MSI is enabled and used for interrupts generated by the root port. When MSI is not enabled or used by the root port, this register always reads a value 0. For each Pending bit that is set, the PCI Express port has a pending associated message. When only one message is allocated to the root port by software, only pending bit 0 is set/cleared by hardware and pending 1:0 RO-V 0h bit 1 always reads 0. Hardware sets this bit whenever it has an interrupt pending to be sent. This bit remains set till either the interrupt is sent by hardware or the status bits associated with the interrupt condition are cleared by software. Refer to the RAS/PM chapters for details of how this bit is set and cleared.

5.1.22 PXPCAPID: PCI Express Capability Identity

Bus: RootBus0Device: 0Function: 0Offset: 90hMode: DMI

Bit Attr Default Description

Capability_ID 7:0 RO 10h Identifies the PCI Express capability assigned by PCI-SIG.

5.1.23 PXPNXTPTR: PCI Express Next Pointer

Bus: RootBus0Device: 0Function: 0Offset: 91hMode: DMI

Bit Attr Default Description

Next_Ptr 7:0 RO E0h Pointer to the next capability. This field is set to the PCI PM capability.

5.1.24 PXPCAP: PCI Express Capability

Bus: RootBus0Device: 0Function: 0Offset: 92hMode: DMI

Bit Attr Default Description

15:14 RV 0 Reserved

Interrupt_Message_Number 13:9 RO 00h Not valid for this device, since the device does not generate interrupts

Slot_Implemented Applies only to the root ports. 1: indicates that the PCI Express link associated with the port is connected to a slot. 8RW-O0b 0: indicates no slot is connected to this port. Notes: This register is set by BIOS N/A in DMI Mode

Device_Port_Type 7:4 RO-V 9h This field identifies the type of device. It is set to 4h while in PCIe mode and 9h indicating Root Complex Integrated Endpoint while in DMI mode

Capability_Version 3:0 RW-O 2h PCI Express Capability is Compliant with Version 2.0 and Version 3.0 of the PCI Express Spec.

118 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 5.1.25 DEVCAP: PCI Express Device Capability

Bus: RootBus0Device: 0Function: 0Offset: 94hMode: DMI

Bit Attr Default Description

31:28 RV 0 Reserved

Captured_Slot_Power_Limit_Scale 27:26 RO 0h Does not apply to root ports or integrated devices

Captured_Slot_Power_Limit_Value 25:18 RO 0h Does not apply to root ports or integrated devices

17:16 RV 0 Reserved

Role_Based_Error_Reporting 15 RO 1b IIO Supports Role Based Error Reporting

Power_Indicator_Present_on_Device 14 RO 0b Does not apply to root ports or integrated devices

Attention_Indicator_Present 13 RO 0b Does not apply to root ports or integrated devices

Attention_Button_Present 12 RO 0b Does not apply to root ports or integrated devices

Endpoint_L1_Acceptable_Latency 11:9 RO 000b Does not apply to root ports or integrated devices

Endpoint_L0s_Acceptable_Latency 8:6 RO 000b Does not apply to root ports or integrated devices

Extended_Tag_Field_Supported 5RW-O0b Not Supported

Phantom_Functions_Supported 4:3 RO 0h IIO does not support phantom functions.

Max_Payload_Size_Supported 2:0 RW-O 0h Max payload is 128B on the DMI/PCIe port corresponding to Port 0.

5.1.26 ROOTCON: PCI Express Root Control

Bus: RootBus0Device: 0Function: 0Offset: AChMode: DMI

Bit Attr Default Description

15:5 RV 0 Reserved

CRSSWVISEN CRS software visibility Enable

4RW0b1: The Root Port to returns Configuration Request Retry Status (CRS) Completion Status to software by returning data of 0x01 when a configuration retry is returned by the connected device. 0: Retry status cannot be returned to software so the Configuration Request is re-issued to the connected device, unless the Configuration Retry Timer expires. If the timer expires, then a master abort response is returned to software.

PMEINTEN PME Interrupt Enable 3RW0bThis field controls the generation of MSI interrupts/INTx interrupts for PME messages. 1: Enables interrupt generation upon receipt of a PME message 0: Disables interrupt generation for PME messages

Intel® Xeon Phi™ Processor 119 Datasheet - Volume 2, December 2016 Bus: RootBus0Device: 0Function: 0Offset: AChMode: DMI

Bit Attr Default Description

SEFEEN System Error on Fatal Error Enable This field enables notifying the internal IIO core error logic of occurrence of an uncorrectable fatal error at the port or below its hierarchy. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message etc). Refer to RAS Chapter for details of how/which system notification is generated for a PCI Express fatal error. 1: indicates that an internal IIO core error logic notification should be generated if a fatal error (ERR_FATAL) is reported by any of the devices in the hierarchy associated with and including this port. 2RW0b0: No internal IIO core error logic notification should be generated on a fatal error (ERR_FATAL) reported by any of the devices in the hierarchy associated with and including this port. Note that generation of system notification on a PCI Express fatal error is orthogonal to generation of an MSI/INTx interrupt for the same error. Both a system error and MSI/INTx can be generated on a fatal error and software can chose one of the two. Refer to PCI Express Base Specification, Revision 2.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port. Note that since this register is defined only in PCIe mode for Device#0, this bit will read a 0 in DMI mode. So, to enable core error logic notification on DMI mode fatal errors, BIOS must set bit MISCCTRLSTS[35] to a 1 to override this bit in DMI mode.

SENFEEN System Error on Non-Fatal Error Enable This field enables notifying the internal IIO core error logic of occurrence of an uncorrectable non- fatal error at the port or below its hierarchy. The internal IIO core error logic then decides if/how to escalate the error further (pins/message etc). Refer to RAS Chapter for details of how/which system notification is generated for a PCI Express non-fatal error. 1: indicates that an internal IIO core error logic notification should be generated if a non-fatal error (ERR_NONFATAL) is reported by any of the devices in the hierarchy associated with and including this port. 0: No internal core error logic notification should be generated on a non-fatal error 1RW0b(ERR_NONFATAL) reported by any of the devices in the hierarchy associated with and including this port. Note that generation of system notification on a PCI Express non-fatal error is orthogonal to generation of an MSI/INTx interrupt for the same error. Both a system error and MSI/INTx can be generated on a non-fatal error and software can chose one of the two. Refer to PCI Express Base Specification, Revision 2.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port. Note that since this register is defined only in PCIe mode for Device#0, this bit will read a 0 in DMI mode. So, to enable core error logic notification on DMI mode non-fatal errors, BIOS must set MISCCTRLSTS[34] to a 1 to override this bit on Device#0 in DMI mode.

SECEEN System Error on Correctable Error Enable This field controls notifying the internal IIO core error logic of the occurrence of a correctable error in the device or below its hierarchy. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message and so forth). Refer to RAS Chapter for details of how/ which system notification is generated for a PCI Express correctable error. 1: indicates that an internal core error logic notification should be generated if a correctable error (ERR_COR) is reported by any of the devices in the hierarchy associated with and including this port. 0RW0b0: No internal core error logic notification should be generated on a correctable error (ERR_COR) reported by any of the devices in the hierarchy associated with and including this port. Note that generation of system notification on a PCI Express correctable error is orthogonal to generation of an MSI/INTx interrupt for the same error. Either a system error and MSI/INTx can be generated on a correctable error or software can chose one of the two. Refer to PCI Express Base Specification, Revision 2.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port. Note that since this register is defined only in PCIe mode for Device#0, this bit will read a 0 in DMI mode. So, to enable core error logic notification on DMI mode correctable errors, BIOS must set MISCCTRLSTS[33] to a 1 to override this bit on Device#0 in DMI mode.

120 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 5.1.27 DEVCAP2: PCI Express Device Capability 2

Bus: RootBus0Device: 0Function: 0Offset: B4hMode: DMI

Bit Attr Default Description

31:14 RV 0 Reserved

TPH_Completer_Supported Indicates the support for TLP Processing Hints. Intel Xeon processor E5 v3 product family does not support the extended TPH header. 13:12 RW-LB 01b 00: TPH and Extended TPH Completer not supported. 01: TPH Completer supported; Extended TPH Completer not supported. 10: Reserved. 11: Both TPH and Extended TPH Completer supported.

LTR_Supported 11 RW-LB 0b A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism capability.

No_RO_Supported If this bit is Set, the routing element never carries out the passing permitted by PCIe Table 2-27 entry A2b that is associated with the Relaxed Ordering Attribute field being Set. 10 RO 0b This bit applies only for Switches and RCs that support peer to peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit. For all other functions, this bit must be 0b.

ATOMICCASCP128 9RO1b AtomicOp CAS Completer 128-bit Operand not supported

ATOMICCP64 8RO1b AtomicOp Completer 64-bit Operand not supported

ATOMICCP32 7RO1b AtomicOp Completer 32-bit Operand not supported

ATOMICRT 6RO0b AtomicOp Routing not supported

ARI_EN 5RW-LB1b Alternative RID Interpretation Capable This bit is set to 1b indicating Root Port supports this capability.

CMPLTODISSUP 4RO1b Completion Timeout Disable Supported IIO supports disabling completion timeout

CMPLTOVALSUP Completion Timeout Values Supported This field indicates device support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout range. Bits are one-hot encoded and set according to the table below to show timeout value ranges supported. A device that supports the optional capability of Completion Timeout Programmability must set at least two bits.Four time values ranges are defined: Range A: 50us to 10ms Range B: 10ms to 250ms Range C: 250ms to 4s 3:0 RO Eh Range D: 4s to 64s Bits are set according to table below to show timeout value ranges supported. 0000b: Completions Timeout programming not supported — values are fixed in the range 50us to 50ms. 0001b: Range A 0010b: Range B 0011b: Range A & B 0110b: Range B & C 0111b: Range A, B, & C 1110b: Range B, C D 1111b: Range A, B, C & D All other values are reserved. IIO supports timeout values up to 10 ms-64s.

Intel® Xeon Phi™ Processor 121 Datasheet - Volume 2, December 2016 5.1.28 LNKCAP2: PCI Express Link Capability 2

Bus: RootBus0Device: 0Function: 0Offset: BChMode: DMI

Bit Attr Default Description

31:8 RV 0 Reserved

LNKSPDVEC Supported Link Speeds Vector This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link 7:1 RW-O 0000111b speed is not supported. Bit definitions are: Bit 12.5 GT/s Bit 25.0 GT/sset if DMIGEN2EN strap is set Bit 38.0 GT/s Bits 7:4reserved IIO supports all speeds up to Gen3, except for Port 0.

0RV0Reserved

5.1.29 PMCAP: Power Management Capability

Bus: RootBus0Device: 0Function: 0Offset: E0hMode: DMI

Bit Attr Default Description

PME_Support In PCIe Mode, Bits 31, 30 and 27 must be set to 1 for PCI- PCI bridge structures representing ports 31:27 RO 00h on root complexes. In DMI mode, PME generation is not supported.

D2_Support 26 RO 0b IIO does not support power management state D2.

D1_Support 25 RO 0b IIO does not support power management state D1.

24:22 RO 0h AUX_Current

21 RO 0b Device_Specific_Initialization

20 RV 0 Reserved

PME_Clock 19 RO 00h This field is hardwired to 0h as it does not apply to PCI Express.

Version 18:16 RO 3h This field is set to 3h (PM 1.2 compliant) as version number for all PCI Express ports.

Next_Capability_Pointer 15:8 RO 00h This is the last capability in the chain and hence set to 0.

Capability_ID 7:0 RO 01h Provides the PM capability ID assigned by PCI-SIG.

122 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 5.1.30 PMCSR: Power Management Control and Status Register

Bus: RootBus0Device: 0Function: 0Offset: E4hMode: DMI

Bit Attr Default Description

Data 31:24 RO 00h Not relevant for IIO

Bus_Power_Clock_Control_Enable 23 RO 0b This field is hardwired to 0h as it does not apply to PCI Express.

B2_B3_Support 22 RO 0b This field is hardwired to 0h as it does not apply to PCI Express.

21:16 RV 0 Reserved

PME_Status Applies only to root ports. This PME Status is a sticky bit. This bit is set, independent of the PME 15 RW1CS 0b Enable bit defined below, on an enabled PCI Express hot-plug event. Software clears this bit by writing a '1' when it has been completed. Refer to PCI Express Base Specification, Revision 2.0 for further details on wake event generation at a root port. No PME event supported in DMI mode, so this bit will not be set.

Data_Scale 14:13 RO 00h Not relevant for IIO

Data_Select 12:9 RO 00h Not relevant for IIO

PME_Enable Applies only to root ports. This field is a sticky bit and when set, enables a virtual PM_PME message to be generated internally on an enabled PCI Express hot-plug event. This virtual PM_PME message 8RO0b then sets the appropriate bits in the ROOTSTS register (which can then trigger an MSI/INT or cause a _PMEGPE event). N/A in DMI Mode.

7:4 RV 0 Reserved

No_Soft_Reset 3RW-O1b Indicates IIO does not reset its registers when transitioning from D3hot to D0.

2RV0Reserved

Power_State This 2-bit field is used to determine the current power state of the function and to set a new power state as well. 00: D0 01: D1 (not supported by IIO) 10: D2 (not supported by IIO) 11: D3_hot If Software tries to write 01 or 10 to this field, the power state does not change from the existing 1:0 RO 0h power state (which is either D0 or D3hot) and nor do these bits 1:0 change value. All devices will respond to only Type 0 configuration transactions (targeting the device's configuration space itself) when in D3hot state (root port will not forward Type 1/0 transactions to the downstream link) and will not respond to memory/IO transactions (that is, D3hot state is equivalent to MSE/IOSE bits being clear) as target and will not generate any memory/IO/ configuration transactions as initiator on the primary bus (messages are still allowed to pass through).

5.1.31 DEVCTRL: PCI Express Device Control

Bus: RootBus0Device: 0Function: 0Offset: F0hMode: DMI

Bit Attr Default Description

15 RV 0 Reserved

Intel® Xeon Phi™ Processor 123 Datasheet - Volume 2, December 2016 Bus: RootBus0Device: 0Function: 0Offset: F0hMode: DMI

Bit Attr Default Description

Max_Read_Request_Size 14:12 RO 000b PCI Express/DMI ports do not generate requests greater than 64B and this field is RO.

Enable_No_Snoop 11 RO 0b Not applicable to DMI or PCIe root ports since they never set the 'No Snoop' bit for transactions they originate (not forwarded from peer) to PCI Express/DMI. This bit has no impact on forwarding of NoSnoop attribute on peer requests.

Auxiliary_Power_Management_Enable 10 RO 0b Not applicable

Phantom_Functions_Enable 9RO0b Not applicable, since IIO never uses phantom functions as a requester.

Extended_Tag_Field_Enable 8RO0bNot applicable, since IIO never generates any requests on its own that uses tags 7:5. However, IIO forwards the entire tag field for peer to peer requests, so tag [7:5] could be set.

Max_Payload_Size 000: 128B max payload size 001: 256B max payload size others: alias to 128B 7:5 RW 000b IIO can receive packets equal to the size set by this field. IIO generate read completions as large as the value set by this field. IIO generates memory writes of max 64B.

Enable_Relaxed_Ordering 4RO0bNot applicable to root/DMI ports since they never set relaxed ordering bit as a requester (this does not include tx forwarded from peer devices). This bit has no impact on forwarding of relaxed ordering attribute on peer requests.

Unsupported_Request_Reporting_Enable This bit controls the reporting of unsupported requests that IIO itself detects on requests it receives from a PCI Express/DMI port. 3RW0b0: Reporting of unsupported requests is disabled 1: Reporting of unsupported requests is enabled. Refer to PCI Express Base Specification, Revision 2.0 for complete details of how this bit is used in conjunction with other bits to UR errors.

Fatal_Error_Reporting_Enable Controls the reporting of fatal errors that IIO detects on the PCI Express/DMI interface. 0: Reporting of Fatal error detected by device is disabled 2RW0b1: Reporting of Fatal error detected by device is enabled Refer to PCI Express Base Specification, Revision 2.0 for complete details of how this bit is used in conjunction with other bits to report errors. This bit is not used to control the reporting of other internal component uncorrectable fatal errors (at the port unit) in any way.

Non_Fatal_Error_Reporting_Enable Controls the reporting of non-fatal errors that IIO detects on the PCI Express/DMI interface. 0: Reporting of Non-Fatal error detected by device is disabled 1RW0b1: Reporting of Non-Fatal error detected by device is enabled Refer to PCI Express Base Specification, Revision 2.0 for complete details of how this bit is used in conjunction with other bits to report errors. This bit is not used to control the reporting of other internal component uncorrectable non-fatal errors (at the port unit) in any way.

Correctable_Error_Reporting_Enable Controls the reporting of correctable errors that IIO detects on the PCI Express/DMI interface 0: Reporting of link Correctable error detected by the port is disabled 0RW0b1: Reporting of link Correctable error detected by port is enabled Refer to PCI Express Base Specification, Revision 2.0 for complete details of how this bit is used in conjunction with other bits to report errors. This bit is not used to control the reporting of other internal component correctable errors (at the port unit) in any way.

124 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 5.1.32 DEVSTS: PCI Express Device Status

Bus: RootBus0Device: 0Function: 0Offset: F2hMode: DMI

Bit Attr Default Description

15:6 RV 0 Reserved

Transactions_Pending 5RO0b Does not apply to Root/DMI ports, that is, bit hardwired to 0 for these devices.

AUX_Power_Detected 4RO0b Does not apply to IIO

Unsupported_Request_Detected This bit indicates that the root port or DMI port detected an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register. 1: Unsupported Request detected at the device/port. These unsupported requests are NP requests inbound that the root port or DMI port received and it detected them as unsupported requests (e.g. 3RW1C0b address decoding failures that the root port detected on a packet, receiving inbound lock reads, BME bit is clear and so forth). 0: No unsupported request detected by the root or DMI port This bit is not set on peer2peer completions with UR status that are forwarded by the root port or DMI port to the PCIe/DMI link.

Fatal_Error_Detected This bit indicates that a fatal (uncorrectable) error is detected by the root or DMI port. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control 2RW1C0b register. 1: Fatal errors detected 0: No Fatal errors detected

Non_Fatal_Error_Detected This bit gets set if a non-fatal uncorrectable error is detected by the root or DMI port. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control 1RW1C0b register. 1: Non-Fatal errors detected 0: No non-Fatal Errors detected

Correctable_Error_Detected This bit gets set if a correctable error is detected by the root or DMI port. Errors are logged in this register regardless of whether error reporting is enabled or not in the PCI Express Device Control 0RW1C0b register. 1: correctable errors detected 0: No correctable errors detected

5.1.33 BDF:BAR# for Various MMIO BARs in IIO

This is needed for any entity trying to access MMIO registers in the IIO module over message channel.

Table 5-1. BDF BAR# for Various MMIO BARs in IIO

BAR Name B D F BAR#

DMIRCBAR DC 0 0 0 CB-BAR0 DC 4 0 0 CB-BAR1 DC 4 1 0 CB-BAR2 DC 4 2 0 CB-BAR3 DC 4 3 0 CB-BAR4 DC 4 4 0

Intel® Xeon Phi™ Processor 125 Datasheet - Volume 2, December 2016 Table 5-1. BDF BAR# for Various MMIO BARs in IIO

CB-BAR5 DC 4 5 0 CB-BAR6 DC 4 6 0 CB-BAR7 DC 4 7 0

5.1.34 Unimplemented Devices/Functions and Registers

If the IIO module receives a configuration access over message channel or directly via the JTAG mini-port, to a device/function or BAR# that does not exist in the IIO module, the IIO module will abort these accesses. Software should not attempt or rely on reads or writes to unimplemented registers or register bits.

5.1.35 PCI vs PCIe Device/Function

PCI devices/functions do NOT have a PCIe capability register set and do not decode offsets 100h and beyond. Accesses to 100h and beyond are master aborted by these devices. I/OxAPIC functions are PCI functions. All other functions in the IIO module are PCIe functions and these have a PCIe capability register set and also decode address offsets 100h and beyond.

126 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6 PCIe Root Port Registers

The PCI Express Root Port Registers used in the IIO are described in this chapter. The PCIe Root Port contains Configuration Mapped Registers only and uses a Type 1 PCI Express register header.

For Intel® Xeon Phi™ Processor, the IIO contains 40 PCIe lanes that can be configured as 2 x16 PCIe links and a x8 PCIe link. Each x16 or x8 link can be bifurcated to x8 and x4 combinations. The DMI port can also be configured as a x4 PCIe Root Port. Altogether, the maximum number of PCIe Root Ports that may be in operation would be 11.

All PCIe Root Ports have the same register definition as described here, unless the port is operating in DMI mode.

6.1 PCIe Root Port Configuration Registers

This is a summary of the components of the PCIe Root Port Configuration Registers: • Standard PCI Type 1 Header • Subsystem ID Capability Structure • MSI Capability Structure • PCI Express Capability Structure • Power Management Capability Structure • REUT Capability Structure • ACS Capability Structure • APIC Base/Limit •AER Capability Structure • Various Port Control Registers • Error Injection Capability Structure • XP Error Logging and Global Error Forwarding • PCI Express Capability 2 Structure • Live Error Recovery and Root Port IO Error Capability Structures • Header Match Logic • Dual Cast Capability Structure • Performance Monitors

Intel® Xeon Phi™ Processor 127 Datasheet - Volume 2, December 2016 Figure 6-1. PCIe Root Port Configuration Register Map Offset 0x00 – 0x1FF

128 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Figure 6-2. PCIe Root Port Configuration Register Map Offset 0x200 – 0x3FF

Intel® Xeon Phi™ Processor 129 Datasheet - Volume 2, December 2016 Figure 6-3. PCIe Root Port Configuration Register Map Offset 0x400 - 0x4FF

130 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.1 VID: Vendor ID

Bus: RootBus Device: 0Function: 2-3 Offset: 0h Bus: RootBus Device: 1Function: 0-3 Offset: 0h Bus: RootBus Device: 2Function: 0-3 Offset: 0h

Bit Attr Default Description

Vendor_Identification_Number 15:0 RO 8086h The value is assigned by PCI-SIG to Intel.

6.1.2 DID: Device ID

Bus: RootBus Device: 0Function: 2-3 Offset: 2h Bus: RootBus Device: 1Function: 0Offset: 2h Bus: RootBus Device: 1Function: 1-3 Offset: 2h Bus: RootBus Device: 2Function: 0-3 Offset: 2h

Bit Attr Default Description

7808h Device_Identification_Number 7809h Device IDs for PCI Express root ports are as follows: 7808h: Port 1A - x8, x4 780Ah 7809h: Port 1B - x4 780Bh 780Ah: Port 2A - x16, x8, x4 780Bh: Port 2B - x4 780Ch 780Ch: Port 2C - x8, x4 780Dh: Port 2D - x4 15:0 RO 780Dh 780Ah: Port 3A - x16, x8, x4 780Bh: Port 3B - x4 780Ah 780Ch: Port 3C - x8, x4 780Dh: Port 3D - x4 780Bh 780Ch 780Dh

6.1.3 PCICMD: PCI Command

Bus: RootBus Device: 0Function: 2-3 Offset: 4h Bus: RootBus Device: 1Function: 0Offset: 4h Bus: RootBus Device: 1Function: 1-3 Offset: 4h Bus: RootBus Device: 2Function: 0-3 Offset: 4h

Bit Attr Default Description

15:11 RV 00h Reserved Interrupt_Disable INTx Interrupt Disable Controls the ability of the PCI-Express port to generate INTx messages on its own behalf. This bit does not affect the ability of the Root Port to forward interrupt messages received from the PCI- Express port, to the internal I/OxAPIC block. However, this bit controls the internal generation of legacy INTx interrupts for PCI-Express RAS events or for INTx interrupts due to HP/PM events or for BW change notification. 1: Internal INTx Legacy Interrupt generation is disabled 10 RW 0b 0: Internal INTx Legacy Interrupt generation is enabled Notes: • When this bit is set to 1, this does NOT mean that MSI is enabled. It just means that INTx is disabled. The selection of whether MSI or INTx is chosen for generation an interrupt is achieved via the MSI enable bit in MSICTRL of this device/function. • If a root port had previously generated an Assert_INTx interrupt when this bit transitions from 0 to 1, then the root port generates a Deassert_INTx message to indicate the interrupt is deasserted.

Fast_Back_To_Back_Enable 9RO0b Not applicable to PCI Express and is hardwired to 0

Intel® Xeon Phi™ Processor 131 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 4h Bus: RootBus Device: 1Function: 0Offset: 4h Bus: RootBus Device: 1Function: 1-3 Offset: 4h Bus: RootBus Device: 2Function: 0-3 Offset: 4h

Bit Attr Default Description

SERRE SERR Reporting Enable For PCI Express ports, this field enables notifying the internal IIO core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the port. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message and so forth). Note this bit also controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL messages received from the port to the internal IIO core error logic. 8RW0b 1: Fatal and Non-fatal error message generation and Fatal and Non-fatal error message forwarding is enabled 0: Fatal and Non-fatal error message generation and Fatal and Non-fatal error message forwarding is disabled Refer to PCI Express Base Specification, Revision 2.0 and RAS Chapter for details of how this bit is used in conjunction with other control bits like the ones in the Root Control register for forwarding errors detected on the PCI Express interface to the IIO core error logic.

IDSEL_Stepping_Wait_Cycle_Control 7RO0b Not applicable to internal IIO devices. Hardwired to 0.

PERRE Parity Error Reporting Enable 6RW0bFor PCI Express ports, IIO ignores this bit and always does parity checking and signaling for data/ address of transactions both to and from root port. This bit though affects the setting of bit 8 in the PCISTS register.

VGA_Palette_Snoop_Enable 5RO0b Not applicable to internal IIO devices. Hardwired to 0.

MWIE 4RO0bMemory Write and Invalidate Enable Not applicable to internal IIO devices. Hardwired to 0.

SCE 3RO0bSpecial Cycle Enable Not applicable to DMI/PCI Express devices. Hardwired to 0

BME Bus Master Enable Controls the ability of the PCI Express port in generating and also in forwarding memory (including MSI writes) or I/O transactions (and not messages) or configuration transactions from the secondary side to the primary side. 1: Enables the PCI Express port to a) generate MSI writes internally for AER/HP/PM events (note: there are several other RP MSI related control/enable bits. See the RAS Chapter and PCI Express 2RW0bBase Specification, Revision 2.0 for complete details) and also to b) forward memory (including MSI writes from devices south of the RP), config or I/O read/write requests from secondary to primary side 0: The Bus Master is disabled. When this bit is 0, IIO root ports will a) treat upstream PCI Express memory writes/reads, IO writes/reads, and configuration reads and writes as unsupported requests (and follow the rules for handling unsupported requests). This behavior is also true towards transactions that are already pending in the IIO root port's internal queues when the BME bit is turned off. b) mask the root port from generating MSI writes internally for AER/HP/PM events at the root port.

MSE Memory Space Enable 1: Enables a PCI Express port's memory range registers, with the exception of the I/OxAPIC range register ('APICBASE: APIC Base Register (APICBASE)' and 'APICLIMIT: APIC Limit Register (APICLIMIT)'), to be decoded as valid target addresses for transactions from primary side. 0: Disables a PCI Express port's memory range registers, with the exception of the I/OxAPIC range 1RW0b register ('APICBASE: APIC Base Register (APICBASE)' and 'APICLIMIT: APIC Limit Register (APICLIMIT)'), to be decoded as valid target addresses for transactions from primary side. Notes: • Note that the I/OxAPIC address range of a root port has its own enable bit. • Note this bit is not ever used by hardware to decode transactions from the secondary side of the root port.

132 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 4h Bus: RootBus Device: 1Function: 0Offset: 4h Bus: RootBus Device: 1Function: 1-3 Offset: 4h Bus: RootBus Device: 2Function: 0-3 Offset: 4h

Bit Attr Default Description

IOSE I/O Space Enable 1: Enables the I/O address range, defined in the IOBASE and IOLIM registers of the PCI-to-PCI bridge header, for target decode from primary side 0RW0b0: Disables the I/O address range, defined in the IOBASE and IOLIM registers of the PCI-to-PCI bridge header, for target decode from primary side Notes: Note this bit is not ever used by hardware to decode transactions from the secondary side of the root port.

6.1.4 PCISTS: PCI Status

Bus: RootBus Device: 0Function: 2-3 Offset: 6h Bus: RootBus Device: 1Function: 0-3 Offset: 6h Bus: RootBus Device: 2Function: 0-3 Offset: 6h

Bit Attr Default Description

DPE Detected Parity Error 15 RW1C 0b This bit is set by a root port when it receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.

SSE Signaled System Error 1: The root port reported fatal/non-fatal (and not correctable) errors it detected on its PCI Express (or DMI) interface to the IIO core error logic (which might eventually escalate the error through the 14 RW1C 0b ERR[2:0] pins or message to CPU core or message to PCH). Note that the SERRE bit in the PCICMD register must be set for a device to report the error the IIO core error logic.Software clears this bit by writing a '1' to it. This bit is also set (when SERR enable bit is set) when a FATAL/NON-FATAL message is forwarded to the IIO core error logic. Note that IIO internal 'core' errors (like parity error in the internal queues) are not reported via this bit. 0: The root port did not report a fatal/non-fatal error

RMA Received Master Abort This bit is set when a root port experiences a master abort condition on a transaction it mastered on the primary interface (uncore internal bus). Note that certain errors might be detected right at the PCI Express interface and those transactions might not 'propagate' to the primary interface before the error is detected (e.g. accesses to memory above TOCM in cases where the PCIE interface logic itself might have visibility into TOCM). 13 RW1C 0b Such errors do not cause this bit to be set, and are reported via the PCI Express interface error bits (secondary status register). Conditions that cause bit 13 to be set, include: • Device receives a completion on the primary interface (internal bus of uncore) with Unsupported Request or master abort completion Status. This includes UR status received on the primary side of a PCI Express port on peer-to-peer completions also. • Other master abort conditions detected on the IIO internal bus amongst those listed in the Chapter 5, 'Inbound Address Decoding,' chapter.

Intel® Xeon Phi™ Processor 133 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 6h Bus: RootBus Device: 1Function: 0-3 Offset: 6h Bus: RootBus Device: 2Function: 0-3 Offset: 6h

Bit Attr Default Description

RTA Received Target Abort This bit is set when a device experiences a completer abort condition on a transaction it mastered on the primary interface (uncore internal bus). Note that certain errors might be detected right at the PCI Express interface and those transactions might not 'propagate' to the primary interface before the error is detected (e.g. accesses to memory above VTBAR). Such errors do not cause this 12 RW1C 0b bit to be set, and are reported via the PCI Express interface error bits (secondary status register). Conditions that cause bit 12 to be set, include: Device receives a completion on the primary interface (internal bus of uncore) with completer abort completion Status. This includes CA status received on the primary side of a PCI Express port on peer-to-peer completions also. Other completer abort conditions detected on the uncore internal bus amongst those listed in the Chapter 5, 'Inbound Address Decoding,' chapter.

DEVSEL_Timing 10:9 RO 0h Not applicable to PCI Express. Hardwired to 0.

MDPE Master Data Parity Error 8RW1C0b This bit is set by a root port if the Parity Error Response bit in the PCI Command register is set and it either receives a completion with poisoned data from the primary side or it forwards a packet with data (including MSI writes) to the primary side with poison.

Fast_Back_To_Back 7RO0b Not applicable to DMI or PCI Express. Hardwired to 0.

6 RV 0b Reserved

pci66MHz_capable 5RO0b Not applicable to DMI or PCI Express. Hardwired to 0.

Capabilities_List 4RO1b This bit indicates the presence of a capabilities list structure.

INTx_Status This Read-only bit reflects the state of the interrupt in the PCI-Express Root Port. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, will this device generate INTx interrupt. Setting the Interrupt Disable bit to a 1 has no effect on the state of 3RO-V0b this bit.This bit does not get set for interrupts forwarded to the root port from downstream devices in the hierarchy. When MSI are enabled, Interrupt status should not be set. The INTx status bit should be deasserted when all the relevant events (RAS errors/HP/link change status/PM) internal to the port using legacy interrupts are cleared by software.

2:0 RV 0h Reserved

6.1.5 RID: RID

Bus: RootBus Device: 0Function: 2-3 Offset: 8h Bus: RootBus Device: 1Function: 0Offset: 8h Bus: RootBus Device: 1Function: 1-3 Offset: 8h Bus: RootBus Device: 2Function: 0-3 Offset: 8h

Bit Attr Default Description

Revision_ID 7:0 RO-V 00h Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to this register.

134 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.6 CCR: Class Code Register

Bus: RootBus Device: 0Function: 2-3 Offset: 9h Bus: RootBus Device: 1Function: 0Offset: 9h Bus: RootBus Device: 1Function: 1-3 Offset: 9h Bus: RootBus Device: 2Function: 0-3 Offset: 9h

Bit Attr Default Description

23:16 RO 06h Base_Class For Root ports (including the mode operation as a DMI Port) this field is hardwired to 06h, indicating it is a 'Bridge Device'.

15:8 RO 04h Sub_Class For Root ports, this field defaults to 04h indicating 'PCI-PCI bridge'. This register changes to the sub class of 00h to indicate 'Host Bridge', when bit 0 in the MISCCTRLSTS register is set.

7:0 RO 00h Interface This field is hardwired to 00h for PCI Express ports.

6.1.7 CLSR: Cacheline Size Register

Bus: RootBus Device: 0Function: 2-3 Offset: Ch Bus: RootBus Device: 1Function: 0-3 Offset: Ch Bus: RootBus Device: 2Function: 0-3 Offset: Ch

Bit Attr Default Description

Cacheline_Size 7:0 RW 00h This register is set as RW for compatibility reasons only. Cacheline size is 64B. IIO ignores this setting.

6.1.8 HDR:Header Type

Bus: RootBus Device: 0Function: 2-3 Offset: Eh Bus: RootBus Device: 1Function: 0Offset: Eh Bus: RootBus Device: 1Function: 1-3 Offset: Eh Bus: RootBus Device: 2Function: 0-3 Offset: Eh

Bit Attr Default Description

Multi_function_Device Device 0 defaults to 0, since it is not a multifunction device This bit defaults to 1 for Devices 1-3 since these are multifunction devices. BIOS can individually control the value of this bit in Function 0 of these devices, based on 7RO-V1b HDRTYPCTRL register. BIOS will write to that register to change this field to 0 in Function 0 of these devices, if it exposes only Function 0 in the device to OS. Notes: In product SKUs where only Function 0 of the device is exposed to any software (BIOS/OS), BIOS would have to still set the control bits mentioned above to set the this bit in this register to be compliant per PCI rules.

Configuration_Layout 6:0 RO 01h This field identifies the format of the configuration header layout. In PCIe mode, the default is 01h, corresponding to Type 1 for a PCIe root port.

Intel® Xeon Phi™ Processor 135 Datasheet - Volume 2, December 2016 6.1.9 PBUS: Primary Bus Number Register

Bus: RootBus Device: 0Function: 2-3 Offset: 18h Bus: RootBus Device: 1Function: 0Offset: 18h Bus: RootBus Device: 1Function: 1-3 Offset: 18h Bus: RootBus Device: 2Function: 0-3 Offset: 18h

Bit Attr Default Description

PBN Primary Bus Number 7:0 RW 00h Configuration software programs this field with the number of the bus on the primary side of the bridge. This register has to be kept consistent with the Internal Bus Number 0 in the CPUBUSNO01 register. BIOS (and OS if internal bus number gets moved) must program this register to the correct value since IIO hardware would depend on this register for inbound configuration cycle decode purposes.

6.1.10 SECBUS: Secondary Bus Number

Bus: RootBus Device: 0Function: 2-3 Offset: 19h Bus: RootBus Device: 1Function: 0Offset: 19h Bus: RootBus Device: 1Function: 1-3 Offset: 19h Bus: RootBus Device: 2Function: 0-3 Offset: 19h

Bit Attr Default Description

SBN Secondary Bus Number 7:0 RW 00h This field is programmed by configuration software to assign a bus number to the secondary bus of the virtual P2P bridge. IIO uses this register to either forward a configuration transaction as a Type 1 or Type 0 to PCI Express.

6.1.11 SUBBUS: Subordinate Bus Number Register

Bus: RootBus Device: 0Function: 2-3 Offset: 1Ah Bus: RootBus Device: 1Function: 0Offset: 1Ah Bus: RootBus Device: 1Function: 1-3 Offset: 1Ah Bus: RootBus Device: 2Function: 0-3 Offset: 1Ah

Bit Attr Default Description

Subordinate_Bus_Number Subordinate Bus Number 7:0 RW 00h This register is programmed by configuration software with the number of the highest subordinate bus that is behind the PCI Express port. Any transaction that falls between the secondary and subordinate bus number (both inclusive) of an Express port is forwarded to the express port.

6.1.12 IOBAS: I/O Base Register

Bus: RootBus Device: 0Function: 2-3 Offset: 1Ch Bus: RootBus Device: 1Function: 0Offset: 1Ch Bus: RootBus Device: 1Function: 1-3 Offset: 1Ch Bus: RootBus Device: 2Function: 0-3 Offset: 1Ch

Bit Attr Default Description

I_O_Base_Address 7:4 RW Fh Corresponds to A[15:12] of the I/O base address of the PCI Express port. See also the IOLIM register description.

More_I_O_Base_Address When EN1K is set in the IIOMISCCTRL register, these bits become RW and allow for 1K granularity of I/O addressing, otherwise these are RO. 3:2 RW-L 0h Note: the default value of this register should be 00b according to the PCI-PCI bridge spec. BIOS must override this default value to fix this issue. Lock:!IIOMISCCTRL.EN1K

I_O_Address_capability 1:0 RO 0h IIO supports only 16 bit addressing

136 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.13 IOLIM: I/O Limit Register

Bus: RootBus Device: 0Function: 2-3 Offset: 1Dh Bus: RootBus Device: 1Function: 0Offset: 1Dh Bus: RootBus Device: 1Function: 1-3 Offset: 1Dh Bus: RootBus Device: 2Function: 0-3 Offset: 1Dh

Bit Attr Default Description

I_O_Address_Limit Corresponds to A[15:12] of the I/O limit address of the PCI Express port.The I/O Base and I/O Limit registers define an address range that is used by the PCI Express port to determine when to forward I/O transactions from one interface to the other using the following formula: IO_BASE <= A[15:12] <=IO_LIMIT The bottom of the defined I/O address range will be aligned to a 4KB boundary (1KB if EN1K bit is 7:4 RW 0h set. Refer to the IIOMISCCTRL register for definition of EN1K bit) while the top of the region specified by IO_LIMIT will be one less than a 4 KB (1KB if EN1K bit is set) multiple. Notes: • Setting the I/O limit less than I/O base disables the I/O range altogether. • General the I/O base and limit registers won't be programmed by software without clearing the IOSE bit first.

More_I_O_Address_Limit When EN1K is set in the IIOMISCCTRL register, these bits become RW and allow for 1K granularity 3:2 RW-L 0h of I/O addressing, otherwise these are RO. Lock:!IIOMISCCTRL.EN1K

I_O_Address_Limit_Capability 1:0 RO 0h IIO supports only 16 bit addressing

6.1.14 SECSTS: Secondary Status Register

Bus: RootBus Device: 0Function: 2-3 Offset: 1Eh Bus: RootBus Device: 1Function: 0Offset: 1Eh Bus: RootBus Device: 1Function: 1-3 Offset: 1Eh Bus: RootBus Device: 2Function: 0-3 Offset: 1Eh

Bit Attr Default Description

DPE Detected Parity Error 15 RW1C 0b This bit is set by the root port whenever it receives a poisoned TLP in the PCI Express port. This bit is set regardless of the state the Parity Error Response Enable bit in the Bridge Control register.

RSE Received System Error 14 RW1C 0b This bit is set by the root port when it receives a ERR_FATAL or ERR_NONFATAL message from PCI Express. Note this does not include the virtual ERR* messages that are internally generated from the root port when it detects an error on its own.

RMA Received Master Abort Status 13 RW1C 0b This bit is set when the root port receives a Completion with 'Unsupported Request Completion' Status or when the root port master aborts a Type0 configuration packet that has a non-zero device number.

RTA 12 RW1C 0b Received Target Abort Status This bit is set when the root port receives a Completion with 'Completer Abort' Status.

STA Signaled Target Abort 11 RW1C 0b This bit is set when the root port sends a completion packet with a 'Completer Abort' Status (including peer-to- peer completions that are forwarded from one port to another)

DEVSEL_Timing 10:9 RO 0h Not applicable to PCI Express. Hardwired to 0.

Intel® Xeon Phi™ Processor 137 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 1Eh Bus: RootBus Device: 1Function: 0Offset: 1Eh Bus: RootBus Device: 1Function: 1-3 Offset: 1Eh Bus: RootBus Device: 2Function: 0-3 Offset: 1Eh

Bit Attr Default Description

MDPE Master Data Parity Error This bit is set by the root port on the secondary side (PCI Express link) if the Parity Error Response Enable bit (PERRE) is set in Bridge Control register and either of the following two conditions 8RW1C0b occurs: The PCI Express port receives a Completion from PCI Express marked poisoned. The PCI Express port poisons an outgoing packet with data If the Parity Error Response Enable bit in Bridge Control Register is cleared, this bit is never set.

Fast_Back_To_Back 7RO0b Not applicable to DMI or PCI Express. Hardwired to 0.

6 RV 0b Reserved

pci66MHz_capable 5RO0b Not applicable to DMI or PCI Express. Hardwired to 0.

4:0 RV 0h Reserved

6.1.15 MBAS: Memory Base

Bus: RootBus Device: 0Function: 2-3 Offset: 20h Bus: RootBus Device: 1Function: 0Offset: 20h Bus: RootBus Device: 1Function: 1-3 Offset: 20h Bus: RootBus Device: 2Function: 0-3 Offset: 20h

Bit Attr Default Description

Memory_Base_Address 15:4 RW FFFh Corresponds to A[31:20] of the 32 bit memory window's base address of the PCI Express port. See also the MLIM register description.

3:0 RV 0 Reserved

6.1.16 MLIM: Memory Limit

Bus: RootBus Device: 0Function: 2-3 Offset: 22h Bus: RootBus Device: 1Function: 0Offset: 22h Bus: RootBus Device: 1Function: 1-3 Offset: 22h Bus: RootBus Device: 2Function: 0-3 Offset: 22h

Bit Attr Default Description

Memory_Limit_Address Corresponds to A[31:20] of the 32 bit memory window's limit address that corresponds to the upper limit of the range of memory accesses that will be passed by the PCI Express bridge.The Memory Base and Memory Limit registers define a memory mapped I/O non-prefetchable address range (32-bit addresses) and the IIO directs accesses in this range to the PCI Express port based on the following formula: MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT The upper 12 bits of both the Memory Base and Memory Limit registers are read/write and 15:4 RW 000h corresponds to the upper 12 address bits, A[31:20] of 32-bit addresses. Thus, the bottom of the defined memory address range will be aligned to a 1 MB boundary and the top of the defined memory address range will be one less than a 1 MB boundary. Refer to Chapter 5, 'Address Map,' (IOH Platform Architecture Specification) for further details on decoding. Notes: • Setting the memory limit less than memory base disables the 32-bit memory range altogether. • Note that in general the memory base and limit registers won't be programmed by software without clearing the MSE bit first.

3:0 RV 0 Reserved

138 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.17 PBAS: Prefetchable Memory Base Register

Bus: RootBus Device: 0Function: 2-3 Offset: 24h Bus: RootBus Device: 1Function: 0Offset: 24h Bus: RootBus Device: 1Function: 1-3 Offset: 24h Bus: RootBus Device: 2Function: 0-3 Offset: 24h

Bit Attr Default Description

Prefetchable_Memory_Base_Address 15:4 RW FFFh Corresponds to A[31:20] of the prefetchable memory address range's base address of the PCI Express port. See also the PLIMU register description.

Prefetchable_Memory_Base_Address_Capability 3:0 RO 1h IIO sets this bit to 01h to indicate 64bit capability.

6.1.18 PLIM: Prefetchable Memory Limit

Bus: RootBus Device: 0Function: 2-3 Offset: 26h Bus: RootBus Device: 1Function: 0Offset: 26h Bus: RootBus Device: 1Function: 1-3 Offset: 26h Bus: RootBus Device: 2Function: 0-3 Offset: 26h

Bit Attr Default Description

Prefetchable_Memory_Limit_Address 15:4 RW 000h Corresponds to A[31:20] of the prefetchable memory address range's limit address of the PCI Express port. See also the PLIMU register description.

Prefetchable_Memory_Limit_ Address_Capability 3:0 RO 1h IIO sets this bit to 01h to indicate 64bit capability.

6.1.19 PBASU: Prefetchable Memory Base (Upper 32 bits)

Bus: RootBus Device: 0Function: 2-3 Offset: 28h Bus: RootBus Device: 1Function: 0Offset: 28h Bus: RootBus Device: 1Function: 1-3 Offset: 28h Bus: RootBus Device: 2Function: 0-3 Offset: 28h

Bit Attr Default Description

Prefetchable_Upper_32_bit_Memory_Base_Address 31:0 RW FFFFFFFFh Corresponds to A[63:32] of the prefetchable memory address range's base address of the PCI Express port. See also the PLIMU register description.

Intel® Xeon Phi™ Processor 139 Datasheet - Volume 2, December 2016 6.1.20 PLIMU: Prefetchable Memory Limit (Upper 32 bits)

Bus: RootBusDevice: 0Function: 2-3Offset: 2Ch Bus: RootBusDevice: 1 Function: 0Offset: 2Ch Bus: RootBusDevice: 1 Function: 1-3Offset: 2Ch Bus: RootBus Device: 2Function: 0-3 Offset: 2Ch

Bit Attr Default Description

Prefetchable_Upper_32_bit_Memory_Limit_Address Corresponds to A[63:32] of the prefetchable memory address range's limit address of the PCI Express port.The Prefetchable Memory Base and Memory Limit registers define a memory mapped I/O prefetchable address range (64-bit addresses) which is used by the PCI Express bridge to determine when to forward memory transactions based on the following formula: PREFETCH_MEMORY_BASE_UPPER:: PREFETCH_MEMORY_BASE <= A[63:20] <= PREFETCH_MEMORY_LIMIT_UPPER::PREFETCH_MEMORY_LIMIT The upper 12 bits of both the Prefetchable Memory Base and Memory Limit registers are read/write and corresponds to the upper 12 address bits, A[31:20] of 32-bit addresses. The bottom of the defined memory address range will be aligned to a 1 MB boundary and the top of the defined memory address range will be one less than a 1 MB boundary. 000000 31:0 RW The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit registers 00h are read-only, contain the same value, and encode whether or not the bridge supports 64-bit addresses. If these four bits have the value 0h, then the bridge supports only 32 bit addresses. If these four bits have the value 1h, then the bridge supports 64-bit addresses and the Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers hold the rest of the 64-bit prefetchable base and limit addresses respectively. Setting the prefetchable memory limit less than prefetchable memory base disables the 64-bit prefetchable memory range altogether. Notes: • In general the memory base and limit registers won't be programmed by software without clearing the MSE bit first.

6.1.21 CAPPTR: Capability Pointer

Bus: RootBus Device: 0Function: 2-3 Offset: 34h Bus: RootBus Device: 1Function: 0Offset: 34h Bus: RootBus Device: 1Function: 1-3 Offset: 34h Bus: RootBus Device: 2Function: 0-3 Offset: 34h

Bit Attr Default Description

Capability_Pointer 7:0 RO 40h Points to the first capability structure for the device which is the SVID/SSID capability.

140 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.22 INTL: Interrupt Line Register

Bus: RootBus Device: 0Function: 2-3 Offset: 3Ch Bus: RootBus Device: 1Function: 0-3 Offset: 3Ch Bus: RootBus Device: 2Function: 0-3 Offset: 3Ch

Bit Attr Default Description

Interrupt_Line 7:0 RW 00h This is RW only for compatibility reasons. IIO hardware does not use it for any reason.

6.1.23 INTPIN: Interrupt Pin Register

Bus: RootBus Device: 0Function: 2-3 Offset: 3Dh Bus: RootBus Device: 1Function: 0-3 Offset: 3Dh Bus: RootBus Device: 2Function: 0-3 Offset: 3Dh

Bit Attr Default Description

INTP The only allowed values in this register are 00h and 01h. BIOS will leave the register at its default value unless it chooses to fully defeature INTx generation from a root port. For the latter scenario, BIOS will write a value of 00h before OS takes control. OS when it reads this register to be 00h understands that the root port does not generate any INTx interrupt. This helps simplify some of the BIOS ACPI tables relating to interrupts, when INTx 7:0 RW-O 01h interrupt generation from a root port is not enabled in the platform. Note that when BIOS writes a value of 00h in this register, that in itself does not disable INTx generation in hardware. Disabling INTx generation in hardware has to be achieved through the INTx Disable bit in the PCICMD register. Also, reader is referred to the MSI enable bit in MSICTRL for a description of how software selects MSI vs. INTx interrupt for the system interrupt method. IIO hardware does not use this bit for anything.

6.1.24 BCTRL: Bridge Control Register

Bus: RootBus Device: 0Function: 2-3 Offset: 3Eh Bus: RootBus Device: 1Function: 0Offset: 3Eh Bus: RootBus Device: 1Function: 1-3 Offset: 3Eh Bus: RootBus Device: 2Function: 0-3 Offset: 3Eh

Bit Attr Default Description

15:12 RV 0 Reserved

DTSERRSTS 11 RO 0b Discard Timer SERR Status Not applicable to PCI Express. This bit is hardwired to 0.

DTS 10 RO 0b Discard Timer Status Not applicable to PCI Express. This bit is hardwired to 0.

SDT 9RO0bSecondary Discard Timer Not applicable to PCI Express. This bit is hardwired to 0.

PDT 8RO0bPrimary Discard Timer Not applicable to PCI Express. This bit is hardwired to 0.

FB2BEN 7RO0bFast Back-to-back Enable Not applicable to PCI Express. This bit is hardwired to 0.

Intel® Xeon Phi™ Processor 141 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 3Eh Bus: RootBus Device: 1Function: 0Offset: 3Eh Bus: RootBus Device: 1Function: 1-3 Offset: 3Eh Bus: RootBus Device: 2Function: 0-3 Offset: 3Eh

Bit Attr Default Description

SBR Secondary Bus Reset 1: Setting this bit triggers a hot reset on the link for the corresponding PCI Express port and the PCI Express hierarchy domain subordinate to the port. This sends the LTSSM into the Training (or Link) Control Reset state, which necessarily implies a reset to the downstream device and all 6RW0bsubordinate devices. The transaction layer corresponding to port will be emptied by virtue of the link going down when this bit is set. This means that in the outbound direction, all posted transactions are dropped and non-posted transactions are sent a UR response. In the inbound direction, completions for inbound NP requests are dropped when they arrive. Inbound posted writes are retired normally.Note also that a secondary bus reset will not reset the virtual PCI-to-PCI bridge configuration registers of the targeted PCI Express port. 0: No reset happens on the PCI Express port.

MAM 5RO0bMaster Abort Mode Not applicable to PCI Express. This bit is hardwired to 0.

VGA16b VGA 16-bit decode This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB. 4RW0b0: execute 10-bit address decodes on VGA I/O accesses. 1: execute 16-bit address decodes on VGA I/O accesses. Notes: This bit only has meaning if bit 3 of this register is also set to 1, enabling VGA I/O decoding and forwarding by the bridge. Refer to PCI-PCI Bridge Specification Revision 1.2 for further details of this bit behavior.

VGAEN VGA Enable 3RW0b Controls the routing of CPU initiated transactions targeting VGA compatible I/O and memory address ranges. This bit must only be set for one p2p port in the entire system.

ISAEN ISA Enable Modifies the response by the root port to an I/O access issued by the core that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIM registers. 2RW0b1: The root port will not forward to PCI Express any I/O transactions addressing the last 768 bytes in each 1KB block even if the addresses are within the range defined by the IOBASE and IOLIM registers. 0: All addresses defined by the IOBASE and IOLIM for core issued I/O transactions will be mapped to PCI Express.

SERRE SERR Response Enable This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL messages from the PCI Express port to the primary side. 1RW0b 1: Enables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL messages. 0: Disables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL Refer to PCI Express Base Specification, Revision 2.0 and RAS Chapter for details of the myriad control bits that control error reporting in IIO.

PERRE 0RW0bParity Error Response Enable This only effect this bit has is on the setting of bit 8 in the SECSTS register.

142 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.25 SCAPID: Subsystem Capability Identity

Bus: RootBus Device: 0Function: 2-3 Offset: 40h Bus: RootBus Device: 1Function: 0Offset: 40h Bus: RootBus Device: 1Function: 1-3 Offset: 40h Bus: RootBus Device: 2Function: 0-3 Offset: 40h

Bit Attr Default Description

Capability_ID 7:0 RO 0Dh Assigned by PCI-SIG for subsystem capability ID

6.1.26 SNXTPTR: Subsystem ID Next Pointer

Bus: RootBus Device: 0Function: 2-3 Offset: 41h Bus: RootBus Device: 1Function: 0Offset: 41h Bus: RootBus Device: 1Function: 1-3 Offset: 41h Bus: RootBus Device: 2Function: 0-3 Offset: 41h

Bit Attr Default Description

Next_Ptr 7:0 RO 60h Next Capability Pointer This field is set to 60h for the next capability list (MSI capability structure) in the chain.

6.1.27 SVID: Subsystem Vendor ID

Bus: RootBusDevice: 0Function: 2-3Offset: 46h Bus: RootBusDevice: 1Function: 0Offset: 46hMode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: 46h Bus: RootBusDevice: 2Function: 0-3Offset: 46h

Bit Attr Default Description

Subsystem_Vendor_ID 15:0 RW-O 8086h The default value specifies Intel but can be set to any value once after reset.

6.1.28 SSID: Subsystem ID

Bus: RootBus Device: 0Function: 2-3 Offset: 46h Bus: RootBus Device: 1Function: 0Offset: 46h Bus: RootBus Device: 1Function: 1-3 Offset: 46h Bus: RootBus Device: 2Function: 0-3 Offset: 46h

Bit Attr Default Description

Subsystem_ID 15:0 RW-O 0000h The default value specifies Intel but can be set to any value once after reset.

6.1.29 MSICAPID: MSI Capability ID

Bus: RootBus Device: 0Function: 2-3 Offset: 60h Bus: RootBus Device: 1Function: 0Offset: 60h Bus: RootBus Device: 1Function: 1-3 Offset: 60h Bus: RootBus Device: 2Function: 0-3 Offset: 60h

Bit Attr Default Description

Capability_ID 7:0 RO 05h Assigned by PCI-SIG for MSI (root ports).

Intel® Xeon Phi™ Processor 143 Datasheet - Volume 2, December 2016 6.1.30 MSINXTPTR: MSI Next Pointer

Bus: RootBus Device: 0Function: 2-3 Offset: 61h Bus: RootBus Device: 1Function: 0Offset: 61h Bus: RootBus Device: 1Function: 1-3 Offset: 61h Bus: RootBus Device: 2Function: 0-3 Offset: 61h

Bit Attr Default Description

RW- Next_Ptr 7:0 90h O This field is set to 90h for the next capability list (PCI Express capability structure) in the chain.

6.1.31 MSIMSGCTL: MSI Control

Bus: RootBus Device: 0Function: 2-3 Offset: 62h Bus: RootBus Device: 1Function: 0Offset: 62h Bus: RootBus Device: 1Function: 1-3 Offset: 62h Bus: RootBus Device: 2Function: 0-3 Offset: 62h

Bit Attr Default Description

15:9 RV 0 Reserved

8RO1bPVMC Per-vector masking capable This bit indicates that PCI Express ports support MSI per- vector masking.

7 RO 0b B64AC Bus 64-bit Address Capable This field is hardwired to 0h since the message addresses are only 32-bit addresses (e.g. FEEx_xxxxh).

6:4 RW 000b MME Multiple Message Enable Applicable only to PCI Express ports. Software writes to this field to indicate the number of allocated messages which is aligned to a power of two. When MSI is enabled, the software will allocate at least one message to the device. A value of 000 indicates 1 message. Any value greater than or equal to 001 indicates a message of 2. See MSIDR for discussion on how the interrupts are distributed amongst the various sources of interrupt based on the number of messages allocated by software for the PCI Express ports.

3:1 RO 001b MMC Multiple Message Capable IIO Root Ports support two messages for all their internal events.

0RW0bMSIEN MSI Enable Software sets this bit to select INTx style interrupt or MSI interrupt for root port generated interrupts. 0: INTx interrupt mechanism is used for root port interrupts, provided the override bits in MISCCTRLSTS allow it 1: MSI interrupt mechanism is used for root port interrupts, provided the override bits in MISCCTRLSTS allow it Note there bits 4:2 and bit 2 MISCCTRLSTS can disable both MSI and INTx interrupt from being generated on root port interrupt events.

144 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.32 MSGADR: MSI Address

Bus: RootBus Device: 0Function: 2-3 Offset: 64h Bus: RootBus Device: 1Function: 0Offset: 64h Bus: RootBus Device: 1Function: 1-3 Offset: 64h Bus: RootBus Device: 2Function: 0-3 Offset: 64h

Bit Attr Default Description

31:2 RW 00000000h Address_ID Refer to the Interrupt Chapter for details of how this field is interpreted by IIO hardware. The definition of this field depends on whether interrupt remapping is enabled or disabled.

1:0 RV 0 Reserved

6.1.33 MSGDAT: MSI Data

Bus: RootBus Device: 0Function: 2-3 Offset: 68h Bus: RootBus Device: 1Function: 0Offset: 68h Bus: RootBus Device: 1Function: 1-3 Offset: 68h Bus: RootBus Device: 2Function: 0-3 Offset: 68h

Bit Attr Default Description

31:16 RV 0 Reserved

6.1.34 MSIMSK: MSI Mask Bit

Bus: RootBus Device: 0Function: 2-3 Offset: 6Ch Bus: RootBus Device: 1Function: 0Offset: 6Ch Bus: RootBus Device: 1Function: 1-3 Offset: 6Ch Bus: RootBus Device: 2Function: 0-3 Offset: 6Ch

Bit Attr Default Description

31:2 RV 0 Reserved

6.1.35 MSIPENDING: MSI Pending Bit

Bus: RootBus Device: 0Function: 2-3 Offset: 70h Bus: RootBus Device: 1Function: 0Offset: 70h Bus: RootBus Device: 1Function: 1-3 Offset: 70h Bus: RootBus Device: 2Function: 0-3 Offset: 70h

Bit Attr Default Description

31:2 RV 0 Reserved

Intel® Xeon Phi™ Processor 145 Datasheet - Volume 2, December 2016 6.1.36 PXPCAPID: PCI Express Capability Identity

Bus: RootBus Device: 0Function: 2-3 Offset: 90h Bus: RootBus Device: 1Function: 0-3 Offset: 90h Bus: RootBus Device: 2Function: 0-3 Offset: 90h

Bit Attr Default Description

Capability_ID 7:0 RO 10h Identifies the PCI Express capability assigned by PCI-SIG.

6.1.37 PXPNXTPTR: PCI Express Next Pointer

Bus: RootBus Device: 0Function: 2-3 Offset: 91h Bus: RootBus Device: 1Function: 0-3 Offset: 91h Bus: RootBus Device: 2Function: 0-3 Offset: 91h

Bit Attr Default Description

7:0 RO E0h Next_Ptr Pointer to the next capability. This field is set to the PCI PM capability.

6.1.38 PXPCAP: PCI Express Capability

Bus: RootBus Device: 0Function: 2-3 Offset: 92h Bus: RootBus Device: 1Function: 0Offset: 92h Bus: RootBus Device: 1Function: 1-3 Offset: 92h Bus: RootBus Device: 2Function: 0-3 Offset: 92h

Bit Attr Default Description

15:14 RV 0 Reserved

Interrupt_Message_Number Applies to root ports. This field indicates the interrupt message number that is generated for PM/HP/ 13:9 RO 00h BW-change events. When there are more than one MSI interrupt Number allocated for the root port MSI interrupts, this register field is required to contain the offset between the base Message Data and the MSI Message that is generated when there are PM/HP/BW-change interrupts. IIO assigns the first vector for PM/HP/BW-change events and so this field is set to 0.

Slot_Implemented Applies only to the root ports. 1: indicates that the PCI Express link associated with the port is connected to a slot. 8RW-O0b0: indicates no slot is connected to this port. Notes: This register is set by BIOS N/A in DMI Mode

Device_Port_Type 7:4 RO 4h This field identifies the type of device. It is set to 4h for all PCIe Root Ports in PCIe mode.

Capability_Version 3:0 RW-O 2h PCI Express Capability is Compliant with Version 2.0 of the PCI Express Spec.

6.1.39 DEVCAP: PCI Express Device Capability

Bus: RootBus Device: 0Function: 2-3 Offset: 94h Bus: RootBus Device: 1Function: 0Offset: 94h Bus: RootBus Device: 1Function: 1-3 Offset: 94h Bus: RootBus Device: 2Function: 0-3 Offset: 94h

Bit Attr Default Description

31:28 RV 0 Reserved

146 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 94h Bus: RootBus Device: 1Function: 0Offset: 94h Bus: RootBus Device: 1Function: 1-3 Offset: 94h Bus: RootBus Device: 2Function: 0-3 Offset: 94h

Bit Attr Default Description

Captured_Slot_Power_Limit_Scale 27:26 RO 0h Does not apply to root ports or integrated devices

Captured_Slot_Power_Limit_Value 25:18 RO 0h Does not apply to root ports or integrated devices

17:16 RV 0 Reserved

Role_Based_Error_Reporting 15 RO 1b IIO Supports Role Based Error Reporting

Power_Indicator_Present_on_Device 14 RO 0b Does not apply to root ports or integrated devices

Attention_Indicator_Present 13 RO 0b Does not apply to root ports or integrated devices

Attention_Button_Present 12 RO 0b Does not apply to root ports or integrated devices

Endpoint_L1_Acceptable_Latency 11:9 RO 000b Does not apply to root ports or integrated devices

Endpoint_L0s_Acceptable_Latency 8:6 RO 000b Does not apply to root ports or integrated devices

Extended_Tag_Field_Supported 5RO1b Supported

Phantom_Functions_Supported 4:3 RO 0h IIO does not support phantom functions.

Max_Payload_Size_Supported 2:0 RO 1h Supports 256B payloads on PCI Express Ports.

6.1.40 DEVCTRL: PCI Express Device Control

Bus: RootBus Device: 0Function: 2-3 Offset: 98h Bus: RootBus Device: 1Function: 0Offset: 98h Bus: RootBus Device: 1Function: 1-3 Offset: 98h Bus: RootBus Device: 2Function: 0-3 Offset: 98h

Bit Attr Default Description

15 RV 0 Reserved

Max_Read_Request_Size 14:12 RO 000b PCI Express ports do not generate requests greater than 64B and this field is RO.

Enable_No_Snoop 11 RO 0b Not applicable to PCIe root ports since they never set the 'No Snoop' bit for transactions they originate (not forwarded from peer) to PCI Express/DMI. This bit has no impact on forwarding of NoSnoop attribute on peer requests.

Auxiliary_Power_Management_Enable 10 RO 0b Not applicable

Phantom_Functions_Enable 9RO0b Not applicable, since IIO never uses phantom functions as a requester.

Extended_Tag_Field_Enable 8RW0bNot applicable, since IIO never generates any requests on its own that uses tags 7:5. However, IIO forwards the entire tag field for peer to peer requests, so tag[7:5] could be set.

Intel® Xeon Phi™ Processor 147 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 98h Bus: RootBus Device: 1Function: 0Offset: 98h Bus: RootBus Device: 1Function: 1-3 Offset: 98h Bus: RootBus Device: 2Function: 0-3 Offset: 98h

Bit Attr Default Description

Enable_Relaxed_Ordering 4RW0bNot applicable to root ports since they never set relaxed ordering bit as a requester (this does not include tx forwarded from peer devices). This bit has no impact on forwarding of relaxed ordering attribute on peer requests.

Unsupported_Request_Reporting_Enable This bit controls the reporting of unsupported requests that IIO itself detects on requests it receives from a PCI Express port. 3RW0b0: Reporting of unsupported requests is disabled 1: Reporting of unsupported requests is enabled. Refer to PCI Express Base Specification, Revision 2.0 for complete details of how this bit is used in conjunction with other bits to UR errors.

Fatal_Error_Reporting_Enable Controls the reporting of fatal errors that IIO detects on the PCI Express/DMI interface. 0: Reporting of Fatal error detected by device is disabled 2RW0b1: Reporting of Fatal error detected by device is enabled. Refer to PCI Express Base Specification, Revision 2.0 for complete details of how this bit is used in conjunction with other bits to report errors. This bit is not used to control the reporting of other internal component uncorrectable fatal errors (at the port unit) in any way.

Non_Fatal_Error_Reporting_Enable Controls the reporting of non-fatal errors that IIO detects on the PCI Express interface. 0: Reporting of Non Fatal error detected by device is disabled 1RW0b1: Reporting of Non Fatal error detected by device is enabled Refer to PCI Express Base Specification, Revision 2.0 for complete details of how this bit is used in conjunction with other bits to report errors. This bit is not used to control the reporting of other internal component uncorrectable non-fatal errors (at the port unit) in any way.

6.1.41 DEVSTS: PCI Express Device Status

Bus: RootBus Device: 0Function: 2-3 Offset: 9Ah Bus: RootBus Device: 1Function: 0-3 Offset: 9Ah Bus: RootBus Device: 2Function: 0-3 Offset: 9Ah

Bit Attr Default Description

15:6 RV 0 Reserved

Transactions_Pending 5RO0b Does not apply to Root/DMI ports, that is, bit hardwired to 0 for these devices.

AUX_Power_Detected 4RO0b Does not apply to IIO

148 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 9Ah Bus: RootBus Device: 1Function: 0-3 Offset: 9Ah Bus: RootBus Device: 2Function: 0-3 Offset: 9Ah

Bit Attr Default Description

Unsupported_Request_Detected This bit indicates that the root port port detected an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register. 1: Unsupported Request detected at the device/port. These unsupported requests are NP requests inbound that the root port received and it detected them as unsupported requests (for example, 3RW1C0b address decoding failures that the root port detected on a packet, receiving inbound lock reads, BME bit is clear and so forth). 0: No unsupported request detected by the root port This bit is not set on peer2peer completions with UR status that are forwarded by the root port to the PCIe link.

Fatal_Error_Detected This bit indicates that a fatal (uncorrectable) error is detected by the root port. Errors are logged in 2RW1C0bthis register regardless of whether error reporting is enabled or not in the Device Control register. 1: Fatal errors detected 0: No Fatal errors detected

Non_Fatal_Error_Detected This bit gets set if a non-fatal uncorrectable error is detected by the root port. Errors are logged in 1RW1C0bthis register regardless of whether error reporting is enabled or not in the Device Control register. 1: Non Fatal errors detected 0: No non-Fatal Errors detected

Correctable_Error_Detected This bit gets set if a correctable error is detected by the root port. Errors are logged in this register 0RW1C0bregardless of whether error reporting is enabled or not in the PCI Express Device Control register. 1: correctable errors detected 0: No correctable errors detected

6.1.42 LNKCAP: PCI Express Link Capabilities

Bus: RootBus Device: 0Function: 2-3 Offset: 9Ch Bus: RootBus Device: 1Function: 0Offset: 9Ch Bus: RootBus Device: 1Function: 1-3 Offset: 9Ch Bus: RootBus Device: 2Function: 0-3 Offset: 9Ch

Bit Attr Default Description

Port_Number 31:24 RW-O 00h This field indicates the PCI Express port number for the link and is initialized by software/BIOS. IIO hardware does nothing with this bit.

23 RV 0 Reserved

22 RO 1b aspm_optionality_compliance

Link_Bandwidth_Notification_Capability A value of 1b indicates support for the Link Bandwidth Notification status and interrupt 21 RO-V 1b mechanisms. Notes: This bit will only be set if either “Report Speed Change” or “Report Configuration Change” bits are set in the DBG2STAT register (bits 22 and 20 respectively).

Correctable_Error_Reporting_Enable 20 RO 1b IIO supports reporting status of the data link layer so software knows when it can enumerate a device on the link or otherwise know the status of the link.

Surprise_Down_Error_Reporting_Capable 19 RO 1b IIO supports reporting a surprise down error condition

Clock_Power_Management 18 RO 0b Does not apply to the IIO

Intel® Xeon Phi™ Processor 149 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 9Ch Bus: RootBus Device: 1Function: 0Offset: 9Ch Bus: RootBus Device: 1Function: 1-3 Offset: 9Ch Bus: RootBus Device: 2Function: 0-3 Offset: 9Ch

Bit Attr Default Description

L1_Exit_Latency This field indicates the L1 exit latency for the given PCI- Express port. It indicates the length of time this port requires to complete transition from L1 to L0. 000: Less than 1us 001: 1 us to less than 2 us 010: 2 us to less than 4 us 17:15 RW-O 010b 011: 4 us to less than 8 us 100: 8 us to less than 16 us 101: 16 us to less than 32 us 110: 32 us to 64 us 111: More than 64us This register is made writable once by BIOS so that the value is settable based on experiments post-si.

L0s_Exit_Latency This field indicates the L0s exit latency (i.e L0s to L0) for the PCI-Express port. 000: Less than 64 ns 001: 64 ns to less than 128 ns 010: 128 ns to less than 256 ns 011: 256 ns to less than 512 ns 14:12 RW-O 011b 100: 512 ns to less than 1 us 101: 1 is to less than 2 us 110: 2 is to 4 us 111: More than 4 us This register is made writable once by BIOS so that the value is settable based on experiments post-si.

Active_State_Link_PM_Support This field indicates the level of active state power management supported on the given PCI-Express port. 11:10 RW-O 10b 00: Disabled 01: L0s Entry Supported 10: L1 Entry Support 11: L0s and L1 Supported

Maximum_Link_Width This field indicates the maximum width of the given PCI Express Link attached to the port. 000001: x1 000010: x2 9:4 RW-O 000100b 000100: x4 001000: x8 010000: x16 Others: Reserved This is left as a RW-O register for BIOS to update based on the platform usage of the links.

MAXLNKSPD Maximum Link Speed 0001: 2.5 Gbps (default for DMI in PCIe mode) 0010: 5 Gbps (This value will not be set in Port 0 if the DMIGEN2EN strap is '0') 0011: 8Gbps (Port 0 does not support this speed) 3:0 RW-O 0011b Others: Reserved JKT supports a maximum of 5Gbps for the DMI port, unless restricted by the DMIGEN2EN strap. IIO supports a maximum of 8Gbps, unless restricted by the Gen3_OFF fuse. If Gen3_OFF fuse is '1', this field defaults to 0010b (5Gbps) If Gen3_OFF fuse is '0' this field defaults to 0011b (8Gbps)

150 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.43 LNKCON: PCI Express Link Control

Bus: RootBus Device: 0Function: 2-3 Offset: A0h Bus: RootBus Device: 1Function: 0Offset: A0h Bus: RootBus Device: 1Function: 1-3 Offset: A0h Bus: RootBus Device: 2Function: 0-3 Offset: A0h

Bit Attr Default Description

15:12 RV 0 Reserved

Link_Autonomous_Bandwidth_Interrupt_Enable For root ports, when set to 1b this bit enables the generation of an interrupt to indicate that the 11 RW 0b Link Autonomous Bandwidth Status bit has been set.For DMI mode on Dev#0, interrupt is not supported and hence this bit is not useful. Expectation is that BIOS will set MISCCTRLSTS[27] to notify the system of autonomous BW change event on that port.

Link_Bandwidth_Management_Interrupt_Enable For root ports, when set to 1b this bit enables the generation of an interrupt to indicate that the 10 RW 0b Link Bandwidth Management Status bit has been set.For DMI mode on Dev#0, interrupt is not supported and hence this bit is not useful. Expectation is that BIOS will set MISCCTRLSTS[27] to notify the system of autonomous BW change event on that port.

Hardware_Autonomous_Width_Disable When Set, this bit disables hardware from changing the Link width for reasons other than 9RW0battempting to correct unreliable Link operation by reducing Link width. Note that IIO does not by itself change width for any reason other than reliability. So this bit only disables such a width change as initiated by the device on the other end of the link.

Enable_Clock_Power_Management 8RO0b N/A to the IIO

Extended_Synch 7RW0bThis bit when set forces the transmission of additional ordered sets when exiting L0s and when in recovery. See PCI Express Base Specification, Revision 2.0 for details.

Common_Clock_Configuration Software sets this bit to indicate that this component and the component at the opposite end of the Link are operating with a common clock source. A value of 0b indicates that this component and the component at the opposite end of the Link are operating with separate reference clock sources. Default value of this bit is 0b. 6RW0bComponents utilize this common clock configuration information to report the correct L0s and L1 Exit Latencies in the NFTS. The values used come from these registers depending on the value of this bit: 0: Use NFTS values from CLSPHYCTL3 1: Use NFTS values from CLSPHYCTL4

Retrain_Link A write of 1 to this bit initiates link retraining in the given PCI Express/DMI port by directing the LTSSM to the recovery state if the current state is [L0, L0s or L1]. If the current state is anything 5WO0bother than L0, L0s, L1 then a write to this bit does nothing. This bit always returns 0 when read.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that already in progress.

Link_Disable This field controls whether the link associated with the PCI Express/DMI port is enabled or disabled. When this bit is a 1, a previously configured link would return to the 'disabled' state as defined in 4RW0bthe PCI Express Base Specification, Revision 2.0. When this bit is clear, an LTSSM in the 'disabled' state goes back to the detect state. 0: Enables the link associated with the PCI Express port 1: Disables the link associated with the PCI Express port

Read_Completion_Boundary 3RO0b Set to zero to indicate IIO could return read completions at 64B boundaries

2RV0Reserved

Active_State_Link_PM_Control 1:0 RW 00b When 01b or 11b, L0s on transmitter is enabled, otherwise it is disabled. 10 and 11 enables L1 ASPM.

Intel® Xeon Phi™ Processor 151 Datasheet - Volume 2, December 2016 6.1.44 LNKSTS: PCI Express Link Status

Bus: RootBus Device: 0Function: 2-3 Offset: A2h Bus: RootBus Device: 1Function: 0Offset: A2h Bus: RootBus Device: 1Function: 1-3 Offset: A2h Bus: RootBus Device: 2Function: 0-3 Offset: A2h

Bit Attr Default Description

Link_Autonomous_Bandwidth_Status This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or 15 RW1C 0b width, without the port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable link operation. IIO does not, on its own, change speed or width autonomously for non-reliability reasons. IIO only sets this bit when it receives a width or speed change indication from downstream component that is not for link reliability reasons.

Link_Bandwidth_Management_Status This bit is set to 1b by hardware to indicate that either of the following has occurred without the 14 RW1C 0b port transitioning through DL_Down status:a) A link retraining initiated by a write of 1b to the Retrain Link bit has completed b) Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation Note IIO also sets this bit when it receives a width or speed change indication from downstream component that is for link reliability reasons.

Data_Link_Layer_Link_Active 13 RO-V 0b Set to 1b when the Data Link Control and Management State Machine is in the DL_Active state, 0b otherwise.When this bit is 0b, the transaction layer associated with the link will abort all transactions that would otherwise be routed to that link.

Slot_Clock_Configuration This bit indicates whether JKT receives clock from the same xtal that also provides clock to the 12 RW-O 1b device on the other end of the link.1: indicates that same xtal provides clocks to JKT and the slot or device on other end of the link 0: indicates that different xtals provide clocks to JKT and the slot or device on other end of the link In general, this field is expected to be set to 1b by BIOS based on board clock routing. Definitely this bit has to be set to 1b on DMI mode operation on Device#0.

Link_Training This field indicates the status of an ongoing link training session in the PCI Express port0: LTSSM has exited the recovery/configuration state 11 RO-V 0b 1: LTSSM is in recovery/configuration state or the Retrain Link was set but training has not yet begun. The IIO hardware clears this bit once LTSSM has exited the recovery/configuration state. Refer to PCI Express Base Specification, Revision 2.0 for details of which states within the LTSSM would set this bit and which states would clear this bit.

10 RV 0 Reserved

Negotiated_Link_Width This field indicates the negotiated width of the given PCI Express link after training is completed. Only x1, x2, x4, x8 and x16 link width negotiations are possible in JKT for Device#1-2 and only x1, 9:4 RO-V 00h x2 and x4 on Device#0. A value of 0x01 in this field corresponds to a link width of x1, 0x02 indicates a link width of x2 and so on, with a value of 0x10 for a link width of x16.The value in this field is reserved and could show any value when the link is not up. Software determines if the link is up or not by reading bit 13 of this register.

Current_Link_Speed This field indicates the negotiated Link speed of the given PCI Express Link. 0001: 2.5 Gbps 0010: 5 Gbps (This value will not be set in Port 0 if the DMIGEN2EN strap is '0') 3:0 RO-V 1h 0011: 8Gbps (Port 0 does not support this speed) Others: Reserved The value in this field is not defined when the link is not up. Software determines if the link is up or not by reading bit 13 of this register.

152 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.45 SLTCAP: PCI Express Slot Capabilities

Bus: RootBus Device: 0Function: 2-3 Offset: A4h Bus: RootBus Device: 1Function: 0Offset: A4h Bus: RootBus Device: 1Function: 1-3 Offset: A4h Bus: RootBus Device: 2Function: 0-3 Offset: A4h

Bit Attr Default Description

Physical_Slot_Number 31:19 RW-O 000h This field indicates the physical slot number of the slot connected to the PCI Express port and is initialized by BIOS.

Command_Complete_Not_Capable 18 RO 0b IIO is capable of command complete interrupt.

Electromechanical_Interlock_Present This bit when set indicates that an Electromechanical Interlock is implemented on the chassis for 17 RW-O 0b this slot and that lock is controlled by bit 11 in Slot Control register. This field is initialized by BIOS based on the system architecture.BIOS note: this capability is not set if the Electromechanical Interlock control is connected to main slot power control. This is expected to be used only for Express Module hot-pluggable slots.

Slot_Power_Limit_Scale This field specifies the scale used for the Slot Power Limit Value and is initialized by BIOS. IIO uses this field when it sends a Set_Slot_Power_Limit message on PCI Express. Range of Values: 16:15 RW-O 00b 00: 1.0x 01: 0.1x 10: 0.01x 11: 0.001x Writes to this register trigger a Set_Slot_Power_Limit message to be sent.

Slot_Power_Limit_Value This field specifies the upper limit on power supplied by slot in conjunction with the Slot Power Limit Scale value defined previously. Power limit (in Watts) = SPLS x SPLV. This field is initialized by 14:7 RW-O 00h BIOS. IIO uses this field when it sends a Set_Slot_Power_Limit message on PCI Express. Writes to this register trigger a Set_Slot_Power_Limit message to be sent. Design note: IIO sends the Set_Slot_Power_Limit message on the link at first link up condition (except on the DMI link operating in DMI mode) without regards to whether this register and the Slot Power Limit Scale register are programmed yet by BIOS.

Hot_plug_Capable This field defines hot-plug support capabilities for the PCI Express port. 0: indicates that this slot is not capable of supporting Hot- plug operations. 6RW-O0b 1: indicates that this slot is capable of supporting Hot-plug operations This bit is programed by BIOS based on the system design. This bit must be programmed by BIOS to be consistent with the VPP enable bit for the port.

Hot_plug_Surprise This field indicates that a device in this slot may be removed from the system without prior notification. This field is initialized by BIOS. 0: indicates that hot-plug surprise is not supported 1: indicates that hot-plug surprise is supported Generally this bit is not expected to be set because 5RW-O0bthe only know usage case for this is the ExpressCard FF. This is not really an expected usage in IIO context. But this bit is present regardless to allow a usage if it arises. This bit is used by IIO hardware to determine if a transition from DL_active to DL_Inactive is to be treated as a surprise down error or not. If a port is associated with a hot-pluggable slot and the hot-plug surprise bit is set, then any transition to DL_Inactive is not considered an error. Refer to PCI Express Base Specification, Revision 2.0 for further details.

Power_Indicator_Present This bit indicates that a Power Indicator is implemented for this slot and is electrically controlled by the chassis. 4RW-O0b 0: indicates that a Power Indicator that is electrically controlled by the chassis is not present 1: indicates that Power Indicator that is electrically controlled by the chassis is present BIOS programs this field with a 1 for CEM/Express Module FFs, if the slot is hot-plug capable.

Intel® Xeon Phi™ Processor 153 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: A4h Bus: RootBus Device: 1Function: 0Offset: A4h Bus: RootBus Device: 1Function: 1-3 Offset: A4h Bus: RootBus Device: 2Function: 0-3 Offset: A4h

Bit Attr Default Description

Attention_Indicator_Present This bit indicates that an Attention Indicator is implemented for this slot and is electrically controlled by the chassis 3RW-O0b 0: indicates that an Attention Indicator that is electrically controlled by the chassis is not present 1: indicates that an Attention Indicator that is electrically controlled by the chassis is present BIOS programs this field with a 1 for CEM/Express Module FFs, if the slot is hot-plug capable.

MRL_Sensor_Present This bit indicates that an MRL Sensor is implemented on the chassis for this slot. 0: indicates that an MRL Sensor is not present 2RW-O0b 1: indicates that an MRL Sensor is present BIOS programs this field with a 0 for Express Module FF always. If CEM slot is hot-plug capable, BIOS programs this field with either 0 or 1 depending on system design.

Power_Controller_Present This bit indicates that a software controllable power controller is implemented on the chassis for this slot. 1RW-O0b 0: indicates that a software controllable power controller is not present 1: indicates that a software controllable power controller is present BIOS programs this field with a 1 for CEM/Express Module FFs, if the slot is hot-plug capable.

Attention_Button_Present This bit indicates that the Attention Button event signal is routed (from slot or on-board in the chassis) to the IIO's hot-plug controller. 0RW-O0b 0: indicates that an Attention Button signal is routed to IIO 1: indicates that an Attention Button is not routed to IIO BIOS programs this field with a 1 for CEM/Express Module FFs, if the slot is hot-plug capable.

6.1.46 SLTCON: PCI Express Slot Control

Bus: RootBus Device: 0Function: 2-3 Offset: A8h Bus: RootBus Device: 1Function: 0Offset: A8h Bus: RootBus Device: 1Function: 1-3 Offset: A8h Bus: RootBus Device: 2Function: 0-3 Offset: A8h

Bit Attr Default Description

15:13 RV 0 Reserved

12 RWS 0b Data_Link_Layer_State_Changed_Enable When set to 1, this field enables software notification when Data Link Layer Link Active bit in the LNKSTS register changes state

11 RW 0b Electromechanical_Interlock_Control When software writes either a 1 to this bit, IIO pulses the EMIL pin for this slot. PCI Express Server/Workstation Module Electromechanical Spec Rev 1.0. Write of 0 has no effect. This bit always returns a 0 when read. If electromechanical lock is not implemented, then either a write of 1 or 0 to this register has no effect.

10 RWS 1b Power_Controller_Control If a power controller is implemented, when writes to this field will set the power state of the slot per the defined encodings. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined.0: Power On 1: Power Off Note: If the link experiences an unexpected DL_Down condition that is not the result of a Hot Plug removal, the Intel Xeon processor E5 v3 product family follows the PCI Express specification for logging Surprise Link Down. SW is required to set SLTCON[10] to 0 (Power On) in all devices that do not connect to a slot that supports Hot-Plug to enable logging of this error in that device. For devices connected to slots supporting Hot-Plug operations, SLTCON[10] usage to control PWREN# assertion is as described elsewhere.

154 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: A8h Bus: RootBus Device: 1Function: 0Offset: A8h Bus: RootBus Device: 1Function: 1-3 Offset: A8h Bus: RootBus Device: 2Function: 0-3 Offset: A8h

Bit Attr Default Description

9:8 RW 3h Power_Indicator_Control If a Power Indicator is implemented, writes to this field will set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write, even if the corresponding hot- plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 00: Reserved. 01: On 10: Blink (IIO drives 1 Hz square wave for Chassis mounted LEDs) 11: Off IIO does not generated the Power_Indicator_On/Off/Blink messages on PCI Express when this field is written to by software.

7:6 RW 3h Attention_Indicator_Control If an Attention Indicator is implemented, writes to this field will set the Attention Indicator to the written state. Reads of this field reflect the value from the latest write, even if the corresponding hot-plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 00: Reserved. 01: On 10: Blink (Intel Xeon processor E5 v3 product family drives 1 Hz square wave) 11: Off IIO does not generated the Attention_Indicator_On/Off/Blink messages on PCI Express when this field is written to by software.

5 RW 0b Hot_plug_Interrupt_Enable When set to 1b, this bit enables generation of Hot-Plug interrupt (MSI or INTx interrupt depending on the setting of the MSI enable bit in MSICTRL) on enabled Hot-Plug events, provided ACPI mode for hot-plug is disabled. 0: disables interrupt generation on Hot-plug events 1: enables interrupt generation on Hot-plug events

4 RW 0b Command_Completed_Interrupt_Enable This field enables software notification (Interrupt - MSI/INTx or WAKE) when a command is completed by the Hot-plug controller connected to the PCI Express port 0: disables hot-plug interrupts on a command completion by a hot-plug Controller 1: Enables hot-plug interrupts on a command completion by a hot-plug Controller

3 RW 0b Presence_Detect_Changed_Enable This bit enables the generation of hot-plug interrupts or wake messages via a presence detect changed event. 0: disables generation of hot-plug interrupts or wake messages when a presence detect changed event happens. 1: Enables generation of hot-plug interrupts or wake messages when a presence detect changed event happens.

2 RW 0b MRL_Sensor_Changed_Enable This bit enables the generation of hot-plug interrupts or wake messages via a MRL Sensor changed event. 0: disables generation of hot-plug interrupts or wake messages when an MRL Sensor changed event happens. 1: Enables generation of hot-plug interrupts or wake messages when an MRL Sensor changed event happens.

1 RW 0b Power_Fault_Detected_Enable This bit enables the generation of hot-plug interrupts or wake messages via a power fault event. 0: disables generation of hot-plug interrupts or wake messages when a power fault event happens. 1: Enables generation of hot-plug interrupts or wake messages when a power fault event happens.

0 RW 0b Attention_Button_Pressed_Enable This bit enables the generation of hot-plug interrupts or wake messages via an attention button pressed event. 0: disables generation of hot-plug interrupts or wake messages when the attention button is pressed. 1: Enables generation of hot-plug interrupts or wake messages when the attention button is pressed.

Intel® Xeon Phi™ Processor 155 Datasheet - Volume 2, December 2016 6.1.47 SLTSTS: PCI Express Slot Status

Bus: RootBus Device: 0Function: 2-3 Offset: AAh Bus: RootBus Device: 1Function: 0Offset: AAh Bus: RootBus Device: 1Function: 1-3 Offset: AAh Bus: RootBus Device: 2Function: 0-3 Offset: AAh

Bit Attr Default Description

15:9 RV 0 Reserved

8 RW1C 0b Data_Link_Layer_State_Changed This bit is set (if it is not already set) when the state of the Data Link Layer Link Active bit in the Link Status register changes. Software must read Data Link Layer Active field to determine the link state before initiating configuration cycles to the hot plugged device.

7 RO-V 0b Electromechanical_Latch_Status When read this register returns the current state of the Electromechanical Interlock (the EMILS pin) which has the defined encodings as: 0: Electromechanical Interlock Disengaged 1: Electromechanical Interlock Engaged

6 RO-V 0b Presence_Detect_State For ports with slots (where the Slot Implemented bit of the PCI Express Capabilities Registers is 1b), this field is the logical OR of the Presence Detect status determined via an in-band mechanism and sideband Present Detect pins. Refer to how PCI Express Base Specification, Revision 2.0 for how the inband presence detect mechanism works (certain states in the LTSSM constitute 'card present' and others don't). 0: Card/Module slot empty 1: Card/module Present in slot (powered or unpowered) For ports with no slots, IIO hardwires this bit to 1b. Note: OS could get confused when it sees an empty PCI Express root port that is, 'no slots + no presence', since this is now disallowed in the spec. So BIOS must hide all unused root ports devices in IIO config space, via the DEVHIDE register. Refer to RAS Chapter for details of how this bit is shifted in on the VPP bit stream.

5RO-V0bMRL_Sensor_State This bit reports the status of an MRL sensor if it is implemented. 0: MRL Closed 1: MRL Open Refer to RAS Chapter for details of how this bit is shifted in on the VPP bit stream.

4 RW1C 0b Command_Completed This bit is set by IIO when the hot-plug command has completed and the hot-plug controller is ready to accept a subsequent command. It is subsequently cleared by software after the field has been read and processed. This bit provides no guarantee that the action corresponding to the command is complete. Any write to SLTCON (regardless of the port is capable or enabled for hot-plug) is considered a 'hot-plug' command. If the port is not hot-plug capable or hot-plug enabled, then the hot-plug command does not trigger any action on the VPP port but the command is still completed via this bit.

3 RW1C 0b Presence_Detect_Changed This bit is set by IIO when the value reported in bit 6 is changes. It is subsequently cleared by software after the field has been read and processed.

2 RW1C 0b MRL_Sensor_Changed This bit is set if the value reported in bit 5 changes. It is subsequently cleared by software after the field has been read and processed.

1 RW1C 0b Power_Fault_Detected This bit is set by IIO when a power fault event is detected by the power controller (which is reported via the VPP bit stream). It is subsequently cleared by software after the field has been read and processed. Refer to RAS Chapter for details of how this bit is shifted in on the VPP bit stream.

0 RW1C 0b Attention_Button_Pressed This bit is set by IIO when the attention button is pressed. It is subsequently cleared by software after the field has been read and processed. Refer to RAS Chapter for details of how this bit is shifted in on the VPP bit stream. IIO silently discards the Attention_Button_Pressed message if received from PCI Express link without updating this bit.

156 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.48 ROOTCON: PCI Express Root Control

Bus: RootBus Device: 0Function: 2-3 Offset: ACh Bus: RootBus Device: 1Function: 0Offset: ACh Bus: RootBus Device: 1Function: 1-3 Offset: ACh Bus: RootBus Device: 2Function: 0-3 Offset: ACh

Bit Attr Default Description

15:5 RV 0 Reserved

4 RW 0b CRSSWVISEN CRS software visibility Enable 1: The Root Port to returns Configuration Request Retry Status (CRS) Completion Status to software by returning data of 0x01 when a configuration retry is returned by the connected device. 0: Retry status cannot be returned to software so the Configuration Request is re-issued to the connected device, unless the Configuration Retry Timer expires. If the timer expires, then a master abort response is returned to software.

3RW0bPMEINTEN PME Interrupt Enable This field controls the generation of MSI interrupts/INTx interrupts for PME messages. 1: Enables interrupt generation upon receipt of a PME message 0: Disables interrupt generation for PME messages

2RW0bSEFEEN System Error on Fatal Error Enable This field enables notifying the internal IIO core error logic of occurrence of an uncorrectable fatal error at the port or below its hierarchy. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message etc). Refer to RAS Chapter for details of how/which system notification is generated for a PCI Express fatal error. 1: indicates that an internal IIO core error logic notification should be generated if a fatal error (ERR_FATAL) is reported by any of the devices in the hierarchy associated with and including this port. 0: No internal IIO core error logic notification should be generated on a fatal error (ERR_FATAL) reported by any of the devices in the hierarchy associated with and including this port. Note that generation of system notification on a PCI Express fatal error is orthogonal to generation of an MSI/INTx interrupt for the same error. Both a system error and MSI/INTx can be generated on a fatal error and software can chose one of the two. Refer to PCI Express Base Specification, Revision 2.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port. Note that since this register is defined only in PCIe mode for Device#0, this bit will read a 0 in DMI mode. So, to enable core error logic notification on DMI mode fatal errors, BIOS must set bit MISCCTRLSTS[35] to a 1 to override this bit in DMI mode.

1 RW 0b SENFEEN System Error on Non-Fatal Error Enable This field enables notifying the internal IIO core error logic of occurrence of an uncorrectable non- fatal error at the port or below its hierarchy. The internal IIO core error logic then decides if/how to escalate the error further (pins/message etc). Refer to RAS Chapter for details of how/which system notification is generated for a PCI Express non-fatal error. 1: indicates that a internal IIO core error logic notification should be generated if a non-fatal error (ERR_NONFATAL) is reported by any of the devices in the hierarchy associated with and including this port. 0: No internal core error logic notification should be generated on a non-fatal error (ERR_NONFATAL) reported by any of the devices in the hierarchy associated with and including this port. Note that generation of system notification on a PCI Express non-fatal error is orthogonal to generation of an MSI/INTx interrupt for the same error. Both a system error and MSI/INTx can be generated on a non-fatal error and software can chose one of the two. Refer to PCI Express Base Specification, Revision 2.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port. Note that since this register is defined only in PCIe mode for Device#0, this bit will read a 0 in DMI mode. So, to enable core error logic notification on DMI mode non-fatal errors, BIOS must set MISCCTRLSTS[34] to a 1 to override this bit on Device#0 in DMI mode.

Intel® Xeon Phi™ Processor 157 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: ACh Bus: RootBus Device: 1Function: 0Offset: ACh Bus: RootBus Device: 1Function: 1-3 Offset: ACh Bus: RootBus Device: 2Function: 0-3 Offset: ACh

Bit Attr Default Description

0 RW 0b SECEEN System Error on Correctable Error Enable This field controls notifying the internal IIO core error logic of the occurrence of a correctable error in the device or below its hierarchy. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message etc). Refer to RAS Chapter for details of how/which system notification is generated for a PCI Express correctable error. 1: indicates that an internal core error logic notification should be generated if a correctable error (ERR_COR) is reported by any of the devices in the hierarchy associated with and including this port. 0: No internal core error logic notification should be generated on a correctable error (ERR_COR) reported by any of the devices in the hierarchy associated with and including this port. Note that generation of system notification on a PCI Express correctable error is orthogonal to generation of an MSI/INTx interrupt for the same error. Both a system error and MSI/INTx can be generated on a correctable error and software can chose one of the two. Refer to PCI Express Base Specification, Revision 2.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port. Note that since this register is defined only in PCIe mode for Device#0, this bit will read a 0 in DMI mode. So, to enable core error logic notification on DMI mode correctable errors, BIOS must set MISCCTRLSTS[33] to a 1 to override this bit on Device#0 in DMI mode.

6.1.49 ROOTCAP: PCI Express Root Capability

Bus: RootBus Device: 0Function: 2-3 Offset: AEh Bus: RootBus Device: 1Function: 0Offset: AEh Bus: RootBus Device: 1Function: 1-3 Offset: AEh Bus: RootBus Device: 2Function: 0-3 Offset: AEh

Bit Attr Default Description

15:1 RV 0 Reserved

0 RO 1b CRS_Software_Visibility This bit, when set, indicates that the Root Port is capable of returning Configuration Request Retry Status (CRS) Completion Status to software. IIO supports this capability.

6.1.50 ROOTSTS: PCI Express Root Capability

Bus: RootBus Device: 0Function: 2-3 Offset: B0h Bus: RootBus Device: 1Function: 0Offset: B0h Bus: RootBus Device: 1Function: 1-3 Offset: B0h Bus: RootBus Device: 2Function: 0-3 Offset: B0h

Bit Attr Default Description

31:18 RV 0 Reserved

17 RO-V 0b PME_Pending This field indicates that another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software; the pending PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately. The PME pending bit is cleared by hardware if no more PMEs are pending.

16 RW1C 0b PME_Status This field indicates a PM_PME message (either from the link or internally from within that root port) was received at the port. 1: PME was asserted by a requester as indicated by the PME Requester ID field This bit is cleared by software by writing a '1'. Note that the root port itself could be the source of a PME event when a hotplug event is observed when the port is in D3hot state.

15:0 RO-V 0000h PME_Requester_ID This field indicates the PCI requester ID of the last PME requestor. If the root port itself was the source of the (virtual) PME message, then a RequesterID of CPUBUSNO0:DevNo:FunctionNo is logged in this field.

158 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.51 DEVCAP2: PCI Express Device Capability 2

Bus: RootBus Device: 0Function: 2-3 Offset: B4h Bus: RootBus Device: 1Function: 0-3 Offset: B4h Bus: RootBus Device: 2Function: 0-3 Offset: B4h

Bit Attr Default Description

31:14 RV 0 Reserved

13:12 RW-LB 01b TPH_Completer_Supported Indicates the support for TLP Processing Hints. Intel Xeon processor E5 v3 product family does not support the extended TPH header. 00: TPH and Extended TPH Completer not supported. 01: TPH Completer supported; Extended TPH Completer not supported. 10: Reserved. 11: Both TPH and Extended TPH Completer supported.

11 RW-LB 1b LTR_Supported A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism capability.

10 RO 0b No_RO_Supported If this bit is Set, the routing element never carries out the passing permitted by PCIe Table 2-27 entry A2b that is associated with the Relaxed Ordering Attribute field being Set. This bit applies only for Switches and RCs that support peer to peer traffic between Root Ports. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. All Ports on a Switch or RC must report the same value for this bit. For all other functions, this bit must be 0b.

9 RO 0b ATOMIC128bCASCOMPSUP AtomicOp CAS Completer 128-bit Operand not supported

8 RO 0b ATOMIC64bCOMPSUP AtomicOp Completer 64-bit Operand not supported

7 RO 0b ATOMIC32bCOMPSUP AtomicOp Completer 32-bit Operand not supported

6RO0bATOMICROUTSUP AtomicOp Routing not supported

5RW-LB1bARI_Supported Alternative RID Interpretation Capable This bit is set to 1b indicating Root Port supports this capability.

4 RO 1b CMPLTODISSUP Completion Timeout Disable Supported IIO supports disabling completion timeout

Intel® Xeon Phi™ Processor 159 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: B4h Bus: RootBus Device: 1Function: 0-3 Offset: B4h Bus: RootBus Device: 2Function: 0-3 Offset: B4h

Bit Attr Default Description

3:0 RO Eh CMPLTOVALSUP Completion Timeout Values Supported This field indicates device support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout range. Bits are one-hot encoded and set according to the table below to show timeout value ranges supported. A device that supports the optional capability of Completion Timeout Programmability must set at least two bits.Four time values ranges are defined: Range A: 50us to 10ms Range B: 10ms to 250ms Range C: 250ms to 4s Range D: 4s to 64s Bits are set according to table below to show timeout value ranges supported. 0000b: Completions Timeout programming not supported -- values are fixed in the range 50us to 50ms. 0001b: Range A 0010b: Range B 0011b: Range A & B 0110b: Range B & C 0111b: Range A, B, & C 1110b: Range B, C D 1111b: Range A, B, C & D All other values are reserved. IIO supports timeout values up to 10ms-64s.

6.1.52 DEVCTRL2: PCI Express Device Control 2

Bus: RootBus Device: 0Function: 2-3 Offset: B8h Bus: RootBus Device: 1Function: 0-3 Offset: B8h Bus: RootBus Device: 2Function: 0-3 Offset: B8h

Bit Attr Default Description

15:6 RV 0 Reserved

5RW-L0bARI_EN Alternative RID Interpretation Enable Applies only to root ports. When set to 1b, ARI is enabled for the Root Port. Lock: !DEVCAP2.ARI_Supported

4RW0bComplTODis Completion Timeout Disable When set to 1b, this bit disables the Completion Timeout mechanism for all NP tx that IIO issues on the PCIE/DMI link. When 0b, completion timeout is enabled. Software can change this field while there is active traffic in the root/DMI port.

3:0 RW 0h ComplTOVal Completion Timeout Value on NP Tx that IIO issues on PCIe/DMI In Devices that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout range. The following encodings and corresponding timeout ranges are defined: 0000b = 10ms to 50ms 0001b = Reserved (IIO aliases to 0000b) 0010b = Reserved (IIO aliases to 0000b) 0101b = 16ms to 55ms 0110b = 65ms to 210ms 1001b = 260ms to 900ms 1010b = 1s to 3.5s 1101b = 4s to 13s 1110b = 17s to 64s When software selects 17s to 64s range, CTOCTRL further controls the timeout value within that range. For all other ranges selected by OS, the timeout value within that range is fixed in IIO hardware. Software can change this field while there is active traffic in the root port. This value will also be used to control PME_TO_ACK Timeout. That is this field sets the timeout value for receiving a PME_TO_ACK message after a PME_TURN_OFF message has been transmitted. The PME_TO_ACK Timeout has meaning only if bit 6 of MISCCTRLSTS register is set to a 1b.

160 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.53 LNKCAP2: PCI Express Link Capability 2

Bus: RootBus Device: 0Function: 2-3 Offset: BCh Bus: RootBus Device: 1Function: 0Offset: BCh Bus: RootBus Device: 1Function: 1-3 Offset: BCh Bus: RootBus Device: 2Function: 0-3 Offset: BCh

Bit Attr Default Description

31:8 RV 0 Reserved

7:1 RW-O 0000111b LNKSPDVEC Supported Link Speeds Vector This field indicates the supported Link speed(s) of the associated Port. For each bit, a value of 1b indicates that the corresponding Link speed is supported; otherwise, the Link speed is not supported. Bit definitions are: Bit 12.5 GT/s Bit 25.0 GT/sset if DMIGEN2EN strap is set Bit 38.0 GT/s(not supported in Port 0) Bits 7:4reserved IIO supports all speeds up to Gen3, except for Port 0.

0RV0 Reserved

6.1.54 LNKCON2: PCI Express Link Control Register 2

Bus: RootBus Device: 0Function: 2-3 Offset: C0h Bus: RootBus Device: 1Function: 0Offset: C0h Bus: RootBus Device: 1Function: 1-3 Offset: C0h Bus: RootBus Device: 2Function: 0-3 Offset: C0h

Bit Attr Default Description

15:12 RWS 0000b Compliance_De_emphasis For 8GT/s Data Rate: This bit sets the Transmitter Preset level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The Encodings are defined as follows: 0000b: -6 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot Others: reserved For 5GT/s Data Rate: This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. Encodings: 0001b: -3.5 dB 0000b: -6 dB For 2.5GT/s Data Rate: The setting of this field has no effect. Components that support only 2.5 GT/s speed are permitted to hardwire this field to 0h. Notes: This bit is intended for debug, compliance testing purposes. System firmware and software is allowed to modify this bit only during debug or compliance testing.

11 RWS 0b Compliance_SOS When set to 1b, the LTSSM is required to send SKP Ordered Sets periodically in between the (modified) compliance patterns.

10 RWS 0b Enter_Modified_Compliance When this bit is set to 1b, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.

9:7 RWS- 000b Transmit_Margin V This field controls the value of the nondeemphasized voltage level at the Transmitter pins.

6 RW-O 0b Selectable_De_emphasis When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis for an Upstream component.Encodings: 1b -3.5 dB 0b -6 dB When the Link is operating at 2.5 GT/s speed, the setting of this bit has no effect.

Intel® Xeon Phi™ Processor 161 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: C0h Bus: RootBus Device: 1Function: 0Offset: C0h Bus: RootBus Device: 1Function: 1-3 Offset: C0h Bus: RootBus Device: 2Function: 0-3 Offset: C0h

Bit Attr Default Description

5 RWS 0b Hardware_Autonomous_Speed_Disable When Set, this bit disables hardware from changing the Link speed for device specific reasons other than attempting to correct unreliable Link operation by reducing Link speed.

4RWS-0b Enter_Compliance V Software is permitted to force a link to enter Compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link.

3:0 RWS- 3h Target_Link_Speed V This field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences. Defined encodings are: 0001b: 2.5Gb/s Target Link Speed 0010b: 5Gb/s Target Link Speed 0011b: 8Gb/s Target Link Speed Others: 2.5Gb/s Target Link Speed All other encodings are reserved. If a value is written to this field that does not correspond to a speed included in the Supported Link Speeds field, IIO will default to Gen1 speed. This field is also used to set the target compliance mode speed when software is using the Enter Compliance bit to force a link into compliance mode. For PCI Express ports (Dev#1-2), this field defaults to 0010b if Gen3_OFF fuse is ON. And when Gen3_OFF fuse is OFF this field defaults to 0011b. For Dev#0, this field defaults to 0010b.

6.1.55 LNKSTS2: PCI Express Link Status Register 2

Bus: RootBus Device: 0Function: 2-3 Offset: C2h Bus: RootBus Device: 1Function: 0Offset: C2h Bus: RootBus Device: 1Function: 1-3 Offset: C2h Bus: RootBus Device: 2Function: 0-3 Offset: C2h

Bit Attr Default Description

15:6 RV 0 Reserved

5RW1CS0bLNKEQREQ Link Equalization Request This bit is Set by hardware to request Link equalization process to be performed on the link.

4 RO-V 0b EQPH3_SUCC Equalization Phase3 Successful When set to 1b, this indicates that Phase 3 of the Transmitter Equalization procedure has successfully completed.

3 RO-V 0b EQPH2_SUCC Equalization Phase2 Successful When set to 1b, this indicates that Phase 2 of the Transmitter Equalization procedure has successfully completed.

2 RO-V 0b EQPH1_SUCC Equalization Phase1 Successful When set to 1b, this indicates that Phase 1 of the Transmitter Equalization procedure has successfully completed.

1 RO-V 0b EQCMP Equalization Complete When set to 1b, this indicates that the Transmitter Equalization procedure has completed.

0 RO-V 0b Current_De_emphasis_Level When operating at Gen2 speed, this reports the current de-emphasis level. This field is Unused for Gen1 speeds1b -3.5 dB 0b -6 dB

162 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.56 PMCAP: Power Management Capability

Bus: RootBusDevice: 0Function: 2-3Offset: E0h Bus: RootBusDevice: 1Function: 0Offset: E0hMode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: E0h Bus: RootBusDevice: 2Function: 0-3Offset: E0h

Bit Attr Default Description

31:27 RO 19h PME_Support In PCIe Mode, Bits 31, 30 and 27 must be set to 1 for PCI- PCI bridge structures representing ports on root complexes.

26 RO 0b D2_Support IIO does not support power management state D2.

25 RO 0b D1_Support IIO does not support power management state D1.

24:22 RO 0h AUX_Current

21 RO 0b Device_Specific_Initialization

20 RV 0 Reserved

19 RO 00h PME_Clock This field is hardwired to 0h as it does not apply to PCI Express.

18:16 RO 3h Version This field is set to 3h (PM 1.2 compliant) as version number for all PCI Express ports.

15:8 RO 00h Next_Capability_Pointer This is the last capability in the chain and hence set to 0.

7:0 RO 01h Capability_ID Provides the PM capability ID assigned by PCI-SIG.

6.1.57 PMCSR: Power Management Control and Status Register

Bus: RootBusDevice: 0Function: 2-3Offset: E4h Bus: RootBusDevice: 1Function: 0Offset: E4hMode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: E4h Bus: RootBusDevice: 2Function: 0-3Offset: E4h

Bit Attr Default Description

31:24 RO 00h Data Not relevant for IIO

23 RO 0b Bus_Power_Clock_Control_Enable This field is hardwired to 0h as it does not apply to PCI Express.

22 RO 0b B2_B3_Support This field is hardwired to 0h as it does not apply to PCI Express.

21:16 RV 0 Reserved

15 RW1CS 0b PME_Status Applies only to root ports. This PME Status is a sticky bit. This bit is set, independent of the PME Enable bit defined below, on an enabled PCI Express hotplug event. Software clears this bit by writing a '1' when it has been completed. Refer to PCI Express Base Specification, Revision 2.0 for further details on wake event generation at a root port.No PME event supported in DMI mode, so this bit will not be set.

14:13 RO 00h Data_Scale Not relevant for IIO

12:9 RO 00h Data_Select Not relevant for IIO

Intel® Xeon Phi™ Processor 163 Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 0Function: 2-3Offset: E4h Bus: RootBusDevice: 1Function: 0Offset: E4hMode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: E4h Bus: RootBusDevice: 2Function: 0-3Offset: E4h

Bit Attr Default Description

8RWS0bPME_Enable Applies only to root ports. This field is a sticky bit and when set, enables a virtual PM_PME message to be generated internally on an enabled PCI Express hotplug event. This virtual PM_PME message then sets the appropriate bits in the ROOTSTS register (which can then trigger an MSI/INT or cause a _PMEGPE event).

7:4 RV 0 Reserved

3 RW-O 1b No_Soft_Reset Indicates IIO does not reset its registers when transitioning from D3hot to D0.

2RV0 Reserved

1:0 RW 0h Power_State This 2-bit field is used to determine the current power state of the function and to set a new power state as well. 00: D0 01: D1 (not supported by IIO) 10: D2 (not supported by IIO) 11: D3_hot If Software tries to write 01 or 10 to this field, the power state does not change from the existing power state (which is either D0 or D3hot) and nor do these bits 1:0 change value. All devices will respond to only Type 0 configuration transactions (targeting the device's configuration space itself) when in D3hot state (root port will not forward Type 1/0 transactions to the downstream link) and will not respond to memory/IO transactions (that is, D3hot state is equivalent to MSE/IOSE bits being clear) as target and will not generate any memory/IO/ configuration transactions as initiator on the primary bus (messages are still allowed to pass through).

6.1.58 XPREUT_HDR_EXT: REUT PCIe Header Extended

Bus: RootBusDevice: 0Function: 2-3Offset: 100h Bus: RootBusDevice: 1Function: 0Offset: 100hMode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: 100h Bus: RootBusDevice: 2Function: 0-3Offset: 100h

Bit Attr Default Description

31:20 RO 110h PcieNextPtr Next Capability Pointer This field contains the offset to the next PCI capability structure or 00h if no other items exist in the linked list of capabilities. In PCIe Mode, it points to the ACS Capability with a value of 110h.

19:16 RO 1h PcieCapVersion Capability Version This field is a PCI-SIG defined version number that indicates the nature and format of the extended capability. This indicates the version of the REUT Capability.

15:0 RO Bh PcieCapID PCIe Extended CapID This field has the value 0Bh to identify the CAP_ID assigned by the PCI SIG indicating a vendor specific capability.

164 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.59 XPREUT_HDR_CAP: REUT Header Capability

Bus: RootBus Device: 0Function: 2-3 Offset: 104h Bus: RootBus Device: 1Function: 0-3 Offset: 104h Bus: RootBus Device: 2Function: 0-3 Offset: 104h

Bit Attr Default Description

31:20 RO Ch VSECLength This field defines the length of the REUT 'capability body'. The size of the leaf body is 12 bytes including the _EXT, _CAP and _LEF registers.

19:16 RO 0h VSECIDRev This field is defined as the version number that indicates the nature and format of the VSEC structure. Software must quality the Vendor ID before interpreting this field.

15:0 RO 0002h VSECID This field is a Intel-defined ID number that indicates the nature and format of the VSEC structure. Software must qualify the Vendor ID before interpreting this field. Notes: A value of '00h' is reserved A value of '01h' is the ID Council defined for REUT engines. A value of '02h' is specified for the REUT 'leaf' capability structure which resides in each link which in supported by a REUT engine.

6.1.60 XPREUT_HDR_LEF: REUT Header Leaf Capability

Bus: RootBus Device: 0Function: 2-3 Offset: 108h Bus: RootBus Device: 1Function: 0-3 Offset: 108h Bus: RootBus Device: 2Function: 0-3 Offset: 108h

Bit Attr Default Description

31:16 RV 0 Reserved

15:8 RO 31h 32h LeafReutDevNum 38h 39h This field identifies the PCI Device/Function # where the REUT engine associated with this link 3Ah 3Bh resides. 33h 34h Device6 = 00110b & function0 = 000b = 30h (DMI) Device6 = 00110b & function1 = 001b = 31h 35h 36h Device6 = 00110b & function2 = 010b = 32h Device6 = 00110b & function3 = 011b = 33h Device6 = 00110b & function4 = 100b = 34h Device6 = 00110b & function5 = 101b = 35h Device6 = 00110b & function6 = 110b = 36h Device7 = 00111b & function0 = 000b = 38h Device7 = 00111b & function1 = 001b = 39h Device7 = 00111b & function2 = 010b = 3Ah Device7 = 00111b & function3 = 011b = 3Bh

7:0 RO 03h 03h LeafReutEngID 06h 06h This field identifies the REUT engine associated with the link (same as the REUT ID). 06h 06h 05h 05h 05h 05h

6.1.61 ACSCAPHDR: Access Control Services Extended Capability Header

Bus: RootBusDevice: 0Function: 2-3Offset: 110h Bus: RootBusDevice: 1Function: 0Offset: 110hMode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: 110h Bus: RootBusDevice: 2Function: 0-3Offset: 110h

Bit Attr Default Description

31:20 RO 148h Next_Capability_Offset This field points to the next Capability in extended configuration space.

Intel® Xeon Phi™ Processor 165 Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 0Function: 2-3Offset: 110h Bus: RootBusDevice: 1Function: 0Offset: 110hMode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: 110h Bus: RootBusDevice: 2Function: 0-3Offset: 110h

Bit Attr Default Description

19:16 RO 1h Capability_Version Set to 1h for this version of the PCI Express logic

15:0 RO 000Dh PCI_Express_Extended_CAP_ID Assigned for Access Control Services capability by PCISIG.

6.1.62 ACSCAP: Access Control Services Capability Register

Bus: RootBusDevice: 0Function: 2-3Offset: 114h Bus: RootBusDevice: 1Function: 0Offset: 114hMode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: 114h Bus: RootBusDevice: 2Function: 0-3Offset: 114h

Bit Attr Default Description

15:8 RO 00h Egress_Control_Vector_Size N/A for IIO

7RV0 Reserved

6RO0bT ACS Direct Translated P2P Indicates that the component does not implement ACS Direct Translated P2P.

5RO0bE ACS P2P Egress Control Indicates that the component does not implement ACS P2P Egress Control.

4RO1bU ACS Upstream Forwarding Indicates that the component implements ACS Upstream Forwarding.

3RO1bC ACS P2P Completion Redirect Indicates that the component implements ACS P2P Completion Redirect.

2RO1bR ACS P2P Request Redirect Indicates that the component implements ACS P2P Request Redirect.

1RO1bB ACS Translation Blocking Indicates that the component implements ACS Translation Blocking.

0RO1bV ACS Source Validation Indicates that the component implements ACS Source Validation.

6.1.63 ACSCTRL: Access Control Services Control Register

Bus: RootBus Device: 0Function: 2-3 Offset: 116h Bus: RootBus Device: 1Function: 0Offset: 116h Bus: RootBus Device: 1Function: 1-3 Offset: 116h Bus: RootBus Device: 2Function: 0-3 Offset: 116h

Bit Attr Default Description

15:7 RV 0 Reserved

6RO0bT ACS Direct Translated P2P Enable This is hardwired to 0b as the component does not implement ACS Direct Translated P2P.

166 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 116h Bus: RootBus Device: 1Function: 0Offset: 116h Bus: RootBus Device: 1Function: 1-3 Offset: 116h Bus: RootBus Device: 2Function: 0-3 Offset: 116h

Bit Attr Default Description

5RO0bE ACS P2P Egress Control Enable The component does not implement ACS P2P Egress Control and hence this bit should not be used by SW.

4RW0bU ACS Upstream Forwarding Enable When this bit is set, transactions arriving from a root port that target the same port back down, will be forwarded. Normally such traffic would be aborted.

3RW0bC ACS P2P Completion Redirect Enable Determines when the component redirects peer-to-peer Completions upstream; applicable only to Read Completions who’s Relaxed Ordering Attribute is clear.

2RW0bR ACS P2P Request Redirect Enable When this bit is set, transactions arriving from a root port that target the same port back down, will be forwarded. Normally such traffic would be aborted.

1RW0bB ACS Translation Blocking Enable When set, the component blocks all upstream Memory Requests whose Address Translation (AT) field is not set to the default value.

0RW0bV ACS Source Validation Enable When set, the component validates the Bus Number from the Requester ID of upstream Requests against the secondary / subordinate Bus Numbers.

6.1.64 APICBASE: APIC Base Register

Bus: RootBus Device: 0Function: 2-3 Offset: 140h Bus: RootBus Device: 1Function: 0Offset: 140h Bus: RootBus Device: 1Function: 1-3 Offset: 140h Bus: RootBus Device: 2Function: 0-3 Offset: 140h

Bit Attr Default Description

15:12 RV 0 Reserved

11:1 RW 000h ADDR Bits 19:9 of the APIC base Applies only to root ports. Bits 31:20 are assumed to be 0xFECh. Bits 8:0 are a don't care for address decode. Address decoding to the APIC range is done as APICBASE.ADDR[31:8] <= A[31:8] <= APICLIMIT.ADDR[31:8]. Outbound accesses to the APIC range are claimed by the root port and forwarded to PCIe, if bit 0 is set, even if the MSE bit of the root port is clear or the root port itself is in D3hot state.

0RW0hEN APIC range enable Enables the decode of the APIC window.

Intel® Xeon Phi™ Processor 167 Datasheet - Volume 2, December 2016 6.1.65 APICLIMIT: APIC Limit Register

Bus: RootBus Device: 0Function: 2-3 Offset: 142h Bus: RootBus Device: 1Function: 0Offset: 142h Bus: RootBus Device: 1Function: 1-3 Offset: 142h Bus: RootBus Device: 2Function: 0-3 Offset: 142h

Bit Attr Default Description

15:12 RV 0 Reserved

11:1 RW 000h ADDR Applies only to root ports. Bits 31:20 are assumed to be 0xFECh. Bits 8:0 are a don't care for address decode. Address decoding to the APIC range is done as APICBASE.ADDR[31:8] <= A[31:8] <= APICLIMIT.ADDR[31:8]. Outbound accesses to the APIC range are claimed by the root port and forwarded to PCIe, if the range is enabled, even if the MSE bit of the root port is clear or the root port itself is in D3hot state.

0RV0 Reserved

6.1.66 ERRCAPHDR: PCI Express Enhanced Capability Header

Bus: RootBus Device: 0Function: 2-3 Offset: 148h Bus: RootBus Device: 1Function: 0Offset: 148h Bus: RootBus Device: 1Function: 1-3 Offset: 148h Bus: RootBus Device: 2Function: 0-3 Offset: 148h

Bit Attr Default Description

31:20 RO 1DOh Next_Capability_Offset This field points to the next Capability in extended configuration space or is 0 if it is that last capability.

19:16 RO 1h Capability_Version Set to 1h for this version of the PCI Express logic

15:0 RO 0001h PCI_Express_Extended_CAP_ID Assigned for advanced error reporting

6.1.67 UNCERRSTS: Uncorrectable Error Status

Bus: RootBus Device: 0Function: 2-3 Offset: 14Ch Bus: RootBus Device: 1Function: 0-3 Offset: 14Ch Bus: RootBus Device: 2Function: 0-3 Offset: 14Ch

Bit Attr Default Description

31:22 RV 0 Reserved

21 RW1CS 0b ACS_Violation_Status

20 RW1CS 0b Received_an_Unsupported_Request

19 RW1CS 0b ECRC_Error_Status

18 RW1CS 0b Malformed_TLP_Status

17 RW1CS 0b Receiver_Buffer_Overflow_Status

16 RW1CS 0b Unexpected_Completion_Status

15 RW1CS 0b Completer_Abort_Status

14 RW1CS 0b Completion_Time_out_Status

13 RW1CS 0b Flow_Control_Protocol_Error_Status

12 RW1CS 0b Poisoned_TLP_Status

11:6 RV 0 Reserved

168 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 14Ch Bus: RootBus Device: 1Function: 0-3 Offset: 14Ch Bus: RootBus Device: 2Function: 0-3 Offset: 14Ch

Bit Attr Default Description

5 RW1CS 0b Surprise_Down_Error_Status

4 RW1CS 0b Data_Link_Protocol_Error_Status

3:0 RV 0 Reserved

6.1.68 UNCERRMSK: Uncorrectable Error Mask

Bus: RootBus Device: 0Function: 2-3 Offset: 150h Bus: RootBus Device: 1Function: 0-3 Offset: 150h Bus: RootBus Device: 2Function: 0-3 Offset: 150h

Bit Attr Default Description

31:2 RV 0 Reserved 2

21 RWS 0b ACS_Violation_Mask

20 RWS 0b Unsupported_Request_Error_Mask

19 RWS 0b ECRC_Error_Mask

18 RWS 0b Malformed_TLP_Mask

17 RWS 0b Receiver_Buffer_Overflow_Mask

16 RWS 0b Unexpected_Completion_Mask

15 RWS 0b Completer_Abort_Mask

14 RWS 0b Completion_Time_out_Mask

13 RWS 0b Flow_Control_Protocol_Error_Mask

12 RWS 0b Poisoned_TLP_Mask

11:6 RV 0 Reserved

5 RWS 0b Surprise_Down_Error_Mask

4 RWS 0b Data_Link_Protocol_Error_Mask

3:0 RV 0 Reserved

6.1.69 UNCERRSEV: Uncorrectable Error Severity

Bus: RootBus Device: 0Function: 2-3 Offset: 154h Bus: RootBus Device: 1Function: 0-3 Offset: 154h Bus: RootBus Device: 2Function: 0-3 Offset: 154h

Bit Attr Default Description

31:22 RV 0 Reserved

21 RWS 0b ACS_Violation_Severity

20 RWS 0b Unsupported_Request_Error_Severity

19 RWS 0b ECRC_Error_Severity

18 RWS 1b Malformed_TLP_Severity

17 RWS 1b Receiver_Buffer_Overflow_Severity

16 RWS 0b Unexpected_Completion_Severity

15 RWS 0b Completer_Abort_Severity

14 RWS 0b Completion_Time_out_Severity

Intel® Xeon Phi™ Processor 169 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 154h Bus: RootBus Device: 1Function: 0-3 Offset: 154h Bus: RootBus Device: 2Function: 0-3 Offset: 154h

Bit Attr Default Description

13 RWS 1b Flow_Control_Protocol_Error_Severity

12 RWS 0b Poisoned_TLP_Severity

11:6 RV 0 Reserved

5 RWS 1b Surprise_Down_Error_Severity

4 RWS 1b Data_Link_Protocol_Error_Severity

3:0 RV 0 Reserved

6.1.70 CORERRSTS: Correctable Error Status

Bus: RootBus Device: 0Function: 2-3 Offset: 158h Bus: RootBus Device: 1Function: 0-3 Offset: 158h Bus: RootBus Device: 2Function: 0-3 Offset: 158h

Bit Attr Default Description

31:14 RV 0 Reserved

13 RW1CS 0b Advisory_Non_fatal_Error_Status

12 RW1CS 0b Replay_Timer_Time_out_Status

11:9 RV 0 Reserved

8 RW1CS 0b Replay_Num_Rollover_Status

7 RW1CS 0b Bad_DLLP_Status

6RW1CS0bBad_TLP_Status

5:1 RV 0 Reserved

0 RW1CS 0b Receiver_Error_Status

6.1.71 CORERRMSK: Correctable Error Mask

Bus: RootBus Device: 0Function: 2-3 Offset: 15Ch Bus: RootBus Device: 1Function: 0-3 Offset: 15Ch Bus: RootBus Device: 2Function: 0-3 Offset: 15Ch

Bit Attr Default Description

31: RV 0 Reserved 14

13 RWS 1b Advisory_Non_fatal_Error_Mask

12 RWS 0b Replay_Timer_Time_out_Mask

11: RV 0 Reserved 9

8 RWS 0b Replay_Num_Rollover_Mask

7 RWS 0b Bad_DLLP_Mask

6RWS 0bBad_TLP_Mask

5:1 RV 0 Reserved

0 RWS 0b Receiver_Error_Mask

170 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.72 ERRCAP: Advanced Error Capabilities and Control Register

Bus: RootBus Device: 0Function: 2-3 Offset: 160h Bus: RootBus Device: 1Function: 0-3 Offset: 160h Bus: RootBus Device: 2Function: 0-3 Offset: 160h

Bit Attr Default Description

31:9 RV 0 Reserved

8 RWS 0b ECRC_Check_Enable 0: ECRC checking is disabled 1: ECRC checking is enabled

7 RW-O 0b ECRC_Check_Capable BIOS must set this bit to allow software to recognize that this Root Port supports checking of ECRC on received packets.

6RWS0b ECRC_Generation_Enable 0: ECRC generation is disabled 1: ECRC generation is enabled

5 RW-O 0b ECRC_Generation_Capable BIOS must set this bit to allow software to recognize that this Root Port supports generation of ECRC on transmitted packets.

4:0 ROS-V 00h First_error_pointer The First Error Pointer is a read-only register that identifies the bit position of the first unmasked error reported in the Uncorrectable Error register. In case of two errors happening at the same time, fatal error gets precedence over non-fatal, in terms of being reported as first error. This field is rearmed to capture new errors when the status bit indicated by this field is cleared by software.

6.1.73 HDRLOG0: Header Log 0

Bus: RootBus Device: 0Function: 2-3 Offset: 164h Bus: RootBus Device: 1Function: 0-3 Offset: 164h Bus: RootBus Device: 2Function: 0-3 Offset: 164h

Bit Attr Default Description

31:0 ROS-V 00000000h HDR Log of Header Dword 0: Logs the first DWORD of the header on an error condition

6.1.74 HDRLOG1: Header Log 1

Bus: RootBus Device: 0Function: 2-3 Offset: 168h Bus: RootBus Device: 1Function: 0-3 Offset: 168h Bus: RootBus Device: 2Function: 0-3 Offset: 168h

Bit Attr Default Description

31:0 ROS-V 00000000h HDR Log of Header Dword 1: Logs the second DWORD of the header on an error condition

6.1.75 HDRLOG2: Header Log 2

Bus: RootBus Device: 0Function: 2-3 Offset: 16Ch Bus: RootBus Device: 1Function: 0-3 Offset: 16Ch Bus: RootBus Device: 2Function: 0-3 Offset: 16Ch

Bit Attr Default Description

31:0 ROS-V 00000000h HDR Log of Header Dword 2: Logs the third DWORD of the header on an error condition

Intel® Xeon Phi™ Processor 171 Datasheet - Volume 2, December 2016 6.1.76 HDRLOG3: Header Log 3

Bus: RootBus Device: 0Function: 2-3 Offset: 170h Bus: RootBus Device: 1Function: 0-3 Offset: 170h Bus: RootBus Device: 2Function: 0-3 Offset: 170h

Bit Attr Default Description

31:0 ROS-V 00000000h HDR Log of Header Dword 3: Logs the fourth DWORD of the header on an error condition

6.1.77 RPERRCMD: Root Port Error Command

Bus: RootBus Device: 0Function: 2-3 Offset: 174h Bus: RootBus Device: 1Function: 0-3 Offset: 174h Bus: RootBus Device: 2Function: 0-3 Offset: 174h

Bit Attr Default Description

31:3 RV 0 Reserved

2 RW 0b FATAL_Error_Reporting_Enable Applies to root ports onlyEnable MSI/INTx interrupt on fatal errors when set. Refer to Chapter 10, 'PCI Express Error Reporting Specifics,' for details of MSI/INTx generation for PCI Express error events.

1 RW 0b Non_FATAL_Error_Reporting_Enable Applies to root ports onlyEnable interrupt on a non-fatal error when set. Refer to Chapter 10, 'PCI Express Error Reporting Specifics,' for details of MSI/INTx generation for PCI Express error events.

0 RW 0b Correctable_Error_Reporting_Enable Applies to root ports onlyEnable interrupt on correctable errors when set. Refer to Chapter 10, 'PCI Express Error Reporting Specifics,' for details of MSI/INTx generation for PCI Express error events.

6.1.78 RPERRSTS: Root Port Error Status

The Root Error Status register reports status of error Messages (ERR_COR), ERR_NONFATAL, and ERR_FATAL) received by the Root Complex in IIO, and errors detected by the Root Port itself (which are treated conceptually as if the Root Port had sent an error Message to itself).

The ERR_NONFATAL and ERR_FATAL Messages are grouped together as uncorrectable. Each correctable and uncorrectable (Non-fatal and Fatal) error source has a first error bit and a next error bit associated with it respectively. When an error is received by a Root Complex, the respective first error bit is set and the Requestor ID is logged in the Error Source Identification register.

A set individual error status bit indicates that a particular error category occurred; software may clear an error status by writing a 1 to the respective bit. If software does not clear the first reported error before another error Message is received of the same category (correctable or uncorrectable), the corresponding next error status bit will be set but the Requestor ID of the subsequent error Message is discarded. The next error status bits may be cleared by software by writing a 1 to the respective bit as well.

172 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 178h Bus: RootBus Device: 1Function: 0-3 Offset: 178h Bus: RootBus Device: 2Function: 0-3 Offset: 178h

Bit Attr Default Description

31:27 RO 0b Advanced_Error_Interrupt_Message_Number Advanced Error Interrupt Message Number offset between base message data and the MSI message if assigned more than one message number.

26:7 RV 0 Reserved

6 RW1CS 0b Fatal_Error_Messages_Received Set when one or more Fatal Uncorrectable error Messages have been received.

5 RW1CS 0b Non_Fatal_Error_Messages_Received Set when one or more Non-Fatal Uncorrectable error Messages have been received.

4 RW1CS 0b First_Uncorrectable_Fatal Set when bit 2 is set (from being clear) and the message causing bit 2 to be set is an ERR_FATAL message.

3 RW1CS 0b Multiple_Error_Fatal_Nonfatal_Received Set when either a fatal or a non-fatal error message is received and Error Fatal/Nonfatal Received is already set, that is, log from the 2nd Fatal or No fatal error message onwards.

2 RW1CS 0b Error_Fatal_Nonfatal_Received Set when either a fatal or a non-fatal error message is received and this bit is already not set. that is, log the first error message. Note that when this bit is set bit 3 could be either set or clear.

1 RW1CS 0b Multiple_Correctable_Error_Received Set when either a correctable error message is received or Correctable Error Received bit is already set, i.e log from the 2nd Correctable error message onwards.

0 RW1CS 0b Correctable_Error_Received Set when a correctable error message is received and this bit is already not set. That is, log the first error message.

6.1.79 ERRSID: Error Source Identification

Bus: RootBus Device: 0Function: 2-3 Offset: 17Ch Bus: RootBus Device: 1Function: 0-3 Offset: 17Ch Bus: RootBus Device: 2Function: 0-3 Offset: 17Ch

Bit Attr Default Description

31:16 ROS-V 0000h Fatal_Non_Fatal_Error_Source_ID Requestor ID of the source when an Fatal or Non Fatal error message is received and the Error Fatal/ Nonfatal Received bit is not already set. i.e log ID of the first Fatal or Non Fatal error message. Note that when the root port itself is the cause of the received message (virtual message), then a Source ID of CPUBUSNO0:DevNo:0 is logged into this register.

15:0 ROS-V 0000h Correctable_Error_Source_ID Requestor ID of the source when a correctable error message is received and the Correctable Error Received bit is not already set. i.e log ID of the first correctable error message. Note that when the root port itself is the cause of the received message (virtual message), then a Source ID of CPUBUSNO0:DevNo:0 is logged into this register.

6.1.80 PERFCTRLSTS_0: Performance Control and Status

Bus: RootBus Device: 0Function: 2-3 Offset: 180h Bus: RootBus Device: 1Function: 0-3 Offset: 180h Bus: RootBus Device: 2Function: 0-3 Offset: 180h

Bit Attr Default Description

31:21 RV 0 Reserved

Intel® Xeon Phi™ Processor 173 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 180h Bus: RootBus Device: 1Function: 0-3 Offset: 180h Bus: RootBus Device: 2Function: 0-3 Offset: 180h

Bit Attr Default Description

20:16 RW 18h outstanding_requests_gen1 Number of outstanding RFOs and non-posted requests from a given PCIe port. This register controls the number of outstanding inbound non-posted requests - I/O, Config, Memory - (maximum length of these requests is a single 64B cacheline) that a Gen1 PCI Express downstream port can have. This register provides the value for the port when it is operating in Gen1 mode and for a link width of x4. BIOS programs this register based on the read latency to main memory. This register also specifies the number of RFOs that can be kept outstanding on IDI for a given port. The link speed of the port can change during a PCI Express hotplug event and the port must use the appropriate multiplier. A value of 1 indicates one outstanding pre-allocated request, 2 indicates two outstanding pre- allocated requests, and so on. If software programs a value greater than the buffer size the HW supports, then the maximum hardware supported value is used. Current BIOS recommendation is to leave this field at its default value.

15:14 RV 0 Reserved

13:8 RW 30h outstanding_requests_gen2 Number of outstanding RFOs and non-posted requests from a given PCIe port. This register controls the number of outstanding inbound non-posted requests - I/O, Config, Memory - (maximum length of these requests is a single 64B cacheline) that a Gen2 PCI Express downstream port can have. This register provides the value for the port when it is operating in Gen2 mode and for a link width of x4. BIOS programs this register based on the read latency to main memory. This register also specifies the number of RFOs that can be kept outstanding on IDI for a given port. The link speed of the port can change during a PCI Express hotplug event and the port must use the appropriate multiplier. A value of 1 indicates one outstanding pre-allocated request, 2 indicates two outstanding pre- allocated requests, and so on. If software programs a value greater than the buffer size the HW supports, then the maximum hardware supported value is used. Current BIOS recommendation is to leave this field at it's default value.

7 RW 0b ForceNoSnoopWrEn Force No-Snoop on VC0 writes received on this port 1: All writes received on this port are treated as though the NS bit is set and will use the Non- Snoop non-allocating flow. 0: Writes will be treated as non-snoop only if the NS bit is set and the NoSnoopWrEn bit is set. Notes: VC1/VCm traffic is not impacted by this bit since all writes from VC1 and VCm are always Non- Snoop This bit has precedence over the NoSnoopWrEn field in this register Forcing writes to be non-snoop with this bit takes precendence over TPH

6:5 RV 0b Reserved

4 RW 1b read_stream_interleave_size

3 RW 0b NoSnoopWrEn Enable No-Snoop on VC0 writes received on this port This applies to writes with the following conditions: NS=1 AND (TPH=0 OR TPHDIS=1) 1: Inbound writes to memory with above conditions will be treated as non-coherent (no snoops) writes - IIO will use the non-allocating NS flow 0: Inbound writes to memory with above conditions will be treated as allocating writes. Notes: If TPH=1 and TPHDIS=0 then NS is ignored and this bit is ignored VC1/VCm writes are not controlled by this bit since they are always non-snoop and can be no other way. TPH and ForceNoSnoopWrEn have higher precedence than this bit

2 RO 0b NoSnoopOpRdEn Enable No-Snoop on VC0 reads and VCp reads Not used by IIO

1 RW 0b read_passing_read_disable Disable reads bypassing other reads

174 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 180h Bus: RootBus Device: 1Function: 0-3 Offset: 180h Bus: RootBus Device: 2Function: 0-3 Offset: 180h

Bit Attr Default Description

0RW1bread_stream_policy

6.1.81 PERFCTRLSTS_1: Performance Control and Status

Bus: RootBus Device: 0Function: 2-3 Offset: 184h Bus: RootBus Device: 1Function: 0-3 Offset: 184h Bus: RootBus Device: 2Function: 0-3 Offset: 184h

Bit Attr Default Description

31:10 RV 0 Reserved

9RW0bTPHDIS TLP Processing Hint Disable When set, writes or reads with TPH=1, will be treated as if TPH=0. Refer to the Transaction Flow chapter for details about the flows for the different cases of TPH.

8 RW 0b DCA_ReqID_Override When this bit is set, Requester ID match for DCA writes is bypassed. All writes from the port are treated as DCA writes and the tag field will convey if DCA is enabled or not and the target information.

7:4 RV 0 Reserved

3 RW 0b max_read_completion_combine_size Selects the maximum completion combining size. 1: Completions are combined up to 256B 0: Completions are combined up to 128B This bit is no longer used in the RTL. Completions are always combined up to the maximum allowed by the Max Payload Size field in the Device Control register.

2:0 RV 0 Reserved

6.1.82 MISCCTRLSTS_0: Miscellaneous Control and Status

Bus: RootBus Device: 0Function: 2-3 Offset: 188h Bus: RootBus Device: 1Function: 0-3 Offset: 188h Bus: RootBus Device: 2Function: 0-3 Offset: 188h

Bit Attr Default Description

31 RW 0b Disable_L0s_on_transmitter When set, IIO never puts its tx in L0s state, even if OS enables it via the Link Control register.

30 RW-O 0b inbound_io_disable Disable Inbound IO Requests

29 RW 0b cfg_to_en Disables/enables config timeouts, independently of other timeouts. If completion timeouts are enabled when this bit is set, configuration requests will not timeout.

28 RW 0b to_dis Disables timeouts completely.

27 RWS 0b System_Interrupt_Only_on_Link_BW_Management_Status This bit, when set, will disable generating MSI and Intx interrupts on link bandwidth (speed and/or width) and management changes, even if MSI or INTx is enabled that is, will disable generating MSI or INTx when LNKSTS bits 15 and 14 are set. Whether or not this condition results in a system event like SMI/PMI/CPEI is dependent on whether this event masked or not in the XPCORERRMSK register.

26 RW 0b EOIFD EOI Forwarding Disable - Disable EOI broadcast to this PCIe link When set, EOI message will not be broadcast down this PCIe link. When clear, the port is a valid target for EOI broadcast.

Intel® Xeon Phi™ Processor 175 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 188h Bus: RootBus Device: 1Function: 0-3 Offset: 188h Bus: RootBus Device: 2Function: 0-3 Offset: 188h

Bit Attr Default Description

25 RO 0b Peer2peer_Memory_Write_Disable When set, peer2peer memory writes are master aborted otherwise they are allowed to progress per the peer2peer decoding rules. This has not be implemented and so is read-only.

24 RW 0b Peer2peer_Memory_Read_Disable When set, peer2peer memory reads are master aborted otherwise they are allowed to progress per the peer2peer decoding rules.

23 RW 0b Phold_Disable Applies only to Dev#0 When set, the IIO responds with Unsupported request on receiving assert_phold message from ICH and results in generating a fatal error.

22 RWS 0b check_cpl_tc

21 RW-O 0b zero_ob_tc Force Outbound TC to Zero Forces the TC field to zero for outbound requests. 1: TC is forced to zero on all outbound transactions regardless of the source TC value 0: TC is not altered In DMI mode, TC is always forced to zero and this bit has no effect.

20 RW 1b maltlp_32baddr64bhdr_en Malformed TLP 32b address in 64b header Enable When set, enables reporting a Malformed packet when the TLP is a 32 bit address in a 4DW header. PCI Express forbids using 4DW header sizes when the address is less than 4GB, but some cards may use the 4DW header anyway. In these cases, the upper 32 bits of address are all 0.

19 RV 0 Reserved

18 RWS 0b Max_Read_Completion_Combine_Size Disable Read Completion Combining When set, all completions are returned without combining. Completions are naturally broken on cacheline boundaries, so all completions will be 64B or less.

17 RO 0b force_data_perr Force Data Parity Error

16 RO 0b force_ep_biterr Force EP Bit Error (Poison Bit)

15 RWS 0b dis_hdr_storage

14 RWS 0b allow_one_np_os Force serialiazation of Non-Posted Requests

13 RWS 0b tlp_on_any_lane

12 RWS 1b disable_ob_parity_check

11:10 RV 0 Reserved

9 RWS 0b dispdspolling Disables gen2 if timeout happens in polling.cfg.

8:7 RW 00b PME2ACKTOCTRL

6 RW 0b Enable_timeout_for_receiving_PME_TO_ACK Enable timeout for receiving PME_TO_ACK When set, IIO enables the timeout to receiving the PME_TO_ACK

5 RW-V 0b Send_PME_TURN_OFF_message When this bit is written with a 1b, IIO sends a PME_TURN_OFF message to the PCIE link. Hardware clears this bit when the message has been sent on the link.

176 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 188h Bus: RootBus Device: 1Function: 0-3 Offset: 188h Bus: RootBus Device: 2Function: 0-3 Offset: 188h

Bit Attr Default Description

4 RW 0b Enable_System_Error_only_for_AER Applies only to Root ports. For Dev#0 in DMI mode, this bit is to be left at default value always.When this bit is set, the PCI Express errors do not trigger an MSI or Intx interrupt, regardless of the whether MSI or INTx is enabled or not. Whether or not PCI Express errors result in a system event like NMI/SMI/PMI/CPEI is dependent on whether the appropriate system error or override system error enable bits are set or not. See section titled PCI Express Error Reporting Specifics in the RAS chapter for details of how this bit interacts with other control bits in signalling errors to the IIO global error reporting logic. When this bit is clear, PCI Express errors are reported via MSI or INTx and/or NMI/SMI/MCA/CPEI. When this bit is clear and if MSI enable bit in the Section 2.1.5.8, 'MSI Control Register (MSICTRL)' on page 55 is set (clear), then an MSI (INTx) interrupt is generated for PCI Express errors. When this bit is clear, and 'System Error on Fatal Error Enable' bit in ROOTCON register is set, then NMI/SMI/MCA is (also) generated for a PCI Express fatal error. Similar behavior for non-fatal and corrected errors. Refer to Figure 10-10, 'MSI generation for PCI Express Errors' on page 331 for details of MSI generation logic for PCI Express errors.

3RW0bEnable_ACPI_mode_for_Hotplug Applies only to root ports. For Dev#0 in DMI mode, this bit is to be left at default value always.When this bit is set, all HP events from the PCI Express port are handled via _HPGPE messages to the ICH and no MSI/INTx messages are ever generated for HP events (regardless of whether MSI or INTx is enabled at the root port or not) at the root port. When this bit is clear, _HPGPE message generation on behalf of root port HP events is disabled and OS can chose to generate MSI or INTx interrupt for HP events, by setting the MSI enable bit in root ports. This bit does not apply to the DMI ports. Refer to PCI Express Base Specification, Revision 2.0 and Chapter 10, 'PCI Express Hot Plug Interrupts,' for details of MSI and GPE message generation for hotplug events. Clearing this bit (from being 1) schedules a Deassert_HPGPE event on behalf of the root port, provided there was any previous Assert_HPGPE message that was sent without an associated Deassert message.

2 RW 0b Enable_ACPI_mode_for_PM Applies only to root ports. For Dev#0 in DMI mode, this bit is to be left at default value always.When this bit is set, all PM events at the PCI Express port are handled via _PMEGPE messages to the ICH, and no MSI interrupts are ever generated for PM events at the root port (regardless of whether MSI is enabled at the root port or not). When clear, _PMEGPE message generation for PM events is disabled and OS can chose to generate MSI interrupts for delivering PM events by setting the MSI enable bit in root ports. This bit does not apply to the DMI ports. Refer to PCI Express Base Specification, Revision 2.0 and Chapter 19, 'Power Management,' for details of MSI and GPE Clearing this bit (from being 1) schedules a Deassert_PMEGPE event on behalf of the root port, provided there was any previous Assert_PMEGPE message that was sent without an associated Deassert message.

1 RW-O 0b inbound_configuration_enable Enable Inbound Configuration Requests

0RV0 Reserved

6.1.83 MISCCTRLSTS_1: Miscellaneous Control and Status

Bus: RootBus Device: 0Function: 2-3 Offset: 18Ch Bus: RootBus Device: 1Function: 0-3 Offset: 18Ch Bus: RootBus Device: 2Function: 0-3 Offset: 18Ch

Bit Attr Default Description

31:18 RV 0 Reserved

17 RW1C 0b Locked_read_timed_out S Indicates that a locked read request incurred a completion timeout on PCI Express/DMI

16 RW1C 0b Received_PME_TO_ACK Indicates that IIO received a PME turn off ack packet or it timed out waiting for the packet

15:10 RV 0 Reserved

9 RW 0b override_socketid_in_cplid For TPH/DCA requests, the Completer ID can be returned with SocketID when this bit is set.

8:7 RV 0 Reserved

Intel® Xeon Phi™ Processor 177 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 18Ch Bus: RootBus Device: 1Function: 0-3 Offset: 18Ch Bus: RootBus Device: 2Function: 0-3 Offset: 18Ch

Bit Attr Default Description

6 RW 0b Problematic_Port_for_Lock_Flows This bit is set by BIOS when it knows that this port is connected to a device that creates Posted- Posted dependency on its In-Out queues. BIOS writers must read the 'Ordering Chapter' of IIO HAS to get a complete list of devices that are considered to have this dependency. Briefly, this bit is set on a link if: This link is connected to a buggy Intel NIC device: one of zoar/Oplin/Hartwell IIO lock flows depend on the setting of this bit to treat this port in a special way during the flows. Note that if BIOS is setting up the lock flow to be in the 'QPI compatible' mode (refer to UBOX HAS for details), then this bit must be set to 0. An inbound MSI request can block the posted channel until EOI's are posted to all outbound queues enabled to receive EOI. Because of this, this bit cannot be set unless EOIFD is also set.

5 RW 0b Disable_MCTP_Broadcast_to_this_link When set, this bit will prevent a broadcast MCTP message (w/ Routing Type of 'Broadcast from RC') from being sent to this link.This bit is provided as a general chicken bit in case there are devices that barf when they receive this message or for the case where p2p posted traffic is to be specifically prohibited to this port to avoid deadlocks, like can happen if this port is the 'problematic' port.

4RWS0bForm_Factor Indicates what form-factor a particular root port controls0 - CEM 1 - Express Module This bit is used to interpret bit 6 in the VPP serial stream for the port as either MRL# (CEM) input or EMLSTS# (Express Module) input.

3 RW 0b Override_System_Error_on_PCIE_Fatal_Error_Enable When set, fatal errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register. When clear, the fatal errors are only propagated to the IIO core error logic if the equivalent bit in ROOTCTRL register is set.See section titled PCI Express Error Reporting Specifics in the RAS chapter for details of how this bit interacts with other control bits in signalling errors to the IIO global error reporting logic. For Dev#0 in DMI mode, unless this bit is set, DMI link related fatal errors will never be notified to system software.

2 RW 0b Override_System_Error_on_PCIE_Non_fatal_Error_Enable When set, non-fatal errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register. When clear, the non-fatal errors are only propagated to the IIO core error logic if the equivalent bit in ROOTCTRL register is set.See section titled PCI Express Error Reporting Specifics in the RAS chapter for details of how this bit interacts with other control bits in signalling errors to the IIO global error reporting logic. For Dev#0 in DMI mode, unless this bit is set, DMI link related non- fatal errors will never be notified to system software.

1 RW 0b Override_System_Error_on_PCIE_Correctable_Error_Enable When set, correctable errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register. When clear, the correctable errors are only propagated to the IIO core error logic if the equivalent bit in ROOTCTRL register is set.See section titled PCI Express Error Reporting Specifics in the RAS chapter for details of how this bit interacts with other control bits in signalling errors to the IIO global error reporting logic. For Dev#0 in DMI mode, unless this bit is set, DMI link related correctable errors will never be notified to system software.

0 RW 0b ACPI_PME_Interrupt_Enable When set, Assert/Deassert_PMEGPE messages are enabled to be generated when ACPI mode is enabled for handling PME messages from PCI Express. See Power Management Chapter for more details of this bit's usage.When this bit is cleared (from a 1), a Deassert_PMEGPE message is scheduled on behalf of the root port if an Assert_PMEGPE message was sent last from the root port.

178 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.84 PCIE_BIF_CTRL: PCIe Bifurcation Control

Bus: RootBus Device: 0Function: 2Offset: 190h Bus: RootBus Device: 1Function: 0Offset: 190h Bus: RootBus Device: 2Function: 0Offset: 190h

Bit Attr Default Description

31:4 RV 0 Reserved

3RW-0b Start_Bifurcation LB When software writes the bit so the value changes from 0 to 1, then the bifurcation control value will take effect the next time lanes are in a linkdown condition. When software writes the bit so the value changes from 1 to 0, links that enter linkdown will not be allowed to retrain to linkup (this does not force a linkdown). Notes: This bit can be written to a 1 in the same write that changes values for bits 2:0 in this register and in that case, the new value from the write to bits 2:0 take effect. Writing a 1 when this bit is already a 1 will not allow new bifurcation control values to take effect.

2:0 RWS- 000b Bifurcation_Control LB To select how 16 lanes may be bifurcated into multiple links: 000: x4x4x4x4 (lanes [15:12], [11:8], [7:4], [3:0]) 001: x4x4x8 (lanes [15:12], [11:8], [7:0]) 010: x8x4x4 (lanes [15:8], [7:4], [3:0]) 011: x8x8 (lanes [15:8], [7:0]) 100: x16 (lanes [15:0]) others: Reserved

6.1.85 ERRINJCAP: PCI Express Error Injection Capability

Bus: RootBusDevice: 0Function: 2-3Offset: 1D0h Bus: RootBusDevice: 1Function: 0Offset: 1D0h Mode: PCIe Bus: RootBusDevice: 1Function: 1-3Offset: 1D0h Bus: RootBusDevice: 2Function: 0-3Offset: 1D0h

Bit Attr Default Description

31:20 RO 250h NXTPTR Next Capability Offset This field points to the next capability or 0 if there isn't a next capability.

19:16 RO 1h CAPVER Capability Version Set to 1h for this version of the PCI Express logic

15:0 RO 000Bh EXTCAPID PCI Express Extended CAP ID Vendor Specific Capability

6.1.86 ERRINJHDR: PCI Express Error Injection Capability Header

Bus: RootBus Device: 0Function: 2-3 Offset: 1D4h Bus: RootBus Device: 1Function: 0-3 Offset: 1D4h Bus: RootBus Device: 2Function: 0-3 Offset: 1D4h

Bit Attr Default Description

31:20 RO 0Ah VSECLEN Vendor Specific Capability Length Indicates the length of the capability structure, including header bytes.

19:16 RO 1h VSECREV Vendor Specific Capability Revision Set to 1h for this version of the WHEA Error Injection logic

Intel® Xeon Phi™ Processor 179 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 1D4h Bus: RootBus Device: 1Function: 0-3 Offset: 1D4h Bus: RootBus Device: 2Function: 0-3 Offset: 1D4h

Bit Attr Default Description

15:0 RO 0003h VSECID Vendor Specific ID Assigned for WHEA Error Injection

6.1.87 ERRINJCON: PCI Express Error Injection Control Register

Bus: RootBus Device: 0Function: 2-3 Offset: 1D8h Bus: RootBus Device: 1Function: 0-3 Offset: 1D8h Bus: RootBus Device: 2Function: 0-3 Offset: 1D8h

Bit Attr Default Description

15:3 RV 0 Reserved

2 RW 0b CAUSE_CTOERR Cause a Completion Timeout Error When this bit is written to transition from 0 to 1, one and only one error assertion pulse is produced on the error source signal for the given port. This error will appear equivalent to an actual error assertion because this event is OR'd into the existing error reporting structure. To log another error, this bit must be cleared first, before setting again. Leaving this bit in a 1 state does not produce a persistent error condition. Notes: This bit is used for an uncorrectable error test This bit must be cleared by software before creating another event. This bit is disabled by bit 0 of this register

1 RW 0b CAUSE_RCVERR Cause a Receiver Error When this bit is written to transition from 0 to 1, one and only one error assertion pulse is produced on the error source signal for the given port. This error will appear equivalent to an actual error assertion because this event is OR'd into the existing error reporting structure. To log another error, this bit must be cleared first, before setting again. Leaving this bit in a 1 state does not produce a persistent error condition. Notes: This bit is used for an correctable error test This bit must be cleared by software before creating another event. This bit is disabled by bit 0 of this register

0 RW-O 0b ERRINJDIS Error Injection Disable This bit disables the use of the PCIe error injection bits. Notes: This is a write once bit.

180 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.88 CTOCTRL: Completion Timeout Control

Bus: RootBus Device: 0Function: 2-3 Offset: 1E0h Bus: RootBus Device: 1Function: 0-3 Offset: 1E0h Bus: RootBus Device: 2Function: 0-3 Offset: 1E0h

Bit Attr Default Description

31:10 RV 0 Reserved

9:8 RW 00b XP_to_PCIE_timeout_select When OS selects a timeout range of 17s to 64s for XP (that affect NP tx issued to the PCIE/DMI) using the root port's DEVCTRL2 register, this field selects the sub-range within that larger range, for additional controllability. 00: 17s-30s 01: 31s-45s 10: 46s-64s 11: Reserved

7:0 RV 0 Reserved

6.1.89 XPCORERRSTS: XP Correctable Error Status

The contents of the next set of registers - XPCORERRSTS, XPCORERRMSK, XPUNCERRSTS, XPUNCERRMSK, XPUNCERRSEV, XPUNCERRPTR - to be defined by the design team based on micro-architecture. The architecture model for error logging and escalation of internal errors is similar to that of PCI Express AER, except that these internal errors never trigger an MSI and are always reported to the system software. Mask bits mask the reporting of an error and severity bit controls escalation to either fatal or non-fatal error to the internal core error logic. Note that internal errors detected in the PCI Express cluster are not dependent on any other control bits for error escalation other than the mask bit defined in these registers. All these registers are sticky.

Bus: RootBus Device: 0Function: 2-3 Offset: 200h Bus: RootBus Device: 1Function: 0-3 Offset: 200h Bus: RootBus Device: 2Function: 0-3 Offset: 200h

Bit Attr Default Description

31:1 RV 0 Reserved

0 RW1CS 0b PCI_link_bandwidth_changed_status This bit is set when: (LNKSTS[15] and LNKCON[11])=1 or LNKSTS[14]=1 or (LNKSTS[5] and LNKCON[1])=1 This bit is cleared by software.

6.1.90 XPCORERRMSK: XP Correctable Error Mask

Bus: RootBus Device: 0Function: 2-3 Offset: 204h Bus: RootBus Device: 1Function: 0-3 Offset: 204h Bus: RootBus Device: 2Function: 0-3 Offset: 204h

Bit Attr Default Description

31:1 RV 0 Reserved

0 RWS 0b PCI_link_bandwidth_Changed_mask Masks the BW change event from being propagated to the IIO core error logic as a correctable error

Intel® Xeon Phi™ Processor 181 Datasheet - Volume 2, December 2016 6.1.91 XPUNCERRSTS: XP Uncorrectable Error Status

Bus: RootBus Device: 0Function: 2-3 Offset: 208h Bus: RootBus Device: 1Function: 0-3 Offset: 208h Bus: RootBus Device: 2Function: 0-3 Offset: 208h

Bit Attr Default Description

31:10 RV 0 Reserved

9 RW1CS 0b Outbound_Poisoned_Data

8 RW1CS 0b Received_MSI_writes_greater_than_a_DWOR D_data

7 RW1CS 0b Unused7

6 RW1CS 0b Received_PCIE_completion_with_UR_status

5 RW1CS 0b Received_PCIE_completion_with_CA_status

4 RW1CS 0b Sent_completion_with_Unsupported_Request

3 RW1CS 0b Sent_completion_with_Completer_Abort

2 RW1CS 0b Unused2

1 RW1CS 0b Outbound_Switch_FIFO_data_parity_error_de tected

0 RW1CS 0b Unused0

6.1.92 XPUNCERRMSK: XP Uncorrectable Error Mask

Bus: RootBus Device: 0Function: 2-3 Offset: 20Ch Bus: RootBus Device: 1Function: 0-3 Offset: 20Ch Bus: RootBus Device: 2Function: 0-3 Offset: 20Ch

Bit Attr Default Description

31:10 RV 0 Reserved

9 RWS 0b Outbound_Poisoned_Data_Mask

8 RWS 0b Received_MSI_writes_greater_than_a_DWORD_data_ mask

7RWS0bUnused7

6 RWS 0b Received_PCIE_completion_with_UR_status_mask

5 RWS 0b Received_PCIE_completion_with_CA_status_mask

4 RWS 0b Sent_completion_with_Unsupported_Request_mask

3 RWS 0b Sent_completion_with_Completer_Abort_mask

2RWS0bUnused2

1 RWS 0b Outbound_Switch_FIFO_data_parity_error_detected_ mask

0RWS0bUnused0

182 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.93 XPUNCERRSEV: XP Uncorrectable Error Severity

Bus: RootBus Device: 0Function: 2-3 Offset: 210h Bus: RootBus Device: 1Function: 0-3 Offset: 210h Bus: RootBus Device: 2Function: 0-3 Offset: 210h

Bit Attr Default Description

31:10 RV 0 Reserved

9 RWS 0b Outbound_Poisoned_Data_Severity

8 RWS 0b Received_MSI_writes_greater_than_a_DWORD_data_seve rity

7 RWS 0b Unused7

6 RWS 0b Received_PCIE_completion_with_UR_status_severity

5 RWS 0b Received_PCIE_completion_with_CA_status_severity

4 RWS 0b Sent_completion_with_Unsupported_Request_severity

3 RWS 0b Sent_completion_with_Completer_Abort_severity

2 RWS 0b Unused2

1 RWS 0b Outbound_Switch_FIFO_data_parity_error_detected_sever ity

0 RWS 0b Unused0

6.1.94 XPUNCERRPTR: XP Uncorrectable Error Pointer

Bus: RootBus Device: 0Function: 2-3 Offset: 214h Bus: RootBus Device: 1Function: 0-3 Offset: 214h Bus: RootBus Device: 2Function: 0-3 Offset: 214h

Bit Attr Default Description

7:5 RV 0 Reserved

4:0 ROS-V 00h XP_Uncorrectable_First_Error_Pointer This field points to which of the unmasked uncorrectable errors happened first. This field is only valid when the corresponding error is unmasked and the status bit is set and this field is rearmed to load again when the status bit indicated to by this pointer is cleared by software from 1 to 0.Value of 0x0 corresponds to bit 0 in XPUNCERRSTS register, value of 0x1 corresponds to bit 1 and so forth.

6.1.95 UNCEDMASK: Uncorrectable Error Detect Status Mask

This register masks PCIe link related uncorrectable errors from causing the associated AER status bit to be set.

Bus: RootBus Device: 0Function: 2-3 Offset: 218h Bus: RootBus Device: 1Function: 0-3 Offset: 218h Bus: RootBus Device: 2Function: 0-3 Offset: 218h

Bit Attr Default Description

31:22 RV 0 Reserved

21 RWS 0b ACS_Violation_Detect_Mask

20 RWS 0b Unsupported_Request_Error_Detect_Mask

19 RWS 0b ECRC_Error_Detect_Mask

18 RWS 0b Malformed_TLP_Detect_Mask

17 RWS 0b Receiver_Buffer_Overflow_Detect_Mask

16 RWS 0b Unexpected_Completion_Detect_Mask

Intel® Xeon Phi™ Processor 183 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 218h Bus: RootBus Device: 1Function: 0-3 Offset: 218h Bus: RootBus Device: 2Function: 0-3 Offset: 218h

Bit Attr Default Description

15 RWS 0b Completer_Abort_Detect_Mask

14 RWS 0b Completion_Time_out_Detect_Mask

13 RWS 0b Flow_Control_Protocol_Error_Detect_Mask

12 RWS 0b Poisoned_TLP_Detect_Mask

11:6 RV 0 Reserved

5 RWS 0b Surprise_Down_Error_Detect_Mask

4 RWS 0b Data_Link_Protocol_Error_Detect_Mask

3:0 RV 0 Reserved

6.1.96 COREDMASK: Correctable Error Detect Status Mask

This register masks PCIe link related correctable errors from causing the associated status bit in AER status register to be set

Bus: RootBus Device: 0Function: 2-3 Offset: 21Ch Bus: RootBus Device: 1Function: 0-3 Offset: 21Ch Bus: RootBus Device: 2Function: 0-3 Offset: 21Ch

Bit Attr Default Description

31:14 RV 0 Reserved

13 RWS 0b Advisory_Non_fatal_Error_Detect_Mask

12 RWS 0b Replay_Timer_Time_out_Detect_Mask

11:9 RV 0 Reserved

8 RWS 0b Replay_Num_Rollover_Detect_Mask

7 RWS 0b Bad_DLLP_Detect_Mask

6RWS0bBad_TLP_Detect_Mask

5:1 RV 0 Reserved

0 RWS 0b Receiver_Error_Detect_Mask

6.1.97 RPEDMASK: Root Port Error Detect Status Mask

This register masks the associated error messages (received from PCIe link and NOT the virtual ones generated internally), from causing the associated status bits in AER to be set

Bus: RootBus Device: 0Function: 2-3 Offset: 220h Bus: RootBus Device: 1Function: 0-3 Offset: 220h Bus: RootBus Device: 2Function: 0-3 Offset: 220h

Bit Attr Default Description

31:3 RV 0 Reserved

2 RWS 0b Fatal_error_Detected_Status_mask

1 RWS 0b Non_fatal_error_detected_Status_mask

0 RWS 0b Correctable_error_detected_status_mask

184 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.98 XPUNCEDMASK: XP Uncorrectable Error Detect Mask

This register masks other uncorrectable errors from causing the associated XPUNCERRSTS status bit to be set.

Bus: RootBus Device: 0Function: 2-3 Offset: 224h Bus: RootBus Device: 1Function: 0-3 Offset: 224h Bus: RootBus Device: 2Function: 0-3 Offset: 224h

Bit Attr Default Description

31:10 RV 0 Reserved

9 RWS 0b Outbound_Poisoned_Data_Detect_Mask

8 RWS 0b Received_MSI_writes_greater_than_a_DWORD_dat a_Detect_Mask

7RWS0bUnused7

6 RWS 0b Received_PCIE_completion_with_UR_status_Detect _Mask

5 RWS 0b Received_PCIE_completion_with_CA_status_Detect _Mask

4 RWS 0b Sent_completion_with_Unsupported_Request_Dete ct_Mask

3 RWS 0b Sent_completion_with_Completer_Abort_Detect_Ma sk

2RWS0bUnused2

1 RWS 0b Outbound_Switch_FIFO_data_parity_error_detecte d_Detect_Mask

0RWS0bUnused0

6.1.99 XPCORERRDMSK: XP Correctable Detect Error Mask

This register masks other correctable errors from causing the associated XPCORERRSTS status bit to be set.

Bus: RootBus Device: 0Function: 2-3 Offset: 228h Bus: RootBus Device: 1Function: 0-3 Offset: 228h Bus: RootBus Device: 2Function: 0-3 Offset: 228h

Bit Attr Default Description

31:1 RV 0 Reserved

0 RWS 0b PCI_link_bandwidth_Changed_Detect_Mask Masks the BW change event from being propagated to the IIO core error logic as a correctable error

6.1.100 XPGLBERRSTS: XP Global Error Status

This register captures a concise summary of the error logging in AER registers so that sideband system management software can view the errors independent of the main OS that might be controlling the AER errors.

Bus: RootBus Device: 0Function: 2-3 Offset: 230h Bus: RootBus Device: 1Function: 0-3 Offset: 230h Bus: RootBus Device: 2Function: 0-3 Offset: 230h

Bit Attr Default Description

31:3 RV 0 Reserved

Intel® Xeon Phi™ Processor 185 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 230h Bus: RootBus Device: 1Function: 0-3 Offset: 230h Bus: RootBus Device: 2Function: 0-3 Offset: 230h

Bit Attr Default Description

2 RW1CS 0b PCIE_AER_Correctable_error A PCIe correctable error (ERR_COR message received from externally or through a virtual ERR_COR message generated internally) was detected anew. Note that if that error was masked in the PCIE AER, it is not reported in this field. Software clears this bit by writing a 1 and at that stage, only 'subsequent' PCIE unmasked correctable errors will set this bit.Conceptually, per the flow of PCI Express Base Spec 2.0 defined Error message control, this bit is set by the ERR_COR message that is enabled to cause a System Error notification. See section titled PCI Express Error Reporting Specifics in the RAS chapter for details of how this bit interacts with other control/status bits in signalling errors to the IIO global error reporting logic.

1 RW1CS 0b PCIE_AER_Non_fatal_error A PCIe non-fatal error (ERR_NONFATAL message received from externally or through a virtual ERR_NONFATAL message generated internally) was detected anew. Note that if that error was masked in the PCIe AER, it is not reported in this field. Software clears this bit by writing a 1 and at that stage only 'subsequent' PCIE unmasked non- fatal errors will set this bit again.See section titled PCI Express Error Reporting Specifics in the RAS chapter for details of how this bit interacts with other control/status bits in signalling errors to the IIO global error reporting logic.

0 RW1CS 0b PCIE_AER_Fatal_error A PCIe fatal error (ERR_FATAL message received from externally or through a virtual ERR_FATAL message generated internally) was detected anew. Note that if that error was masked in the PCIE AER, it is not reported in this field. Software clears this bit by writing a 1 and at that stage, only 'subsequent' PCIE unmasked fatal errors will set this bit.See section titled PCI Express Error Reporting Specifics in the RAS chapter for details of how this bit interacts with other control/status bits in signaling errors to the IIO global error reporting logic.

6.1.101 XPGLBERRPTR: XP Global Error Pointer

Bus: RootBus Device: 0Function: 2-3 Offset: 232h Bus: RootBus Device: 1Function: 0-3 Offset: 232h Bus: RootBus Device: 2Function: 0-3 Offset: 232h

Bit Attr Default Description

15:3 RV 0 Reserved

2:0 ROS-V 0h XP_Cluster_Global_First_Error_Pointer This field points to which of the 3 errors indicated in the XPGLBERRSTS register happened first. This field is only valid when the corresponding status bit is set and this field is rearmed to load again when the status bit indicated to by this pointer is cleared by software from 1 to 0.Value of 0x0 corresponds to bit 0 in XPGLBERRSTS register, value of 0x1 corresponds to bit 1 and so forth.

186 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.102 PXP2CAP: Secondary PCI Express Extended Capability Header

Bus: RootBus Device: 0Function: 2-3 Offset: 250h Bus: RootBus Device: 1Function: 0-3 Offset: 250h Bus: RootBus Device: 2Function: 0-3 Offset: 250h

Bit Attr Default Description

31:20 RO-V 280h NXTPTR Next Capability Offset This should change to 298h if LER is disabled and RPPIO is not disabled by fuse. This should change to 300h if RPPIOERR capability structure is also disabled by fuse. If dual-cast capability is also disabled, then this value would be 000h.

19:16 RW-O 1h VERSION Capability Version

15:0 RW-O 0019h ID PCI Express Extended CAP ID This field is a PCI SIG defined ID number that indicates the nature and format of the Extended Capability. PCI Express Extended Capability ID for the Secondary PCI Expresss Extended Capability is 0019h.

6.1.103 LNKCON3: Link Control 3 Register

Bus: RootBus Device: 0Function: 2-3 Offset: 254h Bus: RootBus Device: 1Function: 0-3 Offset: 254h Bus: RootBus Device: 2Function: 0-3 Offset: 254h

Bit Attr Default Description

31:2 RV 0 Reserved

1 RW 0b LNKEQREQINTEN Link Equalization Request Interrupt Enable When Set, this bit enables the generation of interrupt to indicate that the Link Equalization Request bit has been set.

0RW0bPERFEQ Perform Equalization When this register is 1b and a 1b is written to the `Link Retrain' register with `Target Link Speed' set to 8GT/s, the Upstream component must perform Transmitter Equalization.

Intel® Xeon Phi™ Processor 187 Datasheet - Volume 2, December 2016 6.1.104 LNERRSTS: Lane Error Status Register (16 lanes)

Bus: RootBus Device: 0Function: 2-3 Offset: 258h Bus: RootBus Device: 1Function: 0-3 Offset: 258h Bus: RootBus Device: 2Function: 0-3 Offset: 258h

Bit Attr Default Description

15:0 RW1CS 0000h LANE Lane Error Status A value of 1b in any bit indicates if the corresponding PCIe Express Lane detected lane based error. bit 0 Lane 0 Error Detected bit 1 Lane 1 Error Detected bit 2 Lane 2 Error Detected bit 3 Lane 3 Error Detected bit 4 Lane 4 Error Detected (not used when the link is bifurcated as x4) bit 5 Lane 5 Error Detected (not used when the link is bifurcated as x4) bit 6 Lane 6 Error Detected (not used when the link is bifurcated as x4) bit 7 Lane 7 Error Detected (not used when the link is bifurcated as x4) bit 8 Lane 8 Error Detected (not used when the link is bifurcated as x4 or x8) bit 9 Lane 9 Error Detected (not used when the link is bifurcated as x4 or x8) bit 10 Lane 10 Error Detected (not used when the link is bifurcated as x4 or x8) bit 11 Lane 11 Error Detected (not used when the link is bifurcated as x4 or x8) bit 12 Lane 12 Error Detected (not used when the link is bifurcated as x4 or x8) bit 13 Lane 13 Error Detected (not used when the link is bifurcated as x4 or x8) bit 14 Lane 14 Error Detected (not used when the link is bifurcated as x4 or x8) bit 15 Lane 15 Error Detected (not used when the link is bifurcated as x4 or x8)

6.1.105 LN0EQ: Lane 0 Equalization Control

Bus: RootBus Device: 0Function: 2-3 Offset: 25Ch Bus: RootBus Device: 1Function: 0-3 Offset: 25Ch Bus: RootBus Device: 2Function: 0-3 Offset: 25Ch

Bit Attr Default Description

15 RV 0 Reserved

14:12 RW- 2h DNRXPRESET O Downstream Component Receiver Preset Hint Receiver Preset Hint for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: Reserved For a Downstream Component, this field reflects the latest Receiver Preset value requested from the Upstream Component on Lane 0. The default value is 111b.

188 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 25Ch Bus: RootBus Device: 1Function: 0-3 Offset: 25Ch Bus: RootBus Device: 2Function: 0-3 Offset: 25Ch

Bit Attr Default Description

11:8 RW- 8h DNTXPRESET O Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0Reserved

6:4 RO 7h UPRXPRESET Upstream Component Receiver Preset Hint Receiver Preset Hint for Upstream Component. The upstream component uses this hint for receiver equalization. The Root Ports are upstream components. The encodings are defined below. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: Reserved

3:0 RW- 8h UPTXPRESET O Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

Intel® Xeon Phi™ Processor 189 Datasheet - Volume 2, December 2016 6.1.106 LN1EQ: Lane 1 Equalization Control

Bus: RootBus Device: 0Function: 2-3 Offset: 25Eh Bus: RootBus Device: 1Function: 0-3 Offset: 25Eh Bus: RootBus Device: 2Function: 0-3 Offset: 25Eh

Bit Attr Default Description

15 RV 0 Reserved

14:12 RW-O 2h DNRXPRESET Downstream Component Receiver Preset Hint Receiver Preset Hint for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: Reserved For a Downstream Component, this field reflects the latest Receiver Preset value requested from the Upstream Component on Lane 0. The default value is 111b.

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de-emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de- emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0 Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de-emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de- emphasis, 3.5 dB for preshoot others: reserved

190 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.107 LN2EQ: Lane 2 Equalization Control

Bus: RootBus Device: 0Function: 2-3 Offset: 260h Bus: RootBus Device: 1Function: 0-3 Offset: 260h Bus: RootBus Device: 2Function: 0-3 Offset: 260h

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0 Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

Intel® Xeon Phi™ Processor 191 Datasheet - Volume 2, December 2016 6.1.108 LN3EQ: Lane 3 Equalization Control

Bus: RootBus Device: 0Function: 2-3 Offset: 262h Bus: RootBus Device: 1Function: 0-3 Offset: 262h Bus: RootBus Device: 2Function: 0-3 Offset: 262h

Bit Attr Default Description

15 RV 0 Reserved

7RV0Reserved

192 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.109 LN4EQ: Lane 4 Equalization Control

Bus: RootBusDevice: 0Function: 2Offset: 264h Bus: RootBusDevice: 1Function: 0, 2Offset: 264h Bus: RootBusDevice: 2Function: 0, 2Offset: 264h

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0 Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

Intel® Xeon Phi™ Processor 193 Datasheet - Volume 2, December 2016 6.1.110 LN5EQ: Lane 5 Equalization Control

Bus: RootBusDevice: 0Function: 2Offset: 266h Bus: RootBusDevice: 1Function: 0, 2Offset: 266h Bus: RootBusDevice: 2Function: 0, 2Offset: 266h

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0 Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

194 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.111 LN6EQ: Lane 6 Equalization Control

Bus: RootBusDevice: 0Function: 2Offset: 268h Bus: RootBusDevice: 1Function: 0, 2Offset: 268h Bus: RootBusDevice: 2Function: 0, 2Offset: 268h

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0 Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

Intel® Xeon Phi™ Processor 195 Datasheet - Volume 2, December 2016 6.1.112 LN7EQ: Lane 7 Equalization Control

Bus: RootBusDevice: 0Function: 2Offset: 26Ah Bus: RootBusDevice: 1Function: 0, 2Offset: 26Ah Bus: RootBusDevice: 2Function: 0, 2Offset: 26Ah

Bit Attr Default Description

15 RV 0 Reserved

7RV0Reserved

196 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.113 LN8EQ: Lane 8 Equalization Control

Bus: RootBusDevice: 1Function: 0Offset: 26Ch Bus: RootBusDevice: 2Function: 0Offset: 26Ch

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

Intel® Xeon Phi™ Processor 197 Datasheet - Volume 2, December 2016 6.1.114 LN9EQ: Lane 9 Equalization Control

Bus: RootBusDevice: 1Function: 0Offset: 26Eh Bus: RootBusDevice: 2Function: 0Offset: 26Eh

Bit Attr Default Description

15 RV 0 Reserved

7RV0Reserved

198 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.115 LN10EQ: Lane 10 Equalization Control

Bus: RootBusDevice: 1Function: 0Offset: 270h Bus: RootBusDevice: 2Function: 0Offset: 270h

Bit Attr Default Description

15 RV 0 Reserved

7RV0 Reserved

Intel® Xeon Phi™ Processor 199 Datasheet - Volume 2, December 2016 6.1.116 LN11EQ: Lane 11 Equalization Control

Bus: RootBusDevice: 1Function: 0Offset: 272h Bus: RootBusDevice: 2Function: 0Offset: 272h

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0 Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

200 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.117 LN12EQ: Lane 12 Equalization Control

Bus: RootBusDevice: 1Function: 0Offset: 274h Bus: RootBusDevice: 2Function: 0Offset: 274h

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de- emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de-emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de- emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de-emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

Intel® Xeon Phi™ Processor 201 Datasheet - Volume 2, December 2016 6.1.118 LN13EQ: Lane 13 Equalization Control

Bus: RootBusDevice: 1Function: 0Offset: 276h Bus: RootBusDevice: 2Function: 0Offset: 276h

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de- emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de-emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de- emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de-emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

202 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.119 LN14EQ: Lane 14 Equalization Control

Bus: RootBusDevice: 1Function: 0Offset: 278h Bus: RootBusDevice: 2Function: 0Offset: 278h

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0 Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de-emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de- emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

Intel® Xeon Phi™ Processor 203 Datasheet - Volume 2, December 2016 6.1.120 LN15EQ: Lane 15 Equalization Control

Bus: RootBusDevice: 1Function: 0Offset: 27Ah Bus: RootBusDevice: 2Function: 0Offset: 27Ah

Bit Attr Default Description

15 RV 0 Reserved

11:8 RW-O 8h DNTXPRESET Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. The Upstream component must pass on this value in the EQ TS2'es. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de- emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de-emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved For a Downstream Component, this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane 0.

7RV0Reserved

3:0 RW-O 8h UPTXPRESET Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The Root Ports are upstream components. The encodings are defined below. 0000b: -6.0 dB for de-emphasis, 0 dB for preshoot 0001b: -3.5 dB for de-emphasis, 0 dB for preshoot 0010b: -4.5 dB for de-emphasis, 0 dB for preshoot 0011b: -2.5 dB for de-emphasis, 0 dB for preshoot 0100b: 0 dB for de-emphasis, 0 dB for preshoot 0101b: 0 dB for de- emphasis, 2.0 dB for preshoot 0110b: 0 dB for de-emphasis, 2.5 dB for preshoot 0111b: -6.0 dB for de-emphasis, 3.5 dB for preshoot 1000b: -3.5 dB for de-emphasis, 3.5 dB for preshoot 1001b: 0 dB for de-emphasis, 3.5 dB for preshoot others: reserved

204 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.121 LER_CAP: Live Error Recovery Capability

Bus: RootBus Device: 0Function: 2-3 Offset: 280h Bus: RootBus Device: 1Function: 0-3 Offset: 280h Bus: RootBus Device: 2Function: 0-3 Offset: 280h

Bit Attr Default Description

31:20 RO-V 298h NXTPTR Next Capability Offset This should change to 300h if RPPIOERR capability structure is disabled by fuse. If dual-cast capability is also disabled, then this value would be 000h.

19:16 RO 1h CAPVER Capability Version

15:0 RO 000Bh CAPID PCI Express Extended CAP ID Vendor Specific Capability

6.1.122 LER_HDR: Live Error Recovery Capability Header

Bus: RootBus Device: 0Function: 2-3 Offset: 284h Bus: RootBus Device: 1Function: 0-3 Offset: 284h Bus: RootBus Device: 2Function: 0-3 Offset: 284h

Bit Attr Default Description

31:20 RO 18h VSECLEN Vendor Specific Capability Length

19:16 RO 3h VSECREV Vendor Specific Capability Revision

15:0 RO 0005h VSECID Vendor Specific ID Represents the Live Error Recovery capability

6.1.123 LER_CTRLSTS: Live Error Recovery Control and Status

Bus: RootBus Device: 0Function: 2-3 Offset: 288h Bus: RootBus Device: 1Function: 0-3 Offset: 288h Bus: RootBus Device: 2Function: 0-3 Offset: 288h

Bit Attr Default Description

31 RW1CS 0b LER_ SS_Status Live Error Recovery Status Indicates that an error was detected that caused the PCIE port to go into a live error recovery (LER) mode. While in LER mode, the link goes into a LinkDown "Disabled" state and all outbound transactions are aborted (including packets that may have caused the error). This bit cannot be cleared until all the associated unmasked status bits are cleared, or the corresponding LER mask bits are set. Once the unmasked error considtion are cleared, then this bit may be cleared by software writing a '1'. Once this status becomes cleared by clearing the error condition, the link will retrain into LinkUp state and outbound transactions will no longer be aborted. A link that is forced into a LinkDown state due to LER does not trigger a "surprise LinkDown" error in the UNCERRSTS register. It should be noted that many PCIe cards will go into internal reset when they receive training sequences that indicate the "Disabled" state.

30 ROS-V 0b LER_SS_Lnk_Up_OK Live Error Recovery Port Quiesced Indicates when the port has no more pending inbound or outbound packets after the port has entered LER mode. It is used by software to determine when it is safe to clear the LER_Status bit to bring the port out of LER mode.

Intel® Xeon Phi™ Processor 205 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 288h Bus: RootBus Device: 1Function: 0-3 Offset: 288h Bus: RootBus Device: 2Function: 0-3 Offset: 288h

Bit Attr Default Description

29:4 RV 0 Reserved

3 RWS 0b LER_SS_INTEN Live Error Recovery Interrupt Enable If set, causes and INTx or MSI interrupt from the root port (if enabled in the root port) to be generated when LER_Status is set.

2 RWS 0b LER_SS_Drop_TXN Live Error Recovery Drop Transaction If set, after entering LER subsequent transactions will be dropped as soon as the port configuration allows.

1 RWS 0b LER_SS_Severity_En Live Error Recovery Severity Enable If set, forces the errors that trigger LER mode to be signalled as correctable error of Severity 0. If cleared, then errors are signaled as Uncorrectable Non-Fatal Severity 1 or Uncorrectable Fatal Severity 2 as specified for the given error.

0 RWS 0b LER_SS_Enable Live Error Recovery Enable When set, allows the LER_Status to assert on error. When the status bit is set, the port is in LER mode. When this bit is cleared, the LER_Status bit cannot become set on an error. If this bit is cleared when LER_Status bit is already set, then clearing this bit does not clear the status bit and does not exit LER mode. To exit LER mode, the status bit must be cleared by software.

6.1.124 LER_UNCERRMSK: Live Error Recovery Uncorrectable Error Mask

This register masks uncorrectable errors from being signaled as LER events.

Bus: RootBus Device: 0Function: 2-3 Offset: 28Ch Bus: RootBus Device: 1Function: 0-3 Offset: 28Ch Bus: RootBus Device: 2Function: 0-3 Offset: 28Ch

Bit Attr Default Description

31:22 RV 0 Reserved

21 RWS 0b ACS_Violation_Mask

20 RWS 0b Unsupported_Request_Error_Mask

19 RWS 0b ECRC_Error_Mask

18 RWS 0b Malformed_TLP_Mask

17 RWS 0b Receiver_Buffer_Overflow_Mask

16 RWS 0b Unexpected_Completion_Mask

15 RWS 0b Completer_Abort_Mask

14 RWS 0b Completion_Time_out_Mask

13 RWS 0b Flow_Control_Protocol_Error_Mask

12 RWS 0b Poisoned_TLP_Mask

11:6 RV 0 Reserved

5 RWS 0b Surprise_Down_Error_Mask

4 RWS 0b Data_Link_Layer_Protocol_Error_Mask

3:0 RV 0 Reserved

206 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.125 LER_XPUNCERRMSK: Live Error Recovery XP Uncorrectable Error Mask

Bus: RootBus Device: 0Function: 2-3 Offset: 290h Bus: RootBus Device: 1Function: 0-3 Offset: 290h Bus: RootBus Device: 2Function: 0-3 Offset: 290h

Bit Attr Default Description

31:10 RV 0 Reserved

9 RWS 0b Outbound_Poisoned_Data_Mask Masks signaling of stop and scream condition to the core error logic

8:7 RV 0 Reserved

6 RWS 0b Received_PCIE_completion_with_UR_status_mask

5 RWS 0b Received_PCIE_completion_with_CA_status_mask

4 RWS 0b Sent_completion_with_UR_mask

3 RWS 0b Sent_completion_with_CA_mask

2:0 RV 0 Reserved

6.1.126 LER_RPERRMSK: Live Error Recovery Root Port Error Mask

Bus: RootBus Device: 0Function: 2-3 Offset: 294h Bus: RootBus Device: 1Function: 0-3 Offset: 294h Bus: RootBus Device: 2Function: 0-3 Offset: 294h

Bit Attr Default Description

31:3 RV 0 Reserved

6 RWS 0b Fatal_Error_Message_Received_Mask Masks LER response to Fatal Error Messages received

5 RWS 0b Non_Fatal_Error_Message_Received_Mask Masks LER response to Non-Fatal Error Messages received.

4:0 RV 0 Reserved

6.1.127 RPPIOERR_CAP: Enhanced RP Error Reporting Capability

Bus: RootBus Device: 0Function: 2-3 Offset: 298h Bus: RootBus Device: 1Function: 0-3 Offset: 298h Bus: RootBus Device: 2Function: 0-3 Offset: 298h

Bit Attr Default Description

31:20 RO 300h NXTPTR Next Capability Offset

19:16 RO 1h CAPVER Capability Version

15:0 RO 000Bh CAPID PCI Express Extended CAP ID Vendor Specific Capability

Intel® Xeon Phi™ Processor 207 Datasheet - Volume 2, December 2016 6.1.128 RPPIOERR_HDR: Enhanced RP Error Reporting Header

Bus: RootBus Device: 0Function: 2-3 Offset: 29Ch Bus: RootBus Device: 1Function: 0-3 Offset: 29Ch Bus: RootBus Device: 2Function: 0-3 Offset: 29Ch

Bit Attr Default Description

31:20 RO 24h VSECLEN Vendor Specific Capability Length

19:16 RO 0h VSECREV Vendor Specific Capability Revision

15:0 RO 0007h VSECID Vendor Specific ID Represents the Enhanced Root Port Error Reporting capability

6.1.129 RPPIOERR_HF: Enhanced RP Error Reporting Hard Fail

RW register that indicates which PIO error should cause an IOMCA event.

Bus: RootBus Device: 0Function: 2-3 Offset: 2A0h Bus: RootBus Device: 1Function: 0-3 Offset: 2A0h Bus: RootBus Device: 2Function: 0-3 Offset: 2A0h

Bit Attr Default Description

31:19 RV 0h Reserved

18 RW-L 0h MEM_TO_HF If set to 1, when an outbound mem read request was not received within a timeout parameter, IIO will return all 1s for data and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Default 0. Lock: FUSE_DISENH_ERR_REP

17 RW-L 0h MEM_CA_HF If set to 1, an outbound read request to memory that received a CA will cause IIO to return all 1s for data and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Lock: FUSE_DISENH_ERR_REP

16 RW-L 0h MEM_UR_HF If set to 1, an outbound read request to memory that received a UR will cause IIO to return all 1s for data and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Lock: FUSE_DISENH_ERR_REP

15:11 RV 0h Reserved

10 RW-L 0h IO_TO_HF If set to 1, an outbound NCIOWr/Rd request was not received within a timeout parameter, IIO will return all 1s for data and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Lock: FUSE_DISENH_ERR_REP

9RW-L0hIO_CA_HF If set to 1, an outbound NCIOWr/Rd request receiving a CA will cause IIO to return all1s for data and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Lock: FUSE_DISENH_ERR_REP

8RW-L0hIO_UR_HF If set to 1, an outbound NCIOWr/Rd request receiving a UR will cause IIO to return all 1s for data and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Lock: FUSE_DISENH_ERR_REP

7:3 RV 0h Reserved

2RW-L0hCFG_TO_HF If set to 1, an outbound NCCfgWr/Rd request did not complete within a timeout parameter, IIO will return all 1s and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Lock: FUSE_DISENH_ERR_REP

208 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 2A0h Bus: RootBus Device: 1Function: 0-3 Offset: 2A0h Bus: RootBus Device: 2Function: 0-3 Offset: 2A0h

Bit Attr Default Description

1RW-L0hCFG_CA_HF If set to 1, an outbound NCCfgWr/Rd request receiving CA will cause IIO to return all 1s for data and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Lock: FUSE_DISENH_ERR_REP

0RW-L0hCFG_UR_HF If set to 1, an outbound NCCfgWr/Rd request receiving UR will cause IIO to return all 1s for data and indicate poison. If set to 0, IIO returns all 1s for data and do not indicate poison. Lock: FUSE_DISENH_ERR_REP

6.1.130 RPPIOERR_STATUS: Enhanced RP Error Reporting Status

Read only register that shows the first error to occur and the status of errors being logged and reported.

Bus: RootBus Device: 0Function: 2-3 Offset: 2A4h Bus: RootBus Device: 1Function: 0-3 Offset: 2A4h Bus: RootBus Device: 2Function: 0-3 Offset: 2A4h

Bits Attr Default Description

31:24 RV 0 Reserved

23:19 RW1CS 0h PIO_ERR_First_Header These 4 bits identify the first error that was observed. The encoding is as follows: 00: No Error 01: CFG_UR_ERR 02: CFG_CA_ERR 03: CFG_TO_ERR 04: IO_UR_ERR 05: IO_CA_ERR 06: IO_TO_ERR 07: MEM_UR_ERR 08: MEM_CA_ERR 09: MEM_TO_ERR Others: undefined

18 RW1CS 0h MEM_TO_ERR If set to 1, indicates a MEM_TO_ERR has occurred.

17 RW1CS 0h MEM_CA_ERR If set to 1, indicates MEM_CA_ERR has occurred.

16 RW1CS 0h MEM_UR_ERR If set to 1, indicates MEM_UR_ERR has occurred.

15:11 RV 0 Reserved

10 RW1CS 0h IO_TO_ERR If set to 1, indicates IO_TO_ERR has occurred.

9 RW1CS 0h IO_CA_ERR If set to 1, indicates IO_CA_ERR has occurred.

8 RW1CS 0h IO_UR_ERR If set to 1, indicates IO_UR_ERR has occurred.

7:3 RV 0 Reserved

2 RW1CS 0h CFG_TO_ERR If set to 1, indicates CFG_TO_ERR has occurred.

1 RW1CS 0h CFG_CA_ERR If set to 1, indicates CFG_CA_ERR has occurred.

0 RW1CS 0h CFG_UR_ERR If set to 1, indicates CFG_UR_ERR has occurred.

Intel® Xeon Phi™ Processor 209 Datasheet - Volume 2, December 2016 6.1.131 RPPIOERR_MASK: Enhanced RP Error Reporting Mask

RW register that masks the errors being logged and reported. When the masked bit is set and error occurs, it wouldn’t be logged and the data returned from IIO will be all 1s. Masking the errors also prevents a LER from the root port.

When masked bit is cleared, the error is logged as an uncorrectable error and classified as either UR or CA in the port’s AER register. A TO error will be considered a UR in the AER register.

Bus: RootBus Device: 0Function: 2-3 Offset: 2A8h Bus: RootBus Device: 1Function: 0-3 Offset: 2A8h Bus: RootBus Device: 2Function: 0-3 Offset: 2A8h

Bits Attr Default Description

31:19 RO 0h Reserved

18 RW 0h MEM_TO_MASK If set to 1, when an outbound mem read request was not received within a timeout parameter, the error would be masked. Default 0.

17 RW 0h MEM_CA_MASK If set to 1, an outbound read request to memory that received a CA be masked. Default 0.

16 RW 0h MEM_UR_MASK If set to 1, an outboundread request to memory that received a UR be masked. Default 0.

15:11 RO 0h Reserved

10 RW 0h IO_TO_MASK If set to 1, an outbound NCIOWr/Rd request was not received within a timeout parameter will be masked. Default 0.

9 RW 0h IO_CA_MASK If set to 1, an outbound NCIOWr/Rd request received a CA will be masked. Default 0.

8 RW 0h IO_UR_MASK If set to 1, an outbound NCIOWr/Rd request received a UR will be masked. Default 0.

7:3 RO 0h Reserved

2RW0hCFG_TO_MASK If set to 1, an outbound NCCfgWr/Rd request did not complete within a timeout parameter will be masked. Default 0.

1RW0hCFG_CA_MASK If set to 1, an outbound NCCfgWr/Rd request received CA will be masked. Default 0.

0 RW 0h CFG_UR_MASK If set to 1, an outbound NCCfgWr/Rd request received UR will be masked. Default 0.

6.1.132 RPPIOERR_HDRLOG0: Enhanced RP Error Log Header 0

This is a set of 4 32 bit registers that log the TLP header of the first PIO error event. The identity of the first error should be logged in the PIO_ERR_STATUS register bits 23:19.

210 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 The register should be the same format as AER Header Log register, specified in section 7.10.8 of the PCI Express Spec version 3.0. The TLP headers are mapped to the register bits in the following manner:

The first TLP header byte 0 should be mapped to bits 31:24 of the first error log register at offset N+10h. This is so when the data is read out of the registers, the format is consistent with the TLP header specification in the PCI Express specification.

Bus: RootBus Device: 0Function: 2-3 Offset: 2ACh Bus: RootBus Device: 1Function: 0-3 Offset: 2ACh Bus: RootBus Device: 2Function: 0-3 Offset: 2ACh

Bits Attr Default Description

31:0 RO 0h TLP_Header_Data

6.1.133 RPPIOERR_HDRLOG1: Enhanced RP Error Log Header 1

Bus: RootBus Device: 0Function: 2-3 Offset: 2B0h Bus: RootBus Device: 1Function: 0-3 Offset: 2B0h Bus: RootBus Device: 2Function: 0-3 Offset: 2B0h

Bits Attr Default Description

31:0 RO 0h TLP_Header_Data

6.1.134 RPPIOERR_HDRLOG2: Enhanced RP Error Log Header 2

Bus: RootBus Device: 0Function: 2-3 Offset: 2B4h Bus: RootBus Device: 1Function: 0-3 Offset: 2B4h Bus: RootBus Device: 2Function: 0-3 Offset: 2B4h

Bits Attr Default Description

31:0 RO 0h TLP_Header_Data

6.1.135 RPPIOERR_HDRLOG3: Enhanced RP Error Log Header 3

Bus: RootBus Device: 0Function: 2-3 Offset: 2B8h Bus: RootBus Device: 1Function: 0-3 Offset: 2B8h Bus: RootBus Device: 2Function: 0-3 Offset: 2B8h

Bits Attr Default Description

31:0 RO 0h TLP_Header_Data

Intel® Xeon Phi™ Processor 211 Datasheet - Volume 2, December 2016 6.1.136 XPPMDFXMAT0: XP PM DFx Match

This register contains bits to enable matching of any event signal on the local debug bus in this cluster. Only 3 byte lanes are possible for PerfMon counting by selecting bits in PMR.DFXLNSEL. This register is active when the PMR.LDES is set.

Bus: RootBusDevice: 1Function: 0Offset: 2F0h Bus: RootBusDevice: 2Function: 0Offset: 2F0h

Bit Attr Default Description

31:28 RV 0 Reserved

27:26 RWS 00b DIV Divider These bits indicate where the Reduction OR (ROR) boundaries are located. 00: Byte lane 0, 3, 6 01: Byte lane 1, 4, 7 10: Byte lane 2, 5, 8 11: Reserved

25:24 RWS 00b ORFLOC OR Function Locater These bits specify where the '+' operator of the DFx event match equation exists. 00: Byte lane 0, 3, 6 01: Byte lane 1, 4, 7 10: Byte lane 2, 5, 8 11: Reserved

23:16 RWS 00h DFXMAT2 DFx Match on Event Signal Lane N+2

15:8 RWS 00h DFXMAT1 DFx Match on Event Signal Lane N+1

7:0 RWS 00h DFXMAT0 DFx Match on Event Signal Lane N

6.1.137 XPPMDFXMAT1: XP PM DFx Match

Bus: RootBusDevice: 1Function: 0Offset: 2F4h Bus: RootBusDevice: 2Function: 0Offset: 2F4h

Bit Attr Default Description

31:28 RV 0 Reserved

27:26 RWS 00b DIV Divider These bits indicate where the Reduction OR (ROR) boundaries are located. 00: Byte lane 0, 3, 6 01: Byte lane 1, 4, 7 10: Byte lane 2, 5, 8 11: Reserved

212 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 2F4h Bus: RootBusDevice: 2Function: 0Offset: 2F4h

Bit Attr Default Description

25:24 RWS 00b ORFLOC OR Function Locator These bits specify where the '+' operator of the DFx event match equation exists. 00: Byte lane 0, 3, 6 01: Byte lane 1, 4, 7 10: Byte lane 2, 5, 8 11: Reserved

23:16 RWS 00h DFXMAT2 DFx Match on Event Signal Lane N+2

15:8 RWS 00h DFXMAT1 DFx Match on Event Signal Lane N+1

7:0 RWS 00h DFXMAT0 DFx Match on Event Signal Lane N

6.1.138 XPPMDFXMSK0: XP PM DFx Mask

This register contains bits for masking any event signal on the local debug bus in this cluster. Only 3 byte lanes are possible for PerfMon counting by selecting bits in PMR.DFXLNSEL. This register is active when the PMR.LDES is set.

Bus: RootBusDevice: 1Function: 0Offset: 2F8h Bus: RootBusDevice: 2Function: 0Offset: 2F8h

Bit Attr Default Description

31:24 RV 0 Reserved

23:16 RWS 00h DFx_Mask_on_Event_Signal_Lane_N_2 DFx Mask on Event Signal Lane N+2

15:8 RWS 00h DFx_Mask_on_Event_Signal_Lane_N_1 DFx Mask on Event Signal Lane N+1

7:0 RWS 00h DFx_Mask_on_Event_Signal_Lane_N DFx Mask on Event Signal Lane N

6.1.139 XPPMDFXMSK1: XP PM DFx Mask

Bus: RootBusDevice: 1Function: 0Offset: 2FCh Bus: RootBusDevice: 2Function: 0Offset: 2FCh

Bit Attr Default Description

31:24 RV 0 Reserved

23:16 RWS 00h DFx_Mask_on_Event_Signal_Lane_N_2 DFx Mask on Event Signal Lane N+2

15:8 RWS 00h DFx_Mask_on_Event_Signal_Lane_N_1 DFx Mask on Event Signal Lane N+1

7:0 RWS 00h DFx_Mask_on_Event_Signal_Lane_N DFx Mask on Event Signal Lane N

Intel® Xeon Phi™ Processor 213 Datasheet - Volume 2, December 2016 6.1.140 MCAST_CAP_HDR: Multicast Capability

Dualcast Capability Header Register (Dualcast is specialized version of PCIe Multicast supported on the Intel® Xeon® processor E5 v3 product family used in conjunction with Non-transparent Bridge Application).

Bus: RootBus Device: 0Function: 2-3 Offset: 300h Bus: RootBus Device: 1Function: 0-3 Offset: 300h Bus: RootBus Device: 2Function: 0-3 Offset: 300h

Bit Attr Default Description

31:20 RO 0 NXTPTR Next Capability Offset

19:16 RO 1h CAPVER Capability Version

15:0 RO 000Bh CAPID PCI Express Extended CAP ID Vendor Specific Capability

6.1.141 MCAST_CAP_EXT: Multicast Header

Dualcast Extended Capability Register (Dualcast is specialized version of PCIe Multicast supported on the Intel® Xeon® processor E5 v3 product family used in conjunction with Non-transparent Bridge Application).

Bus: RootBus Device: 0Function: 2-3 Offset: 304h Bus: RootBus Device: 1Function: 0-3 Offset: 304h Bus: RootBus Device: 2Function: 0-3 Offset: 304h

Bit Attr Default Description

31:20 RO 38h VSECLEN Vendor Specific Capability Length

19:16 RO 0h VSECREV Vendor Specific Capability Revision

15:0 RO 0008h VSECID Vendor Specific ID Intel defines 0x8 as the ID for dualcast.

6.1.142 MCAST_CAP: Multicast Capabilities

Dualcast Capability Register (Dualcast is specialized version of PCIe Multicast supported on the Intel® Xeon® processor E5 v3 product family used in conjunction with Non- transparent Bridge Application). The fields in this register mirror the fields in the PCIe spec-defined Multicast Capability Register (see section 7.21.2 of the PCIe 3.0 spec).

Bus: RootBus Device: 0Function: 2-3 Offset: 30Ch Bus: RootBus Device: 1Function: 0-3 Offset: 30Ch Bus: RootBus Device: 2Function: 0-3 Offset: 30Ch

Bit Attr Default Description

15 RW-O 0 MC_ECRC_Regen_Sup

14 RV 0 Reserved

13:8 RO 0 MC_Window_Size_Req

7:6 RV 0 Reserved

5:0 RO 0Fh MC_Max_Group

214 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.143 MCAST_CTRL: Multicast Control

Bus: RootBus Device: 0Function: 2-3 Offset: 30Eh Bus: RootBus Device: 1Function: 0-3 Offset: 30Eh Bus: RootBus Device: 2Function: 0-3 Offset: 30Eh

Bit Attr Default Description

15 RW-L 0b MC_Enable

14:6 RV 0 Reserved

5:0 RW-L 00h MC_Num_Group This field only supports and implements bits [3:0]. Bits [5:4] are not supported.

6.1.144 MCAST_BASE: Multicast Base Address

Bus: RootBus Device: 0Function: 2-3 Offset: 310h Bus: RootBus Device: 1Function: 0-3 Offset: 310h Bus: RootBus Device: 2Function: 0-3 Offset: 310h

Bit Attr Default Description

63:12 RW-L 0 MC_Base_Address

11:6 RV 0 Reserved

5:0 RW-L 00h MC_Index_Position

6.1.145 MCAST_OVERLAY_BAR: Multicast Overlay Base Address

Bus: RootBus Device: 0Function: 2-3 Offset: 330h Bus: RootBus Device: 1Function: 0-3 Offset: 330h Bus: RootBus Device: 2Function: 0-3 Offset: 330h

Bit Attr Default Description

63:6 RW-L 0 MC_Overlay_Addr

5:0 RW-L 00h MC_Overlay_Size

Intel® Xeon Phi™ Processor 215 Datasheet - Volume 2, December 2016 6.1.146 XPPMDL0: XP PM Data Low Bits

This is the performance monitor counter. This counter is reset at the beginning of a sample period unless pre-loaded with a sample value. Therefore, the counter can cause an early overflow condition with values loaded into the register.

Bus: RootBusDevice: 1Function: 0Offset: 480h Bus: RootBusDevice: 2Function: 0Offset: 480h

Bit Attr Default Description

31:0 RW-V 00000000h PM_data_counter_low_value Low order bits [31:0] for PM data counter[1:0].

6.1.147 XPPMDL1: XP PM Data Low Bits

Bus: RootBusDevice: 1Function: 0Offset: 484h Bus: RootBusDevice: 2Function: 0Offset: 484h

Bit Attr Default Description

31:0 RW-V 0000000 PM_data_counter_low_value 0h Low order bits [31:0] for PM data counter[1:0].

6.1.148 XPPMCL0: XP PM Compare Low Bits

The value of PMD is compared to the value of PMC. If PMD is greater than PMC, this status is reflected in the PERFCON register and/or on the GE[3:0] (TBD) as selected in the Event Status Output field of the PMR register.

Bus: RootBusDevice: 1Function: 0Offset: 488h Bus: RootBusDevice: 2Function: 0Offset: 488h

Bit Attr Default Description

31:0 RW-V FFFFFFFFh PM_compare_low_value Low order bits [31:0] for PM compare register [1:0].

6.1.149 XPPMCL1: XP PM Compare Low Bits

Bus: RootBusDevice: 1Function: 0Offset: 48Ch Bus: RootBusDevice: 2Function: 0Offset: 48Ch

Bit Attr Default Description

31:0 RW-V FFFFFFF PM_compare_low_value Fh Low order bits [31:0] for PM compare register [1:0].

6.1.150 XPPMDH: XP PM Data High Bits

This register contains the high nibbles from each of the PMD 36-bit counter register.

216 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 490h Bus: RootBusDevice: 2Function: 0Offset: 490h

Bit Attr Default Description

15:12 RV 0 Reserved

11:8 RW-V 0h High_Nibble_PEX_Counter1_value High order bits [35:32] of the 36-bit PM Data1 register.

7:4 RV 0 Reserved

3:0 RW-V 0h High_Nibble_PEX_Counter0_value High order bits [35:32] of the 36-bit PM Data0 register.

6.1.151 XPPMCH: XP PM Compare High Bits

This register contains the high nibbles from each of the PMC 36-bit compare registers.

Bus: RootBusDevice: 1Function: 0Offset: 492h Bus: RootBusDevice: 2Function: 0Offset: 492h

Bit Attr Default Description

15:12 RV 0 Reserved

11:8 RW-V Fh High_Nibble_PEX_Compare1_value High order bits [35:32] of the 36-bit PM Compare1 register.

7:4 RV 0 Reserved

3:0 RW-V Fh High_Nibble_PEX_Compare0_value High order bits [35:32] of the 36-bit PM Compare0 register.

6.1.152 XPPMR0: XP PM Response Control

The PMR register controls operation of its associated counter, and provides overflow or max compare status information.

Bus: RootBusDevice: 1Function: 0Offset: 494h Bus: RootBusDevice: 2Function: 0Offset: 494h

Bit Attr Default Description

31 RV 0 Reserved

30 RW 0b Not_greater_than_comparison 0: PMC will compare a greater than function. When clear the perfmon status will assert when the PMD is greater than the PMC. 1: PMC will compare with NOT (greater than) function. When set the perfmon status will assert when the PMD is less than or equal to the PMC.

29 RW 0b Force_PMD_counter_to_add_zero_to_input This feature is used with the queue measurement bus. When this bit is set the value on the queue measurement bus is added to zero so the result in PMD will always reflect the value from the queue measurement bus.0: Do not add zero. Normal PerfMon operation. 1: Add zero with input queue bus.

28 RW 0b Latched_Count_Enable_Select 0: Normal PM operation. Use CENS as count enable. 1: Use Latched count enable from queue empty events

27 RW 0b Reset_Pulse_Enable Setting this bit will select a pulsed version of the reset signal source in the reset block. 0: Normal reset signaling 1: Select a pulsed reset from the reset signal sources.

26:24 RV 0 Reserved

Intel® Xeon Phi™ Processor 217 Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 494h Bus: RootBusDevice: 2Function: 0Offset: 494h

Bit Attr Default Description

23:22 RW 00b DFX_Byte_Lane_Selection_for_PerfMon This bit field is only active when LDES is asserted. These bits select which set of 3 byte lanes from the 72 bit (9 byte lane) local debug bus is active for DFx event counting with the PerfMons. However, for proper PM counting all 72 cluster debug signals for X16 configuration in the PXP unit, Global Event selector logic is to be used based on design. 00: Local Debug Byte Lanes 0-2 01: Local Debug Byte Lanes 3-5 10: Local Debug Byte Lanes 6-8 11: Reserved

21 RW 0b Local_DFT_Event_Select This selection enables the local debug bus to be selected for event counting. Use xxxPMDFXMAT and xxxPMDFXMSK registers for the 24-bit match of the local debug bus. For cluster debug bus signals being properly counted in DMI, PXP1 and PXP2, they need to be routed via programming to Global Event selector logic and count as the Global Events per design. 0: Disable DFx event monitoring 1: Enable DFx event monitoring

20:19 RW 00b Event_Group_Selection Selects which event register to use for performance monitoring. 00: Bus events (XPMEVL,H register) and also Resource Utilizations (XP_PMER Registers) when all XP_PMEH and XP_PMEL Registers are set to '0'. that is, When monitoring PMER events, all PMEV events are to be deselected; when monitoring PMEV events, all PMER events are to be deselected. 01: Reserved 10: Queue measurement (in the XPPMER register). Note: To enable FIFO queue histogramming write bit field CNTMD ='11' and select queues in the XPPMER register. 11: Reserved

18:17 RW 00b Count_Event_Select Selects the condition for incrementing the performance monitor counter. 00: Event source selected by PMEVL,H 01: Partner event status (max compare or overflow) 10: All clocks when enabled 11: Reserved

16 RW 0b Event_Polarity_Invert This bit inverts the polarity of the conditioned event signal. 0: No inversion 1: Invert the polarity of the conditioned event signal

15:14 RW 00b Count_Mode This field sets how the events will be counted. 00: Count clocks when event is logic high. Counting is level sensitive, whenever the event is logic 1 the counter is enabled to count. 01: Count rising edge events. Active low signals should be inverted with EVPOLINV for correct measurements. 10: Latch event and count clocks continuously. After the event is asserted, latch this state and count clocks continuously. The latched state of this condition is cleared by xxxPMRx.CNTRST bit, or PERFCON.GBRST, or GE[3:0]. 11: Enable FIFO (push/pop) queue histogram measurement. This mode will enable histogram measurements on PM0. This mode enable logic to perform the function listed in the table below. The measurement cycle will not begin until the Qempty signal is asserted. Refer to xref. FIFO queue histogram table FIFOn_Push...... FIFOn_POP...... PMD Adder control ....0...... 0...... Add zero ....1...... 0...... Add queue bus value ....0...... 1...... Sub queue bus value ....1...... 1...... Add zero The latched condition of the Qempty signal cannot be cleared by PMR.CLREVLAT. A new measurement cycle requires clearing all counters and the latched value by asserting either PMRx.CNTRST or PERFCON.GBRST.

218 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 494h Bus: RootBusDevice: 2Function: 0Offset: 494h

Bit Attr Default Description

13:11 RW 000b Counter_enable_source These bits identify which input enables the counter. Default value disables counting. 000: Disabled 001: Local Count Enabled (LCEN). This bit is always a 1. 010: Partner counter's event status (max compare or overflow) 011: Reserved 100: GE[0], from the Global Debug Event Block 101: GE[1], from the Global Debug Event Block 110: GE[2], from the Global Debug Event Block 111: GE[3], from the Global Debug Event Block Note: Address/Header MatchOut signal must align with PMEVL,H events for this to be effective.

10:8 RW 000b Reset_Event_Select Counter and event status will reset and counting will continue. 000: No reset condition 001: Partner's event status: When the partner counter causes an event status condition to be activated, either by a counter overflow or max comparison, then this counter will reset and continue counting. 010: Partners PME register event: When the partner counter detects a match condition which meets its selected PME register qualifications, then this counter will reset and continue counting. 011: This PM counter's status output. 100: GE[0], from the Global Debug Event Block. 101: GE[1], from the Global Debug Event Block. 110: GE[2], from the Global Debug Event Block. 111: GE[3], from the Global Debug Event Block.

7:6 RW 00b Compare_Mode This field defines how the PMC (compare) register is to be used. 00: compare mode disabled (PMC register not used) 01: max compare only: The PMC register value is compared with the counter value. If the counter value is greater then the Compare Status (CMPSTAT) will be set. 10: max compare with update of PMC at end of sample: The PMC register value is compared with the counter value, and if the counter value is greater, the PMC register is updated with the counter value. Note, the Compare Status field is not affected in this mode. 11: Reserved

5 RW 0b PM_Status_Signal_Output 0: Level output from status/overflow signals. 1: Pulsed output from status/overflow signals.

4:3 RW 00b PerfMon_Trigger_Output This field selects what the signal is communicated to the chip's event logic structure. 00: No cluster trigger output from PerfMons or header match. 01: PM Status. 10: PM Event Detection. 11: Reserved

2RW1C0bCompare_Status This status bit captures a count compare event. The Compare Status field can be programmed to allow this bit to be driven to Global Event (GE[3:0]) signals which will then distribute the event to the debug logic. 0: no event 1: count compare - PMD counter greater than PMC register when in compare mode. This bit remains set once an event is reported even though the original condition is no longer valid. Writing a logic '1' clears the bit.

1RW1C0bOverflow_Status_Bit This status bit captures the overflow event from the PMD counter. This bit remains set once an event is reported even though the original condition is no longer valid. Writing a logic '1' clears the bit.

0 RW 0b Counter_Reset Setting this bit resets the PMD counter, the associated adder storage register and the count mode state latch (see bits CNTMD) to the default state. It does not change the state of this PMR register, the event selections, or the value in the compare register. Note: This bit must be cleared by software, otherwise the counters remain in reset. There is also a reset bit in the PERFCON register which clears all PM registers including the PMR.

Intel® Xeon Phi™ Processor 219 Datasheet - Volume 2, December 2016 6.1.153 XPPMR1: XP PM Response Control

The PMR register controls operation of its associated counter, and provides overflow or max compare status information.

Bus: RootBusDevice: 1Function: 0Offset: 498h Bus: RootBusDevice: 2Function: 0Offset: 498h

Bit Attr Default Description

31 RV 0 Reserved

28 RW 0b Latched_Count_Enable_Select 0: Normal PM operation. Use CENS as count enable. 1: Use Latched count enable from queue empty events

26:24 RV 0 Reserved

220 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 498h Bus: RootBusDevice: 2Function: 0Offset: 498h

Bit Attr Default Description

16 RW 0b Event_Polarity_Invert This bit inverts the polarity of the conditioned event signal. 0: No inversion 1: Invert the polarity of the conditioned event signal

5 RW 0b PM_Status_Signal_Output 0: Level output from status/overflow signals. 1: Pulsed output from status/overflow signals.

Intel® Xeon Phi™ Processor 221 Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 498h Bus: RootBusDevice: 2Function: 0Offset: 498h

Bit Attr Default Description

4:3 RW 00b CTO This field selects what the signal is communicated to the chip's event logic structure. 00: No cluster trigger output from PerfMons or header match. 01: PM Status. 10: PM Event Detection. 11: Reserved

2 RW1C 0b Compare_Status This status bit captures a count compare event. The Compare Status field can be programmed to allow this bit to be driven to Global Event (GE[3:0]) signals which will then distribute the event to the debug logic. 0: no event 1: count compare - PMD counter greater than PMC register when in compare mode. This bit remains set once an event is reported even though the original condition is no longer valid. Writing a logic '1' clears the bit.

1 RW1C 0b Overflow_Status_Bit This status bit captures the overflow event from the PMD counter. This bit remains set once an event is reported even though the original condition is no longer valid. Writing a logic '1' clears the bit.

6.1.154 XPPMEVL0: XP PM Events Low

Selections in this register correspond to fields within the PCIe header. Each field selection is logically combined according to the match equation. The qualifications for fields in this register are listed below. It should be noted that the bit selections are generic for packet and for either inbound or outbound direction. Because of this, there will be bit fields that do not make sense. For these packet matching situations the user should select Either which acts as a dont care for the match equation PCIe PerfMon Match Equation PMEV Match = ((IO_Cfg_Write_event + IO_Cfg_Read_event _+ Mem_Write_event + Mem_Read_event + Trusted_write_event + Trusted_read_event + General_event) & INOUTBND) + GESEL IO_Cfg_Write_event = (REQCMP[0] & CMPR[1] & RDWR[1] & DATALEN & (TTYP[2] + (TTYP[1] & CFGTYP))) IO_Cfg_Read_event = (REQCMP[0] & CMPR[1] & RDWR[0] & DATALEN & (TTYP[2] + (FMTTYP[1] & CFGTYP))) Mem_Write_event = (REQCMP[0] & CMPR[0] & RDWR[1] & DATALEN & TTYP[3] & LOCK & EXTADDR & SNATTR) Note: An outbound memory write does not have a snoop attribute as an inbound memory write has. So the user should set SNATTR=11 for outbound memory write transaction event counting. Mem_Read_event = (REQCMP[0] & CMPR[1] & RDWR[0] & DATALEN & ((TTYP[3] & LOCK & EXTADDR & SNATTR) + TTYP[2] + (TTYP[1]&

Note: CFGTYP))) For outbound memory reads there is no concept of issuing a snoop cycle. The user should select SNATTR=11 for either snoop attribute. Msg_event = (TTYP[0] & DND) (INOUTBND[0] & (MatchEq) + (IOBND[1] & (MatchEq) Setting both bits in INOUTBND is acceptable however the performance data gathered will not be accurate since once one header can be counted at a time.

222 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 49Ch Bus: Root BusDevice: 2Function: 0Offset: 49Ch

Bit Attr Default Description

31:30 RW 00b Data_or_no_data_attribute x1: Request/completion/message with data 1x: Request/completion/message packet without data

29:28 RW 00b Snoop_Attribute x1: No snoop required 1x: Snoop required 11: Either

27:26 RW 00b Request_or_Completion_Packet_Selection x1: Request packet 1x: Completion packet 11: Either

25:24 RW 00b Read_or_Write_Selection x1: Read 1x: Write 11: Either

23:22 RW 00b Request_packet_only Completion Required x1: No Completion Required 1x: Completion Required 11: Either

21:20 RW 00b Lock_Attribute_Selection x1: No Lock 1x: Lock 11: Either

19:18 RW 00b Extended_Addressing_Header x1: 32b addressing 1x: 64b addressing 11: Either

17:16 RW 00b CFGTYP Config Type x1: Type 0 1x: Type 1 11: Either

15:11 RW 00b FMTTYP Format Type Field 1_xxxx: Trusted x_1xxx: Memory x_x1xx: IO x_xx1x: Configuration x_xxx1: Messages 1_1111: Any transaction type

10:4 RW 00b Data_Length 1xx_xxxx: (129 to 256 bytes) x1x_xxxx: (65 to 128 bytes) xx1_xxxx: (33 to 64 bytes) xxx_1xxx: (17 to 32 bytes) xxx_x1xx: (9 to 16 bytes) xxx_xx1x: (0 to 8 bytes) xxx_xxx1: 0 bytes, used for a special zero length encoded packets 111_1111: Any Data length

3:0 RW 00b for_Completion_Packet_or_message_encoding_for_Request_Packet 1xxx: Completer abort x1xx: Configuration request retry status (only used for inbound completions) xx1x: Unsupported request xxx1: Successful completion 1111: Any status The completion feature is not supported (HSD bug2345906). This field should not be used by software (reserved): write 0 always, read return random.

6.1.155 XPPMEVL1: XP PM Events Low

Intel® Xeon Phi™ Processor 223 Datasheet - Volume 2, December 2016 will be bit fields that do not make sense. For these packet matching situations the user should select Either which acts as a dont care for the match equation PCIe PerfMon Match Equation PMEV Match = ((IO_Cfg_Write_event + IO_Cfg_Read_event _+ Mem_Write_event + Mem_Read_event + Trusted_write_event + Trusted_read_event + General_event) & INOUTBND) + GESEL IO_Cfg_Write_event = (REQCMP[0] & CMPR[1] & RDWR[1] & DATALEN & (TTYP[2] + (TTYP[1] & CFGTYP))) IO_Cfg_Read_event = (REQCMP[0] & CMPR[1] & RDWR[0] & DATALEN & (TTYP[2] + (FMTTYP[1] & CFGTYP))) Mem_Write_event = (REQCMP[0] & CMPR[0] & RDWR[1] & DATALEN & TTYP[3] & LOCK & EXTADDR & SNATTR) Note: An outbound memory write does not have a snoop attribute as an inbound memory write has. So the user should set SNATTR=11 for outbound memory write transaction event counting. Mem_Read_event = (REQCMP[0] & CMPR[1] & RDWR[0] & DATALEN & ((TTYP[3] & LOCK & EXTADDR & SNATTR) + TTYP[2] + (TTYP[1] &

Bus: RootBusDevice: 1Function: 0Offset: 4A0h Bus: RootBusDevice: 2Function: 0Offset: 4A0h

Bit Attr Default Description

31:30 RW 00b Data_or_no_data_attribute x1: Request/completion/message with data 1x: Request/completion/message packet without data

29:28 RW 00b Snoop_Attribute x1: No snoop required 1x: Snoop required 11: Either

27:26 RW 00b Request_or_Completion_Packet_Selection x1: Request packet 1x: Completion packet 11: Either

25:24 RW 00b Read_or_Write_Selection x1: Read 1x: Write 11: Either

23:22 RW 00b CMPREQ Completion Required x1: No Completion Required 1x: Completion Required 11: Either

21:20 RW 00b Lock_Attribute_Selection x1: No Lock 1x: Lock 11: Either

19:18 RW 00b Extended_Addressing_Header x1: 32b addressing 1x: 64b addressing 11: Either

17:16 RW 00b CFGTYP Config Type x1: Type 0 1x: Type 1 11: Either

15:11 RW 00b FMTTYP Format Type Field 1_xxxx: Trusted x_1xxx: Memory x_x1xx: IO x_xx1x: Configuration x_xxx1: Messages 1_1111: Any transaction type

224 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 4A0h Bus: RootBusDevice: 2Function: 0Offset: 4A0h

Bit Attr Default Description

3:0 RW 00b for_Completion_Packet_or_message_encoding_for_Requ est_Packet 1xxx: Completer abort x1xx: Configuration request retry status (only used for inbound completions) xx1x: Unsupported request xxx1: Successful completion 1111: Any status The completion feature is not supported (HSD bug2345906). This field should not be used by software (reserved): write 0 always, read return random.

6.1.155.1 XPPMEVH0: XP PM Events High

Selections in this register correspond to fields within the PEX packet header. Each field selection is ANDed with all other fields in this register including the XPPMEVL except for the Global Event signals. These signals are ORed with any event in the XPPMEVL and enables for debug operations requiring the accumulation of specific debug signals.The qualifications for fields in this register are as follows:

Bus: RootBusDevice: 1Function: 0Offset: 4A4h Bus: RootBusDevice: 2Function: 0Offset: 4A4h

Bit Attr Default Description

31:8 RV 0 Reserved

7:2 RW 00h Global_Event_Selection Selects which GE[3:0] is used for event counting. This field is OR'd with other fields in this register. The GEs cannot be qualified with other PerfMon signals. If more than 1 GE is selected then the resultant event is the OR between each GE. However, properly counting Global Event based on design, XP PM Response Control Register bit [13:11] CENS must be set to choose GE[3:0] and also bit[18:17] CNTEVSEL must be set to 2'b10. 1x_xxxx: GE[5] x1_xxxx: GE[4] xx_1xxx: GE[3] xx_x1xx: GE[2] xx_xx1x: GE[1] xx_xxx1: GE[0]

1:0 RW 00b Inbound_or_Outbound_Selection Selects which path to count transactions. 1x: Outbound x1: Inbound (from PCI bus) 11: Either

6.1.156 XPPMEVH1: XP PM Events High

Bus: RootBusDevice: 1Function: 0Offset: 4A8h Bus: RootBusDevice: 2Function: 0Offset: 4A8h

Bit Attr Default Description

31:8 RV 0 Reserved

Intel® Xeon Phi™ Processor 225 Datasheet - Volume 2, December 2016 Bus: RootBusDevice: 1Function: 0Offset: 4A8h Bus: RootBusDevice: 2Function: 0Offset: 4A8h

Bit Attr Default Description

1:0 RW 00b Inbound_or_Outbound_Selection Selects which path to count transactions. 1x: Outbound x1: Inbound (from PCI bus) 11: Either

6.1.157 XPPMER0: XP PM Resource Events

This register is used to select queuing structures for measurement. Use of this event register is mutually exclusive with the XPPMEVL,H registers. The Event Register Select field in the PMR register must select this register for to enable monitoring operations of the queues.

Bus: RootBusDevice: 1Function: 0Offset: 4ACh Bus: RootBusDevice: 2Function: 0Offset: 4ACh

Bit Attr Default Description

31:21 RV 0 Reserved

20:17 RW 0h XP_Resource_Assignment This selects which PCI-Express links are being monitored. A logic 1 selects that PCIe link for monitoring. 1000: Select NA / PXP6 / PXP10 (depending on device number) for monitoring. 0100: Select PXP2 / PXP5 / PXP9 (depending on device number) for monitoring. 0010: Select PXP1 / PXP4 / PXP8 (depending on device number) for monitoring. 0001: Select PXP / PXP3 / PXP7 (depending on device number) for monitoring.

16:13 RW 0h Link_Send_Utilization This level signal that is active when the link could send a packet or an idle. The choices are a logic idle flit, a link layer packet, or a transaction layer packet. The user can count the number of clocks that the link is not active by inverting this signal in the event conditioning logic (PMR.EVPOLINV = 1). The selection listed combines all the links for clarity. If the user is operating on XP3 then the bit field selects Links[6:3] only. 0000: No event selected 1000: Link 6 (xp3), link 10 (xp7), reserved, reserved 0100: Link 5 (xp3), link 9 (xp7), reserved, reserved 0010: Link 4 (xp3), link 8 (xp7), port 2 (xp0), reserved 0001: Link 3 (xp3), link 7 (xp7), link 1 (xp0), link 0 (xp0 -DMI)

10:8 RV 0h rsvd_tgiopmer0_10_8 Bits[10:8] is defined as PSHPOPQSEL[2:0] :PSHPOPQSEL: Push/Pop Queue Select (TBD) 0000: No queue selected 0001: TBD 0010 - 1111: Reserved

7:6 RW 00b flowcntrclass

5:0 RW 00h QBUSSEL Queue Measurement Bus Select: This field selects a queue to monitor. These queues are connected the QueueMeasBus that is derived from the difference in the write and read pointers. 000000: No queues selected --- 010001: xp0, xp3, xp7 - Inbound data payload 010010: xp1, xp4, xp8 - Inbound data payload 010100: xp2, xp5, xp9 - Inbound data payload 011000: NA, xp6, xp10 - Inbound data payload 100001: xp0, xp3, xp7 - Outbound data payload 100010: xp1, xp4, xp8 - Outbound data payload 100100: xp2, xp5, xp9 - Outbound data payload 101000: NA, xp6, xp10 - Outbound data payload others: reserved NA: not applicable.

226 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 6.1.158 XPPMER1: XP PM Resource Events

Bus: RootBusDevice: 1Function: 0Offset: 4B0h Bus: RootBusDevice: 2Function: 0Offset: 4B0h

Bit Attr Default Description

31:21 RV 0 Reserved

10:8 RV 0h rsvd_tgiopmer1_10_8 Bits[10:8] is defined as PSHPOPQSEL[2:0] :PSHPOPQSEL: Push/Pop Queue Select (TBD) 0000: No queue selected 0001: TBD 0010 - 1111: Reserved

7:6 RW 00b flowcntrclass

6.1.159 PLSR0: Poison Logging/Status 0

Bus: RootBus Device: 0Function: 2-3 Offset: 4B4h Bus: RootBus Device: 1Function: 0-3 Offset: 4B4h Bus: RootBus Device: 2Function: 0-3 Offset: 4B4h

Bit Attr Default Description

31 RWS_ 0b Poison_Log_En L This bit indicates if the shadow logging is enabled or disabled. A value of 0 is disabled and a value of 1 is enabled. If not enabled no logging takes place in this register.

30 RW1C 0b Poison_Log_Valid S_LBV If Valid=0, the log does not contain any valid information. If Valid=1, the log contain valid information. Any additional ring poison detection events will set overflow bit.

Intel® Xeon Phi™ Processor 227 Datasheet - Volume 2, December 2016 Bus: RootBus Device: 0Function: 2-3 Offset: 4B4h Bus: RootBus Device: 1Function: 0-3 Offset: 4B4h Bus: RootBus Device: 2Function: 0-3 Offset: 4B4h

Bit Attr Default Description

29 RW1C 0b Poison_Log_Overflow S_LBV Poison detection event was observed when valid=1. In this case, the register will retain the information about the first error. This is consistent with UCNA/UCNA overwrite rules in Machine Check Architecture.

28 RW1C 0b Poison_Log_Addr_Vld S_LBV If this bit is set then it indicates that the address logged in the plsr1 and plsr2 is valid.

27:18 ROS-V 000h Poison_Log_Len Requestor Length

17:2 ROS-V 0000h Poison_Log_RID Requestor ID

1:0 ROS-V 00b Poison_Log_Type 00: IIO generated inbound poison 01: Inbound from PCIe 10: Poison coming from ring 11: IIO generated outbound poison

6.1.160 PLSR1: Poison Logging/Status 1

Bus: RootBus Device: 0Function: 2-3 Offset: 4B8h Bus: RootBus Device: 1Function: 0-3 Offset: 4B8h Bus: RootBus Device: 2Function: 0-3 Offset: 4B8h

Bit Attr Default Description

31:0 ROS-V 0 Poison_Log_Addr_Lo Address 31:0 associated with the poison data (e.g. Address field in poisoned BL packet).

6.1.161 PLSR2: Poison Logging/Status 2

Bus: RootBus Device: 0Function: 2-3 Offset: 4BCh Bus: RootBus Device: 1Function: 0-3 Offset: 4BCh Bus: RootBus Device: 2Function: 0-3 Offset: 4BCh

Bit Attr Default Description

31:0 ROS-V 0 Poison_Log_Addr_Hi Address 63:32 associated with the poison data

228 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7 Memory Map/Intel® Virtualization Technology for Directed I/O Registers

7.1 Memory Map and Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)

7.2 Configuration Registers

The memory map registers contain the address decode for inbound traffic. The Intel VT-d registers contain the virtualization translation logic.

This is a summary of the components of the Memory Map and Intel VT-d Configuration Registers: • Standard PCI Type 0 Header • PCIe Capability Structure to allow Extended 4k Configuration Space • Memory Mapping Registers • Protection Range Registers • Intel VT-d Registers

Intel® Xeon Phi™ Processor 229 Datasheet - Volume 2, December 2016 Figure 7-1. Memory Map and Intel VT-d Configuration Register Map Offset 0x00 - 0x1FF

230 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Figure 7-2. Memory Map and Intel VT-d Register Map Offset 0x200 - 0x3FF

7.2.1 VID: Vendor ID

Bus: RootBus0Device: 5Function: 0Offset: 0h

Bit Attr Default Description

15:0 RO 8086h Vendor_Identification_Number The value is assigned by PCI-SIG to Intel.

7.2.2 DID: Device ID

Bus: RootBus0Device: 5Function: 0Offset: 2h

Bit Attr Default Description

15:0 RO 7810h Device_Identification_Number The DID value for Device 5 Function 0 MMAP/Intel VT-d function

Intel® Xeon Phi™ Processor 231 Datasheet - Volume 2, December 2016 7.2.3 PCICMD: PCI Command

Bus: RootBus0Device: 5Function: 0Offset: 4h

Bit Attr Default Description

15:11 RV 00h Reserved

10 RO 0h Interrupt_Disable N/A for these devices

9 RO 0h Fast_Back_To_Back_Enable Not applicable to PCI Express and is hardwired to 0

8 RO 0h SERRE This bit has no impact on error reporting from these devices

7 RO 0h IDSEL_Stepping_Wait_Cycle_Control Not applicable to internal devices. Hardwired to 0.

6 RO 0h PERRE This bit has no impact on error reporting from these devices

5 RO 0h VGA_Palette_Snoop_Enable Not applicable to internal devices. Hardwired to 0.

4RO0hMWIE Not applicable to internal devices. Hardwired to 0.

3RO0hSCE Not applicable to internal devices. Hardwired to 0.

2RO0hBME Hardwired to 0 since these devices don't generate any transactions

1RO0hMSE Hardwired to 0 since these devices don't decode any memory BARs

0RO0hIOSE Hardwired to 0 since these devices don't decode any IO BARs

7.2.4 PCISTS: PCI Status

Bus: RootBus0Device: 5Function: 0Offset: 6h

15 RO 0h DPE Hardwired to 0

14 RO 0h SSE Hardwired to 0

13 RO 0h RMA Hardwired to 0

12 RO 0h RTA Hardwired to 0

11 RO 0h STA Hardwired to 0

10:9 RO 0h DEVSEL_Timing Not applicable to PCI Express. Hardwired to 0.

8RO0hMDPE Hardwired to 0

7 RO 0h Fast_Back_To_Back Not applicable to PCI Express. Hardwired to 0.

6 RV 0h Reserved

232 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Bus: RootBus0Device: 5Function: 0Offset: 6h

5 RO 0b pci66MHz_capable Not applicable to PCI Express. Hardwired to 0.

4 RO 1b Capabilities_List This bit indicates the presence of a capabilities list structure

3RO0bINTx_Status Hardwired to 0

2:0 RV 0h Reserved

7.2.5 RID: RID

Bus: RootBus0Device: 5Function: 0Offset: 8h

Bit Attr Default Description

7:0 RO-V 00h Revision_ID Reflects the Uncore Revision ID after reset. Reflects the Compatibility Revision ID after BIOS writes 0x69 to this register.

7.2.6 CCR: Class Code Register

Bus: RootBus0Device: 5Function: 0Offset: 9h

Bit Attr Default Description

23:16 RO 08h Base_Class Set to 08h for Generic Device

15:8 RO 80h Sub_Class Set to 80h for Generic Device

7:0 RO 00h Interface Register Level Programming Interface. Set to 0 for all non- APIC devices.

7.2.7 CLSR: Cacheline Size Register

Bus: RootBus0Device: 5Function: 0Offset: Ch

Bit Attr Default Description

7:0 RW 00h Cacheline_Size This register is set as RW for compatibility reasons only. Cacheline size is 64B.

7.2.8 HDR: Header Type

Bus: RootBus0Device: 5Function: 0 Offset: Eh

Bit Attr Default Description

7 RO 1b Multi_function_Device Set to 1b to indicate functions 1-7 may exist for the device

6:0 RO 00h Configuration_Layout This field identifies the format of the configuration header layout. It is Type 0 for all these devices. The default is 00h, indicating a 'endpoint device'.

Intel® Xeon Phi™ Processor 233 Datasheet - Volume 2, December 2016 7.2.9 SVID: Subsystem Vendor ID

Bus: RootBus0Device: 5Function: 0Offset: 2Ch

Bit Attr Default Description

15:0 RW-O 8086h Subsystem_Vendor_ID The default value specifies Intel but can be set to any value once after reset.

7.2.10 SSID: Subsystem ID

Bus: RootBus0Device: 5Function: 0Offset: 2Eh

Bit Attr Default Description

15:0 RW-O 0000h Subsystem_ ID The default value specifies Intel but can be set to any value once after reset.

7.2.11 CAPPTR: Capability Pointer

Bus: RootBus0Device: 5Function: 0Offset: 34h

Bit Attr Default Description

7:0 RO 40h Capability_Pointer Points to the first capability structure for the device which is the PCIe capability (for devices that support 4kB extended configuration space). A value of zero indicates there are no capability structures (and no extended configuration space).

7.2.12 INTL: Interrupt Line Register

us: RootBus0Device: 5Function: 0Offset: 3Ch

Bit Attr Default Description

7:0 RO 00h Interrupt_Line N/A for these devices.

7.2.13 INTPIN: Interrupt Pin Register

Bus: RootBus0Device: 5Function: 0Offset: 3Dh

Bit Attr Default Description

7:0 RO 00h INTP Interrupt Pin N/A since these devices do not generate any interrupt on their own

234 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.2.14 PXPCAPID: PCI Express Capability Identity

Bus: RootBus0Device: 5Function: 0Offset: 40h

Bit Attr Default Description

7:0 RO 10h Capability_ID Identifies the PCI Express capability assigned by PCI-SIG.

7.2.15 PXPNXTPTR: PCI Express Next Pointer

Bus: RootBus0Device: 5Function: 0Offset: 41h

Bit Attr Default Description

7:0 RO 00h Next_Ptr Pointer to the next capability. This field is set to the PCI PM capability.

7.2.16 PXPCAP: PCI Express Capability

Bus: RootBus0Device: 5Function: 0Offset: 42h

Bit Attr Default Description

15:14 RV 0 Reserved

13:9 RO 00h Interrupt_Message_Number Not valid for this device, since the device does not generate interrupts

8 RO 0b Slot_Implemented Applies only to the root ports. 1: indicates that the PCI Express link associated with the port is connected to a slot. 0: indicates no slot is connected to this port. Notes: This register is set by BIOS N/A in DMI Mode

7:4 RO 9h Device_Port_Type This field identifies the type of device. It is set to 4h while in PCIe mode and 9h indicating Root Complex Integrated Endpoint while in DMI mode

3:0 RO 2h Capability_Version PCI Express Capability is Compliant with Version 2.0 of the PCI Express Spec.

Intel® Xeon Phi™ Processor 235 Datasheet - Volume 2, December 2016 7.3 Intel VT-d VTBAR Memory Mapped Registers

Figure 7-3. Intel VT-d Memory Register Map Offset 0x00 - 0x20B

236 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Figure 7-4. Intel VT-d Memory Register Map Offset 0x1000 - 0x120B

7.3.1 VTD0_VERSION: Version Number

Base: VT_BAROffset: 0h

Bit Attr Default Description

31:8 RV 0 Reserved

7:4 RO 1h Major_Revision

3:0 RO 0h Minor_Revision

Intel® Xeon Phi™ Processor 237 Datasheet - Volume 2, December 2016 7.3.2 VTD0_CAP: VT-d Capabilities

Base: VT_BAROffset: 8h

Bit Attr Default Description

63:56 RV 0 Reserved

55 RO 1b DMA_Read_Draining IIO supports hardware based draining

54 RO 1b DMA_Write_Draining IIO supports hardware based write draining

53:48 RO 12h MAMV IIO support MAMV value of 12h (up to 1G super pages).

47:40 RO 07h Number_of_Fault_Recording_Registers IIO supports 8 fault recording registers

39 RO 1b Page_Selective_Invalidation Supported in IIO

38 RV 0 Reserved

37:34 RW-O 3h Super_Page_Support 2MB, 1G supported.

33:24 RO 10h Fault_Recording_Register_Offset Fault registers are at offset 100h

23 RO 0b Spatial_Separation ISOCH Remapping Engine has ISOCH Support. Note: This bit used to be for “Spatial Separation”. This is no longer the case.

22 RO 1b ZLR Zero-length DMA requests to write-only pages supported.

21:16 RO-V 2Fh MGAW This register is set by hardware based on the setting of the GPA_LIMIT register. The value is the same for both the Azalia and non-Azalia engines (unlike TBG). This is because the translation for Azalia has been extended to be 4-level (instead of 3).

15:13 RV 0 Reserved

12:8 RO 04h SAGAW Supports 4-level walk on both Azalia and non-azalia engines.

7RO0bTCM IIO does not cache invalid pages. This bit should always be set to 0 on HW. It can be set to one when we are doing software virtualization of Intel VT-d.

6RO1bPHMR_Support IIO supports protected high memory range

5RO1bPLMR_Support IIO supports protected low memory range

4RO0bRWBF N/A for IIO

3 RO 0b Advanced_Fault_Logging IIO does not support advanced fault logging

2:0 RO 110b Number_of_Domains_Supported IIO supports 64k domains with 16 bit domain ID

238 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.3 VTD0_EXT_CAP: Extended VT-d Capability

Base: VT_BAROffset: 10h

Bit Attr Default Description

63:24 RV 0 Reserved

23:20 RO Fh Maximum_Handle_Mask_Value IIO supports all 16 bits of handle being masked. Note IIO always performs global interrupt entry invalidation on any interrupt cache invalidation command and h/w never really looks at the mask value.

17:8 RO 20h Invalidation_Unit_Offset IIO has the invalidation registers at offset 200h

7 RO 1b Snoop_Control 1: indicates the hardware supports the 1-setting of the SNP field in the page-table entries. IIO supports snoop override only for the non-isoch VT-d engine

6 RO 1b Pass_through IIO supports pass through.

5 RO 1b Cachin_Hints Reserved.

4 RW-O 1b IA32_Extended_Interrupt_Mode IIO supports the extended interrupt mode

3 RO 1b Interrupt_Remapping_Support IIO supports this

2RW-O1bDevice_TLB_support IIO supports ATS for the non-isoch VT-d engine.

1 RO 1b Queued_Invalidation_support IIO supports this

0 RW-O 0b Coherency_Support BIOS can write to this bit to indicate to hardware to either snoop or not-snoop the DMA/Interrupt table structures in memory (root/context/pd/pt/irt). Note that this bit is expected to be always set to 0 for the Azalia VT-d engine and programmability is only provided for that engine for debug reasons.

7.3.4 VTD0_GLBCMD: Global Command

Base: VT_BAROffset: 18h

Bit Attr Default Description

31 RW 0b Translation_Enable Software writes to this field to request hardware to enable/disable DMA-remapping hardware. 0: Disable DMA-remapping hardware 1: Enable DMA-remapping hardware Hardware reports the status of the translation enable operation through the TES field in the Global Status register. Before enabling (or re-enabling) DMA-remapping hardware through this field, software must: - Setup the DMA-remapping structures in memory - Flush the write buffers (through WBF field), if write buffer flushing is reported as required. - Set the root-entry table pointer in hardware (through SRTP field). - Perform global invalidation of the context-cache and global invalidation of IOTLB - If advanced fault logging supported, setup fault log pointer (through SFL field) and enable advanced fault logging (through EAFL field). There may be active DMA requests in the platform when software updates this field. Hardware must enable or disable remapping logic only at deterministic transaction boundaries, so that any in-flight transaction is either subject to remapping or not at all.

Intel® Xeon Phi™ Processor 239 Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 18h

Bit Attr Default Description

30 RW-V 0b Set_Root_Table_Pointer Software sets this field to set/update the root-entry table pointer used by hardware. The root-entry table pointer is specified through the Root-entry Table Address register.Hardware reports the status of the root table pointer set operation through the RTPS field in the Global Status register. The root table pointer set operation must be performed before enabling or re-enabling (after disabling) DMA remapping hardware. After a root table pointer set operation, software must globally invalidate the context cache followed by global invalidate of IOTLB. This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer, and not any stale cached entries. While DMA-remapping hardware is active, software may update the root table pointer through this field. However, to ensure valid in- flight DMA requests are deterministically remapped, software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer. Clearing this bit has no effect.

29 RO 0b Set_Fault_Log_Pointer N/A to Intel Xeon processor E5 v3 product family

28 RO 0b Enable_Advanced_Fault_Logging N/A to Intel Xeon processor E5 v3 product family

27 RO 0b Write_Buffer_Flush N/A to Intel Xeon processor E5 v3 product family

26 RW 0b Queued_Invalidation_Enable Software writes to this field to enable queued invalidations. 0: Disable queued invalidations. In this case, invalidations must be performed through the Context Command and IOTLB Invalidation Unit registers. 1: Enable use of queued invalidations. Once enabled, all invalidations must be submitted through the invalidation queue and the invalidation registers cannot be used till the translation has been disabled. The invalidation queue address register must be initialized before enabling queued invalidations. Also software must make sure that all invalidations submitted prior via the register interface are all completed before enabling the queued invalidation interface. Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register. Value returned on read of this field is undefined.

25 RW 0b Interrupt_Remapping_Enable 0: Disable Interrupt Remapping Hardware 1: Enable Interrupt Remapping Hardware Hardware reports the status of the interrupt-remap enable operation through the IRES field in the Global Status register. Before enabling (or re-enabling) Interrupt- remapping hardware through this field, software must: - Setup the interrupt-remapping structures in memory - Set the Interrupt Remap table pointer in hardware (through IRTP field). - Perform global invalidation of IOTLB There may be active interrupt requests in the platform when software updates this field. Hardware must enable or disable remapping logic only at deterministic transaction boundaries, so that any in-flight interrupts are either subject to remapping or not at all. IIO must drain any in- flight translated DMA read/write, MSI interrupt requests queued within the root complex before completing the translation enable command and reflecting the status of the command through the IRES field in the GSTS_REG. Value returned on read of this field is undefined.

24 RW-V 0b Set_Interrupt_Remap_Table_Pointer Software sets this field to set/update the interrupt remapping table pointer used by hardware. The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address register.Hardware reports the status of the interrupt remapping table pointer set operation through the IRTPS field in the Global Status register. The interrupt remap table pointer set operation must be performed before enabling or re-enabling (after disabling) interrupt remapping hardware through the IRE field. After an interrupt remap table pointer set operation, software must globally invalidate the interrupt entry cache. This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer, and not any stale cached entries. While interrupt remapping is active, software may update the interrupt remapping table pointer through this field. However, to ensure valid in-flight interrupt requests are deterministically remapped, software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer. Clearing this bit has no effect. IIO hardware internally clears this field before the 'set' operation requested by software has take effect.

240 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 18h

Bit Attr Default Description

23 RW 0b CFI Compatibility Format Interrupt Software writes to this field to enable or disable Compatibility Format interrupts on Intel(R)64 platforms. The value in this field is effective only when interrupt- remapping is enabled and Legacy Interrupt Mode is active. 0: Block Compatibility format interrupts. 1: Process Compatibility format interrupts as pass-through (bypass interrupt remapping). Hardware reports the status of updating this field through the CFIS field in the Global Status register. This field is not implemented on Itanium(TM) platforms.

22:0 RV 0 Reserved

7.3.5 VTD0_GLBSTS: Global Status

Base: VT_BAROffset: 1Ch

Bit Attr Default Description

31 RO-V 0b Translation_Enable_Status When set, indicates that translation hardware is enabled and when clear indicates the translation hardware is not enabled.

30 RO-V 0b Set_Root_Table_Pointer_Status This field indicates the status of the root- table pointer in hardware.This field is cleared by hardware when software sets the SRTP field in the Global Command register. This field is set by hardware when hardware finishes the set root-table pointer operation (by performing an implicit global invalidation of the context-cache and IOTLB, and setting/updating the root-table pointer in hardware with the value provided in the Root-Entry Table Address register).

29 RO 0b Set_Fault_Log_Pointer_Status N/A

28 RO 0b Advanced_Fault_Logging_Status N/A

27 RO 0b Write_Buffer_Flush_Status N/A to Intel Xeon processor E5 v3 product family

26 RO-V 0b Queued_Invalidation_Interface_Status IIO sets this bit once it has completed the software command to enable the queued invalidation interface. Till then this bit is 0.

25 RO-V 0b Interrupt_Remapping_Enable_Status IIO sets this bit once it has completed the software command to enable the interrupt remapping interface. Till then this bit is 0.

24 RO-V 0b Interrupt_Remapping_Table_Pointer_Status This field indicates the status of the interrupt remapping table pointer in hardware. This field is cleared by hardware when software sets the SIRTP field in the Global Command register. This field is set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register.

23 RO-V 0b CFIS Compatibility Format Interrupt Status Compatibility Format Interrupt Status The value reported in this field is applicable only when interrupt-remapping is enabled and Legacy interrupt mode is active. 0: Compatibility format interrupts are blocked. 1: Compatibility format interrupts are processed as pass- through (bypassing interrupt remapping).

22:0 RV 0 Reserved

Intel® Xeon Phi™ Processor 241 Datasheet - Volume 2, December 2016 7.3.6 VTD0_ROOTENTRYADD: Root Entry Table Address

Base: VT_BAROffset: 20h

Bit Attr Default Description

63:12 RW 0 Root_Entry_Table_Base_Address 4K aligned base address for the root entry table. IIO does not utilize bits 63:43 and checks for them to be 0. Software specifies the base address of the root-entry table through this register, and enables it in hardware through the SRTP field in the Global Command register. Reads of this register returns value that was last programmed to it.

11:0 RV 0 Reserved

7.3.7 VTD0_CTXCMD: Context Command

Base: VT_BAROffset: 28h

Bit Attr Default Description

63 RW-V 0b ICC Invalidate Context Entry Cache Software requests invalidation of context-cache by setting this field. Software must also set the requested invalidation granularity by programming the CIRG field. Software must read back and check the ICC field to be clear to confirm the invalidation is complete. Software must not update this register when this field is set. Hardware clears the ICC field to indicate the invalidation request is complete. Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field. Software must not submit another invalidation request through this register while the ICC field is set.Software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this DMA- remapping hardware unit. Since information from the context-cache may be used by hardware to tag IOTLB entries, software must perform domain- selective (or global) invalidation of IOTLB after the context cache invalidation has completed.

62:61 RW 0b CIRG Context Invalidation Request Granularity When requesting hardware to invalidate the context-entry cache (by setting the ICC field), software writes the requested invalidation granularity through this field.Following are the encoding for the 2-bit IRG field. 00: Reserved. Hardware ignores the invalidation request and reports invalidation complete by clearing the ICC field and reporting 00 in the CAIG field. 01: Global Invalidation request. Intel Xeon processor E5 v3 product family supports this. 10: Domain-selective invalidation request. The target domain-id must be specified in the DID field. Intel Xeon processor E5 v3 product family supports this. 11: Device-selective invalidation request. The target SID must be specified in the SID field, and the domain-id (programmed in the context-entry for this device) must be provided in the DID field. Intel Xeon processor E5 v3 product family aliases the h/w behavior for this command to the 'Domain-selective invalidation request'. Hardware indicates completion of the invalidation request by clearing the ICC field. At this time, hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field.

60:59 RO-V 0b CAIG Context Actual Invalidation Granularity Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field). The following are the encoding for the 2-bit CAIG field. 00: Reserved. This is the value on reset. 01: Global Invalidation performed. Intel Xeon processor E5 v3 product family sets this in response to a global invalidation request. 10: Domain-selective invalidation performed using the domain-id that was specified by software in the DID field. Intel Xeon processor E5 v3 product family set this in response to a domain-selective or device-selective invalidation request. 11: Device-selective invalidation. Intel Xeon processor E5 v3 product family never sets this encoding.

242 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 28h

Bit Attr Default Description

58:34 RV 0 Reserved

33:32 RW 00b fm Function Mask Used by IIO when performing device selective invalidation.

31:16 RW 0 Source_ID Used by IIO when performing device selective context cache invalidation.

15:0 RW 0 Domain_ID Indicates the id of the domain whose context-entries needs to be selectively invalidated. S/W needs to program this for both domain and device selective invalidates. IIO ignores bits 15:8 since it supports only a 8 bit Domain ID.

7.3.8 VTD0_FLTSTS: Fault Status

Base: VT_BAROffset: 34h

Bit Attr Default Description

31:16 RV 0 Reserved

15:8 ROS-V 0 Fault_Record_Index This field is valid only when the Primary Fault Pending field is set. This field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the Primary Fault pending field was set by hardware.

7RV0Reserved

6RW1C0 Invalidation_Timeout_Error S Hardware detected a Device-IOTLB invalidation completion time-out. At this time, a fault event may be generated based on the programming of the Fault Event Control register.

5RW1C0 Invalidation_Completion_Error S Hardware received an unexpected or invalid Device-IOTLB invalidation completion. At this time, a fault event is generated based on the programming of the Fault Event Control register.

4RW1C0 Invalidation_Queue_Error S Hardware detected an error associated with the invalidation queue. For example, hardware detected an erroneous or un-supported Invalidation Descriptor in the Invalidation Queue. At this time, a fault event is generated based on the programming of the Fault Event Control register.

3:2 RV 0 Reserved

1 ROS-V 0 Primary_Fault_Pending This field indicates if there are one or more pending faults logged in the fault recording registers. Hardware computes this field as the logical OR of Fault (F) fields across all the fault recording registers of this DMA-remap hardware unit. 0: No pending faults in any of the fault recording registers 1: One or more fault recording registers has pending faults. The fault recording index field is updated by hardware whenever this field is set by hardware. Also, depending on the programming of fault event control register, a fault event is generated when hardware sets this field.

0RW1C0 Primary_Fault_Overflow S Hardware sets this bit to indicate overflow of fault recording registers.

Intel® Xeon Phi™ Processor 243 Datasheet - Volume 2, December 2016 7.3.9 VTD0_FLTEVTCTRL: Fault Event Control

Base: VT_BAROffset: 38h

Bit Attr Default Description

31 RW 1b Interrupt_Message_Mask 1: Hardware is prohibited from issuing interrupt message requests. 0: Software has cleared this bit to indicate interrupt service is available. When a faulting condition is detected, hardware may issue a interrupt request (using the fault event data and fault event address register values) depending on the state of the interrupt mask and interrupt pending bits.

30 RO 0b Interrupt_Pending Hardware sets the IP field whenever it detects an interrupt condition. Interrupt condition is defined as when an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in Fault Status register. - Hardware detected error associated with the Invalidation Queue, setting the IQE field in the Fault Status register. - Hardware detected invalidation completion timeout error, setting the ICT field in the Fault Status register. - If any of the above status fields in the Fault Status register was already set at the time of setting any of these fields, it is not treated as a new interrupt condition. The IP field is kept set by hardware while the interrupt message is held pending. The interrupt message could be held pending due to interrupt mask (IM field) being set, or due to other transient hardware conditions. The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced. This could be due to either (a) Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field. (b) Software servicing all the pending interrupt status fields in the Fault Status register. - PPF field is cleared by hardware when it detects all the Fault Recording registers have Fault (F) field clear. - Other status fields in the Fault Status register is cleared by software writing back the value read from the respective fields.

29:0 RV 0 Reserved

7.3.10 VTD0_FLTEVTDATA: Fault Event Data

Base: VT_BAROffset: 3Ch

Bit Attr Default Description

31:16 RV 0 Reserved

15:0 RW 0 Interrupt_Data

7.3.11 VTD0_FLTEVTADDR: Fault Event Lower Address

Base: VT_BAROffset: 40h

Bit Attr Default Description

31:2 RW 0 MA Message Address (lower) The interrupt address is interpreted as the address of any other interrupt from a PCI Express port.

1:0 RV 0 Reserved

244 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.12 VTD0_FLTEVTUPRADDR: Fault Event Upper Address

Base: VT_BAROffset: 44h

Bit Attr Default Description

31:0 RW 0 MUA Message Upper Address The interrupt address is interpreted as the address of any other interrupt from a PCI Express port.

7.3.13 VTD0_PMEN: Protected Memory Enable

Base: VT_BAROffset: 64h

Bit Attr Default Description

31 RW 0b PROTMEMEN Enable Protected Memory Enable Protected Memory PROT_LOW_BASE/LIMIT and PROT_HIGH_BASE/LIMIT memory regions. Software can use the protected low/high address ranges to protect both the DMA remapping tables and the interrupt remapping tables. There is no separate set of registers provided for each.

30:1 RV 0 Reserved

0RO-V0bPROTREGIONSTS Protected Region Status This bit is set by Intel Xeon processor E5 v3 product family whenever it has completed enabling the protected memory region per the rules stated in the VT-d spec.

7.3.14 VTD0_PROT_LOW_MEM_BASE: Protected Memory Low Base

Base: VT_BAROffset: 68h

Bit Attr Default Description

31:21 RW 000h ADDR Low protected dram region base 16MB aligned base address of the low protected dram region Note that VT-d engine generated reads/writes (page walk, interrupt queue, invalidation queue read, invalidation status) themselves are allowed toward this region, but no DMA accesses (non- translated DMA or ATS translated DMA or pass through DMA that is, no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1), when enabled.

20:0 RV 0 Reserved

Intel® Xeon Phi™ Processor 245 Datasheet - Volume 2, December 2016 7.3.15 VTD0_PROT_LOW_MEM_LIMIT: Protected Memory Low Limit

Base: VT_BAROffset: 6Ch

Bit Attr Default Description

31:21 RW 000h ADDR Low protected dram region 16MB aligned limit address of the low protected dram region Note that VT-d engine generated reads/writes (page walk, interrupt queue, invalidation queue read, invalidation status) themselves are allowed toward this region, but no DMA accesses (non- translated DMA or ATS translated DMA or pass through DMA that is, no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1), when enabled.

20:0 RV 0 Reserved

7.3.16 VTD0_PROT_HIGH_MEM_BASE: Protected Memory High Base

Base: VT_BAROffset: 70h

Bit Attr Default Description

63:21 RW 0 ADDR High protected dram region base 16MB aligned base address of the high protected dram region Note that VT-d engine generated reads/writes (page walk, interrupt queue, invalidation queue read, invalidation status) themselves are allowed toward this region, but no DMA accesses (non- translated DMA or ATS translated DMA or pass through DMA that is, no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1), when enabled.

20:0 RV 0 Reserved

7.3.17 VTD0_PROT_HIGH_MEM_LIMIT: Protected Memory High Limit

Base: VT_BAROffset: 78h

Bit Attr Default Description

63:21 RW 0 ADDR High protected dram region 16MB aligned limit address of the high protected dram region Note that VT-d engine generated reads/writes (page walk, interrupt queue, invalidation queue read, invalidation status) themselves are allowed toward this region, but no DMA accesses (non- translated DMA or ATS translated DMA or pass through DMA that is, no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1), when enabled.

20:0 RV 0 Reserved

246 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.18 VTD0_INV_QUEUE_HEAD: Invalidation Queue Header Pointer

Base: VT_BAROffset: 80h

Bit Attr Default Description

63:19 RV 0 Reserved

18:4 RO-V 0000h Queue_Head Specifies the offset (128-bit aligned) to the invalidation queue for the command that will be fetched next by hardware. This field is incremented after the command has been fetched successfully and has been verified to be a valid/supported command.

3:0 RV 0 Reserved

7.3.19 VTD0_INV_QUEUE_TAIL: Invalidation Queue Tail Pointer

Base: VT_BAROffset: 88h

Bit Attr Default Description

63:19 RV 0 Reserved

18:4 RW 0000h Queue_Tail Specifies the offset (128-bit aligned) to the invalidation queue for the command that will be written next by software.

3:0 RV 0 Reserved

7.3.20 VTD0_INV_QUEUE_ADD: Invalidation Queue Address

Base: VT_BAROffset: 90h

Bit Attr Default Description

63:12 RW 0 InvReq_Queue_Base_Address Invalidation Request Queue Base Address This field points to the base of size-aligned invalidation request queue.

11:3 RV 0 Reserved

2:0 RW 0h Queue_Size This field specifies the length of the invalidation request queue. The number of entries in the invalidation queue is defined as 2^(X + 8), where X is the value programmed in this field.

7.3.21 VTD0_INV_COMP_STATUS: Invalidation Completion Status

Base: VT_BAROffset: 9Ch

Bit Attr Default Description

31:1 RV 0 Reserved

0RW1C0b Invalidation_Wait_Descriptor_Complete S Indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) field set. Hardware clears this field whenever it is executing a wait descriptor with IF field set and sets this bit when the descriptor is complete.

Intel® Xeon Phi™ Processor 247 Datasheet - Volume 2, December 2016 7.3.22 VTD0_INV_COMP_EVT_CTL: Invalidation Completion Event Control

Base: VT_BAROffset: A0h

Bit Attr Default Description

31 RW 1b inval_nonisoch_msgmsk Interrupt Mask 0: No masking of interrupt. When a invalidation event condition is detected, hardware issues an interrupt message (using the Invalidation Event Data & Invalidation Event Address register values). 1: This is the value on reset. Software may mask interrupt message generation by setting this field. Hardware is prohibited from sending the interrupt message when this field is set.

30 RO 0b Interrupt_Pending Hardware sets the IP field whenever it detects an interrupt condition. Interrupt condition is defined as:- An Invalidation Wait Descriptor with Interrupt Flag (IF) field set completed, setting the IWC field in the Fault Status register. - If the IWC field in the Invalidation Event Status register was already set at the time of setting this field, it is not treated as a new interrupt condition. The IP field is kept set by hardware while the interrupt message is held pending. The interrupt message could be held pending due to interrupt mask (IM field) being set, or due to other transient hardware conditions. The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced. This could be due to either: (a) Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field. (b) Software servicing the IWC field in the Fault Status register.

29:0 RV 0 Reserved

7.3.23 VTD0_INV_COMP_EVT_DATA: Invalidation Completion Event Data

Base: VT_BAROffset: A4h

Bit Attr Default Description

31:16 RV 0 Reserved

15:0 RW 0 Interrupt_Data

7.3.24 VTD0_INV_COMP_EVT_ADDR: Invalidation Completion Event Lower Address

Base: VT_BAROffset: A8h

Bit Attr Default Description

31:2 RW 0 MA Message Address (lower)

1:0 RV 0 Reserved

248 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.25 VTD0_INV_COMP_EVT_UPRADDR: Invalidation Completion Event Upper Address

Base: VT_BAROffset: ACh

Bit Attr Default Description

31:0 RW 0 MUA Message Upper Address

7.3.26 VTD0_INTR_REMAP_TABLE_BASE: Interrupt Remapping Table Base Address

Base: VT_BAROffset: B8h

Bit Attr Default Description

63:12 RW 0 Intr_Remap_Base This field points to the base of page-aligned interrupt remapping table. If the Interrupt Remapping Table is larger than 4KB in size, it must be size-aligned.Reads of this field returns value that was last programmed to it.

11 RW 0b IA32_Extended_Interrupt_Enable 0: IA32 system is operating in legacy IA32 interrupt mode. Hardware interprets only 8-bit APICID in the Interrupt Remapping Table entries. 1: IA32 system is operating in extended IA32 interrupt mode. Hardware interprets 32-bit APICID in the Interrupt Remapping Table entries.

10:4 RV 0 Reserved

3:0 RW 0h Size This field specifies the size of the interrupt remapping table. The number of entries in the interrupt remapping table is 2^(X+1), where X is the value programmed in this field.

7.3.27 VTD0_FLTREC0_GPA: Fault Record

Base: VT_BAROffset: 100h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.28 VTD0_FLTREC0_SRC: Fault Record

Base: VT_BAROffset: 108h

Bit Attr Default Description

63 RW1CS 0b F Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.When this field is set, hardware may collapse additional faults from the same requestor (SID). Software writes the value read from this field to clear it.

Intel® Xeon Phi™ Processor 249 Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 108h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See Intel VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.29 VTD0_FLTREC1_GPA: Fault Record

Base: VT_BAROffset: 110h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.30 VTD0_FLTREC1_SRC: Fault Record

Base: VT_BAROffset: 118h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

250 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 118h

Bit Attr Default Description

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.31 VTD0_FLTREC2_GPA: Fault Record

Base: VT_BAROffset: 120h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.32 VTD0_FLTREC2_SRC: Fault Record

Base: VT_BAROffset: 128h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.33 VTD0_FLTREC3_GPA: Fault Record

Base: VT_BAROffset: 130h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

Intel® Xeon Phi™ Processor 251 Datasheet - Volume 2, December 2016 7.3.34 VTD0_FLTREC3_SRC: Fault Record

Base: VT_BAROffset: 138h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.35 VTD0_FLTREC4_GPA: Fault Record

Base: VT_BAROffset: 140h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.36 VTD0_FLTREC4_SRC: Fault Record

Base: VT_BAROffset: 148h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

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Bit Attr Default Description

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.37 VTD0_FLTREC5_GPA: Fault Record

Base: VT_BAROffset: 150h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.38 VTD0_FLTREC5_SRC: Fault Record

Base: VT_BAROffset: 158h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

Intel® Xeon Phi™ Processor 253 Datasheet - Volume 2, December 2016 7.3.39 VTD0_FLTREC6_GPA: Fault Record

Base: VT_BAROffset: 160h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.40 VTD0_FLTREC6_SRC: Fault Record

Base: VT_BAROffset: 168h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.41 VTD0_FLTREC7_GPA: Fault Record

Base: VT_BAROffset: 170h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

254 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.42 VTD0_FLTREC7_SRC: Fault Record

Base: VT_BAROffset: 178h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.43 VTD0_INVADDRREG: Invalidate Address

Base: VT_BAROffset: 200h

Bit Attr Default Description

63:12 RW 0 Address To request a page-specific invalidation request to hardware, software must first write the corresponding guest physical address to this register, and then issue a page-specific invalidate command through the IOTLB_REG.

11:7 RV 0 Reserved

6 RW 0b Invalidation_Hint The field provides hint to hardware to preserve or flush the respective non-leaf page-table entries that may be cached in hardware. 0: Software may have modified both leaf and non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields. On a page-selective invalidation request, IIO must flush both the cached leaf and nonleaf page-table entries corresponding to mappings specified by ADDR and AM fields. IIO performs a domain-level invalidation on non-leaf entries and page- selective- domain-level invalidation at the leaf level 1: Software has not modified any non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields. On a page-selective invalidation request, IIO preserves the cached non- leaf page-table entries corresponding to mappings specified by ADDR and AM fields and performs only a page-selective invalidation at the leaf level

5:0 RW 000000 Address_Mask b IIO supports values of 0-9. All other values result in undefined results.

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Base: VT_BAROffset: 208h

Bit Attr Default Description

63 RW 0b IVT Invalidate IOTLB cache Software requests IOTLB invalidation by setting this field. Software must also set the requested invalidation granularity by programming the IIRG field.Hardware clears the IVT field to indicate the invalidation request is complete. Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field. Software must read back and check the IVT field to be clear to confirm the invalidation is complete. When IVT field is set, software must not update the contents of this register (and Invalidate Address register, i if it is being used), nor submit new IOTLB invalidation requests.

62 RV 0 Reserved

61:60 RW 00b IIRG IOTLB Invalidation Request Granularity When requesting hardware to invalidate the I/OTLB (by setting the IVT field), software writes the requested invalidation granularity through this IIRG field. Following are the encoding for the 2-bit IIRG field. 00: Reserved. Hardware ignores the invalidation request and reports invalidation complete by clearing the IVT field and reporting 00 in the AIG field. 01: Global Invalidation request. Intel Xeon processor E5 v3 product family supports this. 10: Domain-selective invalidation request. The target domain-id must be specified in the DID field. Intel Xeon processor E5 v3 product family supports this 11: Page-selective invalidation request. The target address, mask and invalidation hint must be specified in the Invalidate Address register, the domain-id must be provided in the DID field. Intel Xeon processor E5 v3 product family supports this.

58:57 RO 00b IAIG IOTLB Actual Invalidation Granularity Hardware reports the granularity at which an invalidation request was proceed through the AIG field at the time of reporting invalidation completion (by clearing the IVT field).The following are the encoding for the 2-bit IAIG field. 00: Reserved. This indicates hardware detected an incorrect invalidation request and ignored the request. Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page-selective invalidation requests or an unsupported/undefined encoding in IIRG. 01: Global Invalidation performed. Intel Xeon processor E5 v2 product family sets this in response to a global IOTLB invalidation request. 10: Domain-selective invalidation performed using the domain-id that was specified by software in the DID field. Intel Xeon processor E5 v2 product family sets this in response to a domain selective IOTLB invalidation request. 11: Intel Xeon processor E5 v2 product family sets this in response to a page selective invalidation request.

7.3.45 VTD1_VERSION: Version Number

Base: VT_BAROffset: 1000h

Bit Attr Default Description

31:8 RV 0 Reserved

7:4 RO 1h Major_Revision

3:0 RO 0h Minor_Revision

256 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.46 VTD1_CAP: Intel VT-d Capabilities

Base: VT_BAROffset: 1008h

Bit Attr Default Description

63:56 RV 0 Reserved

55 RO 1b DMA_Read_Draining IIO supports hardware based draining

54 RO 1b DMA_Write_Draining IIO supports hardware based write draining

53:48 RO 12h MAMV IIO support MAMV value of 12h (up to 1G super pages).

47:40 RO 07h Number_of_Fault_Recording_Registers IIO supports 8 fault recording registers

39 RO 1b Page_Selective_Invalidation Supported in IIO

38 RV 0 Reserved

37:34 RW-O 3h Super_Page_Support 2 MB, 1G supported.

33:24 RO 10h Fault_Recording_Register_Offset Fault registers are at offset 100h

23 RO 0b Spatial_Separation ISOCH Remapping Engine has ISOCH Support. Note: This bit used to be for “Spatial Separation”. This is no longer the case.

22 RO 1b ZLR Zero-length DMA requests to write-only pages supported.

21:16 RO-V 2Fh MGAW This register is set by Intel Xeon processor E5 v3 product family based on the setting of the GPA_LIMIT register. The value is the same for both the Azalia and non-Azalia engines (unlike TBG). This is because the translation for Azalia has been extended to be 4-level (instead of 3).

15:13 RV 0 Reserved

12:8 RO 04h SAGAW Supports 4-level walk on both Azalia and non-azalia engines.

7RO0bTCM IIO does not cache invalid pages. This bit should always be set to 0 on HW. It can be set to one when we are doing software virtualization of Intel VT-d.

6RO1bPHMR_Support IIO supports protected high memory range

5RO1bPLMR_Support IIO supports protected low memory range

4RO0bRWBF N/A for IIO

3 RO 0b Advanced_Fault_Logging IIO does not support advanced fault logging

2:0 RO 110b Number_of_Domains_Supported IIO supports 64k domains with 16 bit domain ID

Intel® Xeon Phi™ Processor 257 Datasheet - Volume 2, December 2016 7.3.47 VTD1_EXT_CAP: Extended Intel VT-d Capability

Base: VT_BAROffset: 1010h

Bit Attr Default Description

63:24 RV 0 Reserved

17:8 RO 20h Invalidation_Unit_Offset IIO has the invalidation registers at offset 200h

7 RW-O 0b Snoop_Control 1: indicates the hardware supports the 1-setting of the SNP field in the page-table entries. IIO supports snoop override only for the non-isoch Intel VT-d engine

6RO1bPass_through IIO supports pass through.

5 RO 1b Cachin_Hints Reserved.

4 RW 1b IA32_Extended_Interrupt_Mode IIO supports the extended interrupt mode

3 RO 1b Interrupt_Remapping_Support IIO supports this

2 RO 0b Device_TLB_support IIO does not support ATS for the isoch VT-d engine.

1 RO 1b Queued_Invalidation_support IIO supports this

0 RW-O 0b Coherency_Support BIOS can write to this bit to indicate to hardware to either snoop or not-snoop the DMA/Interrupt table structures in memory (root/context/pd/pt/irt). Note that this bit is expected to be always set to 0 for the Intel VT-d engine and programmability is only provided for that engine for debug reasons.

7.3.48 VTD1_GLBCMD: Global Command

Base: VT_BAROffset: 1018h

Bit Attr Default Description

258 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 1018h

Bit Attr Default Description

30 RW-V 0b Set_Root_Table_Pointer Software sets this field to set/update the root-entry table pointer used by hardware. The root- entry table pointer is specified through the Root-entry Table Address register.Hardware reports the status of the root table pointer set operation through the RTPS field in the Global Status register. The root table pointer set operation must be performed before enabling or re-enabling (after disabling) DMA remapping hardware. After a root table pointer set operation, software must globally invalidate the context cache followed by global invalidate of IOTLB. This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer, and not any stale cached entries. While DMA-remapping hardware is active, software may update the root table pointer through this field. However, to ensure valid in- flight DMA requests are deterministically remapped, software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer. Clearing this bit has no effect.

29 RO 0b Set_Fault_Log_Pointer N/A to Intel Xeon processor E5 v3 product family

28 RO 0b Enable_Advanced_Fault_Logging N/A to Intel Xeon processor E5 v3 product family

27 RO 0b Write_Buffer_Flush N/A to Intel Xeon processor E5 v3 product family

Intel® Xeon Phi™ Processor 259 Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 1018h

Bit Attr Default Description

22:0 RV 0 Reserved

7.3.49 VTD1_GLBSTS: Global Status

Base: VT_BAROffset: 101Ch

Bit Attr Default Description

31 RO-V 0b Translation_Enable_Status When set, indicates that translation hardware is enabled and when clear indicates the translation hardware is not enabled.

29 RO 0b Set_Fault_Log_Pointer_Status N/A

28 RO 0b Advanced_Fault_Logging_Status N/A

27 RO 0b Write_Buffer_Flush_Status N/A

26 RO-V 0b Queued_Invalidation_Interface_Status IIO sets this bit once it has completed the software command to enable the queued invalidation interface. Till then this bit is 0.

25 RO-V 0b Interrupt_Remapping_Enable_Status IIO sets this bit once it has completed the software command to enable the interrupt remapping interface. Till then this bit is 0.

22:0 RV 0 Reserved

260 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.50 VTD1_ROOTENTRYADD: Root Entry Table Address

Base: VT_BAROffset: 1020h

Bit Attr Default Description

63:12 RW 0 Root_Entry_Table_Base_Address 4K aligned base address for the root entry table. IIO does not utilize bits 63 : 43 and checks for them to be 0. Software specifies the base address of the root-entry table through this register, and enables it in hardware through the SRTP field in the Global Command register. Reads of this register returns value that was last programmed to it.

11:0 RV 0 Reserved

7.3.51 VTD1_CTXCMD: Context Command

Base: VT_BAROffset: 1028h

Bit Attr Default Description

Intel® Xeon Phi™ Processor 261 Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 1028h

Bit Attr Default Description

58:34 RV 0 Reserved

33:32 RW 00b fm Function Mask Used by IIO when performing device selective invalidation.

31:16 RW 0 Source_ID Used by IIO when performing device selective context cache invalidation.

7.3.52 VTD1_FLTSTS: Fault Status

Base: VT_BAROffset: 1034h

Bit Attr Default Description

31:16 RV 0 Reserved

7RV0 Reserved

5RW1C Invalidation_Completion_Error S Hardware received an unexpected or invalid Device-IOTLB invalidation completion. At this time, a 0 fault event is generated based on the programming of the Fault Event Control register.

3:2 RV 0 Reserved

0RW1C0 Primary_Fault_Overflow S Hardware sets this bit to indicate overflow of fault recording registers.

262 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.53 VTD1_FLTEVTCTRL: Fault Event Control

Base: VT_BAROffset: 1038h

Bit Attr Default Description

29:0 RV 0 Reserved

7.3.54 VTD1_FLTEVTDATA: Fault Event Data

Base: VT_BAROffset: 103Ch

Bit Attr Default Description

31:16 RV 0 Reserved

15:0 RW 0 Interrupt_Data

7.3.55 VTD1_FLTEVTADDR: Fault Event Lower Address

Base: VT_BAROffset: 1040h

Bit Attr Default Description

31:2 RW 0 MA Message Address (lower) The interrupt address is interpreted as the address of any other interrupt from a PCI Express port.

1:0 RV 0 Reserved

Intel® Xeon Phi™ Processor 263 Datasheet - Volume 2, December 2016 7.3.56 VTD1_FLTEVTUPRADDR: Fault Event Upper Address

Base: VT_BAROffset: 1044h

Bit Attr Default Description

31:0 RW 0 MUA Message Upper Address The interrupt address is interpreted as the address of any other interrupt from a PCI Express port.

7.3.57 VTD1_PMEN: Protected Memory Enable

Base: VT_BAROffset: 1064h

Bit Attr Default Description

30:1 RV 0 Reserved

0 RO-V 0b PROTREGIONSTS Protected Region Status This bit is set by Intel Xeon processor E5 v3 product family whenever it has completed enabling the protected memory region per the rules stated in the Intel VT-d spec.

7.3.58 VTD1_PROT_LOW_MEM_BASE: Protected Memory Low Base

Base: VT_BAROffset: 1068h

Bit Attr Default Description

20:0 RV 0 Reserved

264 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.59 VTD1_PROT_LOW_MEM_LIMIT: Protected Memory Low Limit

Base: VT_BAROffset: 106Ch

Bit Attr Default Description

31:21 RW 000h ADDR Low protected dram region 16MB aligned limit address of the low protected dram region Note that Intel VT-d engine generated reads/writes (page walk, interrupt queue, invalidation queue read, invalidation status) themselves are allowed toward this region, but no DMA accesses (non-translated DMA or ATS translated DMA or pass through DMA that is, no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1), when enabled.

20:0 RV 0 Reserved

7.3.60 VTD1_PROT_HIGH_MEM_BASE: Protected Memory High Base

Base: VT_BAROffset: 1070h

Bit Attr Default Description

20:0 RV 0 Reserved

7.3.61 VTD1_PROT_HIGH_MEM_LIMIT: Protected Memory High Limit

Base: VT_BAROffset: 1078h

Bit Attr Default Description

20:0 RV 0 Reserved

Intel® Xeon Phi™ Processor 265 Datasheet - Volume 2, December 2016 7.3.62 VTD1_INV_QUEUE_HEAD: Invalidation Queue Header Pointer

Base: VT_BAROffset: 1080h

Bit Attr Default Description

63:19 RV 0 Reserved

3:0 RV 0 Reserved

7.3.63 VTD1_INV_QUEUE_TAIL: Invalidation Queue Tail Pointer

Base: VT_BAROffset: 1088h

Bit Attr Default Description

63:19 RV 0 Reserved

18:4 RW 0000h Queue_Tail Specifies the offset (128-bit aligned) to the invalidation queue for the command that will be written next by software.

3:0 RV 0 Reserved

7.3.64 VTD1_INV_QUEUE_ADD: Invalidation Queue Address

Base: VT_BAROffset: 1090h

Bit Attr Default Description

63:12 RW 0 InvReq_Queue_Base_Address Invalidation Request Queue Base Address This field points to the base of size-aligned invalidation request queue.

11:3 RV 0 Reserved

7.3.65 VTD1_INV_COMP_STATUS: Invalidation Completion Status

Base: VT_BAROffset: 109Ch

Bit Attr Default Description

31:1 RV 0 Reserved

266 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.66 VTD1_INV_COMP_EVT_CTL: Invalidation Completion Event Control

Base: VT_BAROffset: 10A0h

Bit Attr Default Description

29:0 RV 0 Reserved

7.3.67 VTD1_INV_COMP_EVT_DATA: Invalidation Completion Event Data

Base: VT_BAROffset: 10A4h

Bit Attr Default Description

31:16 RV 0 Reserved

15:0 RW 0 Interrupt_Data

7.3.68 VTD1_INV_COMP_EVT_ADDR: Invalidation Completion Event Lower Address

Base: VT_BAROffset: 10A8h

Bit Attr Default Description

31:2 RW 0 MA Message Address (lower)

1:0 RV 0 Reserved

Intel® Xeon Phi™ Processor 267 Datasheet - Volume 2, December 2016 7.3.69 VTD1_INV_COMP_EVT_UPRADDR: Invalidation Completion Event Upper Address

Base: VT_BAROffset: 10ACh

Bit Attr Default Description

31:0 RW 0 MUA Message Upper Address

7.3.70 VTD1_INTR_REMAP_TABLE_BASE: Interrupt Remapping Table Base Address

Base: VT_BAROffset: 10B8h

Bit Attr Default Description

11 RW-LB 0b IA32_Extended_Interrupt_Enable 0: IA32 system is operating in legacy IA32 interrupt mode. Hardware interprets only 8-bit APICID in the Interrupt Remapping Table entries. 1: IA32 system is operating in extended IA32 interrupt mode. Hardware interprets 32-bit APICID in the Interrupt Remapping Table entries.

10:4 RV 0 Reserved

3:0 RW 0h Size This field specifies the size of the interrupt remapping table. The number of entries in the interrupt remapping table is 2^(X+1), where X is the value programmed in this field.

7.3.71 VTD1_FLTREC0_GPA: Fault Record

Base: VT_BAROffset: 1100h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

268 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.72 VTD1_FLTREC0_SRC: Fault Record

Base: VT_BAROffset: 1108h

Bit Attr Default Description

63 RW1C 0b F S Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR, SID, FR and T fields.When this field is set, hardware may collapse additional faults from the same requestor (SID). Software writes the value read from this field to clear it.

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.73 VTD1_FLTREC1_GPA: Fault Record

Base: VT_BAROffset: 1110h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.74 VTD1_FLTREC1_SRC: Fault Record

Base: VT_BAROffset: 1118h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

Intel® Xeon Phi™ Processor 269 Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 1118h

Bit Attr Default Description

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.75 VTD1_FLTREC2_GPA: Fault Record

Base: VT_BAROffset: 1120h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.76 VTD1_FLTREC2_SRC: Fault Record

Base: VT_BAROffset: 1128h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

270 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 7.3.77 VTD1_FLTREC3_GPA: Fault Record

Base: VT_BAROffset: 1130h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.78 VTD1_FLTREC3_SRC: Fault Record

Base: VT_BAROffset: 1138h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.79 VTD1_FLTREC4_GPA: Fault Record

Base: VT_BAROffset: 1140h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

Intel® Xeon Phi™ Processor 271 Datasheet - Volume 2, December 2016 7.3.80 VTD1_FLTREC4_SRC: Fault Record

Base: VT_BAROffset: 1148h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.81 VTD1_FLTREC5_GPA: Fault Record

Base: VT_BAROffset: 1150h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.82 VTD1_FLTREC5_SRC: Fault Record

Base: VT_BAROffset: 1158h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

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Bit Attr Default Description

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.83 VTD1_FLTREC6_GPA: Fault Record

Base: VT_BAROffset: 1160h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.84 VTD1_FLTREC6_SRC: Fault Record

Base: VT_BAROffset: 1168h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

Intel® Xeon Phi™ Processor 273 Datasheet - Volume 2, December 2016 7.3.85 VTD1_FLTREC7_GPA: Fault Record

Base: VT_BAROffset: 1170h

Bit Attr Default Description

63:12 ROS-V 0 GPA 4k aligned GPA for the faulting transaction. Valid only when F field is set

11:0 RV 0 Reserved

7.3.86 VTD1_FLTREC7_SRC: Fault Record

Base: VT_BAROffset: 1178h

Bit Attr Default Description

62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.

61:60 ROS-V 00b Address_Type This field captures the AT field from the faulted DMA request. This field is valid only when the F field is set.

59:40 RV 0 Reserved

39:32 ROS-V 00h Fault_Reason Reason for the first translation fault. See VT-d spec for details.This field is only valid when Fault bit is set.

31:16 RV 0 Reserved

15:0 ROS-V 0000h Source_Identifier Requester ID of the DMA request that faulted. Valid only when F bit is set.

7.3.87 VTD1_INVADDRREG: Invalidate Address

Base: VT_BAROffset: 1200h

Bit Attr Default Description

11:7 RV 0 Reserved

274 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 1200h

Bit Attr Default Description

6 RW 0b Invalidation_Hint The field provides hint to hardware to preserve or flush the respective non-leaf page-table entries that may be cached in hardware. 0: Software may have modified both leaf and non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields. On a page-selective invalidation request, IIO must flush both the cached leaf and nonleaf page-table entries corresponding to mappings specified by ADDR and AM fields. IIO performs a domain-level invalidation on non-leaf entries and page-selective- domain-level invalidation at the leaf level 1: Software has not modified any non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields. On a page-selective invalidation request, IIO preserves the cached non-leaf page-table entries corresponding to mappings specified by ADDR and AM fields and performs only a page-selective invalidation at the leaf level

5:0 RW 000000b Address_Mask IIO supports values of 0-9. All other values result in undefined results.

7.3.88 VTD1_IOTLBINV: IOTLB Invalidate

Base: VT_BAROffset: 1208h

Bit Attr Default Description

63 RW-V 0b IVT Invalidate IOTLB cache Software requests IOTLB invalidation by setting this field. Software must also set the requested invalidation granularity by programming the IIRG field.Hardware clears the IVT field to indicate the invalidation request is complete. Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field. Software must read back and check the IVT field to be clear to confirm the invalidation is complete. When IVT field is set, software must not update the contents of this register (and Invalidate Address register, i if it is being used), nor submit new IOTLB invalidation requests.

62 RV 0 Reserved

59 RV 0 Reserved

Intel® Xeon Phi™ Processor 275 Datasheet - Volume 2, December 2016 Base: VT_BAROffset: 1208h

Bit Attr Default Description

58:57 RO-V 00b IAIG IOTLB Actual Invalidation Granularity Hardware reports the granularity at which an invalidation request was proceed through the AIG field at the time of reporting invalidation completion (by clearing the IVT field).The following are the encoding for the 2-bit IAIG field. 00: Reserved. This indicates hardware detected an incorrect invalidation request and ignored the request. Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page-selective invalidation requests or an unsupported/undefined encoding in IIRG. 01: Global Invalidation performed. Intel Xeon processor E5 v3 product family sets this in response to a global IOTLB invalidation request. 10: Domain-selective invalidation performed using the domain-id that was specified by software in the DID field. Intel Xeon processor E5 v3 product family sets this in response to a domain selective IOTLB invalidation request. 11: Intel Xeon processor E5 v3 product family sets this in response to a page selective invalidation request.

56:50 RV 0 Reserved

49 RW 0b Drain_Reads IIO uses this to drain or not drain reads on an invalidation request.

48 RW 0b Drain_Writes IIO uses this to drain or not drain writes on an invalidation request.

47:32 RW 0000h Domain_ID Domain to be invalidated and is programmed by software for both page and domain selective invalidation requests. Intel Xeon processor E5 v3 product family ignores the bits 47:40 since it supports only an 8 bit Domain ID.

31:0 RV 0 Reserved

276 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 8 RAS Registers

8.1 RAS Configuration Registers

The RAS register set generally contains the registers that control RAS features for the IIO Stack. In this version, most of the registers are error log registers. The control for Viral also exists in this function.

This is a summary of the components of the RAS Configuration Registers: • Standard PCI Type 0 Header • PCIe Capability Structure to allow Extended 4k Configuration Space • Integrated Device Global Severity Control • Error Pin Controls • Virtual Pin Port Controls • Global Error Logic • Write Cache Unit (IRP) Error Logging • IIO Switch Error Logging • Miscellaneous Cluster Error Logging

Intel® Xeon Phi™ Processor 277 Datasheet - Volume 2, December 2016 Figure 8-1. RAS Configuration Register Map Offset 0x00 - 0x1FF

278 Intel® Xeon Phi™ Processor Datasheet - Volume 2, December 2016 Figure 8-2. RAS Configuration Register Map Offset 0x200 - 0x3FF

8.2 VID: Vendor ID

Bus: RootBus0Device: 5Function: 2Offset: 0h

Bit Attr Default Description

15:0 RO 8086h Vendor_Identification_Number The value is assigned by PCI-SIG to Intel.

Intel® Xeon Phi™ Processor 279 Datasheet - Volume 2, December 2016 8.3 DID: Device ID

Bus: RootBus0Device: 5Function: 2Offset: 2h

Bit Attr Default Description

15:0 RO 7812h Device_Identification_Number Device ID values vary from function to function. Bits 15:8 are equal to 0x3C for Intel Xeon processor E5 v3 product family. The following list is a breakdown of the function groups. 0x3C00 - 0x3C1F : PCI Express and DMI ports 0x3C20 - 0x3C3F : IO Features (APIC, VT, RAS, LT) 0x3C40 - 0x3C5F : Performance Monitors 0x3C60 - 0x3C7F : DFX 0x3CA0 - 0x3CBF : Home Agent/Memory Controller 0x3CC0 - 0x3CDF : Power Management 0x3CE0 - 0x3CFF : Cbo/Ring

8.3.1 PCICMD: PCI Command

Bus: RootBus0Device: 5Function: 2Offset: 4h